blob: 21d4e8ef24a7e704592fb98ec08d11031998cfd3 [file] [log] [blame]
/*
* Copyright (c) 2022 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/ztest.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(test);
/* Not device related, but keep it to ensure core clock config is correct */
ZTEST(stm32_common_devices_clocks, test_sysclk_freq)
{
uint32_t soc_sys_clk_freq;
soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
}
ZTEST_SUITE(stm32_common_devices_clocks, NULL, NULL, NULL, NULL, NULL);