| /* |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| * CCFG (User configuration area) interface registers and bit offsets |
| * for the CC2650 System on Chip. |
| */ |
| |
| |
| #ifndef _CC2650_CCFG_H_ |
| #define _CC2650_CCFG_H_ |
| |
| /* Registers */ |
| |
| enum CC2650_CCFG_Registers { |
| CC2650_CCFG_EXT_LF_CLK = 0xFA8, |
| CC2650_CCFG_MODE_CONF_1 = 0xFAC, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS = 0xFB0, |
| CC2650_CCFG_MODE_CONF = 0xFB4, |
| CC2650_CCFG_VOLT_LOAD_0 = 0xFB8, |
| CC2650_CCFG_VOLT_LOAD_1 = 0xFBC, |
| CC2650_CCFG_RTC_OFFSET = 0xFC0, |
| CC2650_CCFG_FREQ_OFFSET = 0xFC4, |
| CC2650_CCFG_IEEE_MAC_0 = 0xFC8, |
| CC2650_CCFG_IEEE_MAC_1 = 0xFCC, |
| CC2650_CCFG_IEEE_BLE_0 = 0xFD0, |
| CC2650_CCFG_IEEE_BLE_1 = 0xFD4, |
| CC2650_CCFG_BL_CONFIG = 0xFD8, |
| CC2650_CCFG_ERASE_CONF = 0xFDC, |
| CC2650_CCFG_CCFG_TI_OPTIONS = 0xFE0, |
| CC2650_CCFG_CCFG_TAP_DAP_0 = 0xFE4, |
| CC2650_CCFG_CCFG_TAP_DAP_1 = 0xFE8, |
| CC2650_CCFG_IMAGE_VALID_CONF = 0xFEC, |
| CC2650_CCFG_CCFG_PROT_31_0 = 0xFF0, |
| CC2650_CCFG_CCFG_PROT_63_32 = 0xFF4, |
| CC2650_CCFG_CCFG_PROT_95_64 = 0xFF8, |
| CC2650_CCFG_CCFG_PROT_127_96 = 0xFFC |
| }; |
| |
| /* Register-specific bits */ |
| |
| /* EXT_LF_CLK */ |
| enum CC2650_CCFG_EXT_LF_CLK_POS { |
| CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_POS = 0, |
| CC2650_CCFG_EXT_LF_CLK_DIO_POS = 24 |
| }; |
| |
| enum CC2650_CCFG_EXT_LF_CLK_MASK { |
| CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_MASK = 0x00FFFFFF, |
| CC2650_CCFG_EXT_LF_CLK_DIO_MASK = 0xFF000000 |
| }; |
| |
| /* MODE_CONF_1 */ |
| enum CC2650_CCFG_MODE_CONF_1_POS { |
| CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_POS = 0, |
| CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_POS = 8, |
| CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_POS = 12, |
| CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_POS = 16, |
| CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_POS = 19, |
| CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_POS = 20 |
| }; |
| |
| enum CC2650_CCFG_MODE_CONF_1_MASK { |
| CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_MASK = 0x000000FF, |
| CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_MASK = 0x00000F00, |
| CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_MASK = 0x0000F000, |
| CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_MASK = 0x00070000, |
| CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_MASK = 0x00080000, |
| CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_MASK = 0x00F00000 |
| }; |
| |
| /* SIZE_AND_DIS_FLAGS */ |
| enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_POS { |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_POS = 0, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_POS = 1, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_POS = 2, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_POS = 3, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_POS = 4, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_POS = 16 |
| }; |
| |
| enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_MASK { |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_MASK = |
| 0x00000001, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_MASK = |
| 0x00000002, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_MASK = |
| 0x00000004, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_MASK = |
| 0x00000008, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_MASK = |
| 0x0000FFF0, |
| CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_MASK = |
| 0xFFFF0000 |
| }; |
| |
| /* MODE_CONF */ |
| enum CC2650_CCFG_MODE_CONF_POS { |
| CC2650_CCFG_MODE_CONF_VDDR_CAP_POS = 0, |
| CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_POS = 8, |
| CC2650_CCFG_MODE_CONF_HF_COMP_POS = 16, |
| CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_POS = 17, |
| CC2650_CCFG_MODE_CONF_XOSC_FREQ_POS = 18, |
| CC2650_CCFG_MODE_CONF_RTC_COMP_POS = 20, |
| CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_POS = 21, |
| CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_POS = 22, |
| CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_POS = 24, |
| CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_POS = 25, |
| CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_POS = 26, |
| CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_POS = 27, |
| CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_POS = 28 |
| }; |
| |
| enum CC2650_CCFG_MODE_CONF_MASK { |
| CC2650_CCFG_MODE_CONF_VDDR_CAP_MASK = |
| 0x000000FF, |
| CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_MASK = |
| 0x0000FF00, |
| CC2650_CCFG_MODE_CONF_HF_COMP_MASK = |
| 0x00010000, |
| CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_MASK = |
| 0x00020000, |
| CC2650_CCFG_MODE_CONF_XOSC_FREQ_MASK = |
| 0x000C0000, |
| CC2650_CCFG_MODE_CONF_RTC_COMP_MASK = |
| 0x00100000, |
| CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_MASK = |
| 0x00200000, |
| CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_MASK = |
| 0x00C00000, |
| CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_MASK = |
| 0x01000000, |
| CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_MASK = |
| 0x02000000, |
| CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_MASK = |
| 0x04000000, |
| CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_MASK = |
| 0x08000000, |
| CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_MASK = |
| 0xF0000000 |
| }; |
| |
| /* VOLT_LOAD_0 */ |
| enum CC2650_CCFG_VOLT_LOAD_0_POS { |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_POS = 0, |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_POS = 8, |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_POS = 16, |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_POS = 24 |
| }; |
| |
| enum CC2650_CCFG_VOLT_LOAD_0_MASK { |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_MASK = 0x000000FF, |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_MASK = 0x0000FF00, |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_MASK = 0x00FF0000, |
| CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_MASK = 0xFF000000 |
| }; |
| |
| /* VOLT_LOAD_1 */ |
| enum CC2650_CCFG_VOLT_LOAD_1_POS { |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_POS = 0, |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_POS = 8, |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_POS = 16, |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_POS = 24 |
| }; |
| |
| enum CC2650_CCFG_VOLT_LOAD_1_MASK { |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_MASK = 0x000000FF, |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_MASK = 0x0000FF00, |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_MASK = 0x00FF0000, |
| CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_MASK = 0xFF000000 |
| }; |
| |
| /* RTC_OFFSET */ |
| enum CC2650_CCFG_RTC_OFFSET_POS { |
| CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_POS = 0, |
| CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_POS = 8, |
| CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_POS = 16 |
| }; |
| |
| enum CC2650_CCFG_RTC_OFFSET_MASK { |
| CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_MASK = 0x000000FF, |
| CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_MASK = 0x0000FF00, |
| CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_MASK = 0xFFFF0000 |
| }; |
| |
| /* FREQ_OFFSET */ |
| enum CC2650_CCFG_FREQ_OFFSET_POS { |
| CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_POS = 0, |
| CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_POS = 8, |
| CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_POS = 16 |
| }; |
| |
| enum CC2650_CCFG_FREQ_OFFSET_MASK { |
| CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_MASK = 0x000000FF, |
| CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_MASK = 0x0000FF00, |
| CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_MASK = 0xFFFF0000 |
| }; |
| |
| /* IEEE_MAC_0 */ |
| enum CC2650_CCFG_IEEE_MAC_0_POS { |
| CC2650_CCFG_IEEE_MAC_0_ADDR_POS = 0 |
| }; |
| |
| enum CC2650_CCFG_IEEE_MAC_0_MASK { |
| CC2650_CCFG_IEEE_MAC_0_ADDR_MASK = 0xFFFFFFFF |
| }; |
| |
| /* IEEE_MAC_1 */ |
| enum CC2650_CCFG_IEEE_MAC_1_POS { |
| CC2650_CCFG_IEEE_MAC_1_ADDR_POS = 0 |
| }; |
| |
| enum CC2650_CCFG_IEEE_MAC_1_MASK { |
| CC2650_CCFG_IEEE_MAC_1_ADDR_MASK = 0xFFFFFFFF |
| }; |
| |
| /* IEEE_BLE_0 */ |
| enum CC2650_CCFG_IEEE_BLE_POS { |
| CC2650_CCFG_IEEE_BLE_0_ADDR_POS = 0 |
| }; |
| |
| enum CC2650_CCFG_IEEE_BLE_MASK { |
| CC2650_CCFG_IEEE_BLE_0_ADDR_MASK = 0xFFFFFFFF |
| }; |
| |
| /* IEEE_BLE_1 */ |
| enum CC2650_CCFG_IEEE_BLE_1_POS { |
| CC2650_CCFG_IEEE_BLE_1_ADDR_POS = 0 |
| }; |
| |
| enum CC2650_CCFG_IEEE_BLE_1_MASK { |
| CC2650_CCFG_IEEE_BLE_1_ADDR_MASK = 0xFFFFFFFF |
| }; |
| |
| /* BL_CONFIG */ |
| enum CC2650_CCFG_BL_CONFIG_POS { |
| CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS = 0, |
| CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS = 8, |
| CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS = 16, |
| CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS = 24 |
| }; |
| |
| enum CC2650_CCFG_BL_CONFIG_MASK { |
| CC2650_CCFG_BL_CONFIG_BL_ENABLE_MASK = 0x000000FF, |
| CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_MASK = 0x0000FF00, |
| CC2650_CCFG_BL_CONFIG_BL_LEVEL_MASK = 0x00010000, |
| CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_MASK = 0xFF000000 |
| }; |
| |
| enum CC2650_CCFG_BL_CONFIG_VALUES { |
| CC2650_CCFG_BACKDOOR_ENABLED = |
| 0xC5 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS, |
| CC2650_CCFG_BACKDOOR_DISABLED = |
| 0x00 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS, |
| CC2650_CCFG_BACKDOOR_ACTIVE_HIGH = |
| 0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS, |
| CC2650_CCFG_BACKDOOR_ACTIVE_LOW = |
| 0x0 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS, |
| CC2650_CCFG_BOOTLOADER_ENABLED = |
| 0xC5 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS, |
| CC2650_CCFG_BOOTLOADER_DISABLED = |
| 0x00 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS |
| }; |
| |
| /* ERASE_CONF */ |
| enum CC2650_CCFG_ERASE_CONF_POS { |
| CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_POS = 0, |
| CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_POS = 8 |
| }; |
| |
| enum CC2650_CCFG_ERASE_CONF_MASK { |
| CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_MASK = 0x00000001, |
| CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_MASK = 0x00000100 |
| }; |
| |
| /* CCFG_TI_OPTIONS */ |
| enum CC2650_CCFG_TI_OPTIONS_POS { |
| CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS = 0 |
| }; |
| |
| enum CC2650_CCFG_TI_OPTIONS_MASK { |
| CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_MASK = 0x000000FF |
| }; |
| |
| enum CC2650_CCFG_TI_OPTIONS_VALUES { |
| CC2650_CCFG_TI_FA_ENABLED = |
| 0xC5 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS, |
| CC2650_CCFG_TI_FA_DISABLED = |
| 0x00 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS |
| }; |
| |
| /* CCFG_TAP_DAP_0 */ |
| enum CC2650_CCFG_TAP_DAP_0_POS { |
| CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_POS = 0, |
| CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_POS = 8, |
| CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_POS = 16 |
| }; |
| |
| enum CC2650_CCFG_TAP_DAP_0_MASK { |
| CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_MASK = |
| 0x000000FF, |
| CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_MASK = |
| 0x0000FF00, |
| CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_MASK = |
| 0x00FF0000 |
| }; |
| |
| /* CCFG_TAP_DAP_1 */ |
| enum CC2650_CCFG_CCFG_TAP_DAP_1_POS { |
| CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_POS = 0, |
| CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_POS = 8, |
| CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_POS = 16 |
| }; |
| |
| enum CC2650_CCFG_CCFG_TAP_DAP_1_MASK { |
| CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_MASK = |
| 0x000000FF, |
| CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_MASK = |
| 0x0000FF00, |
| CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_MASK = |
| 0x00FF0000 |
| }; |
| |
| /* IMAGE_VALID_CONF */ |
| enum CC2650_CCFG_IMAGE_VALID_CONF_POS { |
| CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS = 0 |
| }; |
| |
| enum CC2650_CCFG_IMAGE_VALID_CONF_MASK { |
| CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_MASK = 0xFFFFFFFF |
| }; |
| |
| enum CC2650_CCFG_IMAGE_VALID_CONF_VALUES { |
| CC2650_CCFG_IMAGE_IS_VALID = |
| 0x00000000 << CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS |
| }; |
| |
| /* CCFG_PROT_31_0 */ |
| enum CC2650_CCFG_CCFG_PROT_31_0_POS { |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_POS = 0, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_POS = 1, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_POS = 2, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_POS = 3, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_POS = 4, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_POS = 5, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_POS = 6, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_POS = 7, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_POS = 8, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_POS = 9, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_POS = 10, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_POS = 11, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_POS = 12, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_POS = 13, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_POS = 14, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_POS = 15, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_POS = 16, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_POS = 17, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_POS = 18, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_POS = 19, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_POS = 20, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_POS = 21, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_POS = 22, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_POS = 23, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_POS = 24, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_POS = 25, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_POS = 26, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_POS = 27, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_POS = 28, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_POS = 29, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_POS = 30, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_POS = 31 |
| }; |
| |
| enum CC2650_CCFG_CCFG_PROT_31_0_MASK { |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_MASK = |
| 0x00000001, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_MASK = |
| 0x00000002, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_MASK = |
| 0x00000004, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_MASK = |
| 0x00000008, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_MASK = |
| 0x00000010, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_MASK = |
| 0x00000020, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_MASK = |
| 0x00000040, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_MASK = |
| 0x00000080, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_MASK = |
| 0x00000100, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_MASK = |
| 0x00000200, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_MASK = |
| 0x00000400, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_MASK = |
| 0x00000800, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_MASK = |
| 0x00001000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_MASK = |
| 0x00002000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_MASK = |
| 0x00004000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_MASK = |
| 0x00008000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_MASK = |
| 0x00010000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_MASK = |
| 0x00020000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_MASK = |
| 0x00040000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_MASK = |
| 0x00080000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_MASK = |
| 0x00100000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_MASK = |
| 0x00200000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_MASK = |
| 0x00400000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_MASK = |
| 0x00800000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_MASK = |
| 0x01000000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_MASK = |
| 0x02000000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_MASK = |
| 0x04000000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_MASK = |
| 0x08000000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_MASK = |
| 0x10000000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_MASK = |
| 0x20000000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_MASK = |
| 0x40000000, |
| CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_MASK = |
| 0x80000000 |
| }; |
| |
| /* CCFG_PROT_63_32 */ |
| enum CC2650_CCFG_CCFG_PROT_63_32_POS { |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_POS = 32, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_POS = 33, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_POS = 34, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_POS = 35, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_POS = 36, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_POS = 37, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_POS = 38, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_POS = 39, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_POS = 40, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_POS = 41, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_POS = 42, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_POS = 43, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_POS = 44, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_POS = 45, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_POS = 46, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_POS = 47, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_POS = 48, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_POS = 49, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_POS = 50, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_POS = 51, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_POS = 52, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_POS = 53, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_POS = 54, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_POS = 55, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_POS = 56, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_POS = 57, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_POS = 58, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_POS = 59, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_POS = 60, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_POS = 61, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_POS = 62, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_POS = 63 |
| }; |
| |
| enum CC2650_CCFG_CCFG_PROT_63_32_MASK { |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_MASK = |
| 0x00000001, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_MASK = |
| 0x00000002, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_MASK = |
| 0x00000004, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_MASK = |
| 0x00000008, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_MASK = |
| 0x00000010, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_MASK = |
| 0x00000020, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_MASK = |
| 0x00000040, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_MASK = |
| 0x00000080, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_MASK = |
| 0x00000100, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_MASK = |
| 0x00000200, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_MASK = |
| 0x00000400, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_MASK = |
| 0x00000800, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_MASK = |
| 0x00001000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_MASK = |
| 0x00002000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_MASK = |
| 0x00004000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_MASK = |
| 0x00008000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_MASK = |
| 0x00010000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_MASK = |
| 0x00020000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_MASK = |
| 0x00040000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_MASK = |
| 0x00080000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_MASK = |
| 0x00100000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_MASK = |
| 0x00200000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_MASK = |
| 0x00400000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_MASK = |
| 0x00800000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_MASK = |
| 0x01000000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_MASK = |
| 0x02000000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_MASK = |
| 0x04000000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_MASK = |
| 0x08000000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_MASK = |
| 0x10000000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_MASK = |
| 0x20000000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_MASK = |
| 0x40000000, |
| CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_MASK = |
| 0x80000000 |
| }; |
| |
| /* CCFG_PROT_95_64 */ |
| enum CC2650_CCFG_CCFG_PROT_95_64_POS { |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_POS = 64, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_POS = 65, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_POS = 66, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_POS = 67, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_POS = 68, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_POS = 69, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_POS = 70, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_POS = 71, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_POS = 72, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_POS = 73, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_POS = 74, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_POS = 75, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_POS = 76, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_POS = 77, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_POS = 78, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_POS = 79, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_POS = 80, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_POS = 81, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_POS = 82, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_POS = 83, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_POS = 84, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_POS = 85, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_POS = 86, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_POS = 87, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_POS = 88, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_POS = 89, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_POS = 90, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_POS = 91, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_POS = 92, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_POS = 93, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_POS = 94, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_POS = 95 |
| }; |
| |
| enum CC2650_CCFG_CCFG_PROT_95_64_MASK { |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_MASK = |
| 0x00000001, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_MASK = |
| 0x00000002, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_MASK = |
| 0x00000004, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_MASK = |
| 0x00000008, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_MASK = |
| 0x00000010, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_MASK = |
| 0x00000020, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_MASK = |
| 0x00000040, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_MASK = |
| 0x00000080, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_MASK = |
| 0x00000100, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_MASK = |
| 0x00000200, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_MASK = |
| 0x00000400, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_MASK = |
| 0x00000800, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_MASK = |
| 0x00001000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_MASK = |
| 0x00002000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_MASK = |
| 0x00004000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_MASK = |
| 0x00008000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_MASK = |
| 0x00010000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_MASK = |
| 0x00020000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_MASK = |
| 0x00040000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_MASK = |
| 0x00080000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_MASK = |
| 0x00100000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_MASK = |
| 0x00200000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_MASK = |
| 0x00400000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_MASK = |
| 0x00800000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_MASK = |
| 0x01000000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_MASK = |
| 0x02000000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_MASK = |
| 0x04000000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_MASK = |
| 0x08000000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_MASK = |
| 0x10000000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_MASK = |
| 0x20000000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_MASK = |
| 0x40000000, |
| CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_MASK = |
| 0x80000000 |
| }; |
| |
| /* CCFG_PROT_127_96 */ |
| enum CC2650_CCFG_CCFG_PROT_127_96_POS { |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_POS = 96, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_POS = 97, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_POS = 98, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_POS = 99, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_POS = 100, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_POS = 101, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_POS = 102, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_POS = 103, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_POS = 104, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_POS = 105, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_POS = 106, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_POS = 107, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_POS = 108, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_POS = 109, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_POS = 110, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_POS = 111, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_POS = 112, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_POS = 113, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_POS = 114, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_POS = 115, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_POS = 116, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_POS = 117, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_POS = 118, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_POS = 119, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_POS = 120, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_POS = 121, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_POS = 122, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_POS = 123, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_POS = 124, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_POS = 125, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_POS = 126, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_POS = 127 |
| }; |
| |
| enum CC2650_CCFG_CCFG_PROT_127_96_MASK { |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_MASK = |
| 0x00000001, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_MASK = |
| 0x00000002, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_MASK = |
| 0x00000004, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_MASK = |
| 0x00000008, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_MASK = |
| 0x00000010, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_MASK = |
| 0x00000020, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_MASK = |
| 0x00000040, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_MASK = |
| 0x00000080, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_MASK = |
| 0x00000100, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_MASK = |
| 0x00000200, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_MASK = |
| 0x00000400, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_MASK = |
| 0x00000800, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_MASK = |
| 0x00001000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_MASK = |
| 0x00002000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_MASK = |
| 0x00004000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_MASK = |
| 0x00008000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_MASK = |
| 0x00010000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_MASK = |
| 0x00020000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_MASK = |
| 0x00040000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_MASK = |
| 0x00080000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_MASK = |
| 0x00100000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_MASK = |
| 0x00200000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_MASK = |
| 0x00400000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_MASK = |
| 0x00800000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_MASK = |
| 0x01000000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_MASK = |
| 0x02000000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_MASK = |
| 0x04000000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_MASK = |
| 0x08000000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_MASK = |
| 0x10000000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_MASK = |
| 0x20000000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_MASK = |
| 0x40000000, |
| CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_MASK = |
| 0x80000000 |
| }; |
| |
| #endif /* _CC2650_CCFG_H_ */ |
