| /* |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| * GPIO registers and bit offsets for the CC2650 System on Chip. |
| */ |
| |
| |
| #ifndef _CC2650_GPIO_H_ |
| #define _CC2650_GPIO_H_ |
| |
| /* Registers */ |
| |
| enum CC2650_GPIO_Registers { |
| CC2650_GPIO_DOUT3_0 = 0x0, |
| CC2650_GPIO_DOUT7_4 = 0x4, |
| CC2650_GPIO_DOUT11_8 = 0x8, |
| CC2650_GPIO_DOUT15_12 = 0xC, |
| CC2650_GPIO_DOUT19_16 = 0x10, |
| CC2650_GPIO_DOUT23_20 = 0x14, |
| CC2650_GPIO_DOUT27_24 = 0x18, |
| CC2650_GPIO_DOUT31_28 = 0x1C, |
| /* Reserved */ |
| CC2650_GPIO_DOUT31_0 = 0x80, |
| /* Reserved */ |
| CC2650_GPIO_DOUTSET31_0 = 0x90, |
| /* Reserved */ |
| CC2650_GPIO_DOUTCLR31_0 = 0XA0, |
| /* Reserved */ |
| CC2650_GPIO_DOUTTGL31_0 = 0xB0, |
| /* Reserved */ |
| CC2650_GPIO_DIN31_0 = 0xC0, |
| /* Reserved */ |
| CC2650_GPIO_DOE31_0 = 0xD0, |
| /* Reserved */ |
| CC2650_GPIO_EVFLAGS31_0 = 0xE0 |
| }; |
| |
| |
| /* Register-specific bits */ |
| |
| /* DOUT3_0 */ |
| enum CC2650_GPIO_DOUT3_0_POS { |
| CC2650_GPIO_DOUT3_0_DIO0_POS = 0, |
| CC2650_GPIO_DOUT3_0_DIO1_POS = 8, |
| CC2650_GPIO_DOUT3_0_DIO2_POS = 16, |
| CC2650_GPIO_DOUT3_0_DIO3_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT3_0_MASK { |
| CC2650_GPIO_DOUT3_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_DOUT3_0_DIO1_MASK = 0x00000100, |
| CC2650_GPIO_DOUT3_0_DIO2_MASK = 0x00010000, |
| CC2650_GPIO_DOUT3_0_DIO3_MASK = 0x01000000 |
| }; |
| |
| /* DOUT7_4 */ |
| enum CC2650_GPIO_DOUT7_4_POS { |
| CC2650_GPIO_DOUT7_4_DIO4_POS = 0, |
| CC2650_GPIO_DOUT7_4_DIO5_POS = 8, |
| CC2650_GPIO_DOUT7_4_DIO6_POS = 16, |
| CC2650_GPIO_DOUT7_4_DIO7_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT7_4_MASK { |
| CC2650_GPIO_DOUT7_4_DIO4_MASK = 0x00000001, |
| CC2650_GPIO_DOUT7_4_DIO5_MASK = 0x00000100, |
| CC2650_GPIO_DOUT7_4_DIO6_MASK = 0x00010000, |
| CC2650_GPIO_DOUT7_4_DIO7_MASK = 0x01000000 |
| }; |
| |
| /* DOUT11_8 */ |
| enum CC2650_GPIO_DOUT11_8_POS { |
| CC2650_GPIO_DOUT11_8_DIO8_POS = 0, |
| CC2650_GPIO_DOUT11_8_DIO9_POS = 8, |
| CC2650_GPIO_DOUT11_8_DIO10_POS = 16, |
| CC2650_GPIO_DOUT11_8_DIO11_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT11_8_MASK { |
| CC2650_GPIO_DOUT11_8_DIO8_MASK = 0x00000001, |
| CC2650_GPIO_DOUT11_8_DIO9_MASK = 0x00000100, |
| CC2650_GPIO_DOUT11_8_DIO10_MASK = 0x00010000, |
| CC2650_GPIO_DOUT11_8_DIO11_MASK = 0x01000000 |
| }; |
| |
| /* DOUT15_12 */ |
| enum CC2650_GPIO_DOUT15_12_POS { |
| CC2650_GPIO_DOUT15_12_DIO12_POS = 0, |
| CC2650_GPIO_DOUT15_12_DIO13_POS = 8, |
| CC2650_GPIO_DOUT15_12_DIO14_POS = 16, |
| CC2650_GPIO_DOUT15_12_DIO15_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT15_12_MASK { |
| CC2650_GPIO_DOUT15_12_DIO12_MASK = 0x00000001, |
| CC2650_GPIO_DOUT15_12_DIO13_MASK = 0x00000100, |
| CC2650_GPIO_DOUT15_12_DIO14_MASK = 0x00010000, |
| CC2650_GPIO_DOUT15_12_DIO15_MASK = 0x01000000 |
| }; |
| |
| /* DOUT19_16 */ |
| enum CC2650_GPIO_DOUT19_16_POS { |
| CC2650_GPIO_DOUT19_16_DIO16_POS = 0, |
| CC2650_GPIO_DOUT19_16_DIO17_POS = 8, |
| CC2650_GPIO_DOUT19_16_DIO18_POS = 16, |
| CC2650_GPIO_DOUT19_16_DIO19_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT19_16_MASK { |
| CC2650_GPIO_DOUT19_16_DIO16_MASK = 0x00000001, |
| CC2650_GPIO_DOUT19_16_DIO17_MASK = 0x00000100, |
| CC2650_GPIO_DOUT19_16_DIO18_MASK = 0x00010000, |
| CC2650_GPIO_DOUT19_16_DIO19_MASK = 0x01000000 |
| }; |
| |
| /* DOUT23_20 */ |
| enum CC2650_GPIO_DOUT23_20_POS { |
| CC2650_GPIO_DOUT23_20_DIO20_POS = 0, |
| CC2650_GPIO_DOUT23_20_DIO21_POS = 8, |
| CC2650_GPIO_DOUT23_20_DIO22_POS = 16, |
| CC2650_GPIO_DOUT23_20_DIO23_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT23_20_MASK { |
| CC2650_GPIO_DOUT23_20_DIO20_MASK = 0x00000001, |
| CC2650_GPIO_DOUT23_20_DIO21_MASK = 0x00000100, |
| CC2650_GPIO_DOUT23_20_DIO22_MASK = 0x00010000, |
| CC2650_GPIO_DOUT23_20_DIO23_MASK = 0x01000000 |
| }; |
| |
| /* DOUT27_24 */ |
| enum CC2650_GPIO_DOUT27_24_POS { |
| CC2650_GPIO_DOUT27_24_DIO24_POS = 0, |
| CC2650_GPIO_DOUT27_24_DIO25_POS = 8, |
| CC2650_GPIO_DOUT27_24_DIO26_POS = 16, |
| CC2650_GPIO_DOUT27_24_DIO27_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT27_24_MASK { |
| CC2650_GPIO_DOUT27_24_DIO24_MASK = 0x00000001, |
| CC2650_GPIO_DOUT27_24_DIO25_MASK = 0x00000100, |
| CC2650_GPIO_DOUT27_24_DIO26_MASK = 0x00010000, |
| CC2650_GPIO_DOUT27_24_DIO27_MASK = 0x01000000 |
| }; |
| |
| /* DOUT31_28 */ |
| enum CC2650_GPIO_DOUT31_28_POS { |
| CC2650_GPIO_DOUT31_28_DIO28_POS = 0, |
| CC2650_GPIO_DOUT31_28_DIO29_POS = 8, |
| CC2650_GPIO_DOUT31_28_DIO30_POS = 16, |
| CC2650_GPIO_DOUT31_28_DIO31_POS = 24 |
| }; |
| |
| enum CC2650_GPIO_DOUT31_28_MASK { |
| CC2650_GPIO_DOUT31_28_DIO28 = 0x00000001, |
| CC2650_GPIO_DOUT31_28_DIO29 = 0x00000100, |
| CC2650_GPIO_DOUT31_28_DIO30 = 0x00010000, |
| CC2650_GPIO_DOUT31_28_DIO31 = 0x01000000 |
| }; |
| |
| /* DOUT31_0 */ |
| enum CC2650_GPIO_DOUT31_0_POS { |
| CC2650_GPIO_DOUT31_0_DIO0_POS = 0, |
| CC2650_GPIO_DOUT31_0_DIO1_POS = 1, |
| CC2650_GPIO_DOUT31_0_DIO2_POS = 2, |
| CC2650_GPIO_DOUT31_0_DIO3_POS = 3, |
| CC2650_GPIO_DOUT31_0_DIO4_POS = 4, |
| CC2650_GPIO_DOUT31_0_DIO5_POS = 5, |
| CC2650_GPIO_DOUT31_0_DIO6_POS = 6, |
| CC2650_GPIO_DOUT31_0_DIO7_POS = 7, |
| CC2650_GPIO_DOUT31_0_DIO8_POS = 8, |
| CC2650_GPIO_DOUT31_0_DIO9_POS = 9, |
| CC2650_GPIO_DOUT31_0_DIO10_POS = 10, |
| CC2650_GPIO_DOUT31_0_DIO11_POS = 11, |
| CC2650_GPIO_DOUT31_0_DIO12_POS = 12, |
| CC2650_GPIO_DOUT31_0_DIO13_POS = 13, |
| CC2650_GPIO_DOUT31_0_DIO14_POS = 14, |
| CC2650_GPIO_DOUT31_0_DIO15_POS = 15, |
| CC2650_GPIO_DOUT31_0_DIO16_POS = 16, |
| CC2650_GPIO_DOUT31_0_DIO17_POS = 17, |
| CC2650_GPIO_DOUT31_0_DIO18_POS = 18, |
| CC2650_GPIO_DOUT31_0_DIO19_POS = 19, |
| CC2650_GPIO_DOUT31_0_DIO20_POS = 20, |
| CC2650_GPIO_DOUT31_0_DIO21_POS = 21, |
| CC2650_GPIO_DOUT31_0_DIO22_POS = 22, |
| CC2650_GPIO_DOUT31_0_DIO23_POS = 23, |
| CC2650_GPIO_DOUT31_0_DIO24_POS = 24, |
| CC2650_GPIO_DOUT31_0_DIO25_POS = 25, |
| CC2650_GPIO_DOUT31_0_DIO26_POS = 26, |
| CC2650_GPIO_DOUT31_0_DIO27_POS = 27, |
| CC2650_GPIO_DOUT31_0_DIO28_POS = 28, |
| CC2650_GPIO_DOUT31_0_DIO29_POS = 29, |
| CC2650_GPIO_DOUT31_0_DIO30_POS = 30, |
| CC2650_GPIO_DOUT31_0_DIO31_POS = 31 |
| }; |
| |
| enum CC2650_GPIO_DOUT31_0_MASK { |
| CC2650_GPIO_DOUT31_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_DOUT31_0_DIO1_MASK = 0x00000002, |
| CC2650_GPIO_DOUT31_0_DIO2_MASK = 0x00000004, |
| CC2650_GPIO_DOUT31_0_DIO3_MASK = 0x00000008, |
| CC2650_GPIO_DOUT31_0_DIO4_MASK = 0x00000010, |
| CC2650_GPIO_DOUT31_0_DIO5_MASK = 0x00000020, |
| CC2650_GPIO_DOUT31_0_DIO6_MASK = 0x00000040, |
| CC2650_GPIO_DOUT31_0_DIO7_MASK = 0x00000080, |
| CC2650_GPIO_DOUT31_0_DIO8_MASK = 0x00000100, |
| CC2650_GPIO_DOUT31_0_DIO9_MASK = 0x00000200, |
| CC2650_GPIO_DOUT31_0_DIO10_MASK = 0x00000400, |
| CC2650_GPIO_DOUT31_0_DIO11_MASK = 0x00000800, |
| CC2650_GPIO_DOUT31_0_DIO12_MASK = 0x00001000, |
| CC2650_GPIO_DOUT31_0_DIO13_MASK = 0x00002000, |
| CC2650_GPIO_DOUT31_0_DIO14_MASK = 0x00004000, |
| CC2650_GPIO_DOUT31_0_DIO15_MASK = 0x00008000, |
| CC2650_GPIO_DOUT31_0_DIO16_MASK = 0x00010000, |
| CC2650_GPIO_DOUT31_0_DIO17_MASK = 0x00020000, |
| CC2650_GPIO_DOUT31_0_DIO18_MASK = 0x00040000, |
| CC2650_GPIO_DOUT31_0_DIO19_MASK = 0x00080000, |
| CC2650_GPIO_DOUT31_0_DIO20_MASK = 0x00100000, |
| CC2650_GPIO_DOUT31_0_DIO21_MASK = 0x00200000, |
| CC2650_GPIO_DOUT31_0_DIO22_MASK = 0x00400000, |
| CC2650_GPIO_DOUT31_0_DIO23_MASK = 0x00800000, |
| CC2650_GPIO_DOUT31_0_DIO24_MASK = 0x01000000, |
| CC2650_GPIO_DOUT31_0_DIO25_MASK = 0x02000000, |
| CC2650_GPIO_DOUT31_0_DIO26_MASK = 0x04000000, |
| CC2650_GPIO_DOUT31_0_DIO27_MASK = 0x08000000, |
| CC2650_GPIO_DOUT31_0_DIO28_MASK = 0x10000000, |
| CC2650_GPIO_DOUT31_0_DIO29_MASK = 0x20000000, |
| CC2650_GPIO_DOUT31_0_DIO30_MASK = 0x40000000, |
| CC2650_GPIO_DOUT31_0_DIO31_MASK = 0x80000000 |
| }; |
| |
| /* DOUTSET31_0 */ |
| enum CC2650_GPIO_DOUTSET31_0_POS { |
| CC2650_GPIO_DOUTSET31_0_DIO0_POS = 0, |
| CC2650_GPIO_DOUTSET31_0_DIO1_POS = 1, |
| CC2650_GPIO_DOUTSET31_0_DIO2_POS = 2, |
| CC2650_GPIO_DOUTSET31_0_DIO3_POS = 3, |
| CC2650_GPIO_DOUTSET31_0_DIO4_POS = 4, |
| CC2650_GPIO_DOUTSET31_0_DIO5_POS = 5, |
| CC2650_GPIO_DOUTSET31_0_DIO6_POS = 6, |
| CC2650_GPIO_DOUTSET31_0_DIO7_POS = 7, |
| CC2650_GPIO_DOUTSET31_0_DIO8_POS = 8, |
| CC2650_GPIO_DOUTSET31_0_DIO9_POS = 9, |
| CC2650_GPIO_DOUTSET31_0_DIO10_POS = 10, |
| CC2650_GPIO_DOUTSET31_0_DIO11_POS = 11, |
| CC2650_GPIO_DOUTSET31_0_DIO12_POS = 12, |
| CC2650_GPIO_DOUTSET31_0_DIO13_POS = 13, |
| CC2650_GPIO_DOUTSET31_0_DIO14_POS = 14, |
| CC2650_GPIO_DOUTSET31_0_DIO15_POS = 15, |
| CC2650_GPIO_DOUTSET31_0_DIO16_POS = 16, |
| CC2650_GPIO_DOUTSET31_0_DIO17_POS = 17, |
| CC2650_GPIO_DOUTSET31_0_DIO18_POS = 18, |
| CC2650_GPIO_DOUTSET31_0_DIO19_POS = 19, |
| CC2650_GPIO_DOUTSET31_0_DIO20_POS = 20, |
| CC2650_GPIO_DOUTSET31_0_DIO21_POS = 21, |
| CC2650_GPIO_DOUTSET31_0_DIO22_POS = 22, |
| CC2650_GPIO_DOUTSET31_0_DIO23_POS = 23, |
| CC2650_GPIO_DOUTSET31_0_DIO24_POS = 24, |
| CC2650_GPIO_DOUTSET31_0_DIO25_POS = 25, |
| CC2650_GPIO_DOUTSET31_0_DIO26_POS = 26, |
| CC2650_GPIO_DOUTSET31_0_DIO27_POS = 27, |
| CC2650_GPIO_DOUTSET31_0_DIO28_POS = 28, |
| CC2650_GPIO_DOUTSET31_0_DIO29_POS = 29, |
| CC2650_GPIO_DOUTSET31_0_DIO30_POS = 30, |
| CC2650_GPIO_DOUTSET31_0_DIO31_POS = 31 |
| }; |
| |
| enum CC2650_GPIO_DOUTSET31_0_MASK { |
| CC2650_GPIO_DOUTSET31_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_DOUTSET31_0_DIO1_MASK = 0x00000002, |
| CC2650_GPIO_DOUTSET31_0_DIO2_MASK = 0x00000004, |
| CC2650_GPIO_DOUTSET31_0_DIO3_MASK = 0x00000008, |
| CC2650_GPIO_DOUTSET31_0_DIO4_MASK = 0x00000010, |
| CC2650_GPIO_DOUTSET31_0_DIO5_MASK = 0x00000020, |
| CC2650_GPIO_DOUTSET31_0_DIO6_MASK = 0x00000040, |
| CC2650_GPIO_DOUTSET31_0_DIO7_MASK = 0x00000080, |
| CC2650_GPIO_DOUTSET31_0_DIO8_MASK = 0x00000100, |
| CC2650_GPIO_DOUTSET31_0_DIO9_MASK = 0x00000200, |
| CC2650_GPIO_DOUTSET31_0_DIO10_MASK = 0x00000400, |
| CC2650_GPIO_DOUTSET31_0_DIO11_MASK = 0x00000800, |
| CC2650_GPIO_DOUTSET31_0_DIO12_MASK = 0x00001000, |
| CC2650_GPIO_DOUTSET31_0_DIO13_MASK = 0x00002000, |
| CC2650_GPIO_DOUTSET31_0_DIO14_MASK = 0x00004000, |
| CC2650_GPIO_DOUTSET31_0_DIO15_MASK = 0x00008000, |
| CC2650_GPIO_DOUTSET31_0_DIO16_MASK = 0x00010000, |
| CC2650_GPIO_DOUTSET31_0_DIO17_MASK = 0x00020000, |
| CC2650_GPIO_DOUTSET31_0_DIO18_MASK = 0x00040000, |
| CC2650_GPIO_DOUTSET31_0_DIO19_MASK = 0x00080000, |
| CC2650_GPIO_DOUTSET31_0_DIO20_MASK = 0x00100000, |
| CC2650_GPIO_DOUTSET31_0_DIO21_MASK = 0x00200000, |
| CC2650_GPIO_DOUTSET31_0_DIO22_MASK = 0x00400000, |
| CC2650_GPIO_DOUTSET31_0_DIO23_MASK = 0x00800000, |
| CC2650_GPIO_DOUTSET31_0_DIO24_MASK = 0x01000000, |
| CC2650_GPIO_DOUTSET31_0_DIO25_MASK = 0x02000000, |
| CC2650_GPIO_DOUTSET31_0_DIO26_MASK = 0x04000000, |
| CC2650_GPIO_DOUTSET31_0_DIO27_MASK = 0x08000000, |
| CC2650_GPIO_DOUTSET31_0_DIO28_MASK = 0x10000000, |
| CC2650_GPIO_DOUTSET31_0_DIO29_MASK = 0x20000000, |
| CC2650_GPIO_DOUTSET31_0_DIO30_MASK = 0x40000000, |
| CC2650_GPIO_DOUTSET31_0_DIO31_MASK = 0x80000000 |
| }; |
| |
| /* DOUTCLR31_0 */ |
| enum CC2650_GPIO_DOUTCLR31_0_POS { |
| CC2650_GPIO_DOUTCLR31_0_DIO0_POS = 0, |
| CC2650_GPIO_DOUTCLR31_0_DIO1_POS = 1, |
| CC2650_GPIO_DOUTCLR31_0_DIO2_POS = 2, |
| CC2650_GPIO_DOUTCLR31_0_DIO3_POS = 3, |
| CC2650_GPIO_DOUTCLR31_0_DIO4_POS = 4, |
| CC2650_GPIO_DOUTCLR31_0_DIO5_POS = 5, |
| CC2650_GPIO_DOUTCLR31_0_DIO6_POS = 6, |
| CC2650_GPIO_DOUTCLR31_0_DIO7_POS = 7, |
| CC2650_GPIO_DOUTCLR31_0_DIO8_POS = 8, |
| CC2650_GPIO_DOUTCLR31_0_DIO9_POS = 9, |
| CC2650_GPIO_DOUTCLR31_0_DIO10_POS = 10, |
| CC2650_GPIO_DOUTCLR31_0_DIO11_POS = 11, |
| CC2650_GPIO_DOUTCLR31_0_DIO12_POS = 12, |
| CC2650_GPIO_DOUTCLR31_0_DIO13_POS = 13, |
| CC2650_GPIO_DOUTCLR31_0_DIO14_POS = 14, |
| CC2650_GPIO_DOUTCLR31_0_DIO15_POS = 15, |
| CC2650_GPIO_DOUTCLR31_0_DIO16_POS = 16, |
| CC2650_GPIO_DOUTCLR31_0_DIO17_POS = 17, |
| CC2650_GPIO_DOUTCLR31_0_DIO18_POS = 18, |
| CC2650_GPIO_DOUTCLR31_0_DIO19_POS = 19, |
| CC2650_GPIO_DOUTCLR31_0_DIO20_POS = 20, |
| CC2650_GPIO_DOUTCLR31_0_DIO21_POS = 21, |
| CC2650_GPIO_DOUTCLR31_0_DIO22_POS = 22, |
| CC2650_GPIO_DOUTCLR31_0_DIO23_POS = 23, |
| CC2650_GPIO_DOUTCLR31_0_DIO24_POS = 24, |
| CC2650_GPIO_DOUTCLR31_0_DIO25_POS = 25, |
| CC2650_GPIO_DOUTCLR31_0_DIO26_POS = 26, |
| CC2650_GPIO_DOUTCLR31_0_DIO27_POS = 27, |
| CC2650_GPIO_DOUTCLR31_0_DIO28_POS = 28, |
| CC2650_GPIO_DOUTCLR31_0_DIO29_POS = 29, |
| CC2650_GPIO_DOUTCLR31_0_DIO30_POS = 30, |
| CC2650_GPIO_DOUTCLR31_0_DIO31_POS = 31 |
| }; |
| |
| enum CC2650_GPIO_DOUTCLR31_0_MASK { |
| CC2650_GPIO_DOUTCLR31_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_DOUTCLR31_0_DIO1_MASK = 0x00000002, |
| CC2650_GPIO_DOUTCLR31_0_DIO2_MASK = 0x00000004, |
| CC2650_GPIO_DOUTCLR31_0_DIO3_MASK = 0x00000008, |
| CC2650_GPIO_DOUTCLR31_0_DIO4_MASK = 0x00000010, |
| CC2650_GPIO_DOUTCLR31_0_DIO5_MASK = 0x00000020, |
| CC2650_GPIO_DOUTCLR31_0_DIO6_MASK = 0x00000040, |
| CC2650_GPIO_DOUTCLR31_0_DIO7_MASK = 0x00000080, |
| CC2650_GPIO_DOUTCLR31_0_DIO8_MASK = 0x00000100, |
| CC2650_GPIO_DOUTCLR31_0_DIO9_MASK = 0x00000200, |
| CC2650_GPIO_DOUTCLR31_0_DIO10_MASK = 0x00000400, |
| CC2650_GPIO_DOUTCLR31_0_DIO11_MASK = 0x00000800, |
| CC2650_GPIO_DOUTCLR31_0_DIO12_MASK = 0x00001000, |
| CC2650_GPIO_DOUTCLR31_0_DIO13_MASK = 0x00002000, |
| CC2650_GPIO_DOUTCLR31_0_DIO14_MASK = 0x00004000, |
| CC2650_GPIO_DOUTCLR31_0_DIO15_MASK = 0x00008000, |
| CC2650_GPIO_DOUTCLR31_0_DIO16_MASK = 0x00010000, |
| CC2650_GPIO_DOUTCLR31_0_DIO17_MASK = 0x00020000, |
| CC2650_GPIO_DOUTCLR31_0_DIO18_MASK = 0x00040000, |
| CC2650_GPIO_DOUTCLR31_0_DIO19_MASK = 0x00080000, |
| CC2650_GPIO_DOUTCLR31_0_DIO20_MASK = 0x00100000, |
| CC2650_GPIO_DOUTCLR31_0_DIO21_MASK = 0x00200000, |
| CC2650_GPIO_DOUTCLR31_0_DIO22_MASK = 0x00400000, |
| CC2650_GPIO_DOUTCLR31_0_DIO23_MASK = 0x00800000, |
| CC2650_GPIO_DOUTCLR31_0_DIO24_MASK = 0x01000000, |
| CC2650_GPIO_DOUTCLR31_0_DIO25_MASK = 0x02000000, |
| CC2650_GPIO_DOUTCLR31_0_DIO26_MASK = 0x04000000, |
| CC2650_GPIO_DOUTCLR31_0_DIO27_MASK = 0x08000000, |
| CC2650_GPIO_DOUTCLR31_0_DIO28_MASK = 0x10000000, |
| CC2650_GPIO_DOUTCLR31_0_DIO29_MASK = 0x20000000, |
| CC2650_GPIO_DOUTCLR31_0_DIO30_MASK = 0x40000000, |
| CC2650_GPIO_DOUTCLR31_0_DIO31_MASK = 0x80000000 |
| }; |
| |
| /* DOUTTGL31_0 */ |
| enum CC2650_GPIO_DOUTTGL31_0_POS { |
| CC2650_GPIO_DOUTTGL31_0_DIO0_POS = 0, |
| CC2650_GPIO_DOUTTGL31_0_DIO1_POS = 1, |
| CC2650_GPIO_DOUTTGL31_0_DIO2_POS = 2, |
| CC2650_GPIO_DOUTTGL31_0_DIO3_POS = 3, |
| CC2650_GPIO_DOUTTGL31_0_DIO4_POS = 4, |
| CC2650_GPIO_DOUTTGL31_0_DIO5_POS = 5, |
| CC2650_GPIO_DOUTTGL31_0_DIO6_POS = 6, |
| CC2650_GPIO_DOUTTGL31_0_DIO7_POS = 7, |
| CC2650_GPIO_DOUTTGL31_0_DIO8_POS = 8, |
| CC2650_GPIO_DOUTTGL31_0_DIO9_POS = 9, |
| CC2650_GPIO_DOUTTGL31_0_DIO10_POS = 10, |
| CC2650_GPIO_DOUTTGL31_0_DIO11_POS = 11, |
| CC2650_GPIO_DOUTTGL31_0_DIO12_POS = 12, |
| CC2650_GPIO_DOUTTGL31_0_DIO13_POS = 13, |
| CC2650_GPIO_DOUTTGL31_0_DIO14_POS = 14, |
| CC2650_GPIO_DOUTTGL31_0_DIO15_POS = 15, |
| CC2650_GPIO_DOUTTGL31_0_DIO16_POS = 16, |
| CC2650_GPIO_DOUTTGL31_0_DIO17_POS = 17, |
| CC2650_GPIO_DOUTTGL31_0_DIO18_POS = 18, |
| CC2650_GPIO_DOUTTGL31_0_DIO19_POS = 19, |
| CC2650_GPIO_DOUTTGL31_0_DIO20_POS = 20, |
| CC2650_GPIO_DOUTTGL31_0_DIO21_POS = 21, |
| CC2650_GPIO_DOUTTGL31_0_DIO22_POS = 22, |
| CC2650_GPIO_DOUTTGL31_0_DIO23_POS = 23, |
| CC2650_GPIO_DOUTTGL31_0_DIO24_POS = 24, |
| CC2650_GPIO_DOUTTGL31_0_DIO25_POS = 25, |
| CC2650_GPIO_DOUTTGL31_0_DIO26_POS = 26, |
| CC2650_GPIO_DOUTTGL31_0_DIO27_POS = 27, |
| CC2650_GPIO_DOUTTGL31_0_DIO28_POS = 28, |
| CC2650_GPIO_DOUTTGL31_0_DIO29_POS = 29, |
| CC2650_GPIO_DOUTTGL31_0_DIO30_POS = 30, |
| CC2650_GPIO_DOUTTGL31_0_DIO31_POS = 31 |
| }; |
| |
| enum CC2650_GPIO_DOUTTGL31_0_MASK { |
| CC2650_GPIO_DOUTTGL31_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_DOUTTGL31_0_DIO1_MASK = 0x00000002, |
| CC2650_GPIO_DOUTTGL31_0_DIO2_MASK = 0x00000004, |
| CC2650_GPIO_DOUTTGL31_0_DIO3_MASK = 0x00000008, |
| CC2650_GPIO_DOUTTGL31_0_DIO4_MASK = 0x00000010, |
| CC2650_GPIO_DOUTTGL31_0_DIO5_MASK = 0x00000020, |
| CC2650_GPIO_DOUTTGL31_0_DIO6_MASK = 0x00000040, |
| CC2650_GPIO_DOUTTGL31_0_DIO7_MASK = 0x00000080, |
| CC2650_GPIO_DOUTTGL31_0_DIO8_MASK = 0x00000100, |
| CC2650_GPIO_DOUTTGL31_0_DIO9_MASK = 0x00000200, |
| CC2650_GPIO_DOUTTGL31_0_DIO10_MASK = 0x00000400, |
| CC2650_GPIO_DOUTTGL31_0_DIO11_MASK = 0x00000800, |
| CC2650_GPIO_DOUTTGL31_0_DIO12_MASK = 0x00001000, |
| CC2650_GPIO_DOUTTGL31_0_DIO13_MASK = 0x00002000, |
| CC2650_GPIO_DOUTTGL31_0_DIO14_MASK = 0x00004000, |
| CC2650_GPIO_DOUTTGL31_0_DIO15_MASK = 0x00008000, |
| CC2650_GPIO_DOUTTGL31_0_DIO16_MASK = 0x00010000, |
| CC2650_GPIO_DOUTTGL31_0_DIO17_MASK = 0x00020000, |
| CC2650_GPIO_DOUTTGL31_0_DIO18_MASK = 0x00040000, |
| CC2650_GPIO_DOUTTGL31_0_DIO19_MASK = 0x00080000, |
| CC2650_GPIO_DOUTTGL31_0_DIO20_MASK = 0x00100000, |
| CC2650_GPIO_DOUTTGL31_0_DIO21_MASK = 0x00200000, |
| CC2650_GPIO_DOUTTGL31_0_DIO22_MASK = 0x00400000, |
| CC2650_GPIO_DOUTTGL31_0_DIO23_MASK = 0x00800000, |
| CC2650_GPIO_DOUTTGL31_0_DIO24_MASK = 0x01000000, |
| CC2650_GPIO_DOUTTGL31_0_DIO25_MASK = 0x02000000, |
| CC2650_GPIO_DOUTTGL31_0_DIO26_MASK = 0x04000000, |
| CC2650_GPIO_DOUTTGL31_0_DIO27_MASK = 0x08000000, |
| CC2650_GPIO_DOUTTGL31_0_DIO28_MASK = 0x10000000, |
| CC2650_GPIO_DOUTTGL31_0_DIO29_MASK = 0x20000000, |
| CC2650_GPIO_DOUTTGL31_0_DIO30_MASK = 0x40000000, |
| CC2650_GPIO_DOUTTGL31_0_DIO31_MASK = 0x80000000 |
| }; |
| |
| /* DIN31_0 */ |
| enum CC2650_GPIO_DIN31_0_POS { |
| CC2650_GPIO_DIN31_0_DIO0_POS = 0, |
| CC2650_GPIO_DIN31_0_DIO1_POS = 1, |
| CC2650_GPIO_DIN31_0_DIO2_POS = 2, |
| CC2650_GPIO_DIN31_0_DIO3_POS = 3, |
| CC2650_GPIO_DIN31_0_DIO4_POS = 4, |
| CC2650_GPIO_DIN31_0_DIO5_POS = 5, |
| CC2650_GPIO_DIN31_0_DIO6_POS = 6, |
| CC2650_GPIO_DIN31_0_DIO7_POS = 7, |
| CC2650_GPIO_DIN31_0_DIO8_POS = 8, |
| CC2650_GPIO_DIN31_0_DIO9_POS = 9, |
| CC2650_GPIO_DIN31_0_DIO10_POS = 10, |
| CC2650_GPIO_DIN31_0_DIO11_POS = 11, |
| CC2650_GPIO_DIN31_0_DIO12_POS = 12, |
| CC2650_GPIO_DIN31_0_DIO13_POS = 13, |
| CC2650_GPIO_DIN31_0_DIO14_POS = 14, |
| CC2650_GPIO_DIN31_0_DIO15_POS = 15, |
| CC2650_GPIO_DIN31_0_DIO16_POS = 16, |
| CC2650_GPIO_DIN31_0_DIO17_POS = 17, |
| CC2650_GPIO_DIN31_0_DIO18_POS = 18, |
| CC2650_GPIO_DIN31_0_DIO19_POS = 19, |
| CC2650_GPIO_DIN31_0_DIO20_POS = 20, |
| CC2650_GPIO_DIN31_0_DIO21_POS = 21, |
| CC2650_GPIO_DIN31_0_DIO22_POS = 22, |
| CC2650_GPIO_DIN31_0_DIO23_POS = 23, |
| CC2650_GPIO_DIN31_0_DIO24_POS = 24, |
| CC2650_GPIO_DIN31_0_DIO25_POS = 25, |
| CC2650_GPIO_DIN31_0_DIO26_POS = 26, |
| CC2650_GPIO_DIN31_0_DIO27_POS = 27, |
| CC2650_GPIO_DIN31_0_DIO28_POS = 28, |
| CC2650_GPIO_DIN31_0_DIO29_POS = 29, |
| CC2650_GPIO_DIN31_0_DIO30_POS = 30, |
| CC2650_GPIO_DIN31_0_DIO31_POS = 31 |
| }; |
| |
| enum CC2650_GPIO_DIN31_0_MASK { |
| CC2650_GPIO_DIN31_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_DIN31_0_DIO1_MASK = 0x00000002, |
| CC2650_GPIO_DIN31_0_DIO2_MASK = 0x00000004, |
| CC2650_GPIO_DIN31_0_DIO3_MASK = 0x00000008, |
| CC2650_GPIO_DIN31_0_DIO4_MASK = 0x00000010, |
| CC2650_GPIO_DIN31_0_DIO5_MASK = 0x00000020, |
| CC2650_GPIO_DIN31_0_DIO6_MASK = 0x00000040, |
| CC2650_GPIO_DIN31_0_DIO7_MASK = 0x00000080, |
| CC2650_GPIO_DIN31_0_DIO8_MASK = 0x00000100, |
| CC2650_GPIO_DIN31_0_DIO9_MASK = 0x00000200, |
| CC2650_GPIO_DIN31_0_DIO10_MASK = 0x00000400, |
| CC2650_GPIO_DIN31_0_DIO11_MASK = 0x00000800, |
| CC2650_GPIO_DIN31_0_DIO12_MASK = 0x00001000, |
| CC2650_GPIO_DIN31_0_DIO13_MASK = 0x00002000, |
| CC2650_GPIO_DIN31_0_DIO14_MASK = 0x00004000, |
| CC2650_GPIO_DIN31_0_DIO15_MASK = 0x00008000, |
| CC2650_GPIO_DIN31_0_DIO16_MASK = 0x00010000, |
| CC2650_GPIO_DIN31_0_DIO17_MASK = 0x00020000, |
| CC2650_GPIO_DIN31_0_DIO18_MASK = 0x00040000, |
| CC2650_GPIO_DIN31_0_DIO19_MASK = 0x00080000, |
| CC2650_GPIO_DIN31_0_DIO20_MASK = 0x00100000, |
| CC2650_GPIO_DIN31_0_DIO21_MASK = 0x00200000, |
| CC2650_GPIO_DIN31_0_DIO22_MASK = 0x00400000, |
| CC2650_GPIO_DIN31_0_DIO23_MASK = 0x00800000, |
| CC2650_GPIO_DIN31_0_DIO24_MASK = 0x01000000, |
| CC2650_GPIO_DIN31_0_DIO25_MASK = 0x02000000, |
| CC2650_GPIO_DIN31_0_DIO26_MASK = 0x04000000, |
| CC2650_GPIO_DIN31_0_DIO27_MASK = 0x08000000, |
| CC2650_GPIO_DIN31_0_DIO28_MASK = 0x10000000, |
| CC2650_GPIO_DIN31_0_DIO29_MASK = 0x20000000, |
| CC2650_GPIO_DIN31_0_DIO30_MASK = 0x40000000, |
| CC2650_GPIO_DIN31_0_DIO31_MASK = 0x80000000 |
| }; |
| |
| /* DOE31_0 */ |
| enum CC2650_GPIO_DOE31_0_POS { |
| CC2650_GPIO_DOE31_0_DIO0_POS = 0, |
| CC2650_GPIO_DOE31_0_DIO1_POS = 1, |
| CC2650_GPIO_DOE31_0_DIO2_POS = 2, |
| CC2650_GPIO_DOE31_0_DIO3_POS = 3, |
| CC2650_GPIO_DOE31_0_DIO4_POS = 4, |
| CC2650_GPIO_DOE31_0_DIO5_POS = 5, |
| CC2650_GPIO_DOE31_0_DIO6_POS = 6, |
| CC2650_GPIO_DOE31_0_DIO7_POS = 7, |
| CC2650_GPIO_DOE31_0_DIO8_POS = 8, |
| CC2650_GPIO_DOE31_0_DIO9_POS = 9, |
| CC2650_GPIO_DOE31_0_DIO10_POS = 10, |
| CC2650_GPIO_DOE31_0_DIO11_POS = 11, |
| CC2650_GPIO_DOE31_0_DIO12_POS = 12, |
| CC2650_GPIO_DOE31_0_DIO13_POS = 13, |
| CC2650_GPIO_DOE31_0_DIO14_POS = 14, |
| CC2650_GPIO_DOE31_0_DIO15_POS = 15, |
| CC2650_GPIO_DOE31_0_DIO16_POS = 16, |
| CC2650_GPIO_DOE31_0_DIO17_POS = 17, |
| CC2650_GPIO_DOE31_0_DIO18_POS = 18, |
| CC2650_GPIO_DOE31_0_DIO19_POS = 19, |
| CC2650_GPIO_DOE31_0_DIO20_POS = 20, |
| CC2650_GPIO_DOE31_0_DIO21_POS = 21, |
| CC2650_GPIO_DOE31_0_DIO22_POS = 22, |
| CC2650_GPIO_DOE31_0_DIO23_POS = 23, |
| CC2650_GPIO_DOE31_0_DIO24_POS = 24, |
| CC2650_GPIO_DOE31_0_DIO25_POS = 25, |
| CC2650_GPIO_DOE31_0_DIO26_POS = 26, |
| CC2650_GPIO_DOE31_0_DIO27_POS = 27, |
| CC2650_GPIO_DOE31_0_DIO28_POS = 28, |
| CC2650_GPIO_DOE31_0_DIO29_POS = 29, |
| CC2650_GPIO_DOE31_0_DIO30_POS = 30, |
| CC2650_GPIO_DOE31_0_DIO31_POS = 31 |
| }; |
| |
| enum CC2650_GPIO_DOE31_0_MASK { |
| CC2650_GPIO_DOE31_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_DOE31_0_DIO1_MASK = 0x00000002, |
| CC2650_GPIO_DOE31_0_DIO2_MASK = 0x00000004, |
| CC2650_GPIO_DOE31_0_DIO3_MASK = 0x00000008, |
| CC2650_GPIO_DOE31_0_DIO4_MASK = 0x00000010, |
| CC2650_GPIO_DOE31_0_DIO5_MASK = 0x00000020, |
| CC2650_GPIO_DOE31_0_DIO6_MASK = 0x00000040, |
| CC2650_GPIO_DOE31_0_DIO7_MASK = 0x00000080, |
| CC2650_GPIO_DOE31_0_DIO8_MASK = 0x00000100, |
| CC2650_GPIO_DOE31_0_DIO9_MASK = 0x00000200, |
| CC2650_GPIO_DOE31_0_DIO10_MASK = 0x00000400, |
| CC2650_GPIO_DOE31_0_DIO11_MASK = 0x00000800, |
| CC2650_GPIO_DOE31_0_DIO12_MASK = 0x00001000, |
| CC2650_GPIO_DOE31_0_DIO13_MASK = 0x00002000, |
| CC2650_GPIO_DOE31_0_DIO14_MASK = 0x00004000, |
| CC2650_GPIO_DOE31_0_DIO15_MASK = 0x00008000, |
| CC2650_GPIO_DOE31_0_DIO16_MASK = 0x00010000, |
| CC2650_GPIO_DOE31_0_DIO17_MASK = 0x00020000, |
| CC2650_GPIO_DOE31_0_DIO18_MASK = 0x00040000, |
| CC2650_GPIO_DOE31_0_DIO19_MASK = 0x00080000, |
| CC2650_GPIO_DOE31_0_DIO20_MASK = 0x00100000, |
| CC2650_GPIO_DOE31_0_DIO21_MASK = 0x00200000, |
| CC2650_GPIO_DOE31_0_DIO22_MASK = 0x00400000, |
| CC2650_GPIO_DOE31_0_DIO23_MASK = 0x00800000, |
| CC2650_GPIO_DOE31_0_DIO24_MASK = 0x01000000, |
| CC2650_GPIO_DOE31_0_DIO25_MASK = 0x02000000, |
| CC2650_GPIO_DOE31_0_DIO26_MASK = 0x04000000, |
| CC2650_GPIO_DOE31_0_DIO27_MASK = 0x08000000, |
| CC2650_GPIO_DOE31_0_DIO28_MASK = 0x10000000, |
| CC2650_GPIO_DOE31_0_DIO29_MASK = 0x20000000, |
| CC2650_GPIO_DOE31_0_DIO30_MASK = 0x40000000, |
| CC2650_GPIO_DOE31_0_DIO31_MASK = 0x80000000 |
| }; |
| |
| /* EVFLAGS31_0 */ |
| enum CC2650_GPIO_EVFLAGS31_0_POS { |
| CC2650_GPIO_EVFLAGS31_0_DIO0_POS = 0, |
| CC2650_GPIO_EVFLAGS31_0_DIO1_POS = 1, |
| CC2650_GPIO_EVFLAGS31_0_DIO2_POS = 2, |
| CC2650_GPIO_EVFLAGS31_0_DIO3_POS = 3, |
| CC2650_GPIO_EVFLAGS31_0_DIO4_POS = 4, |
| CC2650_GPIO_EVFLAGS31_0_DIO5_POS = 5, |
| CC2650_GPIO_EVFLAGS31_0_DIO6_POS = 6, |
| CC2650_GPIO_EVFLAGS31_0_DIO7_POS = 7, |
| CC2650_GPIO_EVFLAGS31_0_DIO8_POS = 8, |
| CC2650_GPIO_EVFLAGS31_0_DIO9_POS = 9, |
| CC2650_GPIO_EVFLAGS31_0_DIO10_POS = 10, |
| CC2650_GPIO_EVFLAGS31_0_DIO11_POS = 11, |
| CC2650_GPIO_EVFLAGS31_0_DIO12_POS = 12, |
| CC2650_GPIO_EVFLAGS31_0_DIO13_POS = 13, |
| CC2650_GPIO_EVFLAGS31_0_DIO14_POS = 14, |
| CC2650_GPIO_EVFLAGS31_0_DIO15_POS = 15, |
| CC2650_GPIO_EVFLAGS31_0_DIO16_POS = 16, |
| CC2650_GPIO_EVFLAGS31_0_DIO17_POS = 17, |
| CC2650_GPIO_EVFLAGS31_0_DIO18_POS = 18, |
| CC2650_GPIO_EVFLAGS31_0_DIO19_POS = 19, |
| CC2650_GPIO_EVFLAGS31_0_DIO20_POS = 20, |
| CC2650_GPIO_EVFLAGS31_0_DIO21_POS = 21, |
| CC2650_GPIO_EVFLAGS31_0_DIO22_POS = 22, |
| CC2650_GPIO_EVFLAGS31_0_DIO23_POS = 23, |
| CC2650_GPIO_EVFLAGS31_0_DIO24_POS = 24, |
| CC2650_GPIO_EVFLAGS31_0_DIO25_POS = 25, |
| CC2650_GPIO_EVFLAGS31_0_DIO26_POS = 26, |
| CC2650_GPIO_EVFLAGS31_0_DIO27_POS = 27, |
| CC2650_GPIO_EVFLAGS31_0_DIO28_POS = 28, |
| CC2650_GPIO_EVFLAGS31_0_DIO29_POS = 29, |
| CC2650_GPIO_EVFLAGS31_0_DIO30_POS = 30, |
| CC2650_GPIO_EVFLAGS31_0_DIO31_POS = 31 |
| }; |
| |
| enum CC2650_GPIO_EVFLAGS31_0_MASK { |
| CC2650_GPIO_EVFLAGS31_0_DIO0_MASK = 0x00000001, |
| CC2650_GPIO_EVFLAGS31_0_DIO1_MASK = 0x00000002, |
| CC2650_GPIO_EVFLAGS31_0_DIO2_MASK = 0x00000004, |
| CC2650_GPIO_EVFLAGS31_0_DIO3_MASK = 0x00000008, |
| CC2650_GPIO_EVFLAGS31_0_DIO4_MASK = 0x00000010, |
| CC2650_GPIO_EVFLAGS31_0_DIO5_MASK = 0x00000020, |
| CC2650_GPIO_EVFLAGS31_0_DIO6_MASK = 0x00000040, |
| CC2650_GPIO_EVFLAGS31_0_DIO7_MASK = 0x00000080, |
| CC2650_GPIO_EVFLAGS31_0_DIO8_MASK = 0x00000100, |
| CC2650_GPIO_EVFLAGS31_0_DIO9_MASK = 0x00000200, |
| CC2650_GPIO_EVFLAGS31_0_DIO10_MASK = 0x00000400, |
| CC2650_GPIO_EVFLAGS31_0_DIO11_MASK = 0x00000800, |
| CC2650_GPIO_EVFLAGS31_0_DIO12_MASK = 0x00001000, |
| CC2650_GPIO_EVFLAGS31_0_DIO13_MASK = 0x00002000, |
| CC2650_GPIO_EVFLAGS31_0_DIO14_MASK = 0x00004000, |
| CC2650_GPIO_EVFLAGS31_0_DIO15_MASK = 0x00008000, |
| CC2650_GPIO_EVFLAGS31_0_DIO16_MASK = 0x00010000, |
| CC2650_GPIO_EVFLAGS31_0_DIO17_MASK = 0x00020000, |
| CC2650_GPIO_EVFLAGS31_0_DIO18_MASK = 0x00040000, |
| CC2650_GPIO_EVFLAGS31_0_DIO19_MASK = 0x00080000, |
| CC2650_GPIO_EVFLAGS31_0_DIO20_MASK = 0x00100000, |
| CC2650_GPIO_EVFLAGS31_0_DIO21_MASK = 0x00200000, |
| CC2650_GPIO_EVFLAGS31_0_DIO22_MASK = 0x00400000, |
| CC2650_GPIO_EVFLAGS31_0_DIO23_MASK = 0x00800000, |
| CC2650_GPIO_EVFLAGS31_0_DIO24_MASK = 0x01000000, |
| CC2650_GPIO_EVFLAGS31_0_DIO25_MASK = 0x02000000, |
| CC2650_GPIO_EVFLAGS31_0_DIO26_MASK = 0x04000000, |
| CC2650_GPIO_EVFLAGS31_0_DIO27_MASK = 0x08000000, |
| CC2650_GPIO_EVFLAGS31_0_DIO28_MASK = 0x10000000, |
| CC2650_GPIO_EVFLAGS31_0_DIO29_MASK = 0x20000000, |
| CC2650_GPIO_EVFLAGS31_0_DIO30_MASK = 0x40000000, |
| CC2650_GPIO_EVFLAGS31_0_DIO31_MASK = 0x80000000 |
| }; |
| |
| #endif /* _CC2650_GPIO_H_ */ |
