commit c959b58bf15659628d2b64b1b38f5a89348d4db4
author Thomas Stranger <thomas.stranger@outlook.com> Tue Jun 28 20:58:05 2022 +0200
committer Carles Cufí <carles.cufi@nordicsemi.no> Mon Jul 04 16:41:24 2022 +0200
tree ee286102f145838ff401df5112a7fb06b34f108a
parent 2801c9969add29d4a632f9d16af45ff2f120d572

drivers/clock_control: stm32 common: enable PLL_P/Q and set PLL_P div

This commit configures the PLL_P divider for SOCs compatible to the
stm32_ll_common driver in case a value was defined via a dts property.

Additionally, in case the divider value is defined in the device
tree, the respective pll output is enabled during initialization
in set_up_plls().

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>

drivers/clock_control/clock_stm32_ll_common.c

diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index 1a17aee..28e2319 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -50,6 +50,9 @@
 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHBPrescaler
 #endif
 
+#define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
+#define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
+
 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
 {
 	return clock / prescaler;
@@ -399,8 +402,13 @@
 	}
 #endif
 
-#if STM32_PLL_Q_ENABLED
+#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
+	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));
+	RCC_PLLP_ENABLE();
+#endif
+#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));
+	RCC_PLLQ_ENABLE();
 #endif
 
 	config_pll_sysclock();