blob: b7b3c9e9d49b3aed8f4d710768ceab8507f35e1e [file] [log] [blame]
/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE frequency differs on available boards, hence:
* This configuration is only available nucleo_h503rb
*/
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(24)>;
};
&pll {
div-m = <6>;
mul-n = <50>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(100)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};