blob: 9dfc07e9b08089326cf08d0396537e6a1f762756 [file] [log] [blame]
/*
* Copyright 2023 NXP
*
* Experimental ENET binding overlay
*/
/ {
soc {
/delete-node/ ethernet@400c0000;
enet: ethernet@400c0000 {
compatible = "nxp,enet";
reg = <0x400c0000 0x620>;
clocks = <&sim KINETIS_SIM_ENET_CLK 0 0>;
enet_mac: ethernet {
compatible = "nxp,enet-mac";
interrupts = <83 0>, <84 0>, <85 0>;
interrupt-names = "TX", "RX", "ERR";
nxp,mdio = <&enet_mdio>;
nxp,ptp-clock = <&enet_ptp_clock>;
phy-connection-type = "rmii";
status = "disabled";
};
enet_mdio: mdio {
compatible = "nxp,enet-mdio";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
enet_ptp_clock: ptp_clock {
compatible = "nxp,enet-ptp-clock";
interrupts = <82 0>;
interrupt-names = "IEEE1588_TMR";
status = "disabled";
};
};
};
};
&enet_mac {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet_mdio>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "microchip,ksz8081";
reg = <0>;
status = "okay";
mc,interface-type = "rmii-25MHz";
};
};
&enet_ptp_clock {
status = "okay";
pinctrl-0 = <&pinmux_ptp>;
pinctrl-names = "default";
};
&pinctrl {
/delete-node/ ptp_default;
/delete-node/ enet_default;
pinmux_enet: pinmux_enet {
group1 {
pinmux = <RMII0_RXER_PTA5>,
<RMII0_RXD1_PTA12>,
<RMII0_RXD0_PTA13>,
<RMII0_CRS_DV_PTA14>,
<RMII0_TXEN_PTA15>,
<RMII0_TXD0_PTA16>,
<RMII0_TXD1_PTA17>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <RMII0_MDIO_PTB0>;
drive-strength = "low";
drive-open-drain;
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <RMII0_MDC_PTB1>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_ptp: pinmux_ptp {
group0 {
pinmux = <ENET0_1588_TMR0_PTC16>,
<ENET0_1588_TMR1_PTC17>,
<ENET0_1588_TMR2_PTC18>;
drive-strength = "low";
slew-rate = "fast";
};
};
};