boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi

/*
 * Copyright 2022-2024 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <nxp/rw/RW612-pinctrl.h>

&pinctrl {
	pinmux_flexcomm3_usart: pinmux_flexcomm3_usart {
		group0 {
			pinmux = <IO_MUX_FC3_USART_DATA>;
			slew-rate = "normal";
		};
	};

	pinmux_flexcomm0_spi: pinmux_flexcomm0_spi {
		group0 {
			pinmux = <IO_MUX_FC0_SPI_SS0_IO0>,
				<IO_MUX_FC0_SPI_SS0_IO2>,
				<IO_MUX_FC0_SPI_SS0_IO3>,
				<IO_MUX_FC0_SPI_SS0_IO4>;
			slew-rate = "ultra";
		};
	};

	pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c {
		group0 {
			pinmux = <IO_MUX_FC2_I2C_16_17>;
			slew-rate = "normal";
			bias-pull-up;
		};
	};

	pinmux_dmic0: pinmux_dmic0 {
		group0 {
			pinmux = <IO_MUX_PDM_IO51
				IO_MUX_PDM_IO52
				IO_MUX_PDM_IO53
				IO_MUX_PDM_IO54>;
			slew-rate = "fast";
		};
	};

	pinmux_flexspi: pinmux_flexspi {
		group0 {
			pinmux = <IO_MUX_QUAD_SPI_FLASH_IO28
				IO_MUX_QUAD_SPI_FLASH_IO30
				IO_MUX_QUAD_SPI_FLASH_IO31
				IO_MUX_QUAD_SPI_FLASH_IO32
				IO_MUX_QUAD_SPI_FLASH_IO33
				IO_MUX_QUAD_SPI_FLASH_IO34>;
			slew-rate = "ultra";
		};

		group1 {
			pinmux = <IO_MUX_QUAD_SPI_FLASH_IO29>;
			slew-rate = "ultra";
			bias-pull-down;
		};
	};
};