blob: 153317fe23c24c9db0e5c4bc6223ba3468d21f53 [file] [log] [blame]
/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm64/armv8-a.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <mem.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <3>;
};
};
gic: interrupt-controller@1410000 {
compatible = "arm,gic-v2", "arm,gic";
reg = <0x01410000 0x10000>, /* GICD */
<0x0142f000 0x1000>; /* GICC */
interrupt-controller;
#interrupt-cells = <4>;
status = "okay";
};
psci: psci {
compatible = "arm,psci-0.2";
method = "smc";
};
sram0: memory@c0000000 {
reg = <0xc0000000 DT_SIZE_M(1)>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 14 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 11 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 10 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
};
uart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550";
reg = <0x21c0600 0x100>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clock-frequency = <350000000>;
reg-shift = <2>;
status = "disabled";
};
};