blob: b17166f22283a20dab8fa380e1c42f84dd3961fa [file] [log] [blame]
# Copyright (C) 2019-2020 Synopsys, Inc.
# SPDX-License-Identifier: Apache-2.0
#
# Configure JTAG cable
# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
# it uses channel B for JTAG, instead of channel A.
adapter driver ftdi
# Only specify FTDI serial number if it is specified via
# "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script
if { [info exists _ZEPHYR_BOARD_SERIAL] } {
adapter serial $_ZEPHYR_BOARD_SERIAL
}
ftdi vid_pid 0x0403 0x6010
ftdi layout_init 0x0088 0x008b
ftdi channel 1
adapter speed 10000
# ARCs supports only JTAG.
transport select jtag
#
# HS Development Kit SoC.
#
# Contains quad-core ARC HS38.
#
source [find cpu/arc/hs.tcl]
set _coreid 0
set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
# OpenOCD is concerned EM and HS are identical.
set _CHIPNAME arc-em
# OpenOCD discovers JTAG TAPs in reverse order.
set _TARGETNAME4 $_CHIPNAME.cpu4
jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
set _TARGETNAME3 $_CHIPNAME.cpu3
jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
set _TARGETNAME2 $_CHIPNAME.cpu2
jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
set _TARGETNAME1 $_CHIPNAME.cpu1
jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
################################
# ARC HS38 core 2
################################
target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2
$_TARGETNAME2 configure -coreid $_coreid
$_TARGETNAME2 configure -dbgbase $_dbgbase
$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs
# Enable L2 cache support for core 2.
$_TARGETNAME2 arc cache l2 auto 1
################################
# ARC HS38 core 3
################################
target create $_TARGETNAME3 arcv2 -chain-position $_TARGETNAME3
$_TARGETNAME3 configure -coreid $_coreid
$_TARGETNAME3 configure -dbgbase $_dbgbase
$_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs
# Enable L2 cache support for core 3.
$_TARGETNAME3 arc cache l2 auto 1
################################
# ARC HS38 core 4
################################
target create $_TARGETNAME4 arcv2 -chain-position $_TARGETNAME4
$_TARGETNAME4 configure -coreid $_coreid
$_TARGETNAME4 configure -dbgbase $_dbgbase
# Flush L2$.
$_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4"
set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs
# Enable L2 cache support for core 4.
$_TARGETNAME4 arc cache l2 auto 1
################################
# ARC HS38 core 1
################################
target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
$_TARGETNAME1 configure -coreid $_coreid
$_TARGETNAME1 configure -dbgbase $_dbgbase
$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
set _coreid [expr {$_coreid + 1}]
set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
arc_hs_init_regs
# Enable L2 cache support for core 1.
$_TARGETNAME1 arc cache l2 auto 1
target smp $_TARGETNAME1 $_TARGETNAME2 $_TARGETNAME3 $_TARGETNAME4
# vi:ft=tcl