boards/xtensa/m5stack_core2/m5stack_mbus_connectors.dtsi

/*
 * Copyright (c) 2023 Martin Kiepfer
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	m5stack_mbus_header: m5stack_mbus_connector {
		compatible = "m5stack,mbus-header";
		#gpio-cells = <2>;
		gpio-map-mask = <0xffffffff 0xffffffc0>;
		gpio-map-pass-thru = <0 0x3f>;
		gpio-map = /* 0 GND */
			   <1 0 &gpio1 4 0>,	/* ADC0 */
			   /* 2 GND */
			   <3 0 &gpio1 5 0>,	/* ADC1 */
			   /* 4  GND */
			   /* 5 RESET */
			   <6 0 &gpio0 23 0>,	/* MOSI */
			   <7 0 &gpio0 25 0>,	/* DAC0 */
			   <8 0 &gpio1 7 0>,	/* MISO */
			   <9 0 &gpio0 26 0>,	/* DAC1 */
			   <10 0 &gpio0 18 0>,	/* SCK */
			   /* 11 3.3V */
			   <12 0 &gpio0 3 0>,	/* RXD0 */
			   <13 0 &gpio0 1 0>,	/* TXD0 */
			   <14 0 &gpio0 13 0>,	/* RXD1 */
			   <15 0 &gpio0 14 0>,	/* TXD1 */
			   <16 0 &gpio0 21 0>,	/* intSDA */
			   <17 0 &gpio0 22 0>,	/* intSCL */
			   <18 0 &gpio1 0 0>,	/* SDA */
			   <19 0 &gpio1 1 0>,	/* SCL */
			   <20 0 &gpio0 27 0>,	/* GPIO */
			   <21 0 &gpio0 19 0>,	/* GPIO */
			   <22 0 &gpio0 2 0>,	/* GPIO */
			   <23 0 &gpio0 0 0>,	/* GPIO */
			   /* 24 NC */
			   <25 0 &gpio1 3 0>;	/* GPIO */
			   /* 26 NC */
			   /* 27 5V */
			   /* 28 NC */
			   /* 29 BAT */
	};
};

m5stack_mbus_i2c0: &i2c0 {};
m5stack_mbus_i2c1: &i2c1 {};
m5stack_mbus_uart0: &uart1 {};
m5stack_mbus_uart1: &uart2 {};
m5stack_mbus_spi: &spi3 {};