drivers/flash/flash_stm32u3x.c

/*
 * Copyright (c) 2021 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#define LOG_DOMAIN flash_stm32u3
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);

#include <soc.h>
#include <stm32_ll_icache.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_system.h>
#include <string.h>
#include <zephyr/cache.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/barrier.h>

#include "flash_stm32.h"

#define BANK2_OFFSET	(KB(CONFIG_FLASH_SIZE) / 2)

/* Macro to check if the flash is Dual bank or not */
#define stm32_flash_has_2_banks(flash_device) \
	((FLASH_STM32_REGS(flash_device)->OPTR & FLASH_STM32_DBANK) == FLASH_STM32_DBANK)

/*
 * offset and len must be aligned on write-block-size for write,
 * positive and not beyond end of flash
 */
bool flash_stm32_valid_range(const struct device *dev, off_t offset,
			     uint32_t len,
			     bool write)
{
	if (write && !flash_stm32_valid_write(offset, len)) {
		return false;
	}

	return flash_stm32_range_exists(dev, offset, len);
}

static int write_nwords(const struct device *dev, off_t offset, const uint32_t *buff, size_t n)
{
	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
	volatile uint32_t *flash = (uint32_t *)(offset
						+ FLASH_STM32_BASE_ADDRESS);
	bool full_zero = true;
	uint32_t tmp;
	int rc;
	int i;

	/* if the non-secure control register is locked,do not fail silently */
	if (regs->CR & FLASH_STM32_NSLOCK) {
		LOG_ERR("NSCR locked");
		return -EIO;
	}

	/* Check that no Flash main memory operation is ongoing */
	rc = flash_stm32_wait_flash_idle(dev);
	if (rc < 0) {
		return rc;
	}

	/* Check if this double/quad word is erased and value isn't 0.
	 *
	 * It is allowed to write only zeros over an already written dword / qword
	 * See 6.3.7 in STM32L5 reference manual.
	 * See 7.3.7 in STM32U5 reference manual.
	 * See 7.3.5 in STM32H5 reference manual.
	 */
	for (i = 0; i < n; i++) {
		if (buff[i] != 0) {
			full_zero = false;
			break;
		}
	}
	if (!full_zero) {
		for (i = 0; i < n; i++) {
			if (flash[i] != 0xFFFFFFFFUL) {
				LOG_ERR("Word at offs %ld not erased", (long)(offset + i));
				return -EIO;
			}
		}
	}

	/* Set the NSPG bit */
	regs->CR |= FLASH_STM32_NSPG;

	/* Flush the register write */
	tmp = regs->CR;

	/* Perform the data write operation at the desired memory address */
	for (i = 0; i < n; i++) {
		flash[i] = buff[i];
	}

	/* Wait until the NSBSY bit is cleared */
	rc = flash_stm32_wait_flash_idle(dev);

	/* Clear the NSPG bit */
	regs->CR &= ~FLASH_STM32_NSPG;

	return rc;
}

static int erase_page(const struct device *dev, unsigned int offset)
{
	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
	uint32_t tmp;
	int rc;
	int page;

	/* if the non-secure control register is locked,do not fail silently */
	if (regs->CR & FLASH_STM32_NSLOCK) {
		LOG_ERR("NSCR locked");
		return -EIO;
	}

	/* Check that no Flash memory operation is ongoing */
	rc = flash_stm32_wait_flash_idle(dev);
	if (rc < 0) {
		return rc;
	}

	if (stm32_flash_has_2_banks(dev)) {
		bool bank_swap;

		/* Check whether bank1/2 are swapped */
		bank_swap = ((regs->OPTR & FLASH_OPTR_SWAP_BANK) == FLASH_OPTR_SWAP_BANK);

		if ((offset < (FLASH_SIZE / 2)) && !bank_swap) {
			/* The pages to be erased is in bank 1 */
			regs->CR &= ~FLASH_STM32_NSBKER_MSK;
			page = offset / FLASH_PAGE_SIZE;
			LOG_DBG("Erase page %d on bank 1", page);
		} else if ((offset >= BANK2_OFFSET) && bank_swap) {
			/* The pages to be erased is in bank 1 */
			regs->CR &= ~FLASH_STM32_NSBKER_MSK;
			page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;
			LOG_DBG("Erase page %d on bank 1", page);
		} else if ((offset < (FLASH_SIZE / 2)) && bank_swap) {
			/* The pages to be erased is in bank 2 */
			regs->CR |= FLASH_STM32_NSBKER;
			page = offset / FLASH_PAGE_SIZE;
			LOG_DBG("Erase page %d on bank 2", page);
		} else if ((offset >= BANK2_OFFSET) && !bank_swap) {
			/* The pages to be erased is in bank 2 */
			regs->CR |= FLASH_STM32_NSBKER;
			page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;
			LOG_DBG("Erase page %d on bank 2", page);
		} else {
			LOG_ERR("Offset %d does not exist", offset);
			return -EINVAL;
		}
	} else {
		/* On 512-Kbyte flash single-bank, set BKER = 0 to select bank 1. */
		if (FLASH_SIZE ==  512 * 1024) {
			regs->CR &= ~FLASH_STM32_NSBKER_MSK;
		}
		page = offset / FLASH_PAGE_SIZE_128_BITS;
		LOG_DBG("Erase page %d", page);
	}

	/* Set the NSPER bit and select the page you wish to erase */
	regs->CR |= FLASH_STM32_NSPER;
	regs->CR &= ~FLASH_STM32_NSPNB_MSK;
	regs->CR |= page << FLASH_STM32_NSPNB_POS;

	/* Set the NSSTRT bit */
	regs->CR |= FLASH_STM32_NSSTRT;

	/* flush the register write */
	tmp = regs->CR;

	/* Wait for the NSBSY bit */
	rc = flash_stm32_wait_flash_idle(dev);

	if (stm32_flash_has_2_banks(dev)) {
		regs->CR &= ~(FLASH_STM32_NSPER | FLASH_STM32_NSBKER);
	} else {
		regs->CR &= ~(FLASH_STM32_NSPER);
	}

	return rc;
}

int flash_stm32_block_erase_loop(const struct device *dev,
				 unsigned int offset,
				 unsigned int len)
{
	unsigned int address = offset;
	int rc = 0;

	/* Disable icache, this will start the invalidation procedure.
	 * All changes(erase/write) to flash memory should happen when
	 * i-cache is disabled. A write to flash performed without
	 * disabling i-cache will set ERRF error flag in SR register.
	 */

	bool cache_enabled = LL_ICACHE_IsEnabled();

	sys_cache_instr_disable();

	/* Prior to erase operation, the voltage range must be set to range 1. */
	uint32_t voltage_scale = LL_PWR_GetRegulVoltageScaling();

	if (voltage_scale != LL_PWR_REGU_VOLTAGE_SCALE1) {
		/* If not, then set the voltage scale 1 */
		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
		while (LL_PWR_GetRegulCurrentVOS() != LL_PWR_REGU_VOLTAGE_SCALE1) {
			/* and wait for the R1RDY flag */
		}
	}

	for (address = offset; address <= offset + len - 1; address += FLASH_PAGE_SIZE) {
		rc = erase_page(dev, address);
		if (rc < 0) {
			break;
		}
	}

	if (cache_enabled) {
		sys_cache_instr_enable();
	}

	/* Restore the voltage scale at its initial range : LL_PWR_REGU_VOLTAGE_SCALE2 */
	if (voltage_scale != LL_PWR_REGU_VOLTAGE_SCALE1) {
		/* If not, then restore the voltage scale */
		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
		while (LL_PWR_GetRegulCurrentVOS() != LL_PWR_REGU_VOLTAGE_SCALE2) {
			/* and wait for the R2RDY flag */
		}
	}

	return rc;
}

int flash_stm32_write_range(const struct device *dev, unsigned int offset,
			    const void *data, unsigned int len)
{
	int i, rc = 0;

	/* Disable icache, this will start the invalidation procedure.
	 * All changes(erase/write) to flash memory should happen when
	 * i-cache is disabled. A write to flash performed without
	 * disabling i-cache will set ERRF error flag in SR register.
	 */

	bool cache_enabled = LL_ICACHE_IsEnabled();

	sys_cache_instr_disable();

	/* Prior to write operation, the voltage range must be set to range 1. */
	uint32_t voltage_scale = LL_PWR_GetRegulVoltageScaling();

	if (voltage_scale != LL_PWR_REGU_VOLTAGE_SCALE1) {
		/* If not, then set the voltage scale 1 */
		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
		while (LL_PWR_GetRegulCurrentVOS() != LL_PWR_REGU_VOLTAGE_SCALE1) {
			/* and wait for the R1RDY flag */
		}
	}

	for (i = 0; i < len; i += FLASH_STM32_WRITE_BLOCK_SIZE) {
		rc = write_nwords(dev, offset + i, ((const uint32_t *)data + (i >> 2)),
				  FLASH_STM32_WRITE_BLOCK_SIZE / 4);
		if (rc < 0) {
			break;
		}
	}

	if (cache_enabled) {
		sys_cache_instr_enable();
	}

	/* Restore the voltage scale at its initial range : LL_PWR_REGU_VOLTAGE_SCALE2 */
	if (voltage_scale != LL_PWR_REGU_VOLTAGE_SCALE1) {
		/* If not, then restore the voltage scale */
		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
		while (LL_PWR_GetRegulCurrentVOS() != LL_PWR_REGU_VOLTAGE_SCALE2) {
			/* and wait for the R2RDY flag */
		}
	}

	return rc;
}

void flash_stm32_page_layout(const struct device *dev,
			     const struct flash_pages_layout **layout,
			     size_t *layout_size)
{
	static struct flash_pages_layout stm32_flash_layout[1];

	if (stm32_flash_layout[0].pages_count == 0) {
		/* Considering one layout of full flash size, even with 2 banks */
		stm32_flash_layout[0].pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
		/* stm32U3 flash pages are always 4 kB in size */
		stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
	}

	*layout = stm32_flash_layout;
	*layout_size = 1;
}

#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)

uint8_t flash_stm32_get_rdp_level(const struct device *dev)
{
	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

	return (regs->OPTR & FLASH_OPTR_RDP_Msk) >> FLASH_OPTR_RDP_Pos;
}

void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
{
	flash_stm32_option_bytes_write(dev, FLASH_OPTR_RDP_Msk,
				       (uint32_t)level << FLASH_OPTR_RDP_Pos);
}
#endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */

int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask, uint32_t value)
{
	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
	int rc;

	if ((regs->OPTR & mask) == value) {
		return 0;
	}

	if (regs->CR & FLASH_CR_OPTLOCK) {
		return -EIO;
	}

	/* Update the target value in the Option Register */
	regs->OPTR = (regs->OPTR & ~mask) | value;
	regs->CR |= FLASH_CR_OPTSTRT;

	/* make sure previous write is completed. */
	barrier_dsync_fence_full();

	rc = flash_stm32_wait_flash_idle(dev);
	if (rc < 0) {
		return rc;
	}

	/* Force the option byte loading (triggers system reset) */
	regs->CR |= FLASH_CR_OBL_LAUNCH;

	return flash_stm32_wait_flash_idle(dev);
}

uint32_t flash_stm32_option_bytes_read(const struct device *dev)
{
	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

	return regs->OPTR;
}