dts/bindings/cpu/riscv-common.yaml

# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0

# Common include file for RISC-V CPUs.

include: cpu.yaml

properties:
  mmu-type:
    description: Memory Management Unit (MMU)
    type: string
    enum:
      - riscv,sv32
      - riscv,sv39
      - riscv,sv48
      - riscv,none

  riscv,isa:
    description: RISC-V instruction set architecture
    type: string
    deprecated: true

  riscv,isa-base:
    description: The base ISA implemented by the hart.
    type: string
    required: true
    enum:
      - rv32i
      - rv32e
      - rv64i
      - rv128i

  riscv,isa-extensions:
    description: |
      Extensions supported by the hart. Take a look at
      https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/extensions.yaml
      and https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
      for a list of possible extensions. Not all options listed there are
      necessarily supported by Zephyr.
    type: string-array
    required: true

  riscv,privilege-modes:
    description: |
      Privilege modes supported by the hart. Each element is one of "m"
      (Machine), "s" (Supervisor), or "u" (User). Used to prevent enabling
      CONFIG_RISCV_S_MODE on harts that do not implement Supervisor mode.
    type: string-array
    default: ["m"]

  riscv,isa-omissions:
    description: |
      Elements of the base ISA expected but not supported by the hart. Currently, the
      only value respected by Zephyr is "fence", to disable use of builtin barrier
      operations.
    type: string-array