| # Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com> |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config RISCV_ISA_RV32I |
| bool |
| help |
| RV32I Base Integer Instruction Set - 32bit |
| |
| config RISCV_ISA_RV32E |
| bool |
| help |
| RV32E Base Integer Instruction Set (Embedded) - 32bit |
| |
| config RISCV_ISA_RV64I |
| bool |
| default y if 64BIT |
| help |
| RV64I Base Integer Instruction Set - 64bit |
| |
| config RISCV_ISA_RV128I |
| bool |
| help |
| RV128I Base Integer Instruction Set - 128bit |
| |
| config RISCV_ISA_EXT_M |
| bool |
| help |
| (M) - Standard Extension for Integer Multiplication and Division |
| |
| Standard integer multiplication and division instruction extension, |
| which is named "M" and contains instructions that multiply or divide |
| values held in two integer registers. |
| |
| config RISCV_ISA_EXT_A |
| bool |
| imply RISCV_ISA_EXT_ZAAMO |
| imply RISCV_ISA_EXT_ZALRSC |
| help |
| (A) - Standard Extension for Atomic Instructions |
| |
| The standard atomic instruction extension is denoted by instruction |
| subset name "A", and contains instructions that atomically |
| read-modify-write memory to support synchronization between multiple |
| RISC-V threads running in the same memory space. |
| |
| config RISCV_ISA_EXT_F |
| bool |
| help |
| (F) - Standard Extension for Single-Precision Floating-Point |
| |
| Standard instruction-set extension for single-precision |
| floating-point, which is named "F" and adds single-precision |
| floating-point computational instructions compliant with the IEEE |
| 754-2008 arithmetic standard. |
| |
| config RISCV_ISA_EXT_D |
| bool |
| depends on RISCV_ISA_EXT_F |
| help |
| (D) - Standard Extension for Double-Precision Floating-Point |
| |
| Standard double-precision floating-point instruction-set extension, |
| which is named "D" and adds double-precision floating-point |
| computational instructions compliant with the IEEE 754-2008 |
| arithmetic standard. |
| |
| config RISCV_ISA_EXT_G |
| bool |
| select RISCV_ISA_EXT_M |
| select RISCV_ISA_EXT_A |
| select RISCV_ISA_EXT_F |
| select RISCV_ISA_EXT_D |
| select RISCV_ISA_EXT_ZICSR |
| select RISCV_ISA_EXT_ZIFENCEI |
| help |
| (IMAFDZicsr_Zifencei) IMAFDZicsr_Zifencei extensions |
| |
| config RISCV_ISA_EXT_Q |
| bool |
| depends on RISCV_ISA_RV64I |
| depends on RISCV_ISA_EXT_F |
| depends on RISCV_ISA_EXT_D |
| help |
| (Q) - Standard Extension for Quad-Precision Floating-Point |
| |
| Standard extension for 128-bit binary floating-point instructions |
| compliant with the IEEE 754-2008 arithmetic standard. The 128-bit or |
| quad-precision binary floatingpoint instruction subset is named "Q". |
| |
| config RISCV_ISA_EXT_C |
| bool |
| select RISCV_ISA_EXT_ZCA |
| select RISCV_ISA_EXT_ZCD if RISCV_ISA_EXT_D |
| select RISCV_ISA_EXT_ZCF if RISCV_ISA_EXT_F && (RISCV_ISA_RV32I || RISCV_ISA_RV32E) |
| help |
| (C) - Standard Extension for Compressed Instructions |
| |
| RISC-V standard compressed instruction set extension, named "C", |
| which reduces static and dynamic code size by adding short 16-bit |
| instruction encodings for common operations. |
| |
| config RISCV_ISA_EXT_ZICNTR |
| bool |
| depends on RISCV_ISA_EXT_ZICSR |
| help |
| (Zicntr) - Standard Extension for Base Counters and Timers |
| |
| The Zicntr standard extension comprises the three counters (CYCLE, TIME, and INSTRET), |
| which have dedicated functions (cycle count, real-time clock and instructions retired, |
| respectively). |
| |
| config RISCV_ISA_EXT_ZICSR |
| bool |
| help |
| (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions |
| |
| The "Zicsr" extension introduces support for the full set of CSR |
| instructions that operate on CSRs registers. |
| |
| config RISCV_ISA_EXT_ZIFENCEI |
| bool |
| help |
| (Zifencei) - Standard Extension for Instruction-Fetch Fence |
| |
| The "Zifencei" extension includes the FENCE.I instruction that |
| provides explicit synchronization between writes to instruction |
| memory and instruction fetches on the same hart. |
| |
| config RISCV_ISA_EXT_ZAAMO |
| bool |
| help |
| (Zaamo) - Atomic memory operation subset of the A extension |
| |
| The Zaamo extension enables support for AMO*.W/D-style instructions. |
| |
| config RISCV_ISA_EXT_ZALRSC |
| bool |
| help |
| (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension |
| |
| The Zalrsc extension enables support for LR.W/D and SC.W/D-style instructions. |
| |
| config RISCV_ISA_EXT_ZCA |
| bool |
| help |
| (Zca) - Zba Extension for Compressed Instructions |
| |
| The Zca extension is a subset of the C extension that does not include |
| the floating-point load and store instructions. |
| |
| config RISCV_ISA_EXT_ZCB |
| bool |
| depends on RISCV_ISA_EXT_ZCA |
| help |
| (Zcb) - Zcb Extension for Simple Compressed Instructions |
| |
| The Zcb extension is a set of simple code-size saving instructions |
| which are easy to implement on all CPUs. |
| |
| config RISCV_ISA_EXT_ZCD |
| bool |
| depends on RISCV_ISA_EXT_D |
| depends on RISCV_ISA_EXT_ZCA |
| help |
| (Zcd) - Zcd Extension for Double-Precision FP Compressed Instructions |
| |
| The Zcd extension consists of compressed double-precision |
| floating-point load and store instructions. |
| |
| config RISCV_ISA_EXT_ZCF |
| bool |
| depends on RISCV_ISA_RV32I || RISCV_ISA_RV32E |
| depends on RISCV_ISA_EXT_F |
| depends on RISCV_ISA_EXT_ZCA |
| help |
| (Zcf) - Zcf Extension for Single-Precision FP Compressed Instructions |
| |
| The Zcf extension consists of compressed single-precision |
| floating-point load and store instructions. |
| |
| config RISCV_ISA_EXT_ZCMP |
| bool |
| depends on RISCV_ISA_EXT_ZCA |
| depends on !RISCV_ISA_EXT_ZCD |
| help |
| (Zcmp) - Zcmp Extension for Complex Compressed Instructions |
| |
| The Zcmp extension consists of complex operations intended for |
| embedded CPUs. |
| |
| config RISCV_ISA_EXT_ZCMT |
| bool |
| depends on RISCV_ISA_EXT_ZICSR |
| depends on RISCV_ISA_EXT_ZCA |
| depends on !RISCV_ISA_EXT_ZCD |
| help |
| (Zcmt) - Zcmt Extension for Compressed Table Jump Instructions |
| |
| The Zcmt extension consists of compressed table jump instructions for |
| embedded CPUs. |
| |
| config RISCV_ISA_EXT_ZBA |
| bool |
| help |
| (Zba) - Zba BitManip Extension |
| |
| The Zba instructions can be used to accelerate the generation of |
| addresses that index into arrays of basic types (halfword, word, |
| doubleword) using both unsigned word-sized and XLEN-sized indices: a |
| shifted index is added to a base address. |
| |
| config RISCV_ISA_EXT_ZBB |
| bool |
| help |
| (Zbb) - Zbb BitManip Extension (Basic bit-manipulation) |
| |
| The Zbb instructions can be used for basic bit-manipulation (logical |
| with negate, count leading / trailing zero bits, count population, |
| etc...). |
| |
| config RISCV_ISA_EXT_ZBC |
| bool |
| help |
| (Zbc) - Zbc BitManip Extension (Carry-less multiplication) |
| |
| The Zbc instructions can be used for carry-less multiplication that |
| is the multiplication in the polynomial ring over GF(2). |
| |
| config RISCV_ISA_EXT_ZBS |
| bool |
| help |
| (Zbs) - Zbs BitManip Extension (Single-bit instructions) |
| |
| The Zbs instructions can be used for single-bit instructions that |
| provide a mechanism to set, clear, invert, or extract a single bit in |
| a register. |
| |
| config RISCV_ISA_EXT_ZMMUL |
| bool |
| help |
| (Zmmul) - Zmmul Extension for Integer Multiplication |
| |
| The Zmmul extension implements the multiplication subset of the M |
| extension. |
