blob: af54b98f71635e5fd30fb8231d4d40a90955d026 [file] [log] [blame]
/*
* Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <freq.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/clock/gd32a50x-clocks.h>
#include <zephyr/dt-bindings/reset/gd32a50x.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-m33f";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
clock-frequency = <DT_FREQ_M(100)>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
soc {
sram0: memory@20000000 {
compatible = "mmio-sram";
};
rcu: reset-clock-controller@40021000 {
compatible = "gd,gd32-rcu";
reg = <0x40021000 0x400>;
status = "okay";
cctl: clock-controller {
compatible = "gd,gd32-cctl";
#clock-cells = <1>;
status = "okay";
};
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40022000 {
compatible = "gd,gd32-flash-controller";
reg = <0x40022000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash";
write-block-size = <4>;
max-erase-time-ms = <2578>;
bank0-page-size = <DT_SIZE_K(1)>;
bank1-page-size = <DT_SIZE_K(1)>;
};
};
usart0: usart@40013800 {
compatible = "gd,gd32-usart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
usart1: usart@40004400 {
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};
usart2: usart@40004800 {
compatible = "gd,gd32-usart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
clocks = <&cctl GD32_CLOCK_USART2>;
resets = <&rctl GD32_RESET_USART2>;
status = "disabled";
};
dac: dac@40007400 {
compatible = "gd,gd32-dac";
reg = <0x40007400 0x400>;
clocks = <&cctl GD32_CLOCK_DAC>;
resets = <&rctl GD32_RESET_DAC>;
num-channels = <1>;
status = "disabled";
#io-channel-cells = <1>;
};
i2c0: i2c@40005400 {
compatible = "gd,gd32-i2c";
reg = <0x40005400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
clocks = <&cctl GD32_CLOCK_I2C0>;
resets = <&rctl GD32_RESET_I2C0>;
status = "disabled";
};
i2c1: i2c@40005800 {
compatible = "gd,gd32-i2c";
reg = <0x40005800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
clocks = <&cctl GD32_CLOCK_I2C1>;
resets = <&rctl GD32_RESET_I2C1>;
status = "disabled";
};
spi0: spi@40013000 {
compatible = "gd,gd32-spi";
reg = <0x40013000 0x400>;
interrupts = <35 0>;
clocks = <&cctl GD32_CLOCK_SPI0>;
resets = <&rctl GD32_RESET_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@40003800 {
compatible = "gd,gd32-spi";
reg = <0x40003800 0x400>;
interrupts = <36 0>;
clocks = <&cctl GD32_CLOCK_SPI1>;
resets = <&rctl GD32_RESET_SPI1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
adc0: adc@40012400 {
compatible = "gd,gd32-adc";
reg = <0x40012400 0x100>;
interrupts = <18 0>;
clocks = <&cctl GD32_CLOCK_ADC0>;
resets = <&rctl GD32_RESET_ADC0>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
};
adc1: adc@40012800 {
compatible = "gd,gd32-adc";
reg = <0x40012800 0x100>;
interrupts = <18 0>;
clocks = <&cctl GD32_CLOCK_ADC1>;
resets = <&rctl GD32_RESET_ADC1>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
};
syscfg: syscfg@40010000 {
compatible = "gd,gd32-syscfg";
reg = <0x40010000 0x400>;
clocks = <&cctl GD32_CLOCK_SYSCFG>;
};
exti: interrupt-controller@40010400 {
compatible = "gd,gd32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40010400 0x400>;
num-lines = <25>;
interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
<10 0>, <41 0>, <40 0>;
interrupt-names = "line0", "line1", "line2", "line3",
"line4", "line5-9", "line10-15";
status = "okay";
};
fwdgt: watchdog@40003000 {
compatible = "gd,gd32-fwdgt";
reg = <0x40003000 0x400>;
status = "disabled";
};
wwdgt: watchdog@40002c00 {
compatible = "gd,gd32-wwdgt";
reg = <0x40002C00 0x400>;
clocks = <&cctl GD32_CLOCK_WWDGT>;
resets = <&rctl GD32_RESET_WWDGT>;
interrupts = <0 0>;
status = "disabled";
};
pinctrl: pin-controller@48000000 {
compatible = "gd,gd32-pinctrl-af";
reg = <0x48000000 0x1800>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
gpioa: gpio@48000000 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000000 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOA>;
resets = <&rctl GD32_RESET_GPIOA>;
status = "disabled";
};
gpiob: gpio@48000400 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000400 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOB>;
resets = <&rctl GD32_RESET_GPIOB>;
status = "disabled";
};
gpioc: gpio@48000800 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000800 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOC>;
resets = <&rctl GD32_RESET_GPIOC>;
status = "disabled";
};
gpiod: gpio@48000c00 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000c00 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOD>;
resets = <&rctl GD32_RESET_GPIOD>;
status = "disabled";
};
gpioe: gpio@48001000 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001000 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOE>;
resets = <&rctl GD32_RESET_GPIOE>;
status = "disabled";
};
gpiof: gpio@48001400 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001400 0x400>;
clocks = <&cctl GD32_CLOCK_GPIOF>;
resets = <&rctl GD32_RESET_GPIOF>;
status = "disabled";
};
};
timer0: timer@40012c00 {
compatible = "gd,gd32-timer";
reg = <0x40012c00 0x400>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
clocks = <&cctl GD32_CLOCK_TIMER0>;
resets = <&rctl GD32_RESET_TIMER0>;
is-advanced;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer1: timer@40000000 {
compatible = "gd,gd32-timer";
reg = <0x40000000 0x400>;
interrupts = <28 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER1>;
resets = <&rctl GD32_RESET_TIMER1>;
is-32bit;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer5: timer@40001000 {
compatible = "gd,gd32-timer";
reg = <0x40001000 0x400>;
interrupts = <54 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER5>;
resets = <&rctl GD32_RESET_TIMER5>;
channels = <0>;
status = "disabled";
};
timer6: timer@40001400 {
compatible = "gd,gd32-timer";
reg = <0x40001400 0x400>;
interrupts = <55 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER6>;
resets = <&rctl GD32_RESET_TIMER6>;
channels = <0>;
status = "disabled";
};
timer7: timer@40013400 {
compatible = "gd,gd32-timer";
reg = <0x40013400 0x400>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
clocks = <&cctl GD32_CLOCK_TIMER7>;
resets = <&rctl GD32_RESET_TIMER7>;
is-advanced;
channels = <4>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer19: timer@40015000 {
compatible = "gd,gd32-timer";
reg = <0x40015000 0x400>;
interrupts = <43 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER19>;
resets = <&rctl GD32_RESET_TIMER19>;
channels = <2>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timer20: timer@40015400 {
compatible = "gd,gd32-timer";
reg = <0x40015400 0x400>;
interrupts = <44 0>;
interrupt-names = "global";
clocks = <&cctl GD32_CLOCK_TIMER20>;
resets = <&rctl GD32_RESET_TIMER20>;
channels = <1>;
status = "disabled";
pwm {
compatible = "gd,gd32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
dma0: dma@40020000 {
compatible = "gd,gd32-dma";
reg = <0x40020000 0x400>;
interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
<15 0>, <16 0>, <17 0>, <47 0>;
clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>;
gd,mem2mem;
#dma-cells = <2>;
status = "disabled";
};
dma1: dma@40020400 {
compatible = "gd,gd32-dma";
reg = <0x40020400 0x400>;
interrupts = <56 0>, <57 0>, <58 0>,
<59 0>, <60 0>;
clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>;
gd,mem2mem;
#dma-cells = <2>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};