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pigweed / third_party / github / zephyrproject-rtos / zephyr / 1066b2fba28e30aabdab637912e9baccc513c39c / . / drivers / counter / Kconfig.stm32_rtc
blob: 562ae1eda66c30079d32cec24a6c9a3e2b25ec0c [file] [log] [blame]
Ulf Magnussonbd6e0442019-11-01 13:45:29 +0100[diff] [blame]1# STM32 Cube LL RTC
2
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]3# Copyright (c) 2018, Linaro Limited
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]4# SPDX-License-Identifier: Apache-2.0
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]5
6menuconfig COUNTER_RTC_STM32
7 bool "STM32 Counter RTC driver"
Kumar Gala0f1ed0f2022-07-21 16:33:07 -0500[diff] [blame]8 default y
9 depends on DT_HAS_ST_STM32_RTC_ENABLED
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]10 select USE_STM32_LL_RTC
11 select USE_STM32_LL_PWR
12 select USE_STM32_LL_RCC
13 select USE_STM32_LL_EXTI
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]14 help
Francois Ramuc098aab2020-07-24 12:31:46 +0200[diff] [blame]15 Build RTC driver for STM32 SoCs.
Francois Ramuc86aefd2020-07-24 11:01:36 +0200[diff] [blame]16 Tested on STM32 F0, F2, F3, F4, L1, L4, F7, G0, G4, H7 series
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]17
Peter Bigot2ffbad42020-10-06 17:09:41 -0500[diff] [blame]18if COUNTER_RTC_STM32
19
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]20choice COUNTER_RTC_STM32_CLOCK_SRC
21 bool "RTC clock source"
22 depends on COUNTER_RTC_STM32
23
24config COUNTER_RTC_STM32_CLOCK_LSI
25 bool "LSI"
26 help
27 Use LSI as RTC clock
28
29config COUNTER_RTC_STM32_CLOCK_LSE
30 bool "LSE"
31 help
32 Use LSE as RTC clock
33
34endchoice #COUNTER_RTC_STM32_CLOCK_SRC
35
36if !SOC_SERIES_STM32F4X
37
38choice COUNTER_RTC_STM32_LSE_DRIVE
39 prompt "LSE oscillator drive capability"
Georgij Cernysiova3ec56c2019-04-12 13:13:02 +0200[diff] [blame]40 depends on COUNTER_RTC_STM32_CLOCK_LSE
Erwan Gouriou458226e2018-11-29 11:08:41 +0100[diff] [blame]41
42config COUNTER_RTC_STM32_LSE_DRIVE_LOW
43 bool "Low"
44 help
45 Xtal mode lower driving capability
46
47config COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMLOW
48 bool "Medium Low"
49 help
50 Xtal mode medium low driving capability
51
52config COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMHIGH
53 bool "Medium High"
54 help
55 Xtal mode medium high driving capability
56
57config COUNTER_RTC_STM32_LSE_DRIVE_HIGH
58 bool "High"
59 help
60 Xtal mode higher driving capability
61
62endchoice
63
64config COUNTER_RTC_STM32_LSE_DRIVE_STRENGTH
65 hex
66 default 0x00000000 if COUNTER_RTC_STM32_LSE_DRIVE_LOW
67 default 0x00000008 if COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMLOW
68 default 0x00000010 if COUNTER_RTC_STM32_LSE_DRIVE_MEDIUMHIGH
69 default 0x00000018 if COUNTER_RTC_STM32_LSE_DRIVE_HIGH
70
Peter Bigot2ffbad42020-10-06 17:09:41 -0500[diff] [blame]71endif # !SOC_SERIES_STM32F4X
Takumi Ando2935e5d2020-03-05 11:20:38 +0900[diff] [blame]72
73config COUNTER_RTC_STM32_LSE_BYPASS
74 bool "LSE oscillator bypass"
75 depends on COUNTER_RTC_STM32_CLOCK_LSE
76 help
77 Enable LSE bypass
Erwin Rol7bf50872019-05-24 10:25:51 +0200[diff] [blame]78
79config COUNTER_RTC_STM32_BACKUP_DOMAIN_RESET
80 bool "Do backup domain reset"
81 default y
82 help
83 Force a backup domain reset on startup
Peter Bigot2ffbad42020-10-06 17:09:41 -0500[diff] [blame]84
Shlomi Vaknin41ca34a2021-03-12 11:24:24 +0200[diff] [blame]85config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS
86 bool "Save rtc time value between resets"
87 default y
88 depends on !COUNTER_RTC_STM32_BACKUP_DOMAIN_RESET
89 help
90 Do not reset the rtc time and date after each reset.
91
Peter Bigot2ffbad42020-10-06 17:09:41 -0500[diff] [blame]92endif # COUNTER_RTC_STM32