Ulf Magnusson | bd6e044 | 2019-11-01 13:45:29 +0100 | [diff] [blame] | 1 | # ARM architecture configuration options |
Juan Manuel Cruz | d15251f | 2015-05-20 11:40:39 -0500 | [diff] [blame] | 2 | |
Juan Manuel Cruz | d15251f | 2015-05-20 11:40:39 -0500 | [diff] [blame] | 3 | # Copyright (c) 2014-2015 Wind River Systems, Inc. |
David B. Kinder | ac74d8b | 2017-01-18 17:01:01 -0800 | [diff] [blame] | 4 | # SPDX-License-Identifier: Apache-2.0 |
Daniel Leung | ef83c14 | 2016-03-15 10:24:36 -0700 | [diff] [blame] | 5 | |
| 6 | menu "ARM Options" |
Anas Nashif | 77ba3c3 | 2015-10-09 06:20:52 -0400 | [diff] [blame] | 7 | depends on ARM |
| 8 | |
| 9 | config ARCH |
| 10 | default "arm" |
Anas Nashif | be26b52 | 2015-08-23 13:08:06 -0400 | [diff] [blame] | 11 | |
Stephanos Ioannidis | 3cf1a91 | 2020-03-31 10:56:32 +0900 | [diff] [blame] | 12 | config CPU_CORTEX |
| 13 | bool |
| 14 | help |
| 15 | This option signifies the use of a CPU of the Cortex family. |
| 16 | |
Stephanos Ioannidis | 2c5ca55 | 2020-02-11 16:21:36 +0900 | [diff] [blame] | 17 | config ARM_CUSTOM_INTERRUPT_CONTROLLER |
| 18 | bool |
Stephanos Ioannidis | 2c5ca55 | 2020-02-11 16:21:36 +0900 | [diff] [blame] | 19 | help |
| 20 | This option indicates that the ARM CPU is connected to a custom (i.e. |
Corey Wharton | 4e5868fa | 2023-09-20 15:19:29 -0700 | [diff] [blame] | 21 | non-GIC or NVIC) interrupt controller. |
Stephanos Ioannidis | 2c5ca55 | 2020-02-11 16:21:36 +0900 | [diff] [blame] | 22 | |
| 23 | A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...) |
| 24 | allow interfacing to a custom external interrupt controller and this |
| 25 | option must be selected when such cores are connected to an interrupt |
Corey Wharton | 4e5868fa | 2023-09-20 15:19:29 -0700 | [diff] [blame] | 26 | controller that is not the ARM Generic Interrupt Controller (GIC) or |
| 27 | the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC). |
Stephanos Ioannidis | 2c5ca55 | 2020-02-11 16:21:36 +0900 | [diff] [blame] | 28 | |
| 29 | When this option is selected, the architecture interrupt control |
| 30 | functions are mapped to the SoC interrupt control interface, which is |
| 31 | implemented at the SoC level. |
| 32 | |
Corey Wharton | 4e5868fa | 2023-09-20 15:19:29 -0700 | [diff] [blame] | 33 | N.B. Since all Cortex-M cores have a NVIC, if this option is selected it |
| 34 | is assumed that the custom interrupt control interface implementation |
| 35 | assumes responsibility for handling the NVIC. |
Stephanos Ioannidis | 2c5ca55 | 2020-02-11 16:21:36 +0900 | [diff] [blame] | 36 | |
Mahesh Mahadevan | 64e973f | 2021-04-28 17:08:37 -0500 | [diff] [blame] | 37 | config CODE_DATA_RELOCATION_SRAM |
| 38 | bool "Relocate code/data sections to SRAM" |
| 39 | depends on CPU_CORTEX_M |
| 40 | select CODE_DATA_RELOCATION |
| 41 | help |
| 42 | When selected this will relocate .text, data and .bss sections from |
| 43 | the specified files and places it in SRAM. The files should be specified |
| 44 | in the CMakeList.txt file with a cmake API zephyr_code_relocate(). This |
| 45 | config is used to create an MPU entry for the SRAM space used for code |
| 46 | relocation. |
| 47 | |
Andrzej Głąbek | 22b17e4 | 2023-02-20 12:07:41 +0100 | [diff] [blame] | 48 | config ARM_ON_ENTER_CPU_IDLE_HOOK |
| 49 | bool |
| 50 | help |
| 51 | Enables a hook (z_arm_on_enter_cpu_idle()) that is called when |
| 52 | the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()). |
| 53 | If needed, this hook can be used to prevent the CPU from actually |
| 54 | entering sleep by skipping the WFE/WFI instruction. |
| 55 | |
Andrzej Kuros | 3d89d58 | 2023-09-26 14:28:36 +0200 | [diff] [blame] | 56 | config ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK |
| 57 | bool |
| 58 | help |
| 59 | Enables a hook (z_arm_on_enter_cpu_idle_prepare()) that is called when |
| 60 | the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()). |
| 61 | If needed, this hook can prepare data to upcoming call to |
| 62 | z_arm_on_enter_cpu_idle(). The z_arm_on_enter_cpu_idle_prepare differs |
| 63 | from z_arm_on_enter_cpu_idle because it is called before interrupts are |
| 64 | disabled. |
| 65 | |
Andrzej Kuros | abd9008 | 2023-07-06 13:32:27 +0200 | [diff] [blame] | 66 | config ARM_ON_EXIT_CPU_IDLE |
| 67 | bool |
| 68 | help |
| 69 | Enables a possibility to inject SoC-specific code just after WFI/WFE |
| 70 | instructions of the cpu idle implementation. |
| 71 | |
| 72 | Enabling this option requires that the SoC provides a soc_cpu_idle.h |
| 73 | header file which defines SOC_ON_EXIT_CPU_IDLE macro guarded by |
| 74 | _ASMLANGUAGE. |
| 75 | |
| 76 | The SOC_ON_EXIT_CPU_IDLE macro is expanded just after |
| 77 | WFI/WFE instructions before any memory access is performed. The purpose |
| 78 | of the SOC_ON_EXIT_CPU_IDLE is to perform an action that mitigate issues |
| 79 | observed on some SoCs caused by a memory access following WFI/WFE |
| 80 | instructions. |
| 81 | |
Huifeng Zhang | df41dea | 2023-07-04 14:21:40 +0800 | [diff] [blame] | 82 | rsource "core/Kconfig" |
| 83 | rsource "core/Kconfig.vfp" |
Stephanos Ioannidis | 3cf1a91 | 2020-03-31 10:56:32 +0900 | [diff] [blame] | 84 | |
Anas Nashif | 98ff441 | 2016-03-14 22:51:58 -0400 | [diff] [blame] | 85 | endmenu |