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Ulf Magnussonbd6e0442019-11-01 13:45:29 +01001# ARM architecture configuration options
Juan Manuel Cruzd15251f2015-05-20 11:40:39 -05002
Juan Manuel Cruzd15251f2015-05-20 11:40:39 -05003# Copyright (c) 2014-2015 Wind River Systems, Inc.
David B. Kinderac74d8b2017-01-18 17:01:01 -08004# SPDX-License-Identifier: Apache-2.0
Daniel Leungef83c142016-03-15 10:24:36 -07005
6menu "ARM Options"
Anas Nashif77ba3c32015-10-09 06:20:52 -04007 depends on ARM
8
9config ARCH
10 default "arm"
Anas Nashifbe26b522015-08-23 13:08:06 -040011
Stephanos Ioannidis3cf1a912020-03-31 10:56:32 +090012config CPU_CORTEX
13 bool
14 help
15 This option signifies the use of a CPU of the Cortex family.
16
Stephanos Ioannidis2c5ca552020-02-11 16:21:36 +090017config ARM_CUSTOM_INTERRUPT_CONTROLLER
18 bool
Stephanos Ioannidis2c5ca552020-02-11 16:21:36 +090019 help
20 This option indicates that the ARM CPU is connected to a custom (i.e.
Corey Wharton4e5868fa2023-09-20 15:19:29 -070021 non-GIC or NVIC) interrupt controller.
Stephanos Ioannidis2c5ca552020-02-11 16:21:36 +090022
23 A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
24 allow interfacing to a custom external interrupt controller and this
25 option must be selected when such cores are connected to an interrupt
Corey Wharton4e5868fa2023-09-20 15:19:29 -070026 controller that is not the ARM Generic Interrupt Controller (GIC) or
27 the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC).
Stephanos Ioannidis2c5ca552020-02-11 16:21:36 +090028
29 When this option is selected, the architecture interrupt control
30 functions are mapped to the SoC interrupt control interface, which is
31 implemented at the SoC level.
32
Corey Wharton4e5868fa2023-09-20 15:19:29 -070033 N.B. Since all Cortex-M cores have a NVIC, if this option is selected it
34 is assumed that the custom interrupt control interface implementation
35 assumes responsibility for handling the NVIC.
Stephanos Ioannidis2c5ca552020-02-11 16:21:36 +090036
Mahesh Mahadevan64e973f2021-04-28 17:08:37 -050037config CODE_DATA_RELOCATION_SRAM
38 bool "Relocate code/data sections to SRAM"
39 depends on CPU_CORTEX_M
40 select CODE_DATA_RELOCATION
41 help
42 When selected this will relocate .text, data and .bss sections from
43 the specified files and places it in SRAM. The files should be specified
44 in the CMakeList.txt file with a cmake API zephyr_code_relocate(). This
45 config is used to create an MPU entry for the SRAM space used for code
46 relocation.
47
Andrzej Głąbek22b17e42023-02-20 12:07:41 +010048config ARM_ON_ENTER_CPU_IDLE_HOOK
49 bool
50 help
51 Enables a hook (z_arm_on_enter_cpu_idle()) that is called when
52 the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
53 If needed, this hook can be used to prevent the CPU from actually
54 entering sleep by skipping the WFE/WFI instruction.
55
Andrzej Kuros3d89d582023-09-26 14:28:36 +020056config ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
57 bool
58 help
59 Enables a hook (z_arm_on_enter_cpu_idle_prepare()) that is called when
60 the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
61 If needed, this hook can prepare data to upcoming call to
62 z_arm_on_enter_cpu_idle(). The z_arm_on_enter_cpu_idle_prepare differs
63 from z_arm_on_enter_cpu_idle because it is called before interrupts are
64 disabled.
65
Andrzej Kurosabd90082023-07-06 13:32:27 +020066config ARM_ON_EXIT_CPU_IDLE
67 bool
68 help
69 Enables a possibility to inject SoC-specific code just after WFI/WFE
70 instructions of the cpu idle implementation.
71
72 Enabling this option requires that the SoC provides a soc_cpu_idle.h
73 header file which defines SOC_ON_EXIT_CPU_IDLE macro guarded by
74 _ASMLANGUAGE.
75
76 The SOC_ON_EXIT_CPU_IDLE macro is expanded just after
77 WFI/WFE instructions before any memory access is performed. The purpose
78 of the SOC_ON_EXIT_CPU_IDLE is to perform an action that mitigate issues
79 observed on some SoCs caused by a memory access following WFI/WFE
80 instructions.
81
Huifeng Zhangdf41dea2023-07-04 14:21:40 +080082rsource "core/Kconfig"
83rsource "core/Kconfig.vfp"
Stephanos Ioannidis3cf1a912020-03-31 10:56:32 +090084
Anas Nashif98ff4412016-03-14 22:51:58 -040085endmenu