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Jay Vasanthc214c592021-10-18 16:44:45 -04001/*
2 * Copyright (c) 2021 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_DRIVERS_ESPI_MCHP_XEC_ESPI_V2_H_
8#define ZEPHYR_DRIVERS_ESPI_MCHP_XEC_ESPI_V2_H_
9
10#include <stdint.h>
Gerard Marull-Paretasfb60aab2022-05-06 10:25:46 +020011#include <zephyr/device.h>
12#include <zephyr/drivers/espi.h>
13#include <zephyr/drivers/pinctrl.h>
Jay Vasanthc214c592021-10-18 16:44:45 -040014
Jay Vasanthf6619a82022-12-12 17:56:06 -050015/* #define ESPI_XEC_V2_DEBUG 1 */
Jay Vasanthc214c592021-10-18 16:44:45 -040016
17struct espi_isr {
18 uint8_t girq_id;
19 uint8_t girq_pos;
20 void (*the_isr)(const struct device *dev);
21};
22
23struct espi_vw_isr {
24 uint8_t signal;
25 uint8_t girq_id;
26 uint8_t girq_pos;
27 void (*the_isr)(int girq, int bpos, void *dev);
28};
29
30struct espi_xec_irq_info {
31 uint8_t gid; /* GIRQ id [8, 26] */
32 uint8_t gpos; /* bit position in GIRQ [0, 31] */
33 uint8_t anid; /* Aggregated GIRQ NVIC number */
34 uint8_t dnid; /* Direct GIRQ NVIC number */
35};
36
37struct espi_xec_config {
38 uint32_t base_addr;
39 uint32_t vw_base_addr;
40 uint8_t pcr_idx;
41 uint8_t pcr_bitpos;
Jay Vasanthc214c592021-10-18 16:44:45 -040042 uint8_t irq_info_size;
Jay Vasanthf8130d52022-01-21 12:15:27 -050043 uint8_t rsvd[1];
44 const struct espi_xec_irq_info *irq_info_list;
45 const struct pinctrl_dev_config *pcfg;
Jay Vasanthc214c592021-10-18 16:44:45 -040046};
47
48#define ESPI_XEC_CONFIG(dev) \
49 ((struct espi_xec_config * const)(dev)->config)
50
51struct espi_xec_data {
52 sys_slist_t callbacks;
53 struct k_sem tx_lock;
54 struct k_sem rx_lock;
55 struct k_sem flash_lock;
Jay Vasanthc214c592021-10-18 16:44:45 -040056#ifdef ESPI_XEC_V2_DEBUG
57 uint32_t espi_rst_count;
58#endif
59};
60
61#define ESPI_XEC_DATA(dev) \
62 ((struct espi_xec_data * const)(dev)->data)
63
64struct xec_signal {
Jay Vasanthf6619a82022-12-12 17:56:06 -050065 uint8_t host_idx;
Jay Vasanthc214c592021-10-18 16:44:45 -040066 uint8_t bit;
Jay Vasanthf6619a82022-12-12 17:56:06 -050067 uint8_t xec_reg_idx;
68 uint8_t flags;
Jay Vasanthc214c592021-10-18 16:44:45 -040069};
70
71enum mchp_msvw_regs {
72 MCHP_MSVW00,
73 MCHP_MSVW01,
74 MCHP_MSVW02,
75 MCHP_MSVW03,
76 MCHP_MSVW04,
77 MCHP_MSVW05,
78 MCHP_MSVW06,
79 MCHP_MSVW07,
80 MCHP_MSVW08,
81};
82
83enum mchp_smvw_regs {
84 MCHP_SMVW00,
85 MCHP_SMVW01,
86 MCHP_SMVW02,
87 MCHP_SMVW03,
88 MCHP_SMVW04,
89 MCHP_SMVW05,
90 MCHP_SMVW06,
91 MCHP_SMVW07,
92 MCHP_SMVW08,
93};
94
95enum xec_espi_girq_idx {
96 pc_girq_idx = 0,
97 bm1_girq_idx,
98 bm2_girq_idx,
99 ltr_girq_idx,
100 oob_up_girq_idx,
101 oob_dn_girq_idx,
102 fc_girq_idx,
103 rst_girq_idx,
104 vw_ch_en_girq_idx,
105 max_girq_idx,
106};
107
Jay Vasanthc214c592021-10-18 16:44:45 -0400108int xec_host_dev_init(const struct device *dev);
109int xec_host_dev_connect_irqs(const struct device *dev);
110
111int espi_xec_read_lpc_request(const struct device *dev,
112 enum lpc_peripheral_opcode op,
113 uint32_t *data);
114
115int espi_xec_write_lpc_request(const struct device *dev,
116 enum lpc_peripheral_opcode op,
117 uint32_t *data);
118
119#endif /* ZEPHYR_DRIVERS_ESPI_MCHP_XEC_ESPI_V2_H_ */