blob: 74c13812239354d96ded4abbb12eaea47afc672f [file] [log] [blame]
Karsten Koenigee2dd732019-08-07 17:13:35 +02001/*
2 * Copyright (c) 2018, NXP
3 *
4 * Forked off the spi_mcux_lpi2c driver.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
Kumar Gala8c60bc02020-04-02 15:15:38 -05009#define DT_DRV_COMPAT openisa_rv32m1_lpspi
10
Karsten Koenigee2dd732019-08-07 17:13:35 +020011#include <errno.h>
Gerard Marull-Paretasfb60aab2022-05-06 10:25:46 +020012#include <zephyr/drivers/spi.h>
13#include <zephyr/drivers/clock_control.h>
Karsten Koenigee2dd732019-08-07 17:13:35 +020014#include <fsl_lpspi.h>
Henrik Brix Andersenc83a0d52022-05-01 22:32:33 +020015#ifdef CONFIG_PINCTRL
Gerard Marull-Paretasfb60aab2022-05-06 10:25:46 +020016#include <zephyr/drivers/pinctrl.h>
Henrik Brix Andersenc83a0d52022-05-01 22:32:33 +020017#endif
Karsten Koenigee2dd732019-08-07 17:13:35 +020018
19#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
Gerard Marull-Paretasfb60aab2022-05-06 10:25:46 +020020#include <zephyr/logging/log.h>
Karsten Koenigee2dd732019-08-07 17:13:35 +020021LOG_MODULE_REGISTER(spi_rv32m1_lpspi);
22
23#include "spi_context.h"
24
25#define CHIP_SELECT_COUNT 4
26#define MAX_DATA_WIDTH 4096
27
28struct spi_mcux_config {
29 LPSPI_Type *base;
Kumar Gala3a8fffb2021-02-11 18:05:31 -060030 const struct device *clock_dev;
Karsten Koenigee2dd732019-08-07 17:13:35 +020031 clock_control_subsys_t clock_subsys;
32 clock_ip_name_t clock_ip_name;
Kumar Galaa1b77fd2020-05-27 11:26:57 -050033 uint32_t clock_ip_src;
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +020034 void (*irq_config_func)(const struct device *dev);
Henrik Brix Andersenc83a0d52022-05-01 22:32:33 +020035#ifdef CONFIG_PINCTRL
36 const struct pinctrl_dev_config *pincfg;
37#endif
Karsten Koenigee2dd732019-08-07 17:13:35 +020038};
39
40struct spi_mcux_data {
Tomasz Bursztyka898f9142020-07-08 10:57:21 +020041 const struct device *dev;
Karsten Koenigee2dd732019-08-07 17:13:35 +020042 lpspi_master_handle_t handle;
43 struct spi_context ctx;
44 size_t transfer_len;
45};
46
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +020047static void spi_mcux_transfer_next_packet(const struct device *dev)
Karsten Koenigee2dd732019-08-07 17:13:35 +020048{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +020049 const struct spi_mcux_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +020050 struct spi_mcux_data *data = dev->data;
Karsten Koenigee2dd732019-08-07 17:13:35 +020051 LPSPI_Type *base = config->base;
52 struct spi_context *ctx = &data->ctx;
53 lpspi_transfer_t transfer;
54 status_t status;
55
56 if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) {
57 /* nothing left to rx or tx, we're done! */
58 spi_context_cs_control(&data->ctx, false);
59 spi_context_complete(&data->ctx, 0);
60 return;
61 }
62
63 transfer.configFlags = kLPSPI_MasterPcsContinuous |
64 (ctx->config->slave << LPSPI_MASTER_PCS_SHIFT);
65
66 if (ctx->tx_len == 0) {
67 /* rx only, nothing to tx */
68 transfer.txData = NULL;
69 transfer.rxData = ctx->rx_buf;
70 transfer.dataSize = ctx->rx_len;
71 } else if (ctx->rx_len == 0) {
72 /* tx only, nothing to rx */
Kumar Galaa1b77fd2020-05-27 11:26:57 -050073 transfer.txData = (uint8_t *) ctx->tx_buf;
Karsten Koenigee2dd732019-08-07 17:13:35 +020074 transfer.rxData = NULL;
75 transfer.dataSize = ctx->tx_len;
76 } else if (ctx->tx_len == ctx->rx_len) {
77 /* rx and tx are the same length */
Kumar Galaa1b77fd2020-05-27 11:26:57 -050078 transfer.txData = (uint8_t *) ctx->tx_buf;
Karsten Koenigee2dd732019-08-07 17:13:35 +020079 transfer.rxData = ctx->rx_buf;
80 transfer.dataSize = ctx->tx_len;
81 } else if (ctx->tx_len > ctx->rx_len) {
82 /* Break up the tx into multiple transfers so we don't have to
83 * rx into a longer intermediate buffer. Leave chip select
84 * active between transfers.
85 */
Kumar Galaa1b77fd2020-05-27 11:26:57 -050086 transfer.txData = (uint8_t *) ctx->tx_buf;
Karsten Koenigee2dd732019-08-07 17:13:35 +020087 transfer.rxData = ctx->rx_buf;
88 transfer.dataSize = ctx->rx_len;
89 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
90 } else {
91 /* Break up the rx into multiple transfers so we don't have to
92 * tx from a longer intermediate buffer. Leave chip select
93 * active between transfers.
94 */
Kumar Galaa1b77fd2020-05-27 11:26:57 -050095 transfer.txData = (uint8_t *) ctx->tx_buf;
Karsten Koenigee2dd732019-08-07 17:13:35 +020096 transfer.rxData = ctx->rx_buf;
97 transfer.dataSize = ctx->tx_len;
98 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
99 }
100
101 if (!(ctx->tx_count <= 1 && ctx->rx_count <= 1)) {
102 transfer.configFlags |= kLPSPI_MasterPcsContinuous;
103 }
104
105 data->transfer_len = transfer.dataSize;
106 status = LPSPI_MasterTransferNonBlocking(base, &data->handle,
107 &transfer);
108 if (status != kStatus_Success) {
109 LOG_ERR("Transfer could not start");
110 }
111}
112
Tomasz Bursztyka4dcfb552020-06-17 14:58:56 +0200113static void spi_mcux_isr(const struct device *dev)
Karsten Koenigee2dd732019-08-07 17:13:35 +0200114{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +0200115 const struct spi_mcux_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200116 struct spi_mcux_data *data = dev->data;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200117 LPSPI_Type *base = config->base;
118
119 LPSPI_MasterTransferHandleIRQ(base, &data->handle);
120}
121
122static void spi_mcux_master_transfer_callback(LPSPI_Type *base,
Tomasz Bursztyka898f9142020-07-08 10:57:21 +0200123 lpspi_master_handle_t *handle,
124 status_t status, void *userData)
Karsten Koenigee2dd732019-08-07 17:13:35 +0200125{
Tomasz Bursztyka898f9142020-07-08 10:57:21 +0200126 struct spi_mcux_data *data = userData;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200127
128 spi_context_update_tx(&data->ctx, 1, data->transfer_len);
129 spi_context_update_rx(&data->ctx, 1, data->transfer_len);
130
Tomasz Bursztyka898f9142020-07-08 10:57:21 +0200131 spi_mcux_transfer_next_packet(data->dev);
Karsten Koenigee2dd732019-08-07 17:13:35 +0200132}
133
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200134static int spi_mcux_configure(const struct device *dev,
Karsten Koenigee2dd732019-08-07 17:13:35 +0200135 const struct spi_config *spi_cfg)
136{
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +0200137 const struct spi_mcux_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200138 struct spi_mcux_data *data = dev->data;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200139 LPSPI_Type *base = config->base;
140 lpspi_master_config_t master_config;
Kumar Galaa1b77fd2020-05-27 11:26:57 -0500141 uint32_t clock_freq;
142 uint32_t word_size;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200143
144 if (spi_context_configured(&data->ctx, spi_cfg)) {
145 /* This configuration is already in use */
146 return 0;
147 }
148
Tomasz Bursztyka01b98132021-09-09 16:16:59 +0200149 if (spi_cfg->operation & SPI_HALF_DUPLEX) {
150 LOG_ERR("Half-duplex not supported");
151 return -ENOTSUP;
152 }
153
Karsten Koenigee2dd732019-08-07 17:13:35 +0200154 LPSPI_MasterGetDefaultConfig(&master_config);
155
156 if (spi_cfg->slave > CHIP_SELECT_COUNT) {
157 LOG_ERR("Slave %d is greater than %d",
158 spi_cfg->slave,
159 CHIP_SELECT_COUNT);
160 return -EINVAL;
161 }
162
163 word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
164 if (word_size > MAX_DATA_WIDTH) {
165 LOG_ERR("Word size %d is greater than %d",
166 word_size, MAX_DATA_WIDTH);
167 return -EINVAL;
168 }
169
170 master_config.bitsPerFrame = word_size;
171
172 master_config.cpol =
173 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
174 ? kLPSPI_ClockPolarityActiveLow
175 : kLPSPI_ClockPolarityActiveHigh;
176
177 master_config.cpha =
178 (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
179 ? kLPSPI_ClockPhaseSecondEdge
180 : kLPSPI_ClockPhaseFirstEdge;
181
182 master_config.direction =
183 (spi_cfg->operation & SPI_TRANSFER_LSB)
184 ? kLPSPI_LsbFirst
185 : kLPSPI_MsbFirst;
186
187 master_config.baudRate = spi_cfg->frequency;
188
Kumar Gala3a8fffb2021-02-11 18:05:31 -0600189 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
Karsten Koenigee2dd732019-08-07 17:13:35 +0200190 &clock_freq)) {
191 return -EINVAL;
192 }
193
194 LPSPI_MasterInit(base, &master_config, clock_freq);
195
196 LPSPI_MasterTransferCreateHandle(base, &data->handle,
Tomasz Bursztyka898f9142020-07-08 10:57:21 +0200197 spi_mcux_master_transfer_callback,
198 data);
Karsten Koenigee2dd732019-08-07 17:13:35 +0200199
Karsten Koenig189ae8c2020-06-10 18:36:15 +0200200 LPSPI_SetDummyData(base, 0);
201
Karsten Koenigee2dd732019-08-07 17:13:35 +0200202 data->ctx.config = spi_cfg;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200203
204 return 0;
205}
206
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200207static int transceive(const struct device *dev,
Karsten Koenigee2dd732019-08-07 17:13:35 +0200208 const struct spi_config *spi_cfg,
209 const struct spi_buf_set *tx_bufs,
210 const struct spi_buf_set *rx_bufs,
211 bool asynchronous,
212 struct k_poll_signal *signal)
213{
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200214 struct spi_mcux_data *data = dev->data;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200215 int ret;
216
Stefan Bigler596cad82020-10-19 08:52:29 +0200217 spi_context_lock(&data->ctx, asynchronous, signal, spi_cfg);
Karsten Koenigee2dd732019-08-07 17:13:35 +0200218
219 ret = spi_mcux_configure(dev, spi_cfg);
220 if (ret) {
221 goto out;
222 }
223
224 spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
225
226 spi_context_cs_control(&data->ctx, true);
227
228 spi_mcux_transfer_next_packet(dev);
229
230 ret = spi_context_wait_for_completion(&data->ctx);
231out:
232 spi_context_release(&data->ctx, ret);
233
234 return ret;
235}
236
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200237static int spi_mcux_transceive(const struct device *dev,
Karsten Koenigee2dd732019-08-07 17:13:35 +0200238 const struct spi_config *spi_cfg,
239 const struct spi_buf_set *tx_bufs,
240 const struct spi_buf_set *rx_bufs)
241{
242 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL);
243}
244
245#ifdef CONFIG_SPI_ASYNC
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200246static int spi_mcux_transceive_async(const struct device *dev,
Karsten Koenigee2dd732019-08-07 17:13:35 +0200247 const struct spi_config *spi_cfg,
248 const struct spi_buf_set *tx_bufs,
249 const struct spi_buf_set *rx_bufs,
250 struct k_poll_signal *async)
251{
252 return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, async);
253}
254#endif /* CONFIG_SPI_ASYNC */
255
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200256static int spi_mcux_release(const struct device *dev,
257 const struct spi_config *spi_cfg)
Karsten Koenigee2dd732019-08-07 17:13:35 +0200258{
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200259 struct spi_mcux_data *data = dev->data;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200260
261 spi_context_unlock_unconditionally(&data->ctx);
262
263 return 0;
264}
265
Tomasz Bursztykae18fcbb2020-04-30 20:33:38 +0200266static int spi_mcux_init(const struct device *dev)
Karsten Koenigee2dd732019-08-07 17:13:35 +0200267{
Bartosz Bilas05f326c2021-10-07 17:08:26 +0200268 int err;
Tomasz Bursztykaaf6140c2020-05-28 20:44:16 +0200269 const struct spi_mcux_config *config = dev->config;
Tomasz Bursztyka98d9b012020-05-28 21:23:02 +0200270 struct spi_mcux_data *data = dev->data;
Karsten Koenigee2dd732019-08-07 17:13:35 +0200271
272 CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
273
274 config->irq_config_func(dev);
275
Tomasz Bursztyka898f9142020-07-08 10:57:21 +0200276 data->dev = dev;
277
Bartosz Bilas05f326c2021-10-07 17:08:26 +0200278 err = spi_context_cs_configure_all(&data->ctx);
279 if (err < 0) {
280 return err;
281 }
282
Henrik Brix Andersenc83a0d52022-05-01 22:32:33 +0200283#ifdef CONFIG_PINCTRL
284 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
285 if (err != 0) {
286 return err;
287 }
288#endif
289
Karsten Koenigee2dd732019-08-07 17:13:35 +0200290 spi_context_unlock_unconditionally(&data->ctx);
291
292 return 0;
293}
294
295static const struct spi_driver_api spi_mcux_driver_api = {
296 .transceive = spi_mcux_transceive,
297#ifdef CONFIG_SPI_ASYNC
298 .transceive_async = spi_mcux_transceive_async,
299#endif
300 .release = spi_mcux_release,
301};
302
Henrik Brix Andersenc83a0d52022-05-01 22:32:33 +0200303#ifdef CONFIG_PINCTRL
304#define PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
305#define PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n);
306#else
307#define PINCTRL_DEFINE(n)
308#define PINCTRL_INIT(n)
309#endif
310
Kumar Gala8c60bc02020-04-02 15:15:38 -0500311#define SPI_RV32M1_INIT(n) \
Henrik Brix Andersenc83a0d52022-05-01 22:32:33 +0200312 PINCTRL_DEFINE(n) \
313 \
Tomasz Bursztykaef560e02020-07-14 17:02:00 +0200314 static void spi_mcux_config_func_##n(const struct device *dev); \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500315 \
316 static const struct spi_mcux_config spi_mcux_config_##n = { \
317 .base = (LPSPI_Type *) DT_INST_REG_ADDR(n), \
Kumar Gala3a8fffb2021-02-11 18:05:31 -0600318 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500319 .clock_subsys = (clock_control_subsys_t) \
320 DT_INST_CLOCKS_CELL(n, name), \
321 .irq_config_func = spi_mcux_config_func_##n, \
322 .clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
323 .clock_ip_src = kCLOCK_IpSrcFircAsync, \
Henrik Brix Andersenc83a0d52022-05-01 22:32:33 +0200324 PINCTRL_INIT(n) \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500325 }; \
326 \
327 static struct spi_mcux_data spi_mcux_data_##n = { \
328 SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx), \
329 SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx), \
Bartosz Bilas05f326c2021-10-07 17:08:26 +0200330 SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500331 }; \
332 \
Gerard Marull-Paretas90118b22021-04-28 12:04:51 +0200333 DEVICE_DT_INST_DEFINE(n, &spi_mcux_init, NULL, \
Kumar Gala03ad31b2020-12-09 12:32:41 -0600334 &spi_mcux_data_##n, \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500335 &spi_mcux_config_##n, \
336 POST_KERNEL, \
Bartosz Bilasea25b922021-10-27 20:33:15 +0200337 CONFIG_SPI_INIT_PRIORITY, \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500338 &spi_mcux_driver_api); \
339 \
Tomasz Bursztykaef560e02020-07-14 17:02:00 +0200340 static void spi_mcux_config_func_##n(const struct device *dev) \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500341 { \
342 IRQ_CONNECT(DT_INST_IRQN(n), \
343 0, \
Kumar Gala03ad31b2020-12-09 12:32:41 -0600344 spi_mcux_isr, DEVICE_DT_INST_GET(n), 0); \
Kumar Gala8c60bc02020-04-02 15:15:38 -0500345 irq_enable(DT_INST_IRQN(n)); \
346 }
Karsten Koenigee2dd732019-08-07 17:13:35 +0200347
Martí Bolívar7e0eed92020-05-06 11:23:07 -0700348DT_INST_FOREACH_STATUS_OKAY(SPI_RV32M1_INIT)