Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, NXP |
| 3 | * |
| 4 | * Forked off the spi_mcux_lpi2c driver. |
| 5 | * |
| 6 | * SPDX-License-Identifier: Apache-2.0 |
| 7 | */ |
| 8 | |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 9 | #define DT_DRV_COMPAT openisa_rv32m1_lpspi |
| 10 | |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 11 | #include <errno.h> |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 12 | #include <zephyr/drivers/spi.h> |
| 13 | #include <zephyr/drivers/clock_control.h> |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 14 | #include <fsl_lpspi.h> |
Henrik Brix Andersen | c83a0d5 | 2022-05-01 22:32:33 +0200 | [diff] [blame] | 15 | #ifdef CONFIG_PINCTRL |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 16 | #include <zephyr/drivers/pinctrl.h> |
Henrik Brix Andersen | c83a0d5 | 2022-05-01 22:32:33 +0200 | [diff] [blame] | 17 | #endif |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 18 | |
| 19 | #define LOG_LEVEL CONFIG_SPI_LOG_LEVEL |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 20 | #include <zephyr/logging/log.h> |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 21 | LOG_MODULE_REGISTER(spi_rv32m1_lpspi); |
| 22 | |
| 23 | #include "spi_context.h" |
| 24 | |
| 25 | #define CHIP_SELECT_COUNT 4 |
| 26 | #define MAX_DATA_WIDTH 4096 |
| 27 | |
| 28 | struct spi_mcux_config { |
| 29 | LPSPI_Type *base; |
Kumar Gala | 3a8fffb | 2021-02-11 18:05:31 -0600 | [diff] [blame] | 30 | const struct device *clock_dev; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 31 | clock_control_subsys_t clock_subsys; |
| 32 | clock_ip_name_t clock_ip_name; |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 33 | uint32_t clock_ip_src; |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 34 | void (*irq_config_func)(const struct device *dev); |
Henrik Brix Andersen | c83a0d5 | 2022-05-01 22:32:33 +0200 | [diff] [blame] | 35 | #ifdef CONFIG_PINCTRL |
| 36 | const struct pinctrl_dev_config *pincfg; |
| 37 | #endif |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | struct spi_mcux_data { |
Tomasz Bursztyka | 898f914 | 2020-07-08 10:57:21 +0200 | [diff] [blame] | 41 | const struct device *dev; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 42 | lpspi_master_handle_t handle; |
| 43 | struct spi_context ctx; |
| 44 | size_t transfer_len; |
| 45 | }; |
| 46 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 47 | static void spi_mcux_transfer_next_packet(const struct device *dev) |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 48 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 49 | const struct spi_mcux_config *config = dev->config; |
Tomasz Bursztyka | 98d9b01 | 2020-05-28 21:23:02 +0200 | [diff] [blame] | 50 | struct spi_mcux_data *data = dev->data; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 51 | LPSPI_Type *base = config->base; |
| 52 | struct spi_context *ctx = &data->ctx; |
| 53 | lpspi_transfer_t transfer; |
| 54 | status_t status; |
| 55 | |
| 56 | if ((ctx->tx_len == 0) && (ctx->rx_len == 0)) { |
| 57 | /* nothing left to rx or tx, we're done! */ |
| 58 | spi_context_cs_control(&data->ctx, false); |
| 59 | spi_context_complete(&data->ctx, 0); |
| 60 | return; |
| 61 | } |
| 62 | |
| 63 | transfer.configFlags = kLPSPI_MasterPcsContinuous | |
| 64 | (ctx->config->slave << LPSPI_MASTER_PCS_SHIFT); |
| 65 | |
| 66 | if (ctx->tx_len == 0) { |
| 67 | /* rx only, nothing to tx */ |
| 68 | transfer.txData = NULL; |
| 69 | transfer.rxData = ctx->rx_buf; |
| 70 | transfer.dataSize = ctx->rx_len; |
| 71 | } else if (ctx->rx_len == 0) { |
| 72 | /* tx only, nothing to rx */ |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 73 | transfer.txData = (uint8_t *) ctx->tx_buf; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 74 | transfer.rxData = NULL; |
| 75 | transfer.dataSize = ctx->tx_len; |
| 76 | } else if (ctx->tx_len == ctx->rx_len) { |
| 77 | /* rx and tx are the same length */ |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 78 | transfer.txData = (uint8_t *) ctx->tx_buf; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 79 | transfer.rxData = ctx->rx_buf; |
| 80 | transfer.dataSize = ctx->tx_len; |
| 81 | } else if (ctx->tx_len > ctx->rx_len) { |
| 82 | /* Break up the tx into multiple transfers so we don't have to |
| 83 | * rx into a longer intermediate buffer. Leave chip select |
| 84 | * active between transfers. |
| 85 | */ |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 86 | transfer.txData = (uint8_t *) ctx->tx_buf; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 87 | transfer.rxData = ctx->rx_buf; |
| 88 | transfer.dataSize = ctx->rx_len; |
| 89 | transfer.configFlags |= kLPSPI_MasterPcsContinuous; |
| 90 | } else { |
| 91 | /* Break up the rx into multiple transfers so we don't have to |
| 92 | * tx from a longer intermediate buffer. Leave chip select |
| 93 | * active between transfers. |
| 94 | */ |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 95 | transfer.txData = (uint8_t *) ctx->tx_buf; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 96 | transfer.rxData = ctx->rx_buf; |
| 97 | transfer.dataSize = ctx->tx_len; |
| 98 | transfer.configFlags |= kLPSPI_MasterPcsContinuous; |
| 99 | } |
| 100 | |
| 101 | if (!(ctx->tx_count <= 1 && ctx->rx_count <= 1)) { |
| 102 | transfer.configFlags |= kLPSPI_MasterPcsContinuous; |
| 103 | } |
| 104 | |
| 105 | data->transfer_len = transfer.dataSize; |
| 106 | status = LPSPI_MasterTransferNonBlocking(base, &data->handle, |
| 107 | &transfer); |
| 108 | if (status != kStatus_Success) { |
| 109 | LOG_ERR("Transfer could not start"); |
| 110 | } |
| 111 | } |
| 112 | |
Tomasz Bursztyka | 4dcfb55 | 2020-06-17 14:58:56 +0200 | [diff] [blame] | 113 | static void spi_mcux_isr(const struct device *dev) |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 114 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 115 | const struct spi_mcux_config *config = dev->config; |
Tomasz Bursztyka | 98d9b01 | 2020-05-28 21:23:02 +0200 | [diff] [blame] | 116 | struct spi_mcux_data *data = dev->data; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 117 | LPSPI_Type *base = config->base; |
| 118 | |
| 119 | LPSPI_MasterTransferHandleIRQ(base, &data->handle); |
| 120 | } |
| 121 | |
| 122 | static void spi_mcux_master_transfer_callback(LPSPI_Type *base, |
Tomasz Bursztyka | 898f914 | 2020-07-08 10:57:21 +0200 | [diff] [blame] | 123 | lpspi_master_handle_t *handle, |
| 124 | status_t status, void *userData) |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 125 | { |
Tomasz Bursztyka | 898f914 | 2020-07-08 10:57:21 +0200 | [diff] [blame] | 126 | struct spi_mcux_data *data = userData; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 127 | |
| 128 | spi_context_update_tx(&data->ctx, 1, data->transfer_len); |
| 129 | spi_context_update_rx(&data->ctx, 1, data->transfer_len); |
| 130 | |
Tomasz Bursztyka | 898f914 | 2020-07-08 10:57:21 +0200 | [diff] [blame] | 131 | spi_mcux_transfer_next_packet(data->dev); |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 132 | } |
| 133 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 134 | static int spi_mcux_configure(const struct device *dev, |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 135 | const struct spi_config *spi_cfg) |
| 136 | { |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 137 | const struct spi_mcux_config *config = dev->config; |
Tomasz Bursztyka | 98d9b01 | 2020-05-28 21:23:02 +0200 | [diff] [blame] | 138 | struct spi_mcux_data *data = dev->data; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 139 | LPSPI_Type *base = config->base; |
| 140 | lpspi_master_config_t master_config; |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 141 | uint32_t clock_freq; |
| 142 | uint32_t word_size; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 143 | |
| 144 | if (spi_context_configured(&data->ctx, spi_cfg)) { |
| 145 | /* This configuration is already in use */ |
| 146 | return 0; |
| 147 | } |
| 148 | |
Tomasz Bursztyka | 01b9813 | 2021-09-09 16:16:59 +0200 | [diff] [blame] | 149 | if (spi_cfg->operation & SPI_HALF_DUPLEX) { |
| 150 | LOG_ERR("Half-duplex not supported"); |
| 151 | return -ENOTSUP; |
| 152 | } |
| 153 | |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 154 | LPSPI_MasterGetDefaultConfig(&master_config); |
| 155 | |
| 156 | if (spi_cfg->slave > CHIP_SELECT_COUNT) { |
| 157 | LOG_ERR("Slave %d is greater than %d", |
| 158 | spi_cfg->slave, |
| 159 | CHIP_SELECT_COUNT); |
| 160 | return -EINVAL; |
| 161 | } |
| 162 | |
| 163 | word_size = SPI_WORD_SIZE_GET(spi_cfg->operation); |
| 164 | if (word_size > MAX_DATA_WIDTH) { |
| 165 | LOG_ERR("Word size %d is greater than %d", |
| 166 | word_size, MAX_DATA_WIDTH); |
| 167 | return -EINVAL; |
| 168 | } |
| 169 | |
| 170 | master_config.bitsPerFrame = word_size; |
| 171 | |
| 172 | master_config.cpol = |
| 173 | (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) |
| 174 | ? kLPSPI_ClockPolarityActiveLow |
| 175 | : kLPSPI_ClockPolarityActiveHigh; |
| 176 | |
| 177 | master_config.cpha = |
| 178 | (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) |
| 179 | ? kLPSPI_ClockPhaseSecondEdge |
| 180 | : kLPSPI_ClockPhaseFirstEdge; |
| 181 | |
| 182 | master_config.direction = |
| 183 | (spi_cfg->operation & SPI_TRANSFER_LSB) |
| 184 | ? kLPSPI_LsbFirst |
| 185 | : kLPSPI_MsbFirst; |
| 186 | |
| 187 | master_config.baudRate = spi_cfg->frequency; |
| 188 | |
Kumar Gala | 3a8fffb | 2021-02-11 18:05:31 -0600 | [diff] [blame] | 189 | if (clock_control_get_rate(config->clock_dev, config->clock_subsys, |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 190 | &clock_freq)) { |
| 191 | return -EINVAL; |
| 192 | } |
| 193 | |
| 194 | LPSPI_MasterInit(base, &master_config, clock_freq); |
| 195 | |
| 196 | LPSPI_MasterTransferCreateHandle(base, &data->handle, |
Tomasz Bursztyka | 898f914 | 2020-07-08 10:57:21 +0200 | [diff] [blame] | 197 | spi_mcux_master_transfer_callback, |
| 198 | data); |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 199 | |
Karsten Koenig | 189ae8c | 2020-06-10 18:36:15 +0200 | [diff] [blame] | 200 | LPSPI_SetDummyData(base, 0); |
| 201 | |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 202 | data->ctx.config = spi_cfg; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 203 | |
| 204 | return 0; |
| 205 | } |
| 206 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 207 | static int transceive(const struct device *dev, |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 208 | const struct spi_config *spi_cfg, |
| 209 | const struct spi_buf_set *tx_bufs, |
| 210 | const struct spi_buf_set *rx_bufs, |
| 211 | bool asynchronous, |
| 212 | struct k_poll_signal *signal) |
| 213 | { |
Tomasz Bursztyka | 98d9b01 | 2020-05-28 21:23:02 +0200 | [diff] [blame] | 214 | struct spi_mcux_data *data = dev->data; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 215 | int ret; |
| 216 | |
Stefan Bigler | 596cad8 | 2020-10-19 08:52:29 +0200 | [diff] [blame] | 217 | spi_context_lock(&data->ctx, asynchronous, signal, spi_cfg); |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 218 | |
| 219 | ret = spi_mcux_configure(dev, spi_cfg); |
| 220 | if (ret) { |
| 221 | goto out; |
| 222 | } |
| 223 | |
| 224 | spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1); |
| 225 | |
| 226 | spi_context_cs_control(&data->ctx, true); |
| 227 | |
| 228 | spi_mcux_transfer_next_packet(dev); |
| 229 | |
| 230 | ret = spi_context_wait_for_completion(&data->ctx); |
| 231 | out: |
| 232 | spi_context_release(&data->ctx, ret); |
| 233 | |
| 234 | return ret; |
| 235 | } |
| 236 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 237 | static int spi_mcux_transceive(const struct device *dev, |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 238 | const struct spi_config *spi_cfg, |
| 239 | const struct spi_buf_set *tx_bufs, |
| 240 | const struct spi_buf_set *rx_bufs) |
| 241 | { |
| 242 | return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL); |
| 243 | } |
| 244 | |
| 245 | #ifdef CONFIG_SPI_ASYNC |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 246 | static int spi_mcux_transceive_async(const struct device *dev, |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 247 | const struct spi_config *spi_cfg, |
| 248 | const struct spi_buf_set *tx_bufs, |
| 249 | const struct spi_buf_set *rx_bufs, |
| 250 | struct k_poll_signal *async) |
| 251 | { |
| 252 | return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, async); |
| 253 | } |
| 254 | #endif /* CONFIG_SPI_ASYNC */ |
| 255 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 256 | static int spi_mcux_release(const struct device *dev, |
| 257 | const struct spi_config *spi_cfg) |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 258 | { |
Tomasz Bursztyka | 98d9b01 | 2020-05-28 21:23:02 +0200 | [diff] [blame] | 259 | struct spi_mcux_data *data = dev->data; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 260 | |
| 261 | spi_context_unlock_unconditionally(&data->ctx); |
| 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 266 | static int spi_mcux_init(const struct device *dev) |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 267 | { |
Bartosz Bilas | 05f326c | 2021-10-07 17:08:26 +0200 | [diff] [blame] | 268 | int err; |
Tomasz Bursztyka | af6140c | 2020-05-28 20:44:16 +0200 | [diff] [blame] | 269 | const struct spi_mcux_config *config = dev->config; |
Tomasz Bursztyka | 98d9b01 | 2020-05-28 21:23:02 +0200 | [diff] [blame] | 270 | struct spi_mcux_data *data = dev->data; |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 271 | |
| 272 | CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src); |
| 273 | |
| 274 | config->irq_config_func(dev); |
| 275 | |
Tomasz Bursztyka | 898f914 | 2020-07-08 10:57:21 +0200 | [diff] [blame] | 276 | data->dev = dev; |
| 277 | |
Bartosz Bilas | 05f326c | 2021-10-07 17:08:26 +0200 | [diff] [blame] | 278 | err = spi_context_cs_configure_all(&data->ctx); |
| 279 | if (err < 0) { |
| 280 | return err; |
| 281 | } |
| 282 | |
Henrik Brix Andersen | c83a0d5 | 2022-05-01 22:32:33 +0200 | [diff] [blame] | 283 | #ifdef CONFIG_PINCTRL |
| 284 | err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); |
| 285 | if (err != 0) { |
| 286 | return err; |
| 287 | } |
| 288 | #endif |
| 289 | |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 290 | spi_context_unlock_unconditionally(&data->ctx); |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static const struct spi_driver_api spi_mcux_driver_api = { |
| 296 | .transceive = spi_mcux_transceive, |
| 297 | #ifdef CONFIG_SPI_ASYNC |
| 298 | .transceive_async = spi_mcux_transceive_async, |
| 299 | #endif |
| 300 | .release = spi_mcux_release, |
| 301 | }; |
| 302 | |
Henrik Brix Andersen | c83a0d5 | 2022-05-01 22:32:33 +0200 | [diff] [blame] | 303 | #ifdef CONFIG_PINCTRL |
| 304 | #define PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), |
| 305 | #define PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n); |
| 306 | #else |
| 307 | #define PINCTRL_DEFINE(n) |
| 308 | #define PINCTRL_INIT(n) |
| 309 | #endif |
| 310 | |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 311 | #define SPI_RV32M1_INIT(n) \ |
Henrik Brix Andersen | c83a0d5 | 2022-05-01 22:32:33 +0200 | [diff] [blame] | 312 | PINCTRL_DEFINE(n) \ |
| 313 | \ |
Tomasz Bursztyka | ef560e0 | 2020-07-14 17:02:00 +0200 | [diff] [blame] | 314 | static void spi_mcux_config_func_##n(const struct device *dev); \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 315 | \ |
| 316 | static const struct spi_mcux_config spi_mcux_config_##n = { \ |
| 317 | .base = (LPSPI_Type *) DT_INST_REG_ADDR(n), \ |
Kumar Gala | 3a8fffb | 2021-02-11 18:05:31 -0600 | [diff] [blame] | 318 | .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 319 | .clock_subsys = (clock_control_subsys_t) \ |
| 320 | DT_INST_CLOCKS_CELL(n, name), \ |
| 321 | .irq_config_func = spi_mcux_config_func_##n, \ |
| 322 | .clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \ |
| 323 | .clock_ip_src = kCLOCK_IpSrcFircAsync, \ |
Henrik Brix Andersen | c83a0d5 | 2022-05-01 22:32:33 +0200 | [diff] [blame] | 324 | PINCTRL_INIT(n) \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 325 | }; \ |
| 326 | \ |
| 327 | static struct spi_mcux_data spi_mcux_data_##n = { \ |
| 328 | SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx), \ |
| 329 | SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx), \ |
Bartosz Bilas | 05f326c | 2021-10-07 17:08:26 +0200 | [diff] [blame] | 330 | SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 331 | }; \ |
| 332 | \ |
Gerard Marull-Paretas | 90118b2 | 2021-04-28 12:04:51 +0200 | [diff] [blame] | 333 | DEVICE_DT_INST_DEFINE(n, &spi_mcux_init, NULL, \ |
Kumar Gala | 03ad31b | 2020-12-09 12:32:41 -0600 | [diff] [blame] | 334 | &spi_mcux_data_##n, \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 335 | &spi_mcux_config_##n, \ |
| 336 | POST_KERNEL, \ |
Bartosz Bilas | ea25b92 | 2021-10-27 20:33:15 +0200 | [diff] [blame] | 337 | CONFIG_SPI_INIT_PRIORITY, \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 338 | &spi_mcux_driver_api); \ |
| 339 | \ |
Tomasz Bursztyka | ef560e0 | 2020-07-14 17:02:00 +0200 | [diff] [blame] | 340 | static void spi_mcux_config_func_##n(const struct device *dev) \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 341 | { \ |
| 342 | IRQ_CONNECT(DT_INST_IRQN(n), \ |
| 343 | 0, \ |
Kumar Gala | 03ad31b | 2020-12-09 12:32:41 -0600 | [diff] [blame] | 344 | spi_mcux_isr, DEVICE_DT_INST_GET(n), 0); \ |
Kumar Gala | 8c60bc0 | 2020-04-02 15:15:38 -0500 | [diff] [blame] | 345 | irq_enable(DT_INST_IRQN(n)); \ |
| 346 | } |
Karsten Koenig | ee2dd73 | 2019-08-07 17:13:35 +0200 | [diff] [blame] | 347 | |
Martí Bolívar | 7e0eed9 | 2020-05-06 11:23:07 -0700 | [diff] [blame] | 348 | DT_INST_FOREACH_STATUS_OKAY(SPI_RV32M1_INIT) |