Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright (c) 2019 Ilya Tagunov |
| 4 | * Copyright (c) 2019 STMicroelectronics |
| 5 | * |
| 6 | * SPDX-License-Identifier: Apache-2.0 |
| 7 | */ |
| 8 | |
| 9 | |
| 10 | #include <soc.h> |
Martin Jäger | d5aff7b | 2020-11-20 20:28:06 +0100 | [diff] [blame] | 11 | #include <stm32_ll_bus.h> |
Marc Desvaux | 72aee4b | 2023-09-26 15:38:47 +0200 | [diff] [blame] | 12 | #include <stm32_ll_crs.h> |
Martin Jäger | d5aff7b | 2020-11-20 20:28:06 +0100 | [diff] [blame] | 13 | #include <stm32_ll_rcc.h> |
| 14 | #include <stm32_ll_utils.h> |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 15 | #include <zephyr/drivers/clock_control.h> |
| 16 | #include <zephyr/sys/util.h> |
| 17 | #include <zephyr/drivers/clock_control/stm32_clock_control.h> |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 18 | #include "clock_stm32_ll_common.h" |
| 19 | |
Thomas Stranger | ddf3f2d | 2022-06-28 21:50:20 +0200 | [diff] [blame] | 20 | #if defined(STM32_PLL_ENABLED) |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 21 | |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 22 | /** |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 23 | * @brief Return PLL source |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 24 | */ |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 25 | __unused |
| 26 | static uint32_t get_pll_source(void) |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 27 | { |
Erwan Gouriou | c4ff7d1 | 2022-03-23 15:34:16 +0100 | [diff] [blame] | 28 | /* Configure PLL source */ |
| 29 | if (IS_ENABLED(STM32_PLL_SRC_HSI)) { |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 30 | return LL_RCC_PLLSOURCE_HSI; |
Erwan Gouriou | c4ff7d1 | 2022-03-23 15:34:16 +0100 | [diff] [blame] | 31 | } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) { |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 32 | return LL_RCC_PLLSOURCE_HSE; |
Erwan Gouriou | c4ff7d1 | 2022-03-23 15:34:16 +0100 | [diff] [blame] | 33 | } |
| 34 | |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 35 | __ASSERT(0, "Invalid source"); |
Erwan Gouriou | c4ff7d1 | 2022-03-23 15:34:16 +0100 | [diff] [blame] | 36 | return 0; |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 37 | } |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 38 | |
| 39 | /** |
Thomas Stranger | 1543025 | 2022-06-28 20:12:41 +0200 | [diff] [blame] | 40 | * @brief get the pll source frequency |
| 41 | */ |
| 42 | __unused |
| 43 | uint32_t get_pllsrc_frequency(void) |
| 44 | { |
| 45 | if (IS_ENABLED(STM32_PLL_SRC_HSI)) { |
| 46 | return STM32_HSI_FREQ; |
| 47 | } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) { |
| 48 | return STM32_HSE_FREQ; |
| 49 | } |
| 50 | |
| 51 | __ASSERT(0, "Invalid source"); |
| 52 | return 0; |
| 53 | } |
| 54 | |
| 55 | /** |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 56 | * @brief Set up pll configuration |
| 57 | */ |
| 58 | __unused |
| 59 | void config_pll_sysclock(void) |
| 60 | { |
| 61 | LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(), |
Thomas Stranger | c112afa | 2022-06-28 16:44:58 +0200 | [diff] [blame] | 62 | pllm(STM32_PLL_M_DIVISOR), |
Erwan Gouriou | 0921786 | 2022-04-22 11:37:28 +0200 | [diff] [blame] | 63 | STM32_PLL_N_MULTIPLIER, |
| 64 | pllr(STM32_PLL_R_DIVISOR)); |
| 65 | |
| 66 | LL_RCC_PLL_EnableDomain_SYS(); |
| 67 | } |
| 68 | |
Thomas Stranger | ddf3f2d | 2022-06-28 21:50:20 +0200 | [diff] [blame] | 69 | #endif /* defined(STM32_PLL_ENABLED) */ |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 70 | |
| 71 | /** |
| 72 | * @brief Activate default clocks |
| 73 | */ |
| 74 | void config_enable_default_clocks(void) |
| 75 | { |
Francois Ramu | f3c6811 | 2021-01-05 16:13:24 +0100 | [diff] [blame] | 76 | /* Enable the power interface clock */ |
| 77 | LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); |
Marc Desvaux | 72aee4b | 2023-09-26 15:38:47 +0200 | [diff] [blame] | 78 | |
| 79 | #if defined(CRS) |
| 80 | if (IS_ENABLED(STM32_HSI48_CRS_USB_SOF)) { |
| 81 | LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS); |
| 82 | /* |
| 83 | * After reset the CRS configuration register |
| 84 | * (CRS_CFGR) value corresponds to an USB SOF |
| 85 | * synchronization. FIXME: write it anyway. |
| 86 | */ |
| 87 | LL_CRS_EnableAutoTrimming(); |
| 88 | LL_CRS_EnableFreqErrorCounter(); |
| 89 | } |
| 90 | #endif /* defined(CRS) */ |
| 91 | |
Francois Ramu | 624c566 | 2019-07-02 11:22:51 +0200 | [diff] [blame] | 92 | } |