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Francois Ramu624c5662019-07-02 11:22:51 +02001/*
2 *
3 * Copyright (c) 2019 Ilya Tagunov
4 * Copyright (c) 2019 STMicroelectronics
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9
10#include <soc.h>
Martin Jägerd5aff7b2020-11-20 20:28:06 +010011#include <stm32_ll_bus.h>
Marc Desvaux72aee4b2023-09-26 15:38:47 +020012#include <stm32_ll_crs.h>
Martin Jägerd5aff7b2020-11-20 20:28:06 +010013#include <stm32_ll_rcc.h>
14#include <stm32_ll_utils.h>
Gerard Marull-Paretasfb60aab2022-05-06 10:25:46 +020015#include <zephyr/drivers/clock_control.h>
16#include <zephyr/sys/util.h>
17#include <zephyr/drivers/clock_control/stm32_clock_control.h>
Francois Ramu624c5662019-07-02 11:22:51 +020018#include "clock_stm32_ll_common.h"
19
Thomas Strangerddf3f2d2022-06-28 21:50:20 +020020#if defined(STM32_PLL_ENABLED)
Francois Ramu624c5662019-07-02 11:22:51 +020021
Francois Ramu624c5662019-07-02 11:22:51 +020022/**
Erwan Gouriou09217862022-04-22 11:37:28 +020023 * @brief Return PLL source
Francois Ramu624c5662019-07-02 11:22:51 +020024 */
Erwan Gouriou09217862022-04-22 11:37:28 +020025__unused
26static uint32_t get_pll_source(void)
Francois Ramu624c5662019-07-02 11:22:51 +020027{
Erwan Gouriouc4ff7d12022-03-23 15:34:16 +010028 /* Configure PLL source */
29 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
Erwan Gouriou09217862022-04-22 11:37:28 +020030 return LL_RCC_PLLSOURCE_HSI;
Erwan Gouriouc4ff7d12022-03-23 15:34:16 +010031 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
Erwan Gouriou09217862022-04-22 11:37:28 +020032 return LL_RCC_PLLSOURCE_HSE;
Erwan Gouriouc4ff7d12022-03-23 15:34:16 +010033 }
34
Erwan Gouriou09217862022-04-22 11:37:28 +020035 __ASSERT(0, "Invalid source");
Erwan Gouriouc4ff7d12022-03-23 15:34:16 +010036 return 0;
Francois Ramu624c5662019-07-02 11:22:51 +020037}
Erwan Gouriou09217862022-04-22 11:37:28 +020038
39/**
Thomas Stranger15430252022-06-28 20:12:41 +020040 * @brief get the pll source frequency
41 */
42__unused
43uint32_t get_pllsrc_frequency(void)
44{
45 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
46 return STM32_HSI_FREQ;
47 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
48 return STM32_HSE_FREQ;
49 }
50
51 __ASSERT(0, "Invalid source");
52 return 0;
53}
54
55/**
Erwan Gouriou09217862022-04-22 11:37:28 +020056 * @brief Set up pll configuration
57 */
58__unused
59void config_pll_sysclock(void)
60{
61 LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
Thomas Strangerc112afa2022-06-28 16:44:58 +020062 pllm(STM32_PLL_M_DIVISOR),
Erwan Gouriou09217862022-04-22 11:37:28 +020063 STM32_PLL_N_MULTIPLIER,
64 pllr(STM32_PLL_R_DIVISOR));
65
66 LL_RCC_PLL_EnableDomain_SYS();
67}
68
Thomas Strangerddf3f2d2022-06-28 21:50:20 +020069#endif /* defined(STM32_PLL_ENABLED) */
Francois Ramu624c5662019-07-02 11:22:51 +020070
71/**
72 * @brief Activate default clocks
73 */
74void config_enable_default_clocks(void)
75{
Francois Ramuf3c68112021-01-05 16:13:24 +010076 /* Enable the power interface clock */
77 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
Marc Desvaux72aee4b2023-09-26 15:38:47 +020078
79#if defined(CRS)
80 if (IS_ENABLED(STM32_HSI48_CRS_USB_SOF)) {
81 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
82 /*
83 * After reset the CRS configuration register
84 * (CRS_CFGR) value corresponds to an USB SOF
85 * synchronization. FIXME: write it anyway.
86 */
87 LL_CRS_EnableAutoTrimming();
88 LL_CRS_EnableFreqErrorCounter();
89 }
90#endif /* defined(CRS) */
91
Francois Ramu624c5662019-07-02 11:22:51 +020092}