Release v1.7.7
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 889db8f..f085e2d 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -236,6 +236,16 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
/**
* @}
*/
@@ -296,8 +306,17 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
#endif /* STM32L4 */
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#endif
+
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -355,6 +374,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
#endif /* STM32H7 */
/**
@@ -450,7 +472,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -486,6 +510,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
/**
* @}
*/
@@ -494,7 +525,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -547,18 +578,25 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#endif
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -599,6 +637,185 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+ * set/reset crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
/**
* @}
*/
@@ -738,6 +955,12 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
/**
* @}
*/
@@ -753,7 +976,6 @@
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
- #define I2S_FLAG_FRE I2S_FLAG_TIFRE
#endif
#if defined(STM32F7)
@@ -824,6 +1046,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -971,6 +1203,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
/**
* @}
*/
@@ -1199,6 +1449,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1221,6 +1495,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
/**
* @}
*/
@@ -1250,16 +1531,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1278,6 +1561,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@@ -1350,14 +1640,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@@ -2476,12 +2766,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@@ -2814,6 +3120,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@@ -2930,7 +3245,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0)
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3058,7 +3373,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3174,7 +3489,7 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
@@ -3421,13 +3736,23 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{
*/
-#if defined (STM32H7) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif
/**
* @}
diff --git a/Inc/Legacy/stm32f4xx_hal_can_legacy.h b/Inc/Legacy/stm32f4xx_hal_can_legacy.h
index 7788f06..aacf0f0 100644
--- a/Inc/Legacy/stm32f4xx_hal_can_legacy.h
+++ b/Inc/Legacy/stm32f4xx_hal_can_legacy.h
@@ -6,13 +6,29 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
diff --git a/Inc/stm32f4xx_hal.h b/Inc/stm32f4xx_hal.h
index 5b800df..209864d 100644
--- a/Inc/stm32f4xx_hal.h
+++ b/Inc/stm32f4xx_hal.h
@@ -197,6 +197,18 @@
* @}
*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
diff --git a/Inc/stm32f4xx_hal_dcmi.h b/Inc/stm32f4xx_hal_dcmi.h
index 021f37e..2a9edb6 100644
--- a/Inc/stm32f4xx_hal_dcmi.h
+++ b/Inc/stm32f4xx_hal_dcmi.h
@@ -49,6 +49,16 @@
* @{
*/
/**
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ */
+typedef struct
+{
+ uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+ uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
+ uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
+ uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
+}DCMI_SyncUnmaskTypeDef;
+/**
* @brief HAL DCMI State structures definition
*/
typedef enum
@@ -458,6 +468,7 @@
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
/**
* @}
*/
diff --git a/Inc/stm32f4xx_hal_dma2d.h b/Inc/stm32f4xx_hal_dma2d.h
index 5bb7b6d..37c7299 100644
--- a/Inc/stm32f4xx_hal_dma2d.h
+++ b/Inc/stm32f4xx_hal_dma2d.h
@@ -25,8 +25,6 @@
extern "C" {
#endif
-#if defined (DMA2D)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -34,6 +32,8 @@
* @{
*/
+#if defined (DMA2D)
+
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
@@ -447,6 +447,8 @@
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
@@ -612,12 +614,12 @@
* @}
*/
+#endif /* defined (DMA2D) */
+
/**
* @}
*/
-#endif /* defined (DMA2D) */
-
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32f4xx_hal_dsi.h b/Inc/stm32f4xx_hal_dsi.h
index df61c5e..822a430 100644
--- a/Inc/stm32f4xx_hal_dsi.h
+++ b/Inc/stm32f4xx_hal_dsi.h
@@ -25,10 +25,11 @@
extern "C" {
#endif
-#if defined(DSI)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(DSI)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -347,6 +348,9 @@
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
+/** @defgroup DSI_Exported_Constants DSI Exported Constants
+ * @{
+ */
/** @defgroup DSI_DCS_Command DSI DCS Command
* @{
*/
@@ -908,7 +912,15 @@
* @}
*/
+/**
+ * @}
+ */
+
/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DSI_Exported_Macros DSI Exported Macros
+ * @{
+ */
+
/**
* @brief Reset DSI handle state.
* @param __HANDLE__: DSI handle
@@ -1101,6 +1113,10 @@
*/
#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup DSI_Exported_Functions DSI Exported Functions
* @{
diff --git a/Inc/stm32f4xx_hal_exti.h b/Inc/stm32f4xx_hal_exti.h
index 24dccff..8bb516c 100644
--- a/Inc/stm32f4xx_hal_exti.h
+++ b/Inc/stm32f4xx_hal_exti.h
@@ -44,9 +44,7 @@
*/
typedef enum
{
- HAL_EXTI_COMMON_CB_ID = 0x00U,
- HAL_EXTI_RISING_CB_ID = 0x01U,
- HAL_EXTI_FALLING_CB_ID = 0x02U,
+ HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
@@ -55,8 +53,7 @@
typedef struct
{
uint32_t Line; /*!< Exti line number */
- void (* RisingCallback)(void); /*!< Exti rising callback */
- void (* FallingCallback)(void); /*!< Exti falling callback */
+ void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
@@ -69,7 +66,10 @@
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
- can be a value of @ref EXTI_Trigger */
+ can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
@@ -84,29 +84,44 @@
/** @defgroup EXTI_Line EXTI Line
* @{
*/
-#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
-#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
-#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
-#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
-#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
-#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
-#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
-#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
-#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
-#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
-#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
-#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
-#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
-#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
-#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
-#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
-#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
-#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
+#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
+#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
+#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
+#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
+#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
+#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
+#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
+#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
+#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
+#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
+#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
+#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
+#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
+#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
+#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
+#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#if defined(EXTI_IMR_IM18)
+#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#else
+#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM18 */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#else
+#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM19 */
+#if defined(EXTI_IMR_IM20)
+#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#else
+#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM20 */
+#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
+#endif /* EXTI_IMR_IM23 */
/**
* @}
@@ -115,8 +130,9 @@
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
-#define EXTI_MODE_INTERRUPT 0x00000000U
-#define EXTI_MODE_EVENT 0x00000004U
+#define EXTI_MODE_NONE 0x00000000u
+#define EXTI_MODE_INTERRUPT 0x00000001u
+#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
@@ -125,13 +141,50 @@
* @{
*/
-#define EXTI_TRIGGER_RISING 0x00000008U
-#define EXTI_TRIGGER_FALLING 0x0000000CU
-#define EXTI_TRIGGER_RISING_FALLING 0x00000010U
+#define EXTI_TRIGGER_NONE 0x00000000u
+#define EXTI_TRIGGER_RISING 0x00000001u
+#define EXTI_TRIGGER_FALLING 0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
-
+
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000u
+#define EXTI_GPIOB 0x00000001u
+#define EXTI_GPIOC 0x00000002u
+#if defined (GPIOD)
+#define EXTI_GPIOD 0x00000003u
+#endif /* GPIOD */
+#if defined (GPIOE)
+#define EXTI_GPIOE 0x00000004u
+#endif /* GPIOE */
+#if defined (GPIOF)
+#define EXTI_GPIOF 0x00000005u
+#endif /* GPIOF */
+#if defined (GPIOG)
+#define EXTI_GPIOG 0x00000006u
+#endif /* GPIOG */
+#if defined (GPIOH)
+#define EXTI_GPIOH 0x00000007u
+#endif /* GPIOH */
+#if defined (GPIOI)
+#define EXTI_GPIOI 0x00000008u
+#endif /* GPIOI */
+#if defined (GPIOJ)
+#define EXTI_GPIOJ 0x00000009u
+#endif /* GPIOJ */
+#if defined (GPIOK)
+#define EXTI_GPIOK 0x0000000Au
+#endif /* GPIOK */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -150,6 +203,20 @@
* @{
*/
/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24u
+#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI bit usage
+ */
+#define EXTI_PIN_MASK 0x0000001Fu
+
+/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
@@ -157,12 +224,16 @@
/**
* @brief EXTI Mask for trigger possibilities
*/
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_NB 24UL
+#else
#define EXTI_LINE_NB 23UL
+#endif /* EXTI_IMR_IM23 */
/**
* @}
@@ -172,38 +243,73 @@
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) (((__LINE__) == EXTI_LINE_0) || \
- ((__LINE__) == EXTI_LINE_1) || \
- ((__LINE__) == EXTI_LINE_2) || \
- ((__LINE__) == EXTI_LINE_3) || \
- ((__LINE__) == EXTI_LINE_4) || \
- ((__LINE__) == EXTI_LINE_5) || \
- ((__LINE__) == EXTI_LINE_6) || \
- ((__LINE__) == EXTI_LINE_7) || \
- ((__LINE__) == EXTI_LINE_8) || \
- ((__LINE__) == EXTI_LINE_9) || \
- ((__LINE__) == EXTI_LINE_10) || \
- ((__LINE__) == EXTI_LINE_11) || \
- ((__LINE__) == EXTI_LINE_12) || \
- ((__LINE__) == EXTI_LINE_13) || \
- ((__LINE__) == EXTI_LINE_14) || \
- ((__LINE__) == EXTI_LINE_15) || \
- ((__LINE__) == EXTI_LINE_16) || \
- ((__LINE__) == EXTI_LINE_17) || \
- ((__LINE__) == EXTI_LINE_18) || \
- ((__LINE__) == EXTI_LINE_19) || \
- ((__LINE__) == EXTI_LINE_20) || \
- ((__LINE__) == EXTI_LINE_21) || \
- ((__LINE__) == EXTI_LINE_22))
+#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
- ((__LINE__) == EXTI_TRIGGER_RISING) || \
+ ((__LINE__) == EXTI_TRIGGER_RISING) || \
((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if !defined (GPIOD)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOF)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOI)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOJ)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI) || \
+ ((__PORT__) == EXTI_GPIOJ) || \
+ ((__PORT__) == EXTI_GPIOK))
+#endif /* GPIOD */
+
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
/**
* @}
diff --git a/Inc/stm32f4xx_hal_fmpi2c_ex.h b/Inc/stm32f4xx_hal_fmpi2c_ex.h
index 2be2c28..f6d04a6 100644
--- a/Inc/stm32f4xx_hal_fmpi2c_ex.h
+++ b/Inc/stm32f4xx_hal_fmpi2c_ex.h
@@ -107,8 +107,6 @@
-
-
/**
* @}
*/
diff --git a/Inc/stm32f4xx_hal_gpio.h b/Inc/stm32f4xx_hal_gpio.h
index 5110d63..5a17538 100644
--- a/Inc/stm32f4xx_hal_gpio.h
+++ b/Inc/stm32f4xx_hal_gpio.h
@@ -262,7 +262,7 @@
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
diff --git a/Inc/stm32f4xx_hal_hash.h b/Inc/stm32f4xx_hal_hash.h
index da6d5d9..ea6f593 100644
--- a/Inc/stm32f4xx_hal_hash.h
+++ b/Inc/stm32f4xx_hal_hash.h
@@ -152,6 +152,8 @@
__IO uint32_t ErrorCode; /*!< HASH Error code */
+ __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
+
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
@@ -226,11 +228,11 @@
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
@@ -276,7 +278,7 @@
*/
/** @brief Check whether or not the specified HASH flag is set.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
@@ -291,7 +293,7 @@
/** @brief Clear the specified HASH flag.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
@@ -301,7 +303,7 @@
/** @brief Enable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to enable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -310,7 +312,7 @@
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
- * @param __INTERRUPT__: specifies the HASH interrupt source to disable.
+ * @param __INTERRUPT__ specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
@@ -319,7 +321,7 @@
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
@@ -335,7 +337,7 @@
/** @brief Reset HASH handle status.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
@@ -362,7 +364,7 @@
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
- * @param __SIZE__: size in bytes of last data written in Data register.
+ * @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
@@ -401,7 +403,7 @@
/**
* @brief Ensure that HASH input data type is valid.
- * @param __DATATYPE__: HASH input data type.
+ * @param __DATATYPE__ HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
@@ -409,21 +411,11 @@
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
-
-
-/**
- * @brief Ensure that input data buffer size is valid for multi-buffer HASH
- * processing in polling mode.
- * @note This check is valid only for multi-buffer HASH processing in polling mode.
- * @param __SIZE__: input data buffer size.
- * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
- */
-#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
- * @param __SIZE__: input data buffer size.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
@@ -432,21 +424,21 @@
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
- * @param __HANDLE__: HASH handle.
- * @param __SIZE__: input data buffer size.
+ * @param __HANDLE__ HASH handle.
+ * @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
- * @param __HANDLE__: HASH handle.
+ * @param __HANDLE__ HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
@@ -496,8 +488,11 @@
/* HASH processing using polling *********************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
/**
* @}
@@ -509,7 +504,11 @@
/* HASH processing using IT **************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@@ -595,6 +594,7 @@
/* Private functions */
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
diff --git a/Inc/stm32f4xx_hal_hash_ex.h b/Inc/stm32f4xx_hal_hash_ex.h
index e594b63..658a727 100644
--- a/Inc/stm32f4xx_hal_hash_ex.h
+++ b/Inc/stm32f4xx_hal_hash_ex.h
@@ -52,9 +52,11 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -65,7 +67,11 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
diff --git a/Inc/stm32f4xx_hal_i2c.h b/Inc/stm32f4xx_hal_i2c.h
index 2f3f947..db290c2 100644
--- a/Inc/stm32f4xx_hal_i2c.h
+++ b/Inc/stm32f4xx_hal_i2c.h
@@ -170,6 +170,7 @@
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
+#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
diff --git a/Inc/stm32f4xx_hal_i2s.h b/Inc/stm32f4xx_hal_i2s.h
index 6530a5c..2d96315 100644
--- a/Inc/stm32f4xx_hal_i2s.h
+++ b/Inc/stm32f4xx_hal_i2s.h
@@ -286,7 +286,8 @@
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
-#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
+#define I2S_FLAG_MASK (SPI_SR_RXNE\
+ | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
@@ -337,7 +338,7 @@
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
@@ -383,7 +384,8 @@
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
@@ -405,19 +407,19 @@
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg_udr = 0x00U;\
- tmpreg_udr = ((__HANDLE__)->Instance->SR);\
- UNUSED(tmpreg_udr); \
+ __IO uint32_t tmpreg_udr = 0x00U;\
+ tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg_udr); \
}while(0U)
/**
* @}
@@ -442,7 +444,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
@@ -497,14 +500,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
@@ -522,7 +517,8 @@
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
-#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
+ & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 regsiter.
@@ -533,7 +529,8 @@
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
@@ -561,7 +558,7 @@
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
- ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
@@ -572,7 +569,7 @@
* @retval None
*/
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
- ((__CPOL__) == I2S_CPOL_HIGH))
+ ((__CPOL__) == I2S_CPOL_HIGH))
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
diff --git a/Inc/stm32f4xx_hal_i2s_ex.h b/Inc/stm32f4xx_hal_i2s_ex.h
index 19cd806..872283b 100644
--- a/Inc/stm32f4xx_hal_i2s_ex.h
+++ b/Inc/stm32f4xx_hal_i2s_ex.h
@@ -74,7 +74,8 @@
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2SExt flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
@@ -96,19 +97,19 @@
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
- tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
- UNUSED(tmpreg_ovr); \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
+ tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_udr = 0x00U; \
- tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
- UNUSED(tmpreg_udr); \
+ __IO uint32_t tmpreg_udr = 0x00U; \
+ tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
+ UNUSED(tmpreg_udr); \
}while(0U)
/**
* @}
diff --git a/Inc/stm32f4xx_hal_irda.h b/Inc/stm32f4xx_hal_irda.h
index b30945e..a393555 100644
--- a/Inc/stm32f4xx_hal_irda.h
+++ b/Inc/stm32f4xx_hal_irda.h
@@ -642,11 +642,11 @@
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
-#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define IRDA_DIV(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*(((uint64_t)(_BAUD_))))))
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
diff --git a/Inc/stm32f4xx_hal_lptim.h b/Inc/stm32f4xx_hal_lptim.h
index 39a8164..0bce87b 100644
--- a/Inc/stm32f4xx_hal_lptim.h
+++ b/Inc/stm32f4xx_hal_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM HAL module.
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -376,6 +377,8 @@
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
+ * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
+ * check for TIMEOUT.
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
@@ -398,6 +401,7 @@
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* @retval None
+ * @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
@@ -406,6 +410,7 @@
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value
* @retval None
+ * @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
@@ -454,6 +459,7 @@
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
@@ -470,6 +476,7 @@
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
@@ -525,6 +532,7 @@
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#if defined(EXTI_IMR_MR23)
/**
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
@@ -583,6 +591,7 @@
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#endif /* EXTI_IMR_MR23 */
/**
* @}
@@ -593,6 +602,10 @@
* @{
*/
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -600,7 +613,14 @@
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -649,12 +669,26 @@
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -672,9 +706,19 @@
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Group5
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
/**
* @}
@@ -778,7 +822,7 @@
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
-void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
diff --git a/Inc/stm32f4xx_hal_ltdc.h b/Inc/stm32f4xx_hal_ltdc.h
index a862f2c..0cab844 100644
--- a/Inc/stm32f4xx_hal_ltdc.h
+++ b/Inc/stm32f4xx_hal_ltdc.h
@@ -25,11 +25,10 @@
extern "C" {
#endif
-#if defined (LTDC)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined (LTDC)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
diff --git a/Inc/stm32f4xx_hal_ltdc_ex.h b/Inc/stm32f4xx_hal_ltdc_ex.h
index b46457f..37a5fdf 100644
--- a/Inc/stm32f4xx_hal_ltdc_ex.h
+++ b/Inc/stm32f4xx_hal_ltdc_ex.h
@@ -25,10 +25,11 @@
extern "C" {
#endif
-#if defined (LTDC) && defined (DSI)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+
+#if defined (LTDC) && defined (DSI)
+
#include "stm32f4xx_hal_dsi.h"
/** @addtogroup STM32F4xx_HAL_Driver
diff --git a/Inc/stm32f4xx_hal_mmc.h b/Inc/stm32f4xx_hal_mmc.h
index 90a44be..a7cd8be 100644
--- a/Inc/stm32f4xx_hal_mmc.h
+++ b/Inc/stm32f4xx_hal_mmc.h
@@ -12,25 +12,21 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_MMC_H
-#define __STM32F4xx_HAL_MMC_H
+#ifndef STM32F4xx_HAL_MMC_H
+#define STM32F4xx_HAL_MMC_H
+
+#if defined(SDIO)
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_sdmmc.h"
@@ -38,8 +34,7 @@
* @{
*/
-/** @defgroup MMC MMC
- * @brief MMC HAL module driver
+/** @addtogroup MMC
* @{
*/
@@ -69,18 +64,17 @@
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
-typedef enum
-{
- HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
- HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
- HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
- HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
- HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
- HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
- HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
- HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
- HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
-}HAL_MMC_CardStateTypeDef;
+typedef uint32_t HAL_MMC_CardStateTypeDef;
+
+#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@@ -121,17 +115,17 @@
typedef struct
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
- uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
- uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
@@ -146,11 +140,12 @@
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
-
+
uint32_t CSD[4U]; /*!< MMC card specific data table */
uint32_t CID[4U]; /*!< MMC card identification number table */
- #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
@@ -199,7 +194,7 @@
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@@ -234,28 +229,8 @@
* @}
*/
-/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
- * @{
- */
-typedef struct
-{
- __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
- __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
- __IO uint16_t CardType; /*!< Carries information about card type */
- __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
- __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
- __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
-
-}HAL_MMC_CardStatusTypeDef;
-/**
- * @}
- */
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback ID enumeration definition
+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
* @{
*/
typedef enum
@@ -268,15 +243,15 @@
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
}HAL_MMC_CallbackIDTypeDef;
-/**
+/**
* @}
*/
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
* @{
*/
typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
-/**
+/**
* @}
*/
#endif
@@ -289,9 +264,7 @@
* @{
*/
-#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
+#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
@@ -332,6 +305,7 @@
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
@@ -339,16 +313,16 @@
* @}
*/
-/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
* @{
*/
-#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@@ -372,8 +346,9 @@
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
-#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
-#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
+#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
+#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
+
/**
* @}
*/
@@ -427,8 +402,8 @@
/**
* @brief Enable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -438,7 +413,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -458,8 +433,8 @@
/**
* @brief Disable the MMC device interrupt.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -469,7 +444,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -489,8 +464,8 @@
/**
* @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -500,7 +475,7 @@
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -520,8 +495,8 @@
/**
* @brief Clear the MMC's pending flags.
- * @param __HANDLE__ MMC Handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -531,7 +506,7 @@
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @retval None
@@ -540,8 +515,8 @@
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -551,7 +526,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -571,8 +546,8 @@
/**
* @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__ MMC Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -582,7 +557,12 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
@@ -605,6 +585,7 @@
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+
/**
* @}
*/
@@ -652,9 +633,9 @@
* @{
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
@@ -740,6 +721,7 @@
* @}
*/
+
/**
* @}
*/
@@ -752,15 +734,12 @@
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
#ifdef __cplusplus
}
#endif
+#endif /* SDIO */
-#endif /* __STM32F4xx_HAL_MMC_H */
+#endif /* STM32F4xx_HAL_MMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_rng.h b/Inc/stm32f4xx_hal_rng.h
index a7b1a59..d2c9937 100644
--- a/Inc/stm32f4xx_hal_rng.h
+++ b/Inc/stm32f4xx_hal_rng.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_RNG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
diff --git a/Inc/stm32f4xx_hal_sai.h b/Inc/stm32f4xx_hal_sai.h
index 16cbccf..ce2d50e 100644
--- a/Inc/stm32f4xx_hal_sai.h
+++ b/Inc/stm32f4xx_hal_sai.h
@@ -104,9 +104,10 @@
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
- uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
- AudioFrequency the user choice
- This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
+ uint32_t Mckdiv; /*!< Specifies the master clock divider.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is used only if AudioFrequency is set to
+ SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
diff --git a/Inc/stm32f4xx_hal_sd.h b/Inc/stm32f4xx_hal_sd.h
index edf33c1..2e254f1 100644
--- a/Inc/stm32f4xx_hal_sd.h
+++ b/Inc/stm32f4xx_hal_sd.h
@@ -12,24 +12,20 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SD_H
-#define __STM32F4xx_HAL_SD_H
+#ifndef STM32F4xx_HAL_SD_H
+#define STM32F4xx_HAL_SD_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(SDIO)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_sdmmc.h"
@@ -58,7 +54,7 @@
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
- HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
+ HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
}HAL_SD_StateTypeDef;
@@ -69,18 +65,17 @@
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
-typedef enum
-{
- HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
- HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
- HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
- HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
- HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
- HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
- HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
- HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
- HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
-}HAL_SD_CardStateTypeDef;
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
+#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
@@ -117,7 +112,11 @@
/**
* @brief SD handle Structure definition
*/
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
{
SD_TypeDef *Instance; /*!< SD registers base address */
@@ -125,11 +124,11 @@
HAL_LockTypeDef Lock; /*!< SD locking object */
- uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
- uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
@@ -139,9 +138,9 @@
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
-
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
@@ -149,7 +148,7 @@
uint32_t CID[4]; /*!< SD card identification number table */
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
@@ -157,7 +156,7 @@
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}SD_HandleTypeDef;
/**
@@ -198,7 +197,7 @@
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
@@ -206,7 +205,6 @@
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-
}HAL_SD_CardCSDTypeDef;
/**
* @}
@@ -254,7 +252,7 @@
* @}
*/
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
* @{
*/
@@ -279,7 +277,7 @@
/**
* @}
*/
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -331,10 +329,9 @@
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
-
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -342,13 +339,13 @@
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
*/
-#define SD_CONTEXT_NONE 0x00000000U /*!< None */
-#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+#define SD_CONTEXT_NONE 0x00000000U /*!< None */
+#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
@@ -357,8 +354,8 @@
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
-#define CARD_SDSC 0x00000000U
-#define CARD_SDHC_SDXC 0x00000001U
+#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */
+#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
#define CARD_SECURED 0x00000003U
/**
@@ -387,7 +384,7 @@
* @param __HANDLE__ : SD handle.
* @retval None
*/
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
@@ -395,7 +392,7 @@
} while(0)
#else
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @brief Enable the SD device.
@@ -423,8 +420,8 @@
/**
* @brief Enable the SD device interrupt.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -434,7 +431,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -447,15 +444,15 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -465,7 +462,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -478,15 +475,15 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
- * @param __HANDLE__ SD Handle
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -496,7 +493,7 @@
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -509,15 +506,15 @@
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SD FLAG (SET or RESET).
*/
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
- * @param __HANDLE__ SD Handle
- * @param __FLAG__ specifies the flag to clear.
+ * @param __HANDLE__: SD Handle
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -527,17 +524,17 @@
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -547,7 +544,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -560,15 +557,15 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SD IT (SET or RESET).
*/
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__ SD Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__: SD Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -578,8 +575,8 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
@@ -627,11 +624,12 @@
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* SD callback registering/unregistering */
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -751,15 +749,13 @@
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* SDIO */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_SD_H */
+#endif /* STM32F4xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_smartcard.h b/Inc/stm32f4xx_hal_smartcard.h
index d329ac8..75e3383 100644
--- a/Inc/stm32f4xx_hal_smartcard.h
+++ b/Inc/stm32f4xx_hal_smartcard.h
@@ -718,9 +718,9 @@
((NACK) == SMARTCARD_NACK_DISABLE))
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
-#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__)))
+#define SMARTCARD_DIV(__PCLK__, __BAUD__) ((uint32_t)((((uint64_t)(__PCLK__))*25U)/(4U*((uint64_t)(__BAUD__)))))
#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U)
+#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U)
/* SMARTCARD BRR = mantissa + overflow + fraction
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
diff --git a/Inc/stm32f4xx_hal_spi.h b/Inc/stm32f4xx_hal_spi.h
index c220b21..41903da 100644
--- a/Inc/stm32f4xx_hal_spi.h
+++ b/Inc/stm32f4xx_hal_spi.h
@@ -319,7 +319,8 @@
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
+#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
+ | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
/**
* @}
*/
@@ -346,7 +347,7 @@
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
@@ -382,7 +383,8 @@
* @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__ specifies the SPI Handle.
@@ -440,9 +442,9 @@
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg_fre = 0x00U; \
- tmpreg_fre = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_fre); \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
}while(0U)
/** @brief Enable the SPI peripheral.
diff --git a/Inc/stm32f4xx_hal_tim.h b/Inc/stm32f4xx_hal_tim.h
index 9f79ad9..d6f1a1a 100644
--- a/Inc/stm32f4xx_hal_tim.h
+++ b/Inc/stm32f4xx_hal_tim.h
@@ -167,7 +167,7 @@
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -179,7 +179,7 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -231,7 +231,12 @@
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
+ This parameter can be a value of @ref TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the effect of
+ an event on the trigger input (TRGI) is delayed to allow a
+ perfect synchronization between the current timer and its
+ slaves (through TRGO). It is not mandatory in case of timer
+ synchronization mode. */
} TIM_MasterConfigTypeDef;
/**
@@ -588,6 +593,15 @@
* @}
*/
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@@ -1020,15 +1034,15 @@
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
/**
* @brief Disable the TIM main Output.
@@ -1037,15 +1051,15 @@
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
/**
* @brief Disable the TIM main Output.
@@ -1172,7 +1186,8 @@
* @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+ == (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
@@ -1220,8 +1235,7 @@
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
- ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
@@ -1230,18 +1244,17 @@
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
/**
* @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
- ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
@@ -1254,11 +1267,11 @@
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
/**
* @brief Get the TIM Clock Division value on runtime.
@@ -1268,8 +1281,7 @@
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
@@ -1289,10 +1301,10 @@
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
/**
* @brief Get the TIM Input Capture prescaler on runtime.
@@ -1328,10 +1340,10 @@
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
@@ -1345,10 +1357,10 @@
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__HANDLE__)->Instance->CCR4))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__HANDLE__)->Instance->CCR4))
/**
* @brief Set the TIM Output compare preload.
@@ -1362,10 +1374,10 @@
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
/**
* @brief Reset the TIM Output compare preload.
@@ -1379,10 +1391,52 @@
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1392,8 +1446,7 @@
* enabled)
* @retval None
*/
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1406,8 +1459,7 @@
* _ Update generation through the slave mode controller
* @retval None
*/
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
* @brief Set the TIM Capture x input polarity on runtime.
@@ -1425,10 +1477,10 @@
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
/**
* @}
@@ -1504,6 +1556,9 @@
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@@ -1681,28 +1736,28 @@
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/**
* @}
@@ -1840,7 +1895,8 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@@ -1864,17 +1920,19 @@
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -1900,7 +1958,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -1930,8 +1989,8 @@
/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
-* @{
-*/
+ * @{
+ */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@@ -1950,8 +2009,8 @@
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
-* @}
-*/
+ * @}
+ */
/* End of private functions --------------------------------------------------*/
/**
diff --git a/Inc/stm32f4xx_hal_tim_ex.h b/Inc/stm32f4xx_hal_tim_ex.h
index 69b4ca3..88ce281 100644
--- a/Inc/stm32f4xx_hal_tim_ex.h
+++ b/Inc/stm32f4xx_hal_tim_ex.h
@@ -202,9 +202,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- * @{
- */
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
@@ -226,9 +226,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -246,9 +246,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- * @{
- */
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -265,9 +265,9 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@@ -281,15 +281,20 @@
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
+ * @brief Peripheral Control functions
+ * @{
+ */
/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
@@ -323,7 +328,7 @@
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
diff --git a/Inc/stm32f4xx_hal_uart.h b/Inc/stm32f4xx_hal_uart.h
index bd47cfb..2154a02 100644
--- a/Inc/stm32f4xx_hal_uart.h
+++ b/Inc/stm32f4xx_hal_uart.h
@@ -535,7 +535,7 @@
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-/** @brief Checks whether the specified UART interrupt has occurred or not.
+/** @brief Checks whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
@@ -798,22 +798,22 @@
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_)))))
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
- ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
+ ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
/**
diff --git a/Inc/stm32f4xx_hal_usart.h b/Inc/stm32f4xx_hal_usart.h
index fa2f1dd..8664355 100644
--- a/Inc/stm32f4xx_hal_usart.h
+++ b/Inc/stm32f4xx_hal_usart.h
@@ -603,11 +603,11 @@
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 12500000U)
-#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define USART_DIV(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
-#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
diff --git a/Inc/stm32f4xx_hal_wwdg.h b/Inc/stm32f4xx_hal_wwdg.h
index fbc628c..05640af 100644
--- a/Inc/stm32f4xx_hal_wwdg.h
+++ b/Inc/stm32f4xx_hal_wwdg.h
@@ -22,7 +22,7 @@
#define STM32F4xx_HAL_WWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -89,12 +89,12 @@
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
-}HAL_WWDG_CallbackIDTypeDef;
+} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif
/**
@@ -239,7 +239,8 @@
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
@@ -294,6 +295,6 @@
}
#endif
-#endif /* __STM32F4xx_HAL_WWDG_H */
+#endif /* STM32F4xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_ll_gpio.h b/Inc/stm32f4xx_ll_gpio.h
index 3f1b3a1..8ff86ac 100644
--- a/Inc/stm32f4xx_ll_gpio.h
+++ b/Inc/stm32f4xx_ll_gpio.h
@@ -340,10 +340,11 @@
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
{
- MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+ MODIFY_REG(GPIOx->OTYPER, (GPIO_OTYPER_OT_0 << POSITION_VAL(Pin)), (OutputType << POSITION_VAL(Pin)));
}
+
/**
* @brief Return gpio output type for several pins on dedicated port.
diff --git a/Inc/stm32f4xx_ll_lptim.h b/Inc/stm32f4xx_ll_lptim.h
index 636e5fa..1b6bad9 100644
--- a/Inc/stm32f4xx_ll_lptim.h
+++ b/Inc/stm32f4xx_ll_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM LL module.
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -258,6 +258,19 @@
/**
* @}
*/
+#if defined(LPTIM_OR_OR)
+
+/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
+ * @{
+ */
+#define LL_LPTIM_INPUT1_SRC_PAD_AF 0x00000000U
+#define LL_LPTIM_INPUT1_SRC_PAD_PA4 LPTIM_OR_OR_0
+#define LL_LPTIM_INPUT1_SRC_PAD_PB9 LPTIM_OR_OR_1
+#define LL_LPTIM_INPUT1_SRC_TIM_DAC LPTIM_OR_OR
+/**
+ * @}
+ */
+#endif /* LPTIM_OR_OR */
/**
* @}
@@ -340,7 +353,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@@ -394,7 +407,7 @@
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
* @note After a write to the LPTIMx_ARR register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the ARROK flag be set, will
+ * is completed. Any successive write before the ARROK flag is set, will
* lead to unpredictable results.
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
@@ -422,7 +435,7 @@
* @brief Set the compare value
* @note After a write to the LPTIMx_CMP register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the CMPOK flag be set, will
+ * is completed. Any successive write before the CMPOK flag is set, will
* lead to unpredictable results.
* @rmtoll CMP CMP LL_LPTIM_SetCompare
* @param LPTIMx Low-Power Timer instance
@@ -607,6 +620,24 @@
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
+#if defined(LPTIM_OR_OR)
+
+/**
+ * @brief Set LPTIM input 1 source (default GPIO).
+ * @rmtoll OR OR LL_LPTIM_SetInput1Src
+ * @param LPTIMx Low-Power Timer instance
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_AF
+ * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PA4
+ * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PB9
+ * @arg @ref LL_LPTIM_INPUT1_SRC_TIM_DAC
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
+{
+ MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
+}
+#endif /* LPTIM_OR_OR */
/**
* @}
@@ -655,7 +686,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@@ -914,7 +945,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@@ -944,7 +975,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@@ -966,7 +997,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@@ -988,7 +1019,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@@ -1010,7 +1041,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@@ -1032,7 +1063,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@@ -1054,7 +1085,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@@ -1076,7 +1107,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@@ -1117,7 +1148,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@@ -1150,7 +1181,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@@ -1183,7 +1214,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@@ -1216,7 +1247,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@@ -1245,11 +1276,11 @@
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@@ -1278,11 +1309,11 @@
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@@ -1311,11 +1342,11 @@
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
diff --git a/Inc/stm32f4xx_ll_sdmmc.h b/Inc/stm32f4xx_ll_sdmmc.h
index 026da3c..c966c90 100644
--- a/Inc/stm32f4xx_ll_sdmmc.h
+++ b/Inc/stm32f4xx_ll_sdmmc.h
@@ -12,24 +12,20 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_SDMMC_H
-#define __STM32F4xx_LL_SDMMC_H
+#ifndef STM32F4xx_LL_SDMMC_H
+#define STM32F4xx_LL_SDMMC_H
#ifdef __cplusplus
extern "C" {
#endif
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+#if defined(SDIO)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -133,196 +129,197 @@
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
-#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
-#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
-#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
-#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
-#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
-#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
-#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
-#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
-#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
-#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
-#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
-#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
-#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
-#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
-#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
-#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
-#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
-#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
-#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
-#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
-#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
-#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
-#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
-#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
-#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
-#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
-#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
+#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
+#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
+#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
+#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
+#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
+#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
+#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
+#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
+#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
+#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
+#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
+#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
+#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
+#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
+#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
+#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
+#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
+#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
+#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
+#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
/**
* @brief SDMMC Commands Index
*/
-#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
-#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
-#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
-#define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
-#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
-#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
-#define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
-#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
-#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
-#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
-#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */
-#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */
+#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */
+#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */
+#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */
+#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */
+#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */
+#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */
+#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
+#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by
STOP_TRANSMISSION command. */
-#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
-#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */
+#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
-#define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
-#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
-#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
-#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
-#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
-#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
-#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
+#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */
+#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */
+#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */
+#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */
+#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command
system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
+#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased.
Reserved for each command system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
-#define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */
+#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
+#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather
than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
+#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card
for general purpose/application specific commands. */
-#define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */
+#define SDMMC_CMD_NO_CMD 64U /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
-#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
send its operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
-#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
-#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
+#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */
+#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
-#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
-#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
-#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
-#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
-#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
-#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
+#define SDMMC_CMD_SD_APP_GET_MKB 43U
+#define SDMMC_CMD_SD_APP_GET_MID 44U
+#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U
+#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U
+#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U
+#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U
+#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U
/**
* @brief Masks for errors Card Status R1 (OCR Register)
*/
-#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
-#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
-#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
-#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
-#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
-#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
-#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
-#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
-#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
-#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
-#define SDMMC_OCR_CC_ERROR 0x00100000U
-#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
-#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
-#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
-#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
-#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
-#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
-#define SDMMC_OCR_ERASE_RESET 0x00002000U
-#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
-#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
+#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
+#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
+#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
+#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
+#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
+#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
+#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
+#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
+#define SDMMC_OCR_CC_ERROR 0x00100000U
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
+#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
+#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
+#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
+#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
+#define SDMMC_OCR_ERASE_RESET 0x00002000U
+#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
+#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
/**
* @brief Masks for R6 Response
*/
-#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
-#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
-#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
+#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
+#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
-#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
-#define SDMMC_HIGH_CAPACITY 0x40000000U
-#define SDMMC_STD_CAPACITY 0x00000000U
-#define SDMMC_CHECK_PATTERN 0x000001AAU
+#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
+#define SDMMC_HIGH_CAPACITY 0x40000000U
+#define SDMMC_STD_CAPACITY 0x00000000U
+#define SDMMC_CHECK_PATTERN 0x000001AAU
+#define SD_SWITCH_1_8V_CAPACITY 0x01000000U
-#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
-
-#define SDMMC_MAX_TRIAL 0x0000FFFFU
-
-#define SDMMC_ALLZERO 0x00000000U
+#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
-#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
-#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
-#define SDMMC_CARD_LOCKED 0x02000000U
+#define SDMMC_MAX_TRIAL 0x0000FFFFU
-#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+#define SDMMC_ALLZERO 0x00000000U
-#define SDMMC_0TO7BITS 0x000000FFU
-#define SDMMC_8TO15BITS 0x0000FF00U
-#define SDMMC_16TO23BITS 0x00FF0000U
-#define SDMMC_24TO31BITS 0xFF000000U
-#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
+#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
+#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
+#define SDMMC_CARD_LOCKED 0x02000000U
-#define SDMMC_HALFFIFO 0x00000008U
-#define SDMMC_HALFFIFOBYTES 0x00000020U
+#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+
+#define SDMMC_0TO7BITS 0x000000FFU
+#define SDMMC_8TO15BITS 0x0000FF00U
+#define SDMMC_16TO23BITS 0x00FF0000U
+#define SDMMC_24TO31BITS 0xFF000000U
+#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
+
+#define SDMMC_HALFFIFO 0x00000008U
+#define SDMMC_HALFFIFOBYTES 0x00000020U
/**
* @brief Command Class supported
*/
-#define SDIO_CCCC_ERASE 0x00000020U
+#define SDIO_CCCC_ERASE 0x00000020U
-#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
-#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
-
+#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
+#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
+#define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */
/** @defgroup SDIO_LL_Clock_Edge Clock Edge
* @{
@@ -331,7 +328,7 @@
#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
- ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+ ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
/**
* @}
*/
@@ -343,7 +340,7 @@
#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
- ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+ ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
/**
* @}
*/
@@ -355,7 +352,7 @@
#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
- ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+ ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
/**
* @}
*/
@@ -368,8 +365,8 @@
#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
- ((WIDE) == SDIO_BUS_WIDE_4B) || \
- ((WIDE) == SDIO_BUS_WIDE_8B))
+ ((WIDE) == SDIO_BUS_WIDE_4B) || \
+ ((WIDE) == SDIO_BUS_WIDE_8B))
/**
* @}
*/
@@ -381,7 +378,7 @@
#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
- ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+ ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
/**
* @}
*/
@@ -410,8 +407,8 @@
#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
- ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
- ((RESPONSE) == SDIO_RESPONSE_LONG))
+ ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+ ((RESPONSE) == SDIO_RESPONSE_LONG))
/**
* @}
*/
@@ -424,8 +421,8 @@
#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
- ((WAIT) == SDIO_WAIT_IT) || \
- ((WAIT) == SDIO_WAIT_PEND))
+ ((WAIT) == SDIO_WAIT_IT) || \
+ ((WAIT) == SDIO_WAIT_PEND))
/**
* @}
*/
@@ -437,7 +434,7 @@
#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
- ((CPSM) == SDIO_CPSM_ENABLE))
+ ((CPSM) == SDIO_CPSM_ENABLE))
/**
* @}
*/
@@ -451,9 +448,9 @@
#define SDIO_RESP4 0x0000000CU
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
- ((RESP) == SDIO_RESP2) || \
- ((RESP) == SDIO_RESP3) || \
- ((RESP) == SDIO_RESP4))
+ ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || \
+ ((RESP) == SDIO_RESP4))
/**
* @}
*/
@@ -486,20 +483,20 @@
#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+ ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
/**
* @}
*/
@@ -508,10 +505,10 @@
* @{
*/
#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
-#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
+#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
- ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+ ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
/**
* @}
*/
@@ -523,7 +520,7 @@
#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
- ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+ ((MODE) == SDIO_TRANSFER_MODE_STREAM))
/**
* @}
*/
@@ -535,7 +532,7 @@
#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
- ((DPSM) == SDIO_DPSM_ENABLE))
+ ((DPSM) == SDIO_DPSM_ENABLE))
/**
* @}
*/
@@ -547,7 +544,7 @@
#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
- ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+ ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
/**
* @}
*/
@@ -555,30 +552,34 @@
/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
* @{
*/
-#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
-#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
-#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
-#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
-#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
-#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
-#define SDIO_IT_CMDREND SDIO_STA_CMDREND
-#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
-#define SDIO_IT_DATAEND SDIO_STA_DATAEND
-#define SDIO_IT_STBITERR SDIO_STA_STBITERR
-#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
-#define SDIO_IT_CMDACT SDIO_STA_CMDACT
-#define SDIO_IT_TXACT SDIO_STA_TXACT
-#define SDIO_IT_RXACT SDIO_STA_RXACT
-#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
-#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
-#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
-#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
-#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
-#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
-#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
-#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
-#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
-#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
+#define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE
+#define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE
+#define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE
+#define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE
+#define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE
+#define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE
+#define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE
+#define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE
+#define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE
+#if defined(SDIO_STA_STBITERR)
+#define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE
+#endif
+#define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE
+#define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE
+#define SDIO_IT_TXACT SDIO_MASK_TXACTIE
+#define SDIO_IT_RXACT SDIO_MASK_RXACTIE
+#define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE
+#define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE
+#define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE
+#define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE
+#define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE
+#define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE
+#define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE
+#define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE
+#define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE
+#if defined(SDIO_CMD_CEATACMD)
+#define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE
+#endif
/**
* @}
*/
@@ -595,7 +596,9 @@
#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
+#if defined(SDIO_STA_STBITERR)
#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
+#endif
#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
#define SDIO_FLAG_TXACT SDIO_STA_TXACT
@@ -609,11 +612,19 @@
#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
+#if defined(SDIO_CMD_CEATACMD)
#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
+#endif
#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
- SDIO_FLAG_DBCKEND))
+ SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))
+
+#define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
+ SDIO_FLAG_CMDSENT))
+
+#define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
+ SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND))
/**
* @}
*/
@@ -705,11 +716,10 @@
SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
/* SDIO Initialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
+#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
/* SDIO Data Transfer Frequency (25MHz max) */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
-
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
/**
* @}
*/
@@ -721,35 +731,36 @@
/**
* @brief Enable the SDIO device.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
- */
+ */
#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
/**
* @brief Disable the SDIO device.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
/**
* @brief Enable the SDIO DMA transfer.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
- */
+ */
#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+
/**
* @brief Disable the SDIO DMA transfer.
- * @param __INSTANCE__ SDIO Instance
+ * @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
/**
* @brief Enable the SDIO device interrupt.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -759,7 +770,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -772,15 +783,15 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
/**
* @brief Disable the SDIO device interrupt.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -790,7 +801,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -803,15 +814,15 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified SDIO flag is set or not.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __FLAG__ specifies the flag to check.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -821,7 +832,7 @@
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -834,16 +845,16 @@
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SDIO_FLAG (SET or RESET).
*/
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
/**
* @brief Clears the SDIO pending flags.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __FLAG__ specifies the flag to clear.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
@@ -853,17 +864,17 @@
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
/**
* @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the SDIO interrupt source to check.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -873,7 +884,7 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -886,15 +897,15 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SDIO_IT (SET or RESET).
*/
#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the SDIO's interrupt pending bits.
- * @param __INSTANCE__ Pointer to SDIO register base
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __INSTANCE__ : Pointer to SDIO register base
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -904,71 +915,69 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
/**
* @brief Disable Start the SD I/O Read Wait operations.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
/**
* @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
/**
* @brief Enable the SD I/O Mode Operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
/**
* @brief Disable the SD I/O Mode Operation.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
/**
* @brief Enable the SD I/O Suspend command sending.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
/**
* @brief Disable the SD I/O Suspend command sending.
- * @param __INSTANCE__ Pointer to SDIO register base
+ * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
- */
+ */
#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+
+#if defined(SDIO_CMD_CEATACMD)
/**
* @brief Enable the command completion signal.
* @retval None
@@ -1004,9 +1013,8 @@
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
+
+#endif
/**
* @}
*/
@@ -1066,7 +1074,9 @@
uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
@@ -1074,7 +1084,7 @@
uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
@@ -1082,11 +1092,8 @@
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
-
uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
/**
* @}
@@ -1104,14 +1111,12 @@
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* SDIO */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_LL_SDMMC_H */
+#endif /* STM32F4xx_LL_SDMMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_ll_spi.h b/Inc/stm32f4xx_ll_spi.h
index 13d1883..b8a330c 100644
--- a/Inc/stm32f4xx_ll_spi.h
+++ b/Inc/stm32f4xx_ll_spi.h
@@ -1056,7 +1056,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
- return (uint32_t) & (SPIx->DR);
+ return (uint32_t) &(SPIx->DR);
}
/**
@@ -1103,7 +1103,7 @@
*spidr = TxData;
#else
*((__IO uint8_t *)&SPIx->DR) = TxData;
-#endif
+#endif /* __GNUC__ */
}
/**
@@ -1120,7 +1120,7 @@
*spidr = TxData;
#else
SPIx->DR = TxData;
-#endif
+#endif /* __GNUC__ */
}
/**
diff --git a/Inc/stm32f4xx_ll_tim.h b/Inc/stm32f4xx_ll_tim.h
index fcdfd6e..57d2ec7 100644
--- a/Inc/stm32f4xx_ll_tim.h
+++ b/Inc/stm32f4xx_ll_tim.h
@@ -147,12 +147,12 @@
* @retval none
*/
#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
/** @brief Calculate the deadtime sampling period(in ps).
* @param __TIMCLK__ timer input clock frequency (in Hz).
@@ -163,9 +163,9 @@
* @retval none
*/
#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
/**
* @}
*/
@@ -878,6 +878,7 @@
* @{
*/
#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
+#define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
/**
@@ -899,7 +900,11 @@
* @{
*/
#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
-#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
+#if defined(SPDIFRX)
+#define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
+#else
+#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
+#endif
#define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
/**
@@ -954,11 +959,11 @@
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
- 0U)
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ 0U)
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
@@ -968,7 +973,7 @@
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -979,7 +984,7 @@
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
@@ -990,8 +995,8 @@
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
-((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
- / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
@@ -1003,8 +1008,8 @@
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
- + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro retrieving the ratio of the input capture prescaler
@@ -1017,7 +1022,7 @@
* @retval Input capture prescaler ratio (1, 2, 4 or 8)
*/
#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
/**
@@ -1166,7 +1171,7 @@
/**
* @brief Set the timer counter counting mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
@@ -1190,7 +1195,7 @@
/**
* @brief Get actual counter mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
@@ -1227,7 +1232,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE);
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
@@ -1243,7 +1248,7 @@
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
@@ -1261,7 +1266,7 @@
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
@@ -1278,7 +1283,7 @@
/**
* @brief Set the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
@@ -1292,7 +1297,7 @@
/**
* @brief Get the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
@@ -1346,7 +1351,7 @@
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* @rmtoll ARR ARR LL_TIM_SetAutoReload
@@ -1362,7 +1367,7 @@
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @param TIMx Timer instance
* @retval Auto-reload value
@@ -1374,7 +1379,7 @@
/**
* @brief Set the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
@@ -1388,7 +1393,7 @@
/**
* @brief Get the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
@@ -1411,7 +1416,7 @@
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
@@ -1424,7 +1429,7 @@
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
@@ -1437,7 +1442,7 @@
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
@@ -1481,7 +1486,7 @@
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
@@ -1735,7 +1740,7 @@
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
- * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
@@ -1927,7 +1932,7 @@
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
@@ -1950,7 +1955,7 @@
/**
* @brief Disable clearing the output channel on an external event.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
@@ -1975,7 +1980,7 @@
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
@@ -1999,7 +2004,7 @@
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
@@ -2015,9 +2020,9 @@
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
@@ -2032,9 +2037,9 @@
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
@@ -2049,9 +2054,9 @@
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
@@ -2066,9 +2071,9 @@
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
@@ -2083,9 +2088,9 @@
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
@@ -2099,9 +2104,9 @@
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
@@ -2115,9 +2120,9 @@
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
@@ -2131,9 +2136,9 @@
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
@@ -2430,7 +2435,7 @@
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
@@ -2443,7 +2448,7 @@
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
@@ -2456,7 +2461,7 @@
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
@@ -2470,9 +2475,9 @@
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
@@ -2486,9 +2491,9 @@
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
@@ -2502,9 +2507,9 @@
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
@@ -2518,9 +2523,9 @@
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
@@ -2541,7 +2546,7 @@
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
@@ -2554,7 +2559,7 @@
/**
* @brief Disable external clock mode 2.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
@@ -2567,7 +2572,7 @@
/**
* @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
@@ -2584,9 +2589,9 @@
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
@@ -2604,7 +2609,7 @@
/**
* @brief Set the encoder interface mode.
- * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
@@ -2628,7 +2633,7 @@
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
@@ -2650,7 +2655,7 @@
/**
* @brief Set the synchronization mode of a slave timer.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
@@ -2668,7 +2673,7 @@
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
@@ -2690,7 +2695,7 @@
/**
* @brief Enable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
@@ -2703,7 +2708,7 @@
/**
* @brief Disable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
@@ -2716,7 +2721,7 @@
/**
* @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
@@ -2729,7 +2734,7 @@
/**
* @brief Configure the external trigger (ETR) input.
- * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
@@ -2777,7 +2782,7 @@
*/
/**
* @brief Enable the break function.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
@@ -2796,7 +2801,7 @@
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
@@ -2811,7 +2816,7 @@
/**
* @brief Configure the break input.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK
* @param TIMx Timer instance
@@ -2831,7 +2836,7 @@
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
@@ -2851,7 +2856,7 @@
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
@@ -2864,7 +2869,7 @@
/**
* @brief Disable automatic output (MOE can be set only by software).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
@@ -2877,7 +2882,7 @@
/**
* @brief Indicate whether automatic output is enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
@@ -2892,7 +2897,7 @@
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
@@ -2907,7 +2912,7 @@
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
@@ -2920,7 +2925,7 @@
/**
* @brief Indicates whether outputs are enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
@@ -2940,7 +2945,7 @@
*/
/**
* @brief Configures the timer DMA burst feature.
- * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
@@ -2999,7 +3004,7 @@
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
- * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
@@ -3028,9 +3033,12 @@
* TIM11: one of the following values
*
* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
- * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
+ * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
+ *
+ * (*) Value not defined in all devices. \n
*
* @retval None
*/
diff --git a/Inc/stm32f4xx_ll_usart.h b/Inc/stm32f4xx_ll_usart.h
index c75c68f..eedcde8 100644
--- a/Inc/stm32f4xx_ll_usart.h
+++ b/Inc/stm32f4xx_ll_usart.h
@@ -357,9 +357,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
+#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__)))))
#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
+#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8) + 50) / 100)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
@@ -373,9 +373,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
-#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
+#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__)))))
#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
+#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100)
/* USART BRR = mantissa + overflow + fraction
= (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
diff --git a/Inc/stm32f4xx_ll_wwdg.h b/Inc/stm32f4xx_ll_wwdg.h
index 9fed6aa..f20b82d 100644
--- a/Inc/stm32f4xx_ll_wwdg.h
+++ b/Inc/stm32f4xx_ll_wwdg.h
@@ -58,8 +58,8 @@
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
+ * @{
+ */
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
@@ -175,7 +175,7 @@
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
-* @retval None
+ * @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
@@ -314,6 +314,6 @@
}
#endif
-#endif /* __STM32F4xx_LL_WWDG_H */
+#endif /* STM32F4xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/README.md b/README.md
index a7ecf09..e22273f 100644
--- a/README.md
+++ b/README.md
@@ -35,6 +35,7 @@
HAL Driver F4 | CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
Tag v1.7.6 | Tag v2.6.3 | Tag v5.4.0_cm4 | Tag v1.24.1 (and following, if any, till next new tag)
+Tag v1.7.7 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.24.2 (and following, if any, till next new tag)
The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4).
diff --git a/Release_Notes.html b/Release_Notes.html
index eb4de4a..0c67712 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -941,7 +941,85 @@
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
<tbody><tr><td style="padding: 0in;" valign="top">
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.6 / 12-April-2019</span></h3>
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.7 / 06-December-2019</span></h3>
+ <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p>
+
+
+
+<span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><ul style="margin-top: 0cm;" type="disc"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">General updates to fix known defects and
+ enhancements implementation</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL Generic </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_SetTickFreq(): update to restore the previous tick frequency when HAL_InitTick() configuration failed.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL/LL GPIO </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">GPIO initialization sequence</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"><span style="font-weight: bold;"> </span>to avoid unwanted pulse on GPIO Pin's</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL EXTI </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li></ul><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;"> </span><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">General update to enhance HAL EXTI driver robustness </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Add additional assert check on EXTI config lines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Update to compute EXTI line mask before read/write access to EXTI registers<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Update
+EXTI callbacks management to be compliant with reference manual: only
+one PR register for rising and falling interrupts.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Update
+parameters in EXTI_HandleTypeDef structure: merge HAL EXTI
+RisingCallback and FallingCallback in only one PendingCallback</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Remove HAL_EXTI_RISING_CB_ID and HAL_EXTI_FALLING_CB_ID values from </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">EXTI_CallbackIDTypeDef enumeration.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_EXTI_IRQHandler() API to serve </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">interrupts </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">correctly.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update to compute EXTI line mask before handle EXTI interrupt.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Update to support GPIO port interrupts:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Add new "GPIOSel" parameter in EXTI_ConfigTypeDef structure</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL/LL RCC </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_RCCEx_PeriphCLKConfig() API to support PLLI2S configuration for STM32F42xxx and STM32F43xxx devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update the HAL_RCC_ClockConfig() and HAL_RCC_DeInit() API to don't overwrite the custom tick priority</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Fix LL_RCC_DeInit() failure detected with gcc compiler and high optimization level is selected(-03)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_RCC_OscConfig() API to don't return HAL_ERROR if request repeats the current PLL configuration<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL ADC </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update LL_ADC_REG_Init() to fix wrong ADC CR1 register configuration</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">The ADC sequencer length is part of ADC SQR1 register not of </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">ADC CR1 register</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL CRYP </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_CRYP_Encrypt() and HAL_CRYP_Decrypt() APIs to take into
+consideration the datatype fed to the DIN register (1-, 8-, 16-, or
+32-bit data) when padding the last block of the payload, in case
+the size of this last block is less than 128 bits.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL RNG</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> update<span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RNG_IRQHandler() API to fix error code management issue: error code is
+assigned "HAL_RNG_ERROR_CLOCK" in case of clock error and
+"HAL_RNG_ERROR_SEED" in case of seed error, not the opposite.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DFSDM </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update DFSDM_GetChannelFromInstance() API to remove unreachable check condition</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_DMA_Start_IT() API to omit the FIFO error</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL FLASH </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update FLASH_Program_DoubleWord() API to fix with EWARM high level optimization issue</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL QSPI </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove Lock mechanism from HAL_QSPI_Init() and HAL_QSPI_DeInit() APIs</span> </li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL HASH </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Null pointer on handler "hhash" is now checked <span style="font-weight: bold;">before</span> accessing structure member "hhash->Init.DataType" in the following API:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_Init()</span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Following <span style="font-weight: bold;">interrupt-based</span> APIs have been added. Interrupt mode
+could allow the MCU to enter "Sleep" mode while a data block is being
+processed. Please refer to the "##### How to use this driver #####"
+section for details about their use.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_SHA1_Accmlt_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_MD5_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Accmlt</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA224_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Accmlt</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA256_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Accmlt</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">_IT()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Following <span style="font-weight: bold;">aliases</span> have been added (just <span style="font-weight: bold;">for clarity sake</span>) as they shall be used at the <span style="font-weight: bold;">end</span> of the computation of a multi-buffers message and not at the start:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_SHA1_Accmlt_End() to be used instead of HAL_HASH_SHA1_Start()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_MD5_Accmlt_End() to be used instead of HAL_HASH_MD5_Start()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_SHA1_Accmlt_End_IT() to be used instead of HAL_HASH_SHA1_Start_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_MD5_Accmlt_End_IT() to be used instead of HAL_HASH_MD5_Start_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA224_Accmlt_End() to be used instead of HAL_HASHEx_SHA224_Start()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA256_Accmlt_End() to be used instead of HAL_HASHEx_SHA256_Start()</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><ul style="margin-top: 0cm;" type="disc"><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA224_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA224_Start</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">_IT</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA256_Accmlt_End</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">_IT</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">() to be used instead of HAL_HASHEx_SHA256_Start</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">_IT</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">()</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">MISRAC-2012 rule R.5.1 </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">(identifiers shall be distinct in the first 31 characters)</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> constrained the naming of </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">the above listed aliases <span style="font-weight: bold;">(</span>e.g. </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA256_<span style="font-weight: bold;">Accmlt</span>_End() </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">could not be named </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA256_<span style="font-weight: bold;">Accumulate</span>_End()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">. Otherwise the name would have conflicted with </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA256_<span style="font-weight: bold;">Accumulate</span>_End_IT()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"><span style="font-weight: bold;">)</span>. In order to have aligned names following APIs have been renamed:</span></li></ul></ul><ul style="margin-top: 0cm;" type="disc"><ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_MD5_Accumulate() renamed HAL_HASH_MD5_Accmlt()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_SHA1_Accumulate() renamed HAL_HASH_SHA1_Accmlt()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA224_Accumulate() renamed HAL_HASHEx_SHA224_Accmlt()</span></li></ul></ul></ul></ul><ul style="margin-top: 0cm;" type="disc"><ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASHEx_SHA256_Accumulate() renamed HAL_HASHEx_SHA2</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">56</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">_Accmlt()</span></li></ul></ul></ul></ul><ul style="margin-top: 0cm;" type="disc"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HASH <span style="font-weight: bold;">handler</span> state is <span style="font-weight: bold;">no more</span> reset to HAL_HASH_STATE_READY <span style="font-weight: bold;">once DMA has been started</span> in the following APIs:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_MD5_Start_DMA()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HMAC_MD5_Start_DMA()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HASH_SHA1_Start_DMA()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_HMAC_SHA1_Start_DMA()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HASH <span style="font-weight: bold;">phase</span> state is now set to HAL_HASH_PHASE_READY <span style="font-weight: bold;">once the digest has been read</span> in the following APIs:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HASH_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HMAC_Processing()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HASH_Start()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HASH_Finish()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Case of a large buffer scattered around in
+memory each piece of which is <span style="font-weight: bold;">not</span> necessarily a <span style="font-weight: bold;">multiple of 4</span> bytes in length</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">In section "</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">##### How to use this driver #####</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">",
+sub-section "*** Remarks on message length ***" added to provide
+recommendations to follow in such case.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">No modification of the driver as the root-cause is at design-level.<br></span></li></ul></ul></ul><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span></b><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span></b><ul style="margin-top: 0cm;" type="disc"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL CAN </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_CAN_GetRxMessage()
+update to get the correct value for the RTR (type of frame for the
+message that will be transmitted) </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">field in the CAN_RxHeaderTypeDef structure.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL DCMI </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new HAL_DCMI_ConfigSyncUnmask() API to set embedded synchronization delimiters unmasks.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+
+<p class="MsoNormal"><span style="font-size: 12pt; font-family: Symbol;"></span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"></span><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL RTC</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></p>
+
+</li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Following
+ IRQ handlers' implementation has been aligned with the STM32Cube firmware
+ specification (in case of interrupt lines shared by multiple events, first
+ check the IT enable bit is set then check the IT flag is set too):</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><ul><ul style="margin-top: 0cm;" type="circle"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_RTC_AlarmIRQHandler()</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_RTCEx_WakeUpTimerIRQHandler()</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_RTCEx_TamperTimeStampIRQHandler()</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li></ul></ul></ul>
+<ul style="margin-top: 0cm;" type="disc"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"> </span><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL WWDG</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">In
+ "##### WWDG Specific features #####" descriptive comment
+ section:</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="circle"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Maximal
+ prescaler value has been corrected (8 instead of 128).</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Maximal
+ APB frequency has been corrected (42MHz instead of 56MHz) and possible
+ timeout values updated.</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL DMA2D </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="circle"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add the following API's to Start DMA2D CLUT Loading.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_CLUTStartLoad() Start DMA2D CLUT Loading.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_CLUTStartLoad_IT() Start DMA2D CLUT Loading with interrupt enabled.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">The following old wrong services will be kept in the HAL DCMI driver for legacy purpose and a specific Note is added:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_CLUTLoad() can be replaced with </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_CLUTStartLoad()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_CLUTLoad_IT() </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">can be replaced with </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_CLUTStartLoad_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_ConfigCLUT() can be omitted as the config can be performed using the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA2D_CLUTStartLoad() API.</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><ul style="margin-top: 0cm;" type="disc"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL SDMMC </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="circle"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri",sans-serif;" lang="EN-US">Fix
+typo in "FileFormatGroup" parameter in the HAL_MMC_CardCSDTypeDef and
+HAL_SD_CardCSDTypeDef structures </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Fix an improve handle state and error management</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Rename the defined MMC card capacity type to be more meaningful:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update <span style="font-weight: bold;">MMC_HIGH_VOLTAGE_CARD</span> to <span style="font-weight: bold;">MMC LOW_CAPACITY_CARD</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update <span style="font-weight: bold;">MMC_DUAL_VOLTAGE_CRAD</span> to <span style="font-weight: bold;">MMC_HIGH_CAPACITY_CARD</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Fix management of peripheral flags depending on commands or data transfers</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Add
+new defines "SDIO_STATIC_CMD_FLAGS" and "SDIO_STATIC_DATA_FLAGS" </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; display: inline ! important; float: none;">Updates HAL SD and HAL MMC drivers to manage the new SDIO static flags.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Due to limitation SDIO hardware flow control indicated in Errata Sheet:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">In
+4-bits bus wide mode, do not use the HAL_SD_WriteBlocks_IT() or
+HAL_SD_WriteBlocks() APIs otherwise underrun will occur and it isn't
+possible to activate the flow control.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Use DMA mode when using 4-bits bus wide mode or decrease the SDIO_CK frequency.</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL UART </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update UART polling processes to handle efficiently </span><span style="color: rgb(9, 112, 172); font-family: Montserrat,Arial,"sans serif"; font-size: 14px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; background-color: rgb(255, 255, 255); text-decoration: underline; display: inline ! important; float: none;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">the Lock mechanism</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Move the process unlock at the top of the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_UART_Receive() and HAL_UART_Transmit() API.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix baudrate calculation error
+for clock higher than 172Mhz</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add a forced cast on UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove
+useless parenthesis from UART_DIVFRAQ_SAMPLING8(),
+UART_DIVFRAQ_SAMPLING16(), UART_BRR_SAMPLING8() and
+UART_BRR_SAMPLING16() macros to solve some MISRA warnings.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update UART interruption handler to manage correctly the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">overrun interrupt</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">in the HAL_UART_IRQHandler() API a </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USART_CR1_RXNEIE bit when an overrun interrupt occurs.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix baudrate calculation error</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> UART9 and UART10</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">In </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">UART_SetConfig() API</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">fix
+UART9 and UART10 clock source when computing baudrate values by adding
+a check on these instances and setting clock sourcePCLK2 instead of
+PCLK1.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update UART_SetConfig() API</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Split
+HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the
+UART_BRR_SAMPLING8() and UART_BRR_SAMPLING8() macros </span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL USART </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix baudrate calculation error
+for clock higher than 172Mhz</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add a forced cast on USART_DIV() macro.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove useless </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">parenthesis</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> from USART_DIVFRAQ() macro to solve some MISRA warnings.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update USART interruption handler to manage correctly the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">overrun interrupt</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">in the HAL_USART_IRQHandler() API a </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USART_CR1_RXNEIE bit when an overrun interrupt occurs.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix baudrate calculation error</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> UART9 and UART10</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">In </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USART_SetConfig() API</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">fix
+UART9 and UART10 clock source when computing baudrate values by adding
+a check on these instances and setting clock sourcePCLK2 instead of
+PCLK1.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update USART_SetConfig() API</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the USART_BRR() macro</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL IRDA </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix baudrate calculation error
+for clock higher than 172Mhz</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add a forced cast on IRDA_DIV() macro.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove useless </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">parenthesis</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> from IRDA_DIVFRAQ() macro </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">to solve some MISRA warnings.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update IRDA interruption handler to manage correctly the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">overrun interrupt</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">in the HAL_IRDA_IRQHandler() API a </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USART_CR1_RXNEIE bit when an overrun interrupt occurs.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix baudrate calculation error</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> UART9 and UART10</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">In </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">IRDA_SetConfig() API</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">fix
+UART9 and UART10 clock source when computing baudrate values by adding
+a check on these instances and setting clock sourcePCLK2 instead of
+PCLK1.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update IRDA_SetConfig() API</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the IRDA_BRR() macro</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL SMARTCARD </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix baudrate calculation error
+for clock higher than 172Mhz</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add a forced cast on SMARTCARD_DIV() macro.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">useless </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">parenthesis</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> from SMARTCARD_DIVFRAQ() macro </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">to solve some MISRA warnings.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update SMARTCARD interruption handler to manage correctly the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">overrun interrupti</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">in the HAL_SMARTCARD_IRQHandler() API a </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USART_CR1_RXNEIE bit when an overrun interrupt occurs.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update SMARTCARD_SetConfig() API</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Split HAL_RCC_GetPCLK1Freq() and HAL_RCC_GetPCLK2Freq() macros from the SMARTCARD_BRR() macro</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL TIM </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update Encoder interface mode to keep </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">TIM_CCER_CCxNP bits low</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> definitions to determine encoder input polarity.</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">IS_TIM_ENCODERINPUT_POLARITY()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> macro to check the encoder input polarity.</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_TIM_Encoder_Init() API </span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update TIM remapping input configuration in HAL_TIMEx_RemapConfig() API</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Remove redundant check on </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">LPTIM_OR_TIM5_ITR1_RMP bit and replace it by check on </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">LPTIM_OR_TIM9_ITR1_RMP </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">bit.</span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> assert fails when using some TIM instances as input trigger.</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Replace </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro. </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add lacking TIM input remapping definition </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add LL_TIM_TIM11_TI1_RMP_SPDIFRX and LL_TIM_TIM2_ITR1_RMP_ETH_PTP.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add lacking definition for linked LPTIM_TIM input trigger remapping </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add
+following definitions : LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO,
+LL_TIM_TIM9_ITR1_RMP_LPTIM, LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO,
+LL_TIM_TIM5_ITR1_RMP_LPTIM, LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO and
+LL_TIM_TIM1_ITR2_RMP_LPTIM.</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add a new mechanism in LL_TIM_SetRemap() API to remap TIM1, TIM9, and TIM5 input triggers mapped on LPTIM register. </span></li></ul></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL LPTIM </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add a polling mechanism to check on </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LPTIM_FLAG_XXOK</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> flags in different API </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add LPTIM_WaitForFlag() </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">API </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">to wait for flag set.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Perform new checks on HAL_LPTIM_STATE_TIMEOUT.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add lacking definitions of LPTIM input trigger remapping and its related API</span></li><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">LL_LPTIM_INPUT1_SRC_PAD_AF, LL_LPTIM_INPUT1_SRC_PAD_PA4, LL_LPTIM_INPUT1_SRC_PAD_PB9 and LL_LPTIM_INPUT1_SRC_TIM_DAC.</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add a new API LL_LPTIM_SetInput1Src()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> to access to the LPTIM_OR register and remap the LPTIM input trigger.</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Perform a new check on indirect EXTI23 line associated to the LPTIM wake up timer</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Condition the use of </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">the LPTIM Wake-up Timer associated EXTI line configuration's macros by </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">EXTI_IMR_MR23 bit in different API :</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">__HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update</span> <span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_LPTIM_TimeOut_Start_IT(),
+HAL_LPTIM_TimeOut_Stop_IT(), HAL_LPTIM_Counter_Start_IT() and
+HAL_LPTIM_Counter_Stop_IT() API by adding Enable/Disable rising edge
+trigger on the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">LPTIM Wake-up Timer Exti line.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() in the end of the HAL_LPTIM_IRQHandler() API conditioned by EXTI_IMR_MR23 bit.</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL I2C </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_I2C_EV_IRQHandler() API to fix I2C send break issue </span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add additional check on hi2c->hdmatx, hdmatx->XferCpltCallback, </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">hi2c->hdmarx,
+hdmarx->XferCpltCallback in I2C_Master_SB() API to
+avoid enabling DMA request when IT mode is used.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">memory IT processes</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Add stop condition generation </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">when</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> NACK occurs.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Update </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_I2C_Init() API to force software reset before setting new I2C configuration</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL I2C processes to report ErrorCode </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">when wrong I2C start condition occurs</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Add new ErrorCode define: HAL_I2C_WRONG_START</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> Set</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">ErrorCode parameter in I2C handle to </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_I2C_WRONG_START</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 11pt; font-family: "Calibri",sans-serif; color: rgb(31, 73, 125);" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_DMAXferCplt(),
+I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when
+hdmatx and hdmarx parameters in i2c handle aren't initialized
+(NULL pointer).</span> </li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL FMPI2C </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix HAL FMPI2C slave interrupt handling issue with I2C sequential transfers.</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
+FMPI2C_Slave_ISR_IT() and FMPI2C_Slave_ISR_DMA() APIs to check on STOP
+condition and handle it before clearing the ADDR flag</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL NAND </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
+HAL_NAND_Write_Page_8b(), HAL_NAND_Write_Page_16b() and
+HAL_NAND_Write_SpareArea_16b() to manage correctly the time out
+condition.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL SAI </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Optimize SAI_DMATxCplt() and SAI_DMARxCplt() APIs to check on "Mode" parameter instead of CIRC bit in the CR register.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove unused SAI_FIFO_SIZE define</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_SAI_Receive_DMA() programming sequence to be inline with reference manual<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 274px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.6 / 12-April-2019</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
diff --git a/Src/Legacy/stm32f4xx_hal_can.c b/Src/Legacy/stm32f4xx_hal_can.c
index e2cc8f2..7a4cf53 100644
--- a/Src/Legacy/stm32f4xx_hal_can.c
+++ b/Src/Legacy/stm32f4xx_hal_can.c
@@ -82,13 +82,29 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
diff --git a/Src/stm32f4xx_hal.c b/Src/stm32f4xx_hal.c
index 22497fb..17a52b4 100644
--- a/Src/stm32f4xx_hal.c
+++ b/Src/stm32f4xx_hal.c
@@ -50,11 +50,11 @@
* @{
*/
/**
- * @brief STM32F4xx HAL Driver version number V1.7.6
+ * @brief STM32F4xx HAL Driver version number V1.7.7
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
@@ -341,14 +341,26 @@
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
+ HAL_TickFreqTypeDef prevTickFreq;
+
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
+
+ if (status != HAL_OK)
+ {
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
+ }
}
return status;
@@ -557,7 +569,7 @@
/**
* @brief Enables the Internal FLASH Bank Swapping.
*
- * @note This function can be used only for STM32F42xxx/43xxx devices.
+ * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
*
* @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
@@ -572,7 +584,7 @@
/**
* @brief Disables the Internal FLASH Bank Swapping.
*
- * @note This function can be used only for STM32F42xxx/43xxx devices.
+ * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
*
* @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
diff --git a/Src/stm32f4xx_hal_adc.c b/Src/stm32f4xx_hal_adc.c
index eb6c282..e218f76 100644
--- a/Src/stm32f4xx_hal_adc.c
+++ b/Src/stm32f4xx_hal_adc.c
@@ -467,7 +467,6 @@
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
- * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
* @param pCallback pointer to the Callback function
@@ -571,7 +570,6 @@
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
- * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
* @retval HAL status
diff --git a/Src/stm32f4xx_hal_adc_ex.c b/Src/stm32f4xx_hal_adc_ex.c
index 5d30e09..5d0cf7f 100644
--- a/Src/stm32f4xx_hal_adc_ex.c
+++ b/Src/stm32f4xx_hal_adc_ex.c
@@ -2,10 +2,10 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
+ * @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -15,8 +15,8 @@
(##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
(##) ADC pins configuration
(+++) Enable the clock for the ADC GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE()
- (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
+ __HAL_RCC_GPIOx_CLK_ENABLE()
+ (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
@@ -30,56 +30,44 @@
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream.
- (#) Configure the ADC Prescaler, conversion resolution and data alignment
- using the HAL_ADC_Init() function.
-
+ (#) Configure the ADC Prescaler, conversion resolution and data alignment
+ using the HAL_ADC_Init() function.
+
(#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
and HAL_ADC_ConfigChannel() functions.
-
- (#) Three operation modes are available within this driver :
-
+
+ (#) Three operation modes are available within this driver:
+
*** Polling mode IO operation ***
=================================
- [..]
- (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
+ [..]
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()
(+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
- user can specify the value of timeout according to his end application
+ user can specify the value of timeout according to his end application
(+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.
(+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()
-
- *** Interrupt mode IO operation ***
+
+ *** Interrupt mode IO operation ***
===================================
- [..]
- (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
+ [..]
+ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()
(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
- (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
+ (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
(+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()
-
-
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion
- (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
- (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback
- (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()
-
+
*** Multi mode ADCs Regular channels configuration ***
======================================================
- [..]
- (+) Select the Multi mode ADC regular channels features (dual or triple mode)
- and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
- (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
- of data to be transferred at each end of conversion
+ [..]
+ (+) Select the Multi mode ADC regular channels features (dual or triple mode)
+ and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
+ (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
-
-
+
+
@endverbatim
******************************************************************************
* @attention
@@ -93,7 +81,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
diff --git a/Src/stm32f4xx_hal_can.c b/Src/stm32f4xx_hal_can.c
index a2ccfd5..009a447 100644
--- a/Src/stm32f4xx_hal_can.c
+++ b/Src/stm32f4xx_hal_can.c
@@ -1556,7 +1556,7 @@
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
- pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
diff --git a/Src/stm32f4xx_hal_crc.c b/Src/stm32f4xx_hal_crc.c
index 2c499e5..18fc4bd 100644
--- a/Src/stm32f4xx_hal_crc.c
+++ b/Src/stm32f4xx_hal_crc.c
@@ -111,8 +111,6 @@
HAL_CRC_MspInit(hcrc);
}
- hcrc->State = HAL_CRC_STATE_BUSY;
-
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
diff --git a/Src/stm32f4xx_hal_cryp.c b/Src/stm32f4xx_hal_cryp.c
index cbcaa1c..907db4a 100644
--- a/Src/stm32f4xx_hal_cryp.c
+++ b/Src/stm32f4xx_hal_cryp.c
@@ -5756,9 +5756,8 @@
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
- /*Load CRYP_IV1R register content in a temporary variable. Decrement the value
- by 1 and reinsert the result in CRYP_IV1R register*/
- hcryp->Instance->IV1RR = 0x5U;
+ /*Update CRYP_IV1R register and ALGOMODE*/
+ hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1);
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
/* Enable CRYP to start the final phase */
@@ -5799,7 +5798,7 @@
}
if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
{
- for(index=0U; index< 4U;index++)
+ for(index=0U; index< 4U;index++)
{
/* Read the output block from the output FIFO */
intermediate_data[index] = hcryp->Instance->DOUT;
@@ -5816,25 +5815,85 @@
a GCM encryption with the last block of payload size inferior to 128 bits*/
/* Change the AES mode to GCM mode and Select Final phase */
/* configured CHMOD GCM */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
/* configured final phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
+ if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+ }
+ }
+ else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U);
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U);
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U);
+ }
+ }
+ else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16);
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16);
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16);
+ }
+ }
+ else /*CRYP_DATATYPE_1B*/
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U);
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U);
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U);
+ }
+ }
for (index=0U; index < lastwordsize; index ++)
{
/*Write the intermediate_data in the IN FIFO */
hcryp->Instance->DIN=intermediate_data[index];
- }
- while(index < 4U)
+ }
+ while(index < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DIN = 0x0U;
- index++;
- }
+ index++;
+ }
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
- {
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -5842,23 +5901,23 @@
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Process unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
- if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
- {
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ {
for( index=0U; index< 4U;index++)
- {
+ {
intermediate_data[index]=hcryp->Instance->DOUT;
- }
+ }
}
}
} /* End of GCM encryption */
@@ -5866,9 +5925,9 @@
authentication tags while doing a CCM decryption with the last block
of payload size inferior to 128 bits*/
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
{
- iv1temp = hcryp->Instance->CSGCMCCM7R;
+ iv1temp = hcryp->Instance->CSGCMCCM7R;
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
@@ -5881,13 +5940,13 @@
hcryp->Instance->IV1RR= iv1temp;
/* Configured CHMOD CTR */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
/* Last block optionally pad the data with zeros*/
- for(index=0; index < lastwordsize; index ++)
+ for(index=0; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
@@ -5900,7 +5959,7 @@
index++;
}
/* Wait for OFNE flag to be raised */
- if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -5909,48 +5968,48 @@
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
{
- for(index=0U; index< 4U;index++)
+ for(index=0U; index< 4U;index++)
{
/* Read the Output block from the Output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUT;
+ intermediate_data[index] = hcryp->Instance->DOUT;
/*intermediate data buffer to be used in for the workaround*/
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
- hcryp->CrypOutCount++;
- }
- }
+ hcryp->CrypOutCount++;
+ }
+ }
- if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
- {
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ {
temp2[0]= hcryp->Instance->CSGCMCCM0R;
temp2[1]= hcryp->Instance->CSGCMCCM1R;
temp2[2]= hcryp->Instance->CSGCMCCM2R;
temp2[3]= hcryp->Instance->CSGCMCCM3R;
/* configured CHMOD CCM */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
/* configured Header phase */
- MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
/*set to zero the bits corresponding to the padded bits*/
- for(index = lastwordsize; index<4U; index ++)
+ for(index = lastwordsize; index<4U; index ++)
{
intermediate_data[index] =0U;
- }
+ }
if ((npblb %4U)==1U)
{
intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
@@ -5963,20 +6022,20 @@
{
intermediate_data[lastwordsize-1U] &= 0xFF000000U;
}
- for(index=0U; index < 4U ; index ++)
- {
+ for(index=0U; index < 4U ; index ++)
+ {
intermediate_data[index] ^= temp[index];
intermediate_data[index] ^= temp2[index];
}
- for(index = 0U; index < 4U; index ++)
+ for(index = 0U; index < 4U; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DIN = intermediate_data[index] ;
- }
+ }
/* Wait for BUSY flag to be raised */
- if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
- {
+ if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
@@ -5984,34 +6043,34 @@
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- } /* End of CCM WKA*/
-
+ } /* End of CCM WKA*/
+
/* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
+ __HAL_UNLOCK(hcryp);
+
#else /* AES */
-
+
/*Workaround 2: case GCM encryption, during payload phase and before inserting
the last block of paylaod, which size is inferior to 128 bits */
- if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* configured CHMOD CTR */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
}
- /* last block optionally pad the data with zeros*/
- for(index = 0U; index < lastwordsize; index ++)
+ /* last block optionally pad the data with zeros*/
+ for(index = 0U; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
@@ -6022,41 +6081,102 @@
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
index++;
- }
+ }
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
- hcryp->State = HAL_CRYP_STATE_READY;
+ hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- for(index = 0U; index< 4U;index++)
- {
- /* Read the Output block from the Output FIFO */
- intermediate_data[index] = hcryp->Instance->DOUTR;
+ for(index = 0U; index< 4U;index++)
+ {
+ /* Read the Output block from the Output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUTR;
/*intermediate data buffer to be used in the workaround*/
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index];
hcryp->CrypOutCount++;
- }
+ }
- if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* configured CHMOD GCM */
MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
/* Select final phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
+ if ( (hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+ }
+ }
+ else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U);
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U);
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U);
+ }
+ }
+ else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16);
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16);
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16);
+ }
+ }
+ else /*CRYP_DATATYPE_1B*/
+ {
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U);
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U);
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U);
+ }
+ }
/*Write the intermediate_data in the IN FIFO */
for(index = 0U; index < lastwordsize; index ++)
@@ -6067,21 +6187,21 @@
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
- index++;
+ index++;
}
/* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
@@ -6096,9 +6216,8 @@
{
intermediate_data[index]=hcryp->Instance->DOUTR;
}
- }/*End of Workaround 2*/
-
-#endif /* End AES or CRYP */
+ }/*End of Workaround 2*/
+#endif /* End AES or CRYP */
}
#endif /* AES or GCM CCM defined*/
#if defined (CRYP)
diff --git a/Src/stm32f4xx_hal_dcmi.c b/Src/stm32f4xx_hal_dcmi.c
index 83dce62..d3b10fc 100644
--- a/Src/stm32f4xx_hal_dcmi.c
+++ b/Src/stm32f4xx_hal_dcmi.c
@@ -813,6 +813,37 @@
}
/**
+ * @brief Set embedded synchronization delimiters unmasks.
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
+ * the embedded synchronization delimiters unmasks.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
+{
+ /* Process Locked */
+ __HAL_LOCK(hdcmi);
+
+ /* Lock the DCMI peripheral state */
+ hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+ /* Write DCMI embedded synchronization unmask register */
+ hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) |\
+ ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos)|\
+ ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos)|\
+ ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
+
+ /* Change the DCMI state*/
+ hdcmi->State = HAL_DCMI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdcmi);
+
+ return HAL_OK;
+}
+
+/**
* @}
*/
diff --git a/Src/stm32f4xx_hal_dfsdm.c b/Src/stm32f4xx_hal_dfsdm.c
index 3126cbd..c57ebeb 100644
--- a/Src/stm32f4xx_hal_dfsdm.c
+++ b/Src/stm32f4xx_hal_dfsdm.c
@@ -157,23 +157,26 @@
*** Callback registration ***
=============================
-
+ [..]
The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
- @ref HAL_DFSDM_Filter_RegisterCallback() or
- @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
+ Use functions HAL_DFSDM_Channel_RegisterCallback(),
+ HAL_DFSDM_Filter_RegisterCallback() or
+ HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
- Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
+ [..]
+ Function HAL_DFSDM_Channel_RegisterCallback() allows to register
following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
+ [..]
+ Function HAL_DFSDM_Filter_RegisterCallback() allows to register
following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -182,26 +185,33 @@
(+) ErrorCallback : DFSDM filter error callback.
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
For specific DFSDM filter analog watchdog callback use dedicated register callback:
- @ref HAL_DFSDM_Filter_RegisterAwdCallback().
+ HAL_DFSDM_Filter_RegisterAwdCallback().
- Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
- @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
+ [..]
+ Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
+ HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ [..]
+ HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
This function allows to reset following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
- @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ [..]
+ HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
This function allows to reset following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -211,29 +221,34 @@
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ [..]
For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
- @ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
+ HAL_DFSDM_Filter_UnRegisterAwdCallback().
+ [..]
By default, after the call of init function and if the state is RESET
all callbacks are reset to the corresponding legacy weak functions:
- examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
+ examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak functions in the init and de-init only when these
callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the init and de-init keep and use
the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the init/de-init.
In that case first register the MspInit/MspDeInit user callbacks using
- @ref HAL_DFSDM_Channel_RegisterCallback() or
- @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+ HAL_DFSDM_Channel_RegisterCallback() or
+ HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+ [..]
When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
@@ -4170,7 +4185,7 @@
*/
static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
{
- uint32_t channel = 0xFFU;
+ uint32_t channel;
/* Get channel from instance */
#if defined(DFSDM2_Channel0)
@@ -4202,14 +4217,11 @@
{
channel = 6U;
}
- else if(Instance == DFSDM2_Channel7)
+ else /* DFSDM2_Channel7 */
{
channel = 7U;
}
- else
- {
- /* channel = 0xFFU;*/
- }
+
#else
if(Instance == DFSDM1_Channel0)
{
@@ -4223,14 +4235,10 @@
{
channel = 2U;
}
- else if(Instance == DFSDM1_Channel3)
+ else /* DFSDM1_Channel3 */
{
channel = 3U;
}
- else
- {
- /* channel = 0xFFU;*/
- }
#endif /* defined(DFSDM2_Channel0) */
return channel;
diff --git a/Src/stm32f4xx_hal_dma.c b/Src/stm32f4xx_hal_dma.c
index 0a51f7e..69d848f 100644
--- a/Src/stm32f4xx_hal_dma.c
+++ b/Src/stm32f4xx_hal_dma.c
@@ -478,7 +478,6 @@
/* Enable Common interrupts*/
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
- hdma->Instance->FCR |= DMA_IT_FE;
if(hdma->XferHalfCpltCallback != NULL)
{
diff --git a/Src/stm32f4xx_hal_dma2d.c b/Src/stm32f4xx_hal_dma2d.c
index 8ca7ae7..a915620 100644
--- a/Src/stm32f4xx_hal_dma2d.c
+++ b/Src/stm32f4xx_hal_dma2d.c
@@ -950,6 +950,119 @@
return HAL_OK;
}
+/**
+ * @brief Start DMA2D CLUT Loading.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start DMA2D CLUT Loading with interrupt enabled.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * the configuration information for the color look up table.
+ * @param LayerIdx DMA2D Layer index.
+ * This parameter can be one of the following values:
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA2D_LAYER(LayerIdx));
+ assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
+ assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ /* Change DMA2D peripheral state */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+
+ /* Configure the CLUT of the background DMA2D layer */
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ {
+ /* Write background CLUT memory address */
+ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write background CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the background */
+ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
+ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
+
+ /* Write foreground CLUT size and CLUT color mode */
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+
+ /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+
+ /* Enable the CLUT loading for the foreground */
+ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
+ }
+
+ return HAL_OK;
+}
/**
* @brief Start DMA2D CLUT Loading.
@@ -960,7 +1073,9 @@
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
- * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
+ * @note API obsolete and maintained for compatibility with legacy. User is
+ * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
+ * code compactness, code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@@ -1015,6 +1130,9 @@
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @note API obsolete and maintained for compatibility with legacy. User is
+ * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
+ * from code compactness, code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@@ -1682,6 +1800,9 @@
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
+ * @note API obsolete and maintained for compatibility with legacy. User is invited
+ * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
+ * code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
diff --git a/Src/stm32f4xx_hal_dsi.c b/Src/stm32f4xx_hal_dsi.c
index be4da6d..548a330 100644
--- a/Src/stm32f4xx_hal_dsi.c
+++ b/Src/stm32f4xx_hal_dsi.c
@@ -13,36 +13,57 @@
==============================================================================
##### How to use this driver #####
==============================================================================
+ [..]
+ The DSI HAL driver can be used as follows:
+
+ (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi;
+
+ (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API:
+ (##) Enable the DSI interface clock
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the DSI interrupt priority
+ (+++) Enable the NVIC DSI IRQ Channel
+
+ (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and
+ TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit().
+
+ *** Configuration ***
+ =========================
[..]
- (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
- PLL parameters, number of lanes and TX Escape clock divider.
- (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
+ (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
command mode.
- (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
- (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
- (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
- (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
- Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
+
+ (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host.
+
+ (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
+
+ (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer().
+
+ (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop().
+ Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively
to write DSI short packets, long packets and to read DSI packets.
(#) The DSI Host Offers two Low power modes :
- (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
- It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
- and @ref HAL_DSI_ExitULPMData()
+ (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
+ It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData()
+ and HAL_DSI_ExitULPMData()
- (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
- It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
- and @ref HAL_DSI_ExitULPM()
-
- (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
- When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
- the error code by calling function @ref HAL_DSI_GetError()
+ (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
+ It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM()
+ and HAL_DSI_ExitULPM()
(#) To control DSI state you can use the following function: HAL_DSI_GetState()
- *** DSI HAL driver macros list ***
- =============================================
- [..]
+ *** Error management ***
+ ========================
+ [..]
+ (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor()
+ When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve
+ the error code by calling function HAL_DSI_GetError()
+
+ *** DSI HAL driver macros list ***
+ =============================================
+ [..]
Below the list of most used macros in DSI HAL driver.
(+) __HAL_DSI_ENABLE: Enable the DSI Host.
@@ -59,58 +80,63 @@
(+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
(+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
+ [..]
+ (@) You can refer to the DSI HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function HAL_DSI_RegisterCallback() to register a callback.
- *** Callback registration ***
- =============================================
+ [..]
+ Function HAL_DSI_RegisterCallback() allows to register following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
- The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_DSI_RegisterCallback() to register a callback.
+ [..]
+ Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ [..]
+ This function allows to reset following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
- Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
- (+) TearingEffectCallback : DSI Tearing Effect Callback.
- (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
- (+) ErrorCallback : DSI Error Callback
- (+) MspInitCallback : DSI MspInit.
- (+) MspDeInitCallback : DSI MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
+ [..]
+ By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
+ and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
- Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
- weak function.
- @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (+) TearingEffectCallback : DSI Tearing Effect Callback.
- (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
- (+) ErrorCallback : DSI Error Callback
- (+) MspInitCallback : DSI MspInit.
- (+) MspDeInitCallback : DSI MspDeInit.
+ [..]
+ Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit()
+ or HAL_DSI_Init() function.
- By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
- all callbacks are set to the corresponding weak functions:
- examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
- these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
- or HAL_DSI_Init function.
-
- When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
-
- [..]
- (@) You can refer to the DSI HAL driver header file for more useful macros
+ [..]
+ When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
@@ -186,10 +212,10 @@
* @param ChannelID Virtual channel ID of the header packet
* @param DataType Packet data type of the header packet
* This parameter can be any value of :
- * @ref DSI_SHORT_WRITE_PKT_Data_Type
- * or @ref DSI_LONG_WRITE_PKT_Data_Type
- * or @ref DSI_SHORT_READ_PKT_Data_Type
- * or DSI_MAX_RETURN_PKT_SIZE
+ * @arg DSI_SHORT_WRITE_PKT_Data_Type
+ * @arg DSI_LONG_WRITE_PKT_Data_Type
+ * @arg DSI_SHORT_READ_PKT_Data_Type
+ * @arg DSI_MAX_RETURN_PKT_SIZE
* @param Data0 Word count LSB
* @param Data1 Word count MSB
* @retval None
@@ -210,9 +236,9 @@
* the configuration information for the DSI.
* @param ChannelID Virtual channel ID.
* @param Mode DSI short packet data type.
- * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
+ * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
* @param Param1 DSC command or first generic parameter.
- * This parameter can be any value of @ref DSI_DCS_Command or a
+ * This parameter can be any value of @arg DSI_DCS_Command or a
* generic command code.
* @param Param2 DSC parameter or second generic parameter.
* @retval HAL status
@@ -464,7 +490,7 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ActiveErrors indicates which error interrupts will be enabled.
- * This parameter can be any combination of @ref DSI_Error_Data_Type.
+ * This parameter can be any combination of @arg DSI_Error_Data_Type.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
@@ -581,11 +607,11 @@
* @param hdsi dsi handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
- * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
- * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
- * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+ * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+ * @arg HAL_DSI_ERROR_CB_ID Error Callback ID
+ * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
@@ -676,11 +702,11 @@
* @param hdsi dsi handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
- * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
- * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
- * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+ * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+ * @arg HAL_DSI_ERROR_CB_ID Error Callback ID
+ * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
@@ -1295,7 +1321,7 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param FlowControl flow control feature(s) to be enabled.
- * This parameter can be any combination of @ref DSI_FlowControl.
+ * This parameter can be any combination of @arg DSI_FlowControl.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
@@ -1488,7 +1514,7 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ColorMode Color mode (full or 8-colors).
- * This parameter can be any value of @ref DSI_Color_Mode
+ * This parameter can be any value of @arg DSI_Color_Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
@@ -1514,7 +1540,7 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param Shutdown Shut-down (Display-ON or Display-OFF).
- * This parameter can be any value of @ref DSI_ShutDown
+ * This parameter can be any value of @arg DSI_ShutDown
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
@@ -1541,9 +1567,9 @@
* the configuration information for the DSI.
* @param ChannelID Virtual channel ID.
* @param Mode DSI short packet data type.
- * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
+ * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
* @param Param1 DSC command or first generic parameter.
- * This parameter can be any value of @ref DSI_DCS_Command or a
+ * This parameter can be any value of @arg DSI_DCS_Command or a
* generic command code.
* @param Param2 DSC parameter or second generic parameter.
* @retval HAL status
@@ -1575,10 +1601,10 @@
* the configuration information for the DSI.
* @param ChannelID Virtual channel ID.
* @param Mode DSI long packet data type.
- * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
+ * This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type.
* @param NbParams Number of parameters.
* @param Param1 DSC command or first generic parameter.
- * This parameter can be any value of @ref DSI_DCS_Command or a
+ * This parameter can be any value of @arg DSI_DCS_Command or a
* generic command code
* @param ParametersTable Pointer to parameter values table.
* @retval HAL status
@@ -1665,7 +1691,7 @@
* @param Array pointer to a buffer to store the payload of a read back operation.
* @param Size Data size to be read (in byte).
* @param Mode DSI read packet data type.
- * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
+ * This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type.
* @param DCSCmd DCS get/read command.
* @param ParametersTable Pointer to parameter values table.
* @retval HAL status
@@ -2120,9 +2146,9 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param CommDelay Communication delay to be adjusted.
- * This parameter can be any value of @ref DSI_Communication_Delay
+ * This parameter can be any value of @arg DSI_Communication_Delay
* @param Lane select between clock or data lanes.
- * This parameter can be any value of @ref DSI_Lane_Group
+ * This parameter can be any value of @arg DSI_Lane_Group
* @param Value Custom value of the slew-rate or delay
* @retval HAL status
*/
@@ -2264,9 +2290,9 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param CustomLane Function to be applyed on selected lane.
- * This parameter can be any value of @ref DSI_CustomLane
+ * This parameter can be any value of @arg DSI_CustomLane
* @param Lane select between clock or data lane 0 or data lane 1.
- * This parameter can be any value of @ref DSI_Lane_Select
+ * This parameter can be any value of @arg DSI_Lane_Select
* @param State ENABLE or DISABLE
* @retval HAL status
*/
@@ -2352,7 +2378,7 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param Timing PHY timing to be adjusted.
- * This parameter can be any value of @ref DSI_PHY_Timing
+ * This parameter can be any value of @arg DSI_PHY_Timing
* @param State ENABLE or DISABLE
* @param Value Custom value of the timing
* @retval HAL status
@@ -2500,7 +2526,7 @@
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param Lane select between clock or data lanes.
- * This parameter can be any value of @ref DSI_Lane_Group
+ * This parameter can be any value of @arg DSI_Lane_Group
* @param State ENABLE or DISABLE
* @retval HAL status
*/
diff --git a/Src/stm32f4xx_hal_exti.c b/Src/stm32f4xx_hal_exti.c
index a869906..7cf3e09 100644
--- a/Src/stm32f4xx_hal_exti.c
+++ b/Src/stm32f4xx_hal_exti.c
@@ -45,6 +45,8 @@
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+ member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
@@ -141,6 +143,8 @@
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
@@ -151,37 +155,77 @@
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
- assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~pExtiConfig->Line;
- EXTI->EMR &= ~pExtiConfig->Line;
+ /* Compute line mask */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
- /* Select the Mode for the selected external interrupts */
- regval = (uint32_t)EXTI_BASE;
- regval += pExtiConfig->Mode;
- *(__IO uint32_t *) regval |= pExtiConfig->Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~pExtiConfig->Line;
- EXTI->FTSR &= ~pExtiConfig->Line;
-
- /* Select the trigger for the selected external interrupts */
- if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
+ /* Configure triggers for configurable lines */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
- /* Rising Falling edge */
- EXTI->RTSR |= pExtiConfig->Line;
- EXTI->FTSR |= pExtiConfig->Line;
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Configure rising trigger */
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+ {
+ EXTI->RTSR |= maskline;
+ }
+ else
+ {
+ EXTI->RTSR &= ~maskline;
+ }
+
+ /* Configure falling trigger */
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+ {
+ EXTI->FTSR |= maskline;
+ }
+ else
+ {
+ EXTI->FTSR &= ~maskline;
+ }
+
+
+ /* Configure gpio port selection in case of gpio exti line */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ /* Configure interrupt mode : read current mode */
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+ {
+ EXTI->IMR |= maskline;
}
else
{
- regval = (uint32_t)EXTI_BASE;
- regval += pExtiConfig->Trigger;
- *(__IO uint32_t *) regval |= pExtiConfig->Line;
+ EXTI->IMR &= ~maskline;
}
+
+ /* Configure event mode : read current mode */
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+ {
+ EXTI->EMR |= maskline;
+ }
+ else
+ {
+ EXTI->EMR &= ~maskline;
+ }
+
return HAL_OK;
}
@@ -193,6 +237,10 @@
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
@@ -205,41 +253,67 @@
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
- /* Get EXTI mode to configiguration structure */
- if ((EXTI->IMR & hexti->Line) == hexti->Line)
+ /* Compute line mask */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* 1] Get core mode : interrupt */
+
+ /* Check if selected line is enable */
+ if ((EXTI->IMR & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
- else if ((EXTI->EMR & hexti->Line) == hexti->Line)
- {
- pExtiConfig->Mode = EXTI_MODE_EVENT;
- }
else
{
- /* No MODE selected */
- pExtiConfig->Mode = 0x0Bu;
+ pExtiConfig->Mode = EXTI_MODE_NONE;
}
- /* Get EXTI Trigger to configiguration structure */
- if ((EXTI->RTSR & hexti->Line) == hexti->Line)
+ /* Get event mode */
+ /* Check if selected line is enable */
+ if ((EXTI->EMR & maskline) != 0x00u)
{
- if ((EXTI->FTSR & hexti->Line) == hexti->Line)
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
- }
- else
+ pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ }
+
+ /* 2] Get trigger for configurable lines : rising */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ {
+ /* Check if configuration of selected line is enable */
+ if ((EXTI->RTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
- }
- else if ((EXTI->FTSR & hexti->Line) == hexti->Line)
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;
+ else
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ }
+
+ /* Get falling configuration */
+ /* Check if configuration of selected line is enable */
+ if ((EXTI->FTSR & maskline) != 0x00u)
+ {
+ pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ }
+
+ /* Get Gpio port selection for gpio lines */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+ }
+ else
+ {
+ pExtiConfig->GPIOSel = 0x00u;
+ }
}
else
{
/* No Trigger selected */
- pExtiConfig->Trigger = 0x00u;
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
@@ -252,6 +326,10 @@
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
/* Check null pointer */
if (hexti == NULL)
{
@@ -261,15 +339,32 @@
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
+ /* compute line mask */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
/* 1] Clear interrupt mode */
- EXTI->IMR = (EXTI->IMR & ~hexti->Line);
+ EXTI->IMR = (EXTI->IMR & ~maskline);
/* 2] Clear event mode */
- EXTI->EMR = (EXTI->EMR & ~hexti->Line);
+ EXTI->EMR = (EXTI->EMR & ~maskline);
- /* 3] Clear triggers */
- EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);
- EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);
+ /* 3] Clear triggers in case of configurable lines */
+ if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+ {
+ EXTI->RTSR = (EXTI->RTSR & ~maskline);
+ EXTI->FTSR = (EXTI->FTSR & ~maskline);
+
+ /* Get Gpio port selection for gpio lines */
+ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
return HAL_OK;
}
@@ -289,7 +384,7 @@
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
- hexti->RisingCallback = pPendingCbfn;
+ hexti->PendingCallback = pPendingCbfn;
break;
default:
@@ -349,15 +444,23 @@
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
- if (EXTI->PR != 0x00u)
+ uint32_t regval;
+ uint32_t maskline;
+
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Get pending bit */
+ regval = (EXTI->PR & maskline);
+ if (regval != 0x00u)
{
/* Clear pending bit */
- EXTI->PR = hexti->Line;
+ EXTI->PR = maskline;
/* Call callback */
- if (hexti->RisingCallback != NULL)
+ if (hexti->PendingCallback != NULL)
{
- hexti->RisingCallback();
+ hexti->PendingCallback();
}
}
}
@@ -373,19 +476,21 @@
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
- __IO uint32_t *regaddr;
uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
- /* Get pending bit */
- regaddr = &EXTI->PR;
+ /* Compute line mask */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
/* return 1 if bit is set else 0 */
- regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));
-
+ regval = ((EXTI->PR & maskline) >> linepos);
return regval;
}
@@ -400,11 +505,18 @@
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
+ uint32_t maskline;
+
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
- EXTI->PR = hexti->Line;
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Clear Pending bit */
+ EXTI->PR = maskline;
}
/**
@@ -414,10 +526,17 @@
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
+ uint32_t maskline;
+
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
- EXTI->SWIER = hexti->Line;
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Generate Software interrupt */
+ EXTI->SWIER = maskline;
}
/**
diff --git a/Src/stm32f4xx_hal_flash.c b/Src/stm32f4xx_hal_flash.c
index 5c601ae..69b47a6 100644
--- a/Src/stm32f4xx_hal_flash.c
+++ b/Src/stm32f4xx_hal_flash.c
@@ -619,8 +619,14 @@
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
- /* Program the double-word */
+ /* Program first word */
*(__IO uint32_t*)Address = (uint32_t)Data;
+
+ /* Barrier to ensure programming is performed in 2 steps, in right order
+ (independently of compiler optimization behavior) */
+ __ISB();
+
+ /* Program second word */
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
}
diff --git a/Src/stm32f4xx_hal_fmpi2c.c b/Src/stm32f4xx_hal_fmpi2c.c
index f60c0df..44f64f3 100644
--- a/Src/stm32f4xx_hal_fmpi2c.c
+++ b/Src/stm32f4xx_hal_fmpi2c.c
@@ -223,12 +223,12 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_FMPI2C_RegisterCallback() or @ref HAL_FMPI2C_RegisterAddrCallback()
to register an interrupt callback.
-
+ [..]
Function @ref HAL_FMPI2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@@ -243,9 +243,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_RegisterAddrCallback().
-
+ [..]
Use function @ref HAL_FMPI2C_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_FMPI2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
@@ -262,9 +262,9 @@
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
-
+ [..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_UnRegisterAddrCallback().
-
+ [..]
By default, after the @ref HAL_FMPI2C_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_FMPI2C_MasterTxCpltCallback(), @ref HAL_FMPI2C_MasterRxCpltCallback().
@@ -273,7 +273,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_FMPI2C_Init()/ @ref HAL_FMPI2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
+ [..]
Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state,
@@ -281,7 +281,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_FMPI2C_RegisterCallback() before calling @ref HAL_FMPI2C_DeInit()
or @ref HAL_FMPI2C_Init() function.
-
+ [..]
When the compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -4738,6 +4738,13 @@
/* Process locked */
__HAL_LOCK(hfmpi2c);
+ /* Check if STOPF is set */
+ if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
+ {
+ /* Call FMPI2C Slave complete process */
+ FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags);
+ }
+
if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
@@ -4789,9 +4796,6 @@
{
if (hfmpi2c->XferCount > 0U)
{
- /* Remove RXNE flag on temporary variable as read done */
- tmpITFlags &= ~FMPI2C_FLAG_RXNE;
-
/* Read data from RXDR */
*hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
@@ -4845,13 +4849,6 @@
/* Nothing to do */
}
- /* Check if STOPF is set */
- if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
- {
- /* Call FMPI2C Slave complete process */
- FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -5009,6 +5006,13 @@
/* Process locked */
__HAL_LOCK(hfmpi2c);
+ /* Check if STOPF is set */
+ if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
+ {
+ /* Call FMPI2C Slave complete process */
+ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
+ }
+
if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
@@ -5093,11 +5097,6 @@
{
FMPI2C_ITAddrCplt(hfmpi2c, ITFlags);
}
- else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
- {
- /* Call FMPI2C Slave complete process */
- FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
- }
else
{
/* Nothing to do */
diff --git a/Src/stm32f4xx_hal_gpio.c b/Src/stm32f4xx_hal_gpio.c
index 75b8fcd..89090d6 100644
--- a/Src/stm32f4xx_hal_gpio.c
+++ b/Src/stm32f4xx_hal_gpio.c
@@ -192,24 +192,6 @@
if(iocurrent == ioposition)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameter */
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3U];
- temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
- GPIOx->AFR[position >> 3U] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- GPIOx->MODER = temp;
-
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@@ -227,7 +209,7 @@
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
GPIOx->OTYPER = temp;
- }
+ }
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
@@ -235,6 +217,24 @@
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameter */
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = temp;
+
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@@ -318,10 +318,6 @@
tmp &= (0x0FU << (4U * (position & 0x03U)));
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
{
- /* Configure the External Interrupt or event for the current IO */
- tmp = 0x0FU << (4U * (position & 0x03U));
- SYSCFG->EXTICR[position >> 2U] &= ~tmp;
-
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent);
@@ -329,6 +325,10 @@
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
+
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = 0x0FU << (4U * (position & 0x03U));
+ SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@@ -338,14 +338,14 @@
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
}
}
}
@@ -473,9 +473,10 @@
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
+ /* Read LCKR register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
+ /* Read again in order to confirm lock is active */
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
{
return HAL_OK;
diff --git a/Src/stm32f4xx_hal_hash.c b/Src/stm32f4xx_hal_hash.c
index af5c071..8ed6a15 100644
--- a/Src/stm32f4xx_hal_hash.c
+++ b/Src/stm32f4xx_hal_hash.c
@@ -57,24 +57,29 @@
(#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
initialized and processes the buffer fed in input. When the input data have all been
- fed to the IP, the digest computation can start.
+ fed to the Peripheral, the digest computation can start.
- (#)Multi-buffer processing is possible in polling and DMA mode.
+ (#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
- User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
+ User must resort to HAL_HASH_xxx_Accumulate_End() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In interrupt mode, API HAL_HASH_xxx_Accumulate_IT() must be called for each input buffer,
+ except for the last one.
+ User must resort to HAL_HASH_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
+ From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer thru the
same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASH_xxx_Finish().
(+++) HMAC processing (requires to resort to extended functions):
after initialization, the key and the first input buffer are entered
- in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
@@ -90,16 +95,50 @@
(+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
(##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
- to save in memory the IP context. This context can be restored afterwards
+ to save in memory the Peripheral context. This context can be restored afterwards
to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
- (##) Once the HASH IP has been restored to the same configuration as that at suspension
+ (##) Once the HASH Peripheral has been restored to the same configuration as that at suspension
time, processing can be restarted with the same API call (same API, same handle,
same parameters) as done before the suspension. Relevant parameters to restart at
the proper location are internally saved in the HASH handle.
(#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+ *** Remarks on message length ***
+ ===================================
+ [..]
+ (#) HAL in interruption mode (interruptions driven)
+
+ (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
+ This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ length of which is a multiple of 4 bytes.
+
+ (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
+ to specify which bits to discard at the end of the complete message to process only the message bits
+ and not extra bits.
+
+ (##) If user needs to perform a hash computation of a large input buffer that is spread around various places
+ in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it
+ becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
+ It is advised to the user to
+ (+++) achieve the first formatting operation by software then enter the data
+ (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs.
+ (+++) repeat step 2 until the whole message is processed.
+
+ [..]
+ (#) HAL in DMA mode
+
+ (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
+ The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer
+ to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the
+ end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at
+ the end of the intermediary transfers.
+
+ (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data
+ by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment
+ required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode.
+
*** Callback registration ***
===================================
[..]
@@ -260,7 +299,7 @@
[..] This section provides as well call back functions definitions for user
code to manage:
- (+) Input data transfer to IP completion
+ (+) Input data transfer to Peripheral completion
(+) Calculated digest retrieval completion
(+) Error management
@@ -273,25 +312,25 @@
/**
* @brief Initialize the HASH according to the specified parameters in the
HASH_HandleTypeDef and create the associated handle.
- * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
+ * @note Only MDMAT and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(),
* other configuration bits are set by HASH or HMAC processing APIs.
* @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
* multi-buffer HASH processing, user needs to resort to
* __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
* relevant APIs manage themselves the MDMAT bit.
- * @param hhash: HASH handle
+ * @param hhash HASH handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
- /* Check the parameters */
- assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
-
/* Check the hash handle allocation */
if(hhash == NULL)
{
return HAL_ERROR;
}
+
+ /* Check the parameters */
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
if (hhash->State == HAL_HASH_STATE_RESET)
@@ -334,6 +373,8 @@
hhash->DigestCalculationDisable = RESET;
/* Set phase to READY */
hhash->Phase = HAL_HASH_PHASE_READY;
+ /* Reset suspension request flag */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
/* Set the data type bit */
MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
@@ -356,7 +397,7 @@
/**
* @brief DeInitialize the HASH peripheral.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
@@ -403,13 +444,16 @@
/* Initialise the error code */
hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+ /* Reset multi buffers accumulation flag */
+ hhash->Accumulation = 0U;
+
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the HASH MSP.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
@@ -424,7 +468,7 @@
/**
* @brief DeInitialize the HASH MSP.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
@@ -440,12 +484,12 @@
/**
* @brief Input data transfer complete call back.
* @note HAL_HASH_InCpltCallback() is called when the complete input message
- * has been fed to the IP. This API is invoked only when input data are
+ * has been fed to the Peripheral. This API is invoked only when input data are
* entered under interruption or thru DMA.
* @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
* HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
- * to the IP.
- * @param hhash: HASH handle.
+ * to the Peripheral.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
@@ -462,7 +506,7 @@
* @brief Digest computation complete call back.
* @note HAL_HASH_DgstCpltCallback() is used under interruption, is not
* relevant with DMA.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
@@ -479,7 +523,7 @@
* @brief Error callback.
* @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
* to retrieve the error type.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
@@ -686,17 +730,19 @@
the hash value using one of the following algorithms:
(+) MD5
(++) HAL_HASH_MD5_Start()
- (++) HAL_HASH_MD5_Accumulate()
+ (++) HAL_HASH_MD5_Accmlt()
+ (++) HAL_HASH_MD5_Accmlt_End()
(+) SHA1
(++) HAL_HASH_SHA1_Start()
- (++) HAL_HASH_SHA1_Accumulate()
+ (++) HAL_HASH_SHA1_Accmlt()
+ (++) HAL_HASH_SHA1_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
- several buffers are fed to the IP), the user can resort to successive calls
+ several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
- to HAL_HASH_xxx_Start().
+ to HAL_HASH_xxx_Accumulate_End().
@endverbatim
* @{
@@ -706,11 +752,11 @@
* @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -721,37 +767,52 @@
/**
* @brief If not already done, initialize the HASH peripheral in MD5 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASH_MD5_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASH_MD5_Start().
+ * HAL_HASH_MD5_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
}
/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
* @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -762,28 +823,42 @@
/**
* @brief If not already done, initialize the HASH peripheral in SHA1 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASH_SHA1_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASH_SHA1_Start().
+ * HAL_HASH_SHA1_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
}
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
/**
* @}
@@ -800,12 +875,16 @@
the hash value using one of the following algorithms:
(+) MD5
(++) HAL_HASH_MD5_Start_IT()
+ (++) HAL_HASH_MD5_Accmlt_IT()
+ (++) HAL_HASH_MD5_Accmlt_End_IT()
(+) SHA1
(++) HAL_HASH_SHA1_Start_IT()
+ (++) HAL_HASH_SHA1_Accmlt_IT()
+ (++) HAL_HASH_SHA1_Accmlt_End_IT()
[..] API HAL_HASH_IRQHandler() manages each HASH interruption.
- [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
+ [..] Note that HAL_HASH_IRQHandler() manages as well HASH Peripheral interruptions when in
HMAC processing mode.
@@ -817,10 +896,10 @@
* @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -828,15 +907,51 @@
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
}
+/**
+ * @brief If not already done, initialize the HASH peripheral in MD5 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASH_MD5_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_MD5_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+}
/**
* @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -844,9 +959,47 @@
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA1 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASH_SHA1_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_SHA1_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+}
+
/**
* @brief Handle HASH interrupt request.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
* @note In case of error reported during the HASH interruption processing,
* HAL_HASH_ErrorCallback() API is called so that user code can
@@ -889,7 +1042,7 @@
(++) HAL_HASH_SHA1_Start_DMA()
(++) HAL_HASH_SHA1_Finish()
- [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASH_xxx_Start_DMA() then read the resulting digest with
HAL_HASH_xxx_Finish().
[..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
@@ -903,12 +1056,12 @@
/**
* @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -921,9 +1074,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
* HMAC MD5 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -933,12 +1086,12 @@
/**
* @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -952,9 +1105,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
* HMAC SHA1 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -991,11 +1144,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1009,11 +1162,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1051,10 +1204,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1068,10 +1221,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1099,7 +1252,7 @@
(+) SHA1
(++) HAL_HMAC_SHA1_Start_DMA()
- [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest
with HAL_HASH_xxx_Finish().
@@ -1110,7 +1263,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
* the computed digest.
@@ -1122,9 +1275,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1135,7 +1288,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
* the computed digest.
@@ -1147,9 +1300,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1182,9 +1335,9 @@
[..]
This subsection provides functions allowing to suspend the HASH processing
- (+) when input are fed to the IP by software
+ (+) when input are fed to the Peripheral by software
(++) HAL_HASH_SwFeed_ProcessSuspend()
- (+) when input are fed to the IP by DMA
+ (+) when input are fed to the Peripheral by DMA
(++) HAL_HASH_DMAFeed_ProcessSuspend()
@@ -1196,7 +1349,7 @@
/**
* @brief Return the HASH handle state.
* @note The API yields the current state of the handle (BUSY, READY,...).
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval HAL HASH state
*/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
@@ -1209,7 +1362,7 @@
* @brief Return the HASH HAL status.
* @note The API yields the HAL status of the handle: it is the result of the
* latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
@@ -1219,8 +1372,8 @@
/**
* @brief Save the HASH context in case of processing suspension.
- * @param hhash: HASH handle.
- * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * @param hhash HASH handle.
+ * @param pMemBuffer pointer to the memory buffer where the HASH context
* is saved.
* @note The IMR, STR, CR then all the CSR registers are saved
* in that order. Only the r/w bits are read to be restored later on.
@@ -1264,8 +1417,8 @@
/**
* @brief Restore the HASH context in case of processing resumption.
- * @param hhash: HASH handle.
- * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * @param hhash HASH handle.
+ * @param pMemBuffer pointer to the memory buffer where the HASH context
* is stored.
* @note The IMR, STR, CR then all the CSR registers are restored
* in that order. Only the r/w bits are restored.
@@ -1309,7 +1462,7 @@
/**
* @brief Initiate HASH processing suspension when in polling or interruption mode.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note Set the handle field SuspendRequest to the appropriate value so that
* the on-going HASH processing is suspended as soon as the required
* conditions are met. Note that the actual suspension is carried out
@@ -1325,9 +1478,9 @@
/**
* @brief Suspend the HASH processing when in DMA mode.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note When suspension attempt occurs at the very end of a DMA transfer and
- * all the data have already been entered in the IP, hhash->State is
+ * all the data have already been entered in the Peripheral, hhash->State is
* set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
* recommended to wrap-up the processing in reading the digest as usual.
* @retval HAL status
@@ -1355,7 +1508,7 @@
return HAL_ERROR;
}
- /* Wait for DMAS to be reset */
+ /* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -1366,26 +1519,26 @@
return HAL_ERROR;
}
- /* Wait for DMAS to be set */
+ /* Wait for BUSY flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
/* Disable DMA channel */
- if (HAL_DMA_Abort(hhash->hdmain) ==HAL_OK)
- {
- /*
- Note that the Abort function will
+ /* Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
- */
+ */
+ if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
+ {
+ return HAL_ERROR;
}
/* Clear DMAE bit */
CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+ /* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -1419,8 +1572,8 @@
/* Compute how many words were supposed to be transferred by DMA */
tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
- /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
- by HASH IP, correct it */
+ /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported
+ by HASH Peripheral, correct it */
/* tmp_words_already_pushed reflects the number of words that were already pushed before
the start of DMA transfer (multi-buffer processing case) */
tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
@@ -1429,7 +1582,7 @@
tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
}
- /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
+ /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */
hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
/* And store in HashInCount the remaining size to transfer (in bytes) */
@@ -1447,7 +1600,7 @@
/**
* @brief Return the HASH handle error code.
- * @param hhash: pointer to a HASH_HandleTypeDef structure.
+ * @param hhash pointer to a HASH_HandleTypeDef structure.
* @retval HASH Error Code
*/
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
@@ -1470,7 +1623,7 @@
/**
* @brief DMA HASH Input Data transfer completion callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @note In case of HMAC processing, HASH_DMAXferCplt() initiates
* the next DMA transfer for the following HMAC step.
* @retval None
@@ -1481,42 +1634,42 @@
uint32_t inputaddr;
uint32_t buffersize;
HAL_StatusTypeDef status ;
-
+
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
-
+
/* Disable the DMA transfer */
CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
-
+
if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
{
/* If no HMAC processing, input data transfer is now over */
-
+
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Call Input data transfer complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
+
}
else
{
/* HMAC processing: depending on the current HMAC step and whether or
not multi-buffer processing is on-going, the next step is initiated
and MDMAT bit is set. */
-
-
+
+
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
/* This is the end of HMAC processing */
-
+
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Call Input data transfer complete call back
(note that the last DMA transfer was that of the key
for the outer HASH operation). */
@@ -1525,7 +1678,7 @@
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
+
return;
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
@@ -1533,27 +1686,27 @@
inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
-
+
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
-
+
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
#if defined(HASH_CR_MDMAT)
/* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
if (hhash->DigestCalculationDisable != RESET)
{
/* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
- no digest calculation will be triggered at the end of the input buffer feeding to the IP */
+ no digest calculation will be triggered at the end of the input buffer feeding to the Peripheral */
__HAL_HASH_SET_MDMAT();
}
-#endif
+#endif
}
else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
{
if (hhash->DigestCalculationDisable != RESET)
{
- /* No automatic move to Step 3 as a new message buffer will be fed to the IP
+ /* No automatic move to Step 3 as a new message buffer will be fed to the Peripheral
(case of multi-buffer HMAC processing):
DCAL must not be set.
Phase remains in Step 2, MDMAT remains set at this point.
@@ -1576,34 +1729,34 @@
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
-
+
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
}
}
-
+
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(buffersize);
/* Set the HASH DMA transfert completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-
+
/* Enable the DMA In DMA Stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
-
+
/* Return function status */
if (status != HAL_OK)
{
- /* Update DAC state machine to error */
- hhash->State = HAL_HASH_STATE_ERROR;
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
}
else
{
- /* Change DAC state */
+ /* Change HASH state */
hhash->State = HAL_HASH_STATE_READY;
- }
+ }
}
}
@@ -1612,7 +1765,7 @@
/**
* @brief DMA HASH communication error callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
* can contain user code to manage the error.
* @retval None
@@ -1641,13 +1794,13 @@
}
/**
- * @brief Feed the input buffer to the HASH IP.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to input buffer.
- * @param Size: the size of input buffer in bytes.
+ * @brief Feed the input buffer to the HASH Peripheral.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to input buffer.
+ * @param Size the size of input buffer in bytes.
* @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
* or not the HASH processing must be suspended. If this is the case, the
- * processing is suspended when possible and the IP feeding point reached at
+ * processing is suspended when possible and the Peripheral feeding point reached at
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
@@ -1673,7 +1826,7 @@
/* Reset SuspendRequest */
hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
- /* Depending whether the key or the input data were fed to the IP, the feeding point
+ /* Depending whether the key or the input data were fed to the Peripheral, the feeding point
reached at suspension time is not saved in the same handle fields */
if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
{
@@ -1705,14 +1858,14 @@
} /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
- /* At this point, all the data have been entered to the IP: exit */
+ /* At this point, all the data have been entered to the Peripheral: exit */
return HAL_OK;
}
/**
* @brief Retrieve the message digest.
- * @param pMsgDigest: pointer to the computed digest.
- * @param Size: message digest size in bytes.
+ * @param pMsgDigest pointer to the computed digest.
+ * @param Size message digest size in bytes.
* @retval None
*/
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
@@ -1787,10 +1940,10 @@
/**
* @brief Handle HASH processing Timeout.
- * @param hhash: HASH handle.
- * @param Flag: specifies the HASH flag to check.
- * @param Status: the Flag status (SET or RESET).
- * @param Timeout: Timeout duration.
+ * @param hhash HASH handle.
+ * @param Flag specifies the HASH flag to check.
+ * @param Status the Flag status (SET or RESET).
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
@@ -1848,10 +2001,10 @@
/**
* @brief HASH processing in interruption mode.
- * @param hhash: HASH handle.
+ * @param hhash HASH handle.
* @note HASH_IT() regularly reads hhash->SuspendRequest to check whether
* or not the HASH processing must be suspended. If this is the case, the
- * processing is suspended when possible and the IP feeding point reached at
+ * processing is suspended when possible and the Peripheral feeding point reached at
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
@@ -1872,7 +2025,7 @@
else if (hhash->HashITCounter == 1U)
{
/* This is the first call to HASH_IT, the first input data are about to be
- entered in the IP. A specific processing is carried out at this point to
+ entered in the Peripheral. A specific processing is carried out at this point to
start-up the processing. */
hhash->HashITCounter = 2U;
}
@@ -1893,6 +2046,8 @@
__HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
/* Call digest computation complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->DgstCpltCallback(hhash);
@@ -1903,7 +2058,7 @@
return HAL_OK;
}
- /* If IP ready to accept new data */
+ /* If Peripheral ready to accept new data */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
@@ -1923,7 +2078,7 @@
return HAL_OK;
}
- /* Enter input data in the IP thru HASH_Write_Block_Data() call and
+ /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and
check whether the digest calculation has been triggered */
if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
{
@@ -1937,7 +2092,7 @@
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
{
- /* Wait until IP is not busy anymore */
+ /* Wait until Peripheral is not busy anymore */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
@@ -1954,7 +2109,7 @@
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
- /* Wait until IP is not busy anymore */
+ /* Wait until Peripheral is not busy anymore */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
@@ -1987,8 +2142,8 @@
/**
- * @brief Write a block of data in HASH IP in interruption mode.
- * @param hhash: HASH handle.
+ * @brief Write a block of data in HASH Peripheral in interruption mode.
+ * @param hhash HASH handle.
* @note HASH_Write_Block_Data() is called under interruption by HASH_IT().
* @retval HAL status
*/
@@ -2017,7 +2172,7 @@
HASH->DIN = *(uint32_t*)inputaddr;
if(hhash->HashInCount >= 68U)
{
- /* There are still data waiting to be entered in the IP.
+ /* There are still data waiting to be entered in the Peripheral.
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round. */
hhash->HashInCount -= 68U;
@@ -2056,13 +2211,33 @@
HASH->DIN = *(uint32_t*)inputaddr;
inputaddr+=4U;
}
- /* Start the Digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Return indication that digest calculation has started:
- this return value triggers the call to Input data transfer
- complete call back as well as the proper transition from
- one step to another in HMAC mode. */
- ret = HASH_DIGEST_CALCULATION_STARTED;
+
+ if (hhash->Accumulation == 1U)
+ {
+ /* Field accumulation is set, API only feeds data to the Peripheral and under interruption.
+ The digest computation will be started when the last buffer data are entered. */
+
+ /* Reset multi buffers accumulation flag */
+ hhash->Accumulation = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Return indication that digest calculation has started:
+ this return value triggers the call to Input data transfer
+ complete call back as well as the proper transition from
+ one step to another in HMAC mode. */
+ ret = HASH_DIGEST_CALCULATION_STARTED;
+ }
/* Reset buffer counter */
hhash->HashInCount = 0;
}
@@ -2073,8 +2248,8 @@
/**
* @brief HMAC processing in polling mode.
- * @param hhash: HASH handle.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
@@ -2216,6 +2391,9 @@
/* Read the message digest */
HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
}
/* Change the HASH state */
@@ -2233,58 +2411,58 @@
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+
/* Initiate HASH processing in case of start or resumption */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+ if ((pInBuffer == NULL) || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hhash);
-
+
/* Check if initialization phase has not been already performed */
if(hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
-
+
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
-
+
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
-
+
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
-
+
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
{
- /* if the IP has already been initialized, two cases are possible */
-
+ /* if the Peripheral has already been initialized, two cases are possible */
+
/* Process resumption time ... */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
@@ -2311,48 +2489,51 @@
{
/* Phase error */
hhash->State = HAL_HASH_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
return HAL_ERROR;
}
-
-
+
+
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
-
+
/* If the process has not been suspended, carry on to digest calculation */
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
/* Start the Digest calculation */
__HAL_HASH_START_DIGEST();
-
+
/* Wait for DCIS flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
/* Read the message digest */
HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
-
+
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
-
+
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
return HAL_OK;
-
+
}
else
{
@@ -2365,27 +2546,30 @@
* @brief If not already done, initialize the HASH peripheral then
* processes pInBuffer.
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
+ * the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* Make sure the input buffer size (in bytes) is a multiple of 4 */
- assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
+ if ((Size % 4U) != 0U)
+ {
+ return HAL_ERROR;
+ }
/* Initiate HASH processing in case of start or resumption */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
{
@@ -2462,23 +2646,151 @@
/**
+ * @brief If not already done, initialize the HASH peripheral then
+ * processes pInBuffer in interruption mode.
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t SizeVar = Size;
+
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+ if ((Size % 4U) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Initiate HASH processing in case of start or resumption */
+ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhash);
+
+ /* If resuming the HASH processing */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ }
+ else
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ hhash->HashITCounter = 1;
+ }
+ else
+ {
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ }
+
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises, or until there
+ is not more data to enter. */
+ while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
+ {
+
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ SizeVar-=4U;
+ }
+
+ /* If DINIS is still not set or if all the data have been fed, stop here */
+ if ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) || (SizeVar == 0U))
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+ /* otherwise, carry on in interrupt-mode */
+ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
+ to be fed to the Peripheral */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
+ the next interruption */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
+
+ }
+
+ /* Set multi buffers accumulation flag */
+ hhash->Accumulation = 1U;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Data Input interrupt */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI);
+
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+
+
+/**
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+ uint32_t polling_step = 0U;
+ uint32_t initialization_skipped = 0U;
+ uint32_t SizeVar = Size;
/* If State is ready or suspended, start or resume IT-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
{
@@ -2502,12 +2814,12 @@
MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
- hhash->HashInCount = Size; /* Counter used to keep track of number of data
- to be fed to the IP */
- hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at
+ hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
+ to be fed to the Peripheral */
+ hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at
the next interruption */
/* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
the information describing where the HASH process is stopped.
@@ -2516,10 +2828,82 @@
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
+ else
+ {
+ initialization_skipped = 1; /* info user later on in case of multi-buffer */
+ }
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises. */
+ while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
+ {
+ polling_step = 1U; /* note that some words are entered before enabling the interrupt */
+
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ SizeVar-=4U;
+ }
+
+ if (polling_step == 1U)
+ {
+ if (SizeVar == 0U)
+ {
+ /* If all the data have been entered at this point, it only remains to
+ read the digest */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ /* It remains data to enter and the Peripheral is ready to trigger DINIE,
+ carry on as usual.
+ Update HashInCount and pHashInBuffPtr accordingly. */
+ hhash->HashInCount = SizeVar;
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ if (initialization_skipped == 1U)
+ {
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ }
+ }
+ else
+ {
+ /* DINIS is not set but it remains a few data to enter (not enough for a full word).
+ Manually enter the last bytes before enabling DCIE. */
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+ HASH->DIN = *(uint32_t*)inputaddr;
+
+ /* Start the Digest calculation */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ __HAL_HASH_START_DIGEST();
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DCI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ } /* if (polling_step == 1) */
+
+
/* Process Unlock */
__HAL_UNLOCK(hhash);
@@ -2539,17 +2923,17 @@
/**
* @brief Initialize the HASH peripheral then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
@@ -2566,7 +2950,7 @@
#endif /* MDMA defined*/
/* If State is ready or suspended, start or resume polling-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ( (pInBuffer == NULL ) || (Size == 0U) ||
/* Check phase coherency. Phase must be
@@ -2636,39 +3020,34 @@
/* Enable the DMA In DMA Stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
-
+
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
-
+
/* Process Unlock */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
- hhash->State = HAL_HASH_STATE_ERROR;
+ hhash->State = HAL_HASH_STATE_ERROR;
}
- else
- {
- /* Change HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- }
-
+
return status;
}
else
{
return HAL_BUSY;
- }
+ }
}
/**
* @brief Return the computed digest.
* @note The API waits for DCIS to be set then reads the computed digest.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -2700,6 +3079,9 @@
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
+ /* Reset HASH state machine */
+ hhash->Phase = HAL_HASH_PHASE_READY;
+
/* Process UnLock */
__HAL_UNLOCK(hhash);
@@ -2721,21 +3103,21 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Timeout: Timeout value.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Timeout Timeout value.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* If State is ready or suspended, start or resume polling-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
@@ -2763,7 +3145,7 @@
}
/* Set the phase to Step 1 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
- /* Resort to hhash internal fields to feed the IP.
+ /* Resort to hhash internal fields to feed the Peripheral.
Parameters will be updated in case of suspension to contain the proper
information at resumption time. */
hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
@@ -2792,20 +3174,20 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
-
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
/* If State is ready or suspended, start or resume IT-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
@@ -2836,7 +3218,7 @@
}
/* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
- to feed the IP whatever the HMAC step.
+ to feed the Peripheral whatever the HMAC step.
Lines below are set to start HMAC Step 1 processing where key is entered first. */
hhash->HashInCount = hhash->Init.KeySize; /* Key size */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */
@@ -2893,17 +3275,17 @@
/**
* @brief Initialize the HASH peripheral in HMAC mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
* be a multiple of 4 otherwise, the HASH digest computation is corrupted.
* Only the length of the last buffer of the thread doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param Algorithm: HASH algorithm.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
@@ -2911,13 +3293,13 @@
uint32_t inputaddr;
uint32_t inputSize;
HAL_StatusTypeDef status ;
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
/* If State is ready or suspended, start or resume DMA-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
- {
+ {
/* Check input parameters */
if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
/* Check phase coherency. Phase must be
@@ -2962,7 +3344,7 @@
{
MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
- #endif
+ #endif
/* Store input aparameters in handle fields to manage steps transition
or possible HMAC suspension/resumption */
hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
@@ -3046,20 +3428,16 @@
/* Process Unlocked */
__HAL_UNLOCK(hhash);
-
+
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
hhash->State = HAL_HASH_STATE_ERROR;
}
- else
- {
- /* Change HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- }
+
/* Return function status */
- return status;
+ return status;
}
else
{
diff --git a/Src/stm32f4xx_hal_hash_ex.c b/Src/stm32f4xx_hal_hash_ex.c
index 792b2e5..640079f 100644
--- a/Src/stm32f4xx_hal_hash_ex.c
+++ b/Src/stm32f4xx_hal_hash_ex.c
@@ -33,16 +33,21 @@
e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
- (#)Multi-buffer processing is possible in polling and DMA mode.
+ (#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
- User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
+ User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
+ except for the last one.
+ User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
+ From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer thru the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
@@ -50,7 +55,7 @@
(+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
extended functions): after initialization, the key and the first input buffer are entered
- in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
@@ -112,17 +117,19 @@
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start()
- (++) HAL_HASHEx_SHA224_Accumulate()
+ (++) HAL_HASHEx_SHA224_Accmlt()
+ (++) HAL_HASHEx_SHA224_Accmlt_End()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start()
- (++) HAL_HASHEx_SHA256_Accumulate()
+ (++) HAL_HASHEx_SHA256_Accmlt()
+ (++) HAL_HASHEx_SHA256_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
- several buffers are fed to the IP), the user can resort to successive calls
+ several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
- to HAL_HASHEx_xxx_Start().
+ to HAL_HASHEx_xxx_Accumulate_End().
@endverbatim
* @{
@@ -133,11 +140,11 @@
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -148,37 +155,52 @@
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASHEx_SHA224_Start().
+ * HAL_HASHEx_SHA224_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
+}
+
+/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -189,28 +211,42 @@
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer.
- * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
- * several input buffers back-to-back to the IP that will yield a single
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
- * HAL_HASHEx_SHA256_Start().
+ * HAL_HASHEx_SHA256_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
- * the IP has already been initialized.
- * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
- * to read it, feeding at the same time the last input buffer to the IP.
+ * the Peripheral has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End()
+ * to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
- * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
+}
/**
* @}
@@ -227,8 +263,12 @@
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_IT()
+ (++) HAL_HASHEx_SHA224_Accmlt_IT()
+ (++) HAL_HASHEx_SHA224_Accmlt_End_IT()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_IT()
+ (++) HAL_HASHEx_SHA256_Accmlt_IT()
+ (++) HAL_HASHEx_SHA256_Accmlt_End_IT()
@endverbatim
* @{
@@ -239,10 +279,10 @@
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -251,13 +291,50 @@
}
/**
+ * @brief If not already done, initialize the HASH peripheral in SHA224 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA224_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+}
+
+/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -266,6 +343,43 @@
}
/**
+ * @brief If not already done, initialize the HASH peripheral in SHA256 mode then
+ * processes pInBuffer in interruption mode.
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed
+ * several input buffers back-to-back to the Peripheral that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA256_Accmlt_End_IT().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the Peripheral has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+}
+
+/**
+ * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+}
+
+/**
* @}
*/
@@ -285,7 +399,7 @@
(++) HAL_HASHEx_SHA256_Start_DMA()
(++) HAL_HASHEx_SHA256_Finish()
- [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
HAL_HASHEx_xxx_Finish().
@@ -303,12 +417,12 @@
/**
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -321,9 +435,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
* HMAC SHA224 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -333,12 +447,12 @@
/**
* @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
- * to feed the input buffer to the IP.
+ * to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
* be called to retrieve the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -351,9 +465,9 @@
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
* HMAC SHA256 mode.
- * @param hhash: HASH handle.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -391,11 +505,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -409,11 +523,11 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
- * @param Timeout: Timeout value.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -452,10 +566,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -469,10 +583,10 @@
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
- * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
+ * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -502,7 +616,7 @@
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_DMA()
- [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
with HAL_HASHEx_xxx_Finish().
@@ -515,7 +629,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
* the computed digest.
@@ -527,9 +641,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -539,7 +653,7 @@
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
- * DMA transfers to feed the key and the input buffer to the IP.
+ * DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
@@ -551,9 +665,9 @@
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (buffer to be hashed).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -597,13 +711,13 @@
calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
intiates step 2 with the first input buffer.
- [..] The following buffers are next fed to the IP with a call to the API
+ [..] The following buffers are next fed to the Peripheral with a call to the API
HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
to this API.
[..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
- buffer to the IP then carries out step 3.
+ buffer to the Peripheral then carries out step 3.
[..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
@@ -618,18 +732,18 @@
/**
* @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -640,7 +754,7 @@
/**
* @brief MD5 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -648,9 +762,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -664,7 +778,7 @@
/**
* @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -674,9 +788,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -688,18 +802,18 @@
/**
* @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -710,7 +824,7 @@
/**
* @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -718,9 +832,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -734,7 +848,7 @@
/**
* @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -744,9 +858,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -757,18 +871,18 @@
/**
* @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -779,7 +893,7 @@
/**
* @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -787,9 +901,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -803,7 +917,7 @@
/**
* @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -813,9 +927,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -826,18 +940,18 @@
/**
* @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
- * @note Step 1 consists in writing the inner hash function key in the IP,
+ * @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
- * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -848,7 +962,7 @@
/**
* @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP.
+ * @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
@@ -856,9 +970,9 @@
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -872,7 +986,7 @@
/**
* @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
- * @note Step 2 consists in writing the message text in the IP,
+ * @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
@@ -882,9 +996,9 @@
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
- * @param hhash: HASH handle.
- * @param pInBuffer: pointer to the input buffer (message buffer).
- * @param Size: length of the input buffer in bytes.
+ * @param hhash HASH handle.
+ * @param pInBuffer pointer to the input buffer (message buffer).
+ * @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
diff --git a/Src/stm32f4xx_hal_i2c.c b/Src/stm32f4xx_hal_i2c.c
index 38d555c..81bb5c7 100644
--- a/Src/stm32f4xx_hal_i2c.c
+++ b/Src/stm32f4xx_hal_i2c.c
@@ -215,12 +215,12 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
-
+ [..]
Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@@ -235,9 +235,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
-
+ [..]
Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
@@ -254,9 +254,9 @@
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
-
+ [..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
-
+ [..]
By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
@@ -265,7 +265,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
+ [..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@@ -273,7 +273,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
or @ref HAL_I2C_Init() function.
-
+ [..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -378,6 +378,8 @@
static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
+
/* Private function to Convert Specific options */
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
/**
@@ -486,6 +488,10 @@
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
+ /*Reset I2C*/
+ hi2c->Instance->CR1 |= I2C_CR1_SWRST;
+ hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
+
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
@@ -3303,7 +3309,11 @@
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ if (hi2c->Instance->CR1 & I2C_CR1_START)
+ {
+ hi2c->ErrorCode = HAL_I2C_WRONG_START;
+ }
+ return HAL_TIMEOUT;
}
/* Send slave address */
@@ -3719,16 +3729,24 @@
Prev_State = hi2c->PreviousState;
- if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
+ if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
{
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Enable Pos */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
- enableIT &= ~I2C_IT_BUF;
+ /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
+ enableIT &= ~I2C_IT_BUF;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
}
else
{
@@ -3841,16 +3859,24 @@
if (hi2c->XferSize > 0U)
{
- if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
+ if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
{
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Enable Pos */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- /* Enable Last DMA bit */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ /* Enable Last DMA bit */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
}
else
{
@@ -3885,6 +3911,14 @@
{
/* Generate Start */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Update interrupt for only EVT and ERR */
+ enableIT = (I2C_IT_EVT | I2C_IT_ERR);
+ }
+ else
+ {
+ /* Update interrupt for only ERR */
+ enableIT = I2C_IT_ERR;
}
/* Process Unlocked */
@@ -3903,7 +3937,7 @@
}
/* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ __HAL_I2C_ENABLE_IT(hi2c, enableIT);
}
else
{
@@ -4694,6 +4728,7 @@
uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
uint32_t itsources = READ_REG(hi2c->Instance->CR2);
uint32_t error = HAL_I2C_ERROR_NONE;
+ HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
/* I2C Bus error interrupt occurred ----------------------------------------*/
if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
@@ -4716,7 +4751,7 @@
/* I2C Acknowledge failure error interrupt occurred ------------------------*/
if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
{
- tmp1 = hi2c->Mode;
+ tmp1 = CurrentMode;
tmp2 = hi2c->XferCount;
tmp3 = hi2c->State;
tmp4 = hi2c->PreviousState;
@@ -4734,7 +4769,7 @@
error |= HAL_I2C_ERROR_AF;
/* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
- if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
@@ -5059,59 +5094,7 @@
{
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
- if (hi2c->EventCount == 0U)
- {
- /* If Memory address size is 8Bit */
- if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
- {
- /* Send Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-
- hi2c->EventCount += 2U;
- }
- /* If Memory address size is 16Bit */
- else
- {
- /* Send MSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
-
- hi2c->EventCount++;
- }
- }
- else if (hi2c->EventCount == 1U)
- {
- /* Send LSB of Memory Address */
- hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
-
- hi2c->EventCount++;
- }
- else if (hi2c->EventCount == 2U)
- {
- if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
- {
- /* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
- {
- /* Write data to DR */
- hi2c->Instance->DR = *hi2c->pBuffPtr;
-
- /* Increment Buffer pointer */
- hi2c->pBuffPtr++;
-
- /* Update counter */
- hi2c->XferCount--;
- }
- else
- {
- /* Do nothing */
- }
- }
- else
- {
- /* Do nothing */
- }
+ I2C_MemoryTransmit_TXE_BTF(hi2c);
}
else
{
@@ -5206,6 +5189,77 @@
}
}
}
+ else if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ I2C_MemoryTransmit_TXE_BTF(hi2c);
+ }
+ else
+ {
+ /* Do nothing */
+ }
+}
+
+/**
+ * @brief Handle TXE and BTF flag for Memory transmitter
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval None
+ */
+static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->EventCount == 0U)
+ {
+ /* If Memory address size is 8Bit */
+ if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+ hi2c->EventCount += 2U;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
+
+ hi2c->EventCount++;
+ }
+ }
+ else if (hi2c->EventCount == 1U)
+ {
+ /* Send LSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+ hi2c->EventCount++;
+ }
+ else if (hi2c->EventCount == 2U)
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ /* Generate Restart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+ }
+ else
+ {
+ /* Do nothing */
+ }
}
/**
@@ -5449,13 +5503,11 @@
hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
}
- if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
+ if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
+ || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
{
- if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
- {
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
- }
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
}
}
else
@@ -6065,6 +6117,7 @@
{
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+ uint32_t CurrentError;
if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
{
@@ -6184,15 +6237,24 @@
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
- /* STOP Flag is not set after a NACK reception */
+
+ /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
+ CurrentError = hi2c->ErrorCode;
+
+ if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
+ ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
+ ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
+ ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
+
/* So may inform upper layer that listen phase is stopped */
/* during NACK error treatment */
CurrentState = hi2c->State;
if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
{
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
@@ -6240,7 +6302,11 @@
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ if (hi2c->Instance->CR1 & I2C_CR1_START)
+ {
+ hi2c->ErrorCode = HAL_I2C_WRONG_START;
+ }
+ return HAL_TIMEOUT;
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
@@ -6309,7 +6375,11 @@
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ if (hi2c->Instance->CR1 & I2C_CR1_START)
+ {
+ hi2c->ErrorCode = HAL_I2C_WRONG_START;
+ }
+ return HAL_TIMEOUT;
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
@@ -6346,7 +6416,11 @@
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ if (hi2c->Instance->CR1 & I2C_CR1_START)
+ {
+ hi2c->ErrorCode = HAL_I2C_WRONG_START;
+ }
+ return HAL_TIMEOUT;
}
/* Send header of slave address */
@@ -6382,7 +6456,11 @@
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ if (hi2c->Instance->CR1 & I2C_CR1_START)
+ {
+ hi2c->ErrorCode = HAL_I2C_WRONG_START;
+ }
+ return HAL_TIMEOUT;
}
/* Send slave address */
@@ -6461,7 +6539,11 @@
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ if (hi2c->Instance->CR1 & I2C_CR1_START)
+ {
+ hi2c->ErrorCode = HAL_I2C_WRONG_START;
+ }
+ return HAL_TIMEOUT;
}
/* Send slave address */
@@ -6531,7 +6613,11 @@
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ if (hi2c->Instance->CR1 & I2C_CR1_START)
+ {
+ hi2c->ErrorCode = HAL_I2C_WRONG_START;
+ }
+ return HAL_TIMEOUT;
}
/* Send slave address */
@@ -6564,8 +6650,14 @@
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
/* Clear Complete callback */
- hi2c->hdmatx->XferCpltCallback = NULL;
- hi2c->hdmarx->XferCpltCallback = NULL;
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->hdmatx->XferCpltCallback = NULL;
+ }
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->hdmarx->XferCpltCallback = NULL;
+ }
if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
{
@@ -6688,8 +6780,14 @@
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Clear Complete callback */
- hi2c->hdmatx->XferCpltCallback = NULL;
- hi2c->hdmarx->XferCpltCallback = NULL;
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->hdmatx->XferCpltCallback = NULL;
+ }
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->hdmarx->XferCpltCallback = NULL;
+ }
/* Ignore DMA FIFO error */
if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
@@ -6726,8 +6824,14 @@
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
/* Clear Complete callback */
- hi2c->hdmatx->XferCpltCallback = NULL;
- hi2c->hdmarx->XferCpltCallback = NULL;
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->hdmatx->XferCpltCallback = NULL;
+ }
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->hdmarx->XferCpltCallback = NULL;
+ }
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
@@ -6735,8 +6839,14 @@
hi2c->XferCount = 0U;
/* Reset XferAbortCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->hdmatx->XferAbortCallback = NULL;
+ }
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->hdmarx->XferAbortCallback = NULL;
+ }
/* Disable I2C peripheral to prevent dummy data in buffer */
__HAL_I2C_DISABLE(hi2c);
diff --git a/Src/stm32f4xx_hal_i2s.c b/Src/stm32f4xx_hal_i2s.c
index fc7f6ae..20a0e95 100644
--- a/Src/stm32f4xx_hal_i2s.c
+++ b/Src/stm32f4xx_hal_i2s.c
@@ -113,14 +113,14 @@
Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
Function HAL_I2S_RegisterCallback() allows to register following callbacks:
- (+) TxCpltCallback : I2S Tx Completed callback
- (+) RxCpltCallback : I2S Rx Completed callback
- (+) TxRxCpltCallback : I2S TxRx Completed callback
- (+) TxHalfCpltCallback : I2S Tx Half Completed callback
- (+) RxHalfCpltCallback : I2S Rx Half Completed callback
- (+) ErrorCallback : I2S Error callback
- (+) MspInitCallback : I2S Msp Init callback
- (+) MspDeInitCallback : I2S Msp DeInit callback
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxRxCpltCallback : I2S TxRx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
@@ -130,15 +130,16 @@
HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
- (+) TxCpltCallback : I2S Tx Completed callback
- (+) RxCpltCallback : I2S Rx Completed callback
- (+) TxRxCpltCallback : I2S TxRx Completed callback
- (+) TxHalfCpltCallback : I2S Tx Half Completed callback
- (+) RxHalfCpltCallback : I2S Rx Half Completed callback
- (+) ErrorCallback : I2S Error callback
- (+) MspInitCallback : I2S Msp Init callback
- (+) MspDeInitCallback : I2S Msp DeInit callback
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxRxCpltCallback : I2S TxRx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+ [..]
By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
@@ -148,6 +149,7 @@
If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
@@ -156,7 +158,8 @@
using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
or HAL_I2S_Init() function.
- When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+ [..]
+ When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -428,7 +431,7 @@
/* Write to SPIx I2SCFGR */
SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
}
-#endif
+#endif /* SPI_I2SCFGR_ASTRTEN */
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
@@ -561,7 +564,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -910,7 +914,8 @@
}
/* Check if Slave mode is selected */
- if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+ if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
/* Wait until Busy flag is reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
@@ -1219,7 +1224,10 @@
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
/* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize))
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
+ (uint32_t)hi2s->pTxBuffPtr,
+ (uint32_t)&hi2s->Instance->DR,
+ hi2s->TxXferSize))
{
/* Update SPI error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
@@ -1315,7 +1323,8 @@
}
/* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
+ hi2s->RxXferSize))
{
/* Update SPI error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
@@ -1896,7 +1905,8 @@
* @param Timeout Duration of the timeout
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout)
{
uint32_t tickstart;
diff --git a/Src/stm32f4xx_hal_i2s_ex.c b/Src/stm32f4xx_hal_i2s_ex.c
index abc960f..11cfb82 100644
--- a/Src/stm32f4xx_hal_i2s_ex.c
+++ b/Src/stm32f4xx_hal_i2s_ex.c
@@ -126,7 +126,7 @@
static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
- uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
/**
* @}
*/
@@ -1088,7 +1088,7 @@
* @retval HAL status
*/
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
- uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
{
uint32_t tickstart = HAL_GetTick();
diff --git a/Src/stm32f4xx_hal_irda.c b/Src/stm32f4xx_hal_irda.c
index 97b1475..511a5bf 100644
--- a/Src/stm32f4xx_hal_irda.c
+++ b/Src/stm32f4xx_hal_irda.c
@@ -756,12 +756,15 @@
*/
/**
- * @brief Sends an amount of data in blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Specify timeout value
+ * @brief Sends an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -838,12 +841,15 @@
}
/**
- * @brief Receive an amount of data in blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
- * @param Timeout Specify timeout value
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -926,11 +932,14 @@
}
/**
- * @brief Send an amount of data in non blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @brief Send an amount of data in non blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -968,11 +977,14 @@
}
/**
- * @brief Receive an amount of data in non blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
+ * @brief Receive an amount of data in non blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1013,11 +1025,14 @@
}
/**
- * @brief Send an amount of data in non blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1077,11 +1092,14 @@
}
/**
- * @brief Receives an amount of data in non blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
+ * @brief Receives an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
@@ -1745,7 +1763,7 @@
}
/* IRDA Over-Run interrupt occurred -----------------------------------*/
- if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
}
@@ -2582,6 +2600,8 @@
*/
static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
+ uint32_t pclk;
+
/* Check the parameters */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@@ -2610,20 +2630,29 @@
CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/
-#if defined(USART6)
+#if defined(USART6) && defined(UART9) && defined(UART10)
+ if ((hirda->Instance == USART1) || (hirda->Instance == USART6) || (hirda->Instance == UART9) || (hirda->Instance == UART10))
+ {
+ pclk = HAL_RCC_GetPCLK2Freq();
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
+ }
+#elif defined(USART6)
if((hirda->Instance == USART1) || (hirda->Instance == USART6))
{
- SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
}
#else
if(hirda->Instance == USART1)
{
- SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
}
#endif /* USART6 */
else
{
- SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
}
}
diff --git a/Src/stm32f4xx_hal_iwdg.c b/Src/stm32f4xx_hal_iwdg.c
index cb49dbf..c356973 100644
--- a/Src/stm32f4xx_hal_iwdg.c
+++ b/Src/stm32f4xx_hal_iwdg.c
@@ -48,14 +48,14 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
- (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
- (+) Enable write access to configuration registers:
+ (++) Enable write access to configuration registers:
IWDG_PR and IWDG_RLR.
- (+) Configure the IWDG prescaler and counter reload value. This reload
+ (++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (+) Wait for status flags to be reset.
+ (++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@@ -120,8 +120,8 @@
*/
/** @addtogroup IWDG_Exported_Functions_Group1
- * @brief Initialization and Start functions.
- *
+ * @brief Initialization and Start functions.
+ *
@verbatim
===============================================================================
##### Initialization and Start functions #####
@@ -195,8 +195,8 @@
/** @addtogroup IWDG_Exported_Functions_Group2
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
diff --git a/Src/stm32f4xx_hal_lptim.c b/Src/stm32f4xx_hal_lptim.c
index 1d43bb8..aadaf2a 100644
--- a/Src/stm32f4xx_hal_lptim.c
+++ b/Src/stm32f4xx_hal_lptim.c
@@ -89,19 +89,19 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
-
+ [..]
Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
@ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
-
+ [..]
Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function.
@ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
-
+ [..]
These functions allow to register/unregister following callbacks:
(+) MspInitCallback : LPTIM Base Msp Init Callback.
@@ -114,15 +114,18 @@
(+) DirectionUpCallback : Up-counting direction change Callback.
(+) DirectionDownCallback : Down-counting direction change Callback.
+ [..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+ [..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init/DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
@@ -130,13 +133,14 @@
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+ [..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -145,7 +149,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -166,13 +171,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Constants
+ * @{
+ */
#define TIMEOUT 1000UL /* Timeout is 1s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
/* Exported functions --------------------------------------------------------*/
@@ -325,6 +338,11 @@
/* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
if (hlptim->MspDeInitCallback == NULL)
{
@@ -433,12 +451,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -465,6 +501,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -494,6 +535,41 @@
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -516,12 +592,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -548,6 +618,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -599,12 +674,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -631,6 +724,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -660,6 +758,41 @@
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -682,12 +815,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -714,6 +841,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -765,12 +897,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -797,6 +947,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -826,6 +981,41 @@
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -848,12 +1038,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -880,6 +1064,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -945,9 +1134,18 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -974,6 +1172,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@@ -1021,6 +1224,29 @@
/* Set ENC bit to enable the encoder interface */
hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable "switch to down direction" interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
@@ -1030,9 +1256,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1059,6 +1282,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@@ -1102,12 +1330,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1134,6 +1380,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@@ -1167,22 +1418,55 @@
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
+#if defined(EXTI_IMR_MR23)
+ /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+#endif /* EXTI_IMR_MR23 */
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Compare match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the Timeout value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1205,6 +1489,10 @@
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+#if defined(EXTI_IMR_MR23)
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+#endif /* EXTI_IMR_MR23 */
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
@@ -1212,6 +1500,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@@ -1253,9 +1546,18 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1282,6 +1584,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -1307,6 +1614,10 @@
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
+#if defined(EXTI_IMR_MR23)
+ /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+#endif /* EXTI_IMR_MR23 */
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
@@ -1317,6 +1628,29 @@
hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
}
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -1326,9 +1660,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1351,6 +1682,10 @@
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+#if defined(EXTI_IMR_MR23)
+ /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+#endif /* EXTI_IMR_MR23 */
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
@@ -1358,12 +1693,16 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -1580,6 +1919,9 @@
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
+#if defined(EXTI_IMR_MR23)
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+#endif /* EXTI_IMR_MR23 */
}
/**
@@ -1961,15 +2303,39 @@
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
+ * @brief LPTimer Wait for flag set
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param flag The lptim flag
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+{
+ HAL_StatusTypeDef result = HAL_OK;
+ uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ result = HAL_TIMEOUT;
+ }
+ }
+ while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+
+ return result;
+}
+
+/**
* @brief Disable LPTIM HW instance.
- * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
* @retval None
*/
-void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
{
uint32_t tmpclksource = 0;
uint32_t tmpIER;
@@ -1982,95 +2348,91 @@
/*********** Save LPTIM Config ***********/
/* Save LPTIM source clock */
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
- tmpIER = lptim->Instance->IER;
- tmpCFGR = lptim->Instance->CFGR;
- tmpCMP = lptim->Instance->CMP;
- tmpARR = lptim->Instance->ARR;
- tmpOR = lptim->Instance->OR;
+ tmpIER = hlptim->Instance->IER;
+ tmpCFGR = hlptim->Instance->CFGR;
+ tmpCMP = hlptim->Instance->CMP;
+ tmpARR = hlptim->Instance->ARR;
+ tmpOR = hlptim->Instance->OR;
/*********** Reset LPTIM ***********/
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_FORCE_RESET();
- __HAL_RCC_LPTIM1_RELEASE_RESET();
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
+ default:
+ break;
}
/*********** Restore LPTIM Config ***********/
- uint32_t Ref_Time;
- uint32_t Time_Elapsed;
-
if ((tmpCMP != 0UL) || (tmpARR != 0UL))
{
/* Force LPTIM source kernel clock from APB */
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
{
/* Restore CMP register (LPTIM should be enabled first) */
- lptim->Instance->CR |= LPTIM_CR_ENABLE;
- lptim->Instance->CMP = tmpCMP;
- /* Polling on CMP write ok status after above restore operation */
- Ref_Time = HAL_GetTick();
- do
- {
- Time_Elapsed = HAL_GetTick() - Ref_Time;
- } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT));
+ hlptim->Instance->CR |= LPTIM_CR_ENABLE;
+ hlptim->Instance->CMP = tmpCMP;
- __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
+ }
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
}
if (tmpARR != 0UL)
{
/* Restore ARR register (LPTIM should be enabled first) */
- lptim->Instance->CR |= LPTIM_CR_ENABLE;
- lptim->Instance->ARR = tmpARR;
- /* Polling on ARR write ok status after above restore operation */
- Ref_Time = HAL_GetTick();
- do
- {
- Time_Elapsed = HAL_GetTick() - Ref_Time;
- } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT));
+ hlptim->Instance->CR |= LPTIM_CR_ENABLE;
+ hlptim->Instance->ARR = tmpARR;
- __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
+ }
+
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
}
/* Restore LPTIM source kernel clock */
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
+ default:
+ break;
}
}
/* Restore configuration registers (LPTIM should be disabled first) */
- lptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
- lptim->Instance->IER = tmpIER;
- lptim->Instance->CFGR = tmpCFGR;
- lptim->Instance->OR = tmpOR;
+ hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
+ hlptim->Instance->IER = tmpIER;
+ hlptim->Instance->CFGR = tmpCFGR;
+ hlptim->Instance->OR = tmpOR;
__enable_irq();
}
diff --git a/Src/stm32f4xx_hal_ltdc.c b/Src/stm32f4xx_hal_ltdc.c
index 6620eb6..7e44130 100644
--- a/Src/stm32f4xx_hal_ltdc.c
+++ b/Src/stm32f4xx_hal_ltdc.c
@@ -14,12 +14,24 @@
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
- (#) Program the required configuration through the following parameters:
- the LTDC timing, the horizontal and vertical polarity,
- the pixel clock polarity, Data Enable polarity and the LTDC background color value
- using HAL_LTDC_Init() function
+ [..]
+ The LTDC HAL driver can be used as follows:
+ (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc;
+
+ (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API:
+ (##) Enable the LTDC interface clock
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the LTDC interrupt priority
+ (+++) Enable the NVIC LTDC IRQ Channel
+
+ (#) Initialize the required configuration through the following parameters:
+ the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity,
+ Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function
+
+ *** Configuration ***
+ =========================
+ [..]
(#) Program the required configuration through the following parameters:
the pixel format, the blending factors, input alpha value, the window size
and the image size using HAL_LTDC_ConfigLayer() function for foreground
@@ -73,58 +85,65 @@
(+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
(+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
-
- *** Callback registration ***
- =============================================
-
- The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_LTDC_RegisterCallback() to register a callback.
-
- Function @ref HAL_LTDC_RegisterCallback() allows to register following callbacks:
- (+) LineEventCallback : LTDC Line Event Callback.
- (+) ReloadEventCallback : LTDC Reload Event Callback.
- (+) ErrorCallback : LTDC Error Callback
- (+) MspInitCallback : LTDC MspInit.
- (+) MspDeInitCallback : LTDC MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
-
- Use function @ref HAL_LTDC_UnRegisterCallback() to reset a callback to the default
- weak function.
- @ref HAL_LTDC_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (+) LineEventCallback : LTDC Line Event Callback.
- (+) ReloadEventCallback : LTDC Reload Event Callback.
- (+) ErrorCallback : LTDC Error Callback
- (+) MspInitCallback : LTDC MspInit.
- (+) MspDeInitCallback : LTDC MspDeInit.
-
- By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
- all callbacks are set to the corresponding weak functions:
- examples @ref HAL_LTDC_LineEventCallback(), @ref HAL_LTDC_ErrorCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the HAL_LTDC_Init/ @ref HAL_LTDC_DeInit only when
- these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_LTDC_Init/ @ref HAL_LTDC_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_LTDC_RegisterCallback() before calling @ref HAL_LTDC_DeInit
- or HAL_LTDC_Init function.
-
- When The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
-
[..]
(@) You can refer to the LTDC HAL driver header file for more useful macros
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use function HAL_LTDC_RegisterCallback() to register a callback.
+
+ [..]
+ Function HAL_LTDC_RegisterCallback() allows to register following callbacks:
+ (+) LineEventCallback : LTDC Line Event Callback.
+ (+) ReloadEventCallback : LTDC Reload Event Callback.
+ (+) ErrorCallback : LTDC Error Callback
+ (+) MspInitCallback : LTDC MspInit.
+ (+) MspDeInitCallback : LTDC MspDeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle
+ and the callback ID.
+ [..]
+ This function allows to reset following callbacks:
+ (+) LineEventCallback : LTDC Line Event Callback
+ (+) ReloadEventCallback : LTDC Reload Event Callback
+ (+) ErrorCallback : LTDC Error Callback
+ (+) MspInitCallback : LTDC MspInit
+ (+) MspDeInitCallback : LTDC MspDeInit.
+
+ [..]
+ By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit()
+ only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit()
+ or HAL_LTDC_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
@@ -143,12 +162,14 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
-#ifdef HAL_LTDC_MODULE_ENABLED
-#if defined (LTDC)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+#ifdef HAL_LTDC_MODULE_ENABLED
+
+#if defined (LTDC)
+
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
@@ -2131,12 +2152,12 @@
* @}
*/
+#endif /* LTDC */
+
+#endif /* HAL_LTDC_MODULE_ENABLED */
/**
* @}
*/
-#endif /* LTDC */
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f4xx_hal_ltdc_ex.c b/Src/stm32f4xx_hal_ltdc_ex.c
index af75587..8c39194 100644
--- a/Src/stm32f4xx_hal_ltdc_ex.c
+++ b/Src/stm32f4xx_hal_ltdc_ex.c
@@ -24,6 +24,8 @@
* @{
*/
+#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
+
#if defined (LTDC) && defined (DSI)
/** @defgroup LTDCEx LTDCEx
@@ -31,8 +33,6 @@
* @{
*/
-#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -134,14 +134,14 @@
* @}
*/
-#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
-
/**
* @}
*/
#endif /* LTDC && DSI */
+#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/Src/stm32f4xx_hal_mmc.c b/Src/stm32f4xx_hal_mmc.c
index 28e8f0c..eaf7088 100644
--- a/Src/stm32f4xx_hal_mmc.c
+++ b/Src/stm32f4xx_hal_mmc.c
@@ -3,34 +3,34 @@
* @file stm32f4xx_hal_mmc.c
* @author MCD Application Team
* @brief MMC card HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + MMC card Control functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
- the user in HAL_MMC_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_MMC_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
- This driver is a generic layered driver for SDMMC memories which uses the HAL
- SDMMC driver functions to interface with MMC and eMMC cards devices.
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with MMC and eMMC cards devices.
It is used as follows:
-
+
(#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
- (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
(##) SDMMC pins configuration for MMC card
- (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA()
@@ -38,8 +38,8 @@
(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
(+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
- (+++) Configure the SDMMC and DMA interrupt priorities using functions
- HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
+ (+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority();
+ DMA priority is superior to SDMMC's priority
(+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
@@ -47,70 +47,71 @@
and __HAL_MMC_CLEAR_IT()
(##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
and HAL_MMC_WriteBlocks_IT() APIs).
- (+++) Configure the SDMMC interrupt priorities using function
- HAL_NVIC_SetPriority();
+ (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+ (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
and __HAL_MMC_CLEAR_IT()
- (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
+ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
-
+
*** MMC Card Initialization and configuration ***
- ================================================
+ ================================================
[..]
- To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
- SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
+ To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
+ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
(#) Initialize the SDMMC peripheral interface with defaullt configuration.
- The initialization process is done at 400KHz. You can change or adapt
- this frequency by adjusting the "ClockDiv" field.
+ The initialization process is done at 400KHz. You can change or adapt
+ this frequency by adjusting the "ClockDiv" field.
The MMC Card frequency (SDMMC_CK) is computed as follows:
-
+
SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
-
- In initialization mode and according to the MMC Card standard,
+
+ In initialization mode and according to the MMC Card standard,
make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
- This phase of initialization is done through SDMMC_Init() and
+ This phase of initialization is done through SDMMC_Init() and
SDMMC_PowerState_ON() SDMMC low level APIs.
(#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
- This phase allows the card initialization and identification
+ This phase allows the card initialization and identification
and check the MMC Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with MMC standard.
- This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
+ This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
- (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
+ (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
frequency is set to 24MHz. You can change or adapt this frequency by adjusting
the "ClockDiv" field.
- In transfer mode and according to the MMC Card standard, make sure that the
+ In transfer mode and according to the MMC Card standard, make sure that the
SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
- To be able to use a frequency higher than 24MHz, you should use the SDMMC
- peripheral in bypass mode. Refer to the corresponding reference manual
+ To be able to use a frequency higher than 24MHz, you should use the SDMMC
+ peripheral in bypass mode. Refer to the corresponding reference manual
for more details.
-
+
(#) Select the corresponding MMC Card according to the address read with the step 2.
-
+
(#) Configure the MMC Card in wide bus mode: 4-bits data.
-
+
*** MMC Card Read operation ***
==============================
- [..]
- (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ [..]
+ (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
@@ -123,20 +124,22 @@
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Rx interrupt event.
-
+
*** MMC Card Write operation ***
- ===============================
- [..]
- (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ ===============================
+ [..]
+ (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 byte).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
@@ -149,12 +152,6 @@
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Tx interrupt event.
-
- *** MMC card status ***
- ======================
- [..]
- (+) The MMC Status contains status bits that are related to the MMC Memory
- Card proprietary features. To get MMC card status use the HAL_MMC_GetCardStatus().
*** MMC card information ***
===========================
@@ -179,7 +176,7 @@
==================================
[..]
Below the list of most used macros in MMC HAL driver.
-
+
(+) __HAL_MMC_ENABLE : Enable the MMC device
(+) __HAL_MMC_DISABLE : Disable the MMC device
(+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer
@@ -188,10 +185,10 @@
(+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
(+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
(+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
-
- [..]
- (@) You can refer to the MMC HAL driver header file for more useful macros
-
+
+ [..]
+ (@) You can refer to the MMC HAL driver header file for more useful macros
+
*** Callback registration ***
=============================================
[..]
@@ -222,7 +219,7 @@
By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
+ reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -232,12 +229,13 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL__RegisterCallback before calling @ref HAL_MMC_DeInit
+ using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
or @ref HAL_MMC_Init function.
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
@@ -248,10 +246,10 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -260,28 +258,25 @@
* @{
*/
-/** @addtogroup MMC
+/** @defgroup MMC MMC
+ * @brief MMC HAL module driver
* @{
*/
#ifdef HAL_MMC_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(SDIO)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup MMC_Private_Defines
* @{
*/
-
+
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -290,33 +285,32 @@
* @{
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
-static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
-static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
-static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc);
-static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc);
-static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void MMC_DMAError(DMA_HandleTypeDef *hdma);
-static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
-static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
+static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
+static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
+static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
+static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAError(DMA_HandleTypeDef *hdma);
+static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MMC_Exported_Functions
* @{
*/
/** @addtogroup MMC_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to initialize/de-initialize the MMC
card device to be ready for use.
@@ -325,9 +319,9 @@
*/
/**
- * @brief Initializes the MMC according to the specified parameters in the
+ * @brief Initializes the MMC according to the specified parameters in the
MMC_HandleTypeDef and create the associated handle.
- * @param hmmc Pointer to the MMC handle
+ * @param hmmc: Pointer to the MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
@@ -351,7 +345,7 @@
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_MMC_STATE_RESET only */
hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
@@ -368,20 +362,23 @@
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_MMC_MspInit(hmmc);
-#endif
+#endif
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize the Card parameters */
- HAL_MMC_InitCard(hmmc);
+ if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
/* Initialize the error code */
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
-
+
/* Initialize the MMC state */
hmmc->State = HAL_MMC_STATE_READY;
@@ -390,17 +387,18 @@
/**
* @brief Initializes the MMC Card.
- * @param hmmc Pointer to MMC handle
- * @note This function initializes the MMC card. It could be used when a card
+ * @param hmmc: Pointer to MMC handle
+ * @note This function initializes the MMC card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
MMC_InitTypeDef Init;
+ HAL_StatusTypeDef status;
- /* Default SDMMC peripheral configuration for MMC card initialization */
+ /* Default SDIO peripheral configuration for MMC card initialization */
Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
@@ -408,22 +406,26 @@
Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDIO_INIT_CLK_DIV;
- /* Initialize SDMMC peripheral interface with default configuration */
- SDIO_Init(hmmc->Instance, Init);
+ /* Initialize SDIO peripheral interface with default configuration */
+ status = SDIO_Init(hmmc->Instance, Init);
+ if(status == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
- /* Disable SDMMC Clock */
+ /* Disable SDIO Clock */
__HAL_MMC_DISABLE(hmmc);
/* Set Power State to ON */
- SDIO_PowerState_ON(hmmc->Instance);
-
- /* Enable SDMMC Clock */
+ status = SDIO_PowerState_ON(hmmc->Instance);
+ if(status == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable MMC Clock */
__HAL_MMC_ENABLE(hmmc);
-
- /* Required power up waiting time before starting the SD initialization
- sequence */
- HAL_Delay(2U);
-
+
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -447,7 +449,7 @@
/**
* @brief De-Initializes the MMC card.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
@@ -457,16 +459,16 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
hmmc->State = HAL_MMC_STATE_BUSY;
-
- /* Set SD power state to off */
+
+ /* Set MMC power state to off */
MMC_PowerOFF(hmmc);
-
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
if(hmmc->MspDeInitCallback == NULL)
{
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
@@ -478,24 +480,24 @@
/* De-Initialize the MSP layer */
HAL_MMC_MspDeInit(hmmc);
#endif
-
+
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_RESET;
-
+
return HAL_OK;
}
/**
* @brief Initializes the MMC MSP.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspInit could be implemented in the user file
*/
@@ -503,14 +505,14 @@
/**
* @brief De-Initialize MMC MSP.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspDeInit could be implemented in the user file
*/
@@ -521,14 +523,14 @@
*/
/** @addtogroup MMC_Exported_Functions_Group2
- * @brief Data transfer functions
+ * @brief Data transfer functions
*
-@verbatim
+@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to manage the data
+ This subsection provides a set of functions allowing to manage the data
transfer from/to MMC card.
@endverbatim
@@ -536,142 +538,155 @@
*/
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc Pointer to MMC handle
- * @param pData pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of MMC blocks to read
- * @param Timeout Specify timeout value
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of MMC blocks to read
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
/* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
+ (void)SDIO_ConfigData(hmmc->Instance, &config);
+
/* Read block(s) in polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
-
+
/* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Poll on SDMMC flags */
-#ifdef SDIO_STA_STBITERR
- while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
+
+ /* Poll on SDIO flags */
+ dataremaining = config.DataLength;
+#if defined(SDIO_STA_STBITERR)
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
#endif /* SDIO_STA_STBITERR */
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF))
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))
{
- /* Read data from SDMMC Rx FIFO */
+ /* Read data from SDIO Rx FIFO */
for(count = 0U; count < 8U; count++)
{
- *(tempbuff + count) = SDIO_ReadFIFO(hmmc->Instance);
+ data = SDIO_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State= HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
-
+
/* Send stop transmission command in case of multiblock read */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
-
+
/* Get error state */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -679,7 +694,7 @@
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -687,33 +702,48 @@
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Empty FIFO if there is still any data */
- while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL)))
+ else
{
- *tempbuff = SDIO_ReadFIFO(hmmc->Instance);
+ /* Nothing to do */
+ }
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))
+ {
+ data = SDIO_ReadFIFO(hmmc->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State= HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
-
+
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
+
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -728,21 +758,22 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc Pointer to MMC handle
- * @param pData pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of MMC blocks to write
- * @param Timeout Specify timeout value
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of MMC blocks to write
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U;
- uint32_t *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
@@ -751,111 +782,122 @@
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
-
+
/* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
+ (void)SDIO_ConfigData(hmmc->Instance, &config);
+
/* Write block(s) in polling mode */
-#ifdef SDIO_STA_STBITERR
+ dataremaining = config.DataLength;
+#if defined(SDIO_STA_STBITERR)
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
#endif /* SDIO_STA_STBITERR */
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE))
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))
{
/* Write data to SDIO Tx FIFO */
for(count = 0U; count < 8U; count++)
{
- SDIO_WriteFIFO(hmmc->Instance, (tempbuff + count));
+ data = (uint32_t)(*tempbuff);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 8U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 16U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 24U);
+ tempbuff++;
+ dataremaining--;
+ (void)SDIO_WriteFIFO(hmmc->Instance, &data);
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
-
+
/* Send stop transmission command in case of multiblock write */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
-
+
/* Get error state */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
{
@@ -869,7 +911,7 @@
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
@@ -881,12 +923,16 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
+
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -897,99 +943,104 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Rx
+ * @note You could also check the IT transfer process through the MMC Rx
* interrupt event.
- * @param hmmc Pointer to MMC handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
- hmmc->pRxBuffPtr = (uint32_t *)pData;
- hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ hmmc->pRxBuffPtr = pData;
+ hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
+#if defined(SDIO_STA_STBITERR)
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
+#endif /* SDIO_STA_STBITERR */
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ (void)SDIO_ConfigData(hmmc->Instance, &config);
+
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
-
+
/* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
+
/* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
+
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
@@ -999,99 +1050,103 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the IT transfer process through the MMC Tx
- * interrupt event.
- * @param hmmc Pointer to MMC handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @note You could also check the IT transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
- hmmc->pTxBuffPtr = (uint32_t *)pData;
- hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
+ hmmc->pTxBuffPtr = pData;
+ hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
+
/* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+#if defined(SDIO_STA_STBITERR)
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
+#endif /* SDIO_STA_STBITERR */
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
+ (void)SDIO_ConfigData(hmmc->Instance, &config);
return HAL_OK;
}
@@ -1102,116 +1157,126 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Rx
+ * @note You could also check the DMA transfer process through the MMC Rx
* interrupt event.
- * @param hmmc Pointer MMC handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hmmc: Pointer MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
-#ifdef SDIO_STA_STBITERR
+
+#if defined(SDIO_STA_STBITERR)
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
#endif /* SDIO_STA_STBITERR */
-
+
/* Set the DMA transfer complete callback */
hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt;
-
+
/* Set the DMA error callback */
hmmc->hdmarx->XferErrorCallback = MMC_DMAError;
-
+
/* Set the DMA Abort callback */
hmmc->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Enable MMC DMA transfer */
- __HAL_MMC_DMA_ENABLE(hmmc);
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
/* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
+ hmmc->ErrorCode = errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
+
+ /* Enable the DMA Channel */
+ if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
{
- hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode = HAL_MMC_ERROR_DMA;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
}
else
{
- hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
- }
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
+ /* Enable MMC DMA transfer */
+ __HAL_MMC_DMA_ENABLE(hmmc);
- return HAL_OK;
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ (void)SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+ hmmc->ErrorCode = errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
}
else
{
@@ -1220,117 +1285,127 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @note You could also check the DMA transfer process through the MMC Tx
+ * @note You could also check the DMA transfer process through the MMC Tx
* interrupt event.
- * @param hmmc Pointer to MMC handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-
+
/* Enable MMC Error interrupts */
-#ifdef SDIO_STA_STBITERR
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+#if defined(SDIO_STA_STBITERR)
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
- __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
-#endif /* SDIO_STA_STBITERR */
-
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
+#endif /* SDIO_STA_STBITERR */
+
/* Set the DMA transfer complete callback */
hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt;
-
+
/* Set the DMA error callback */
hmmc->hdmatx->XferErrorCallback = MMC_DMAError;
-
+
/* Set the DMA Abort callback */
hmmc->hdmatx->XferAbortCallback = NULL;
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
-
+
/* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Enable SDIO DMA transfer */
__HAL_MMC_DMA_ENABLE(hmmc);
-
+
/* Enable the DMA Channel */
- HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hmmc->Instance, &config);
-
- return HAL_OK;
+ if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
+ {
+ __HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ (void)SDIO_ConfigData(hmmc->Instance, &config);
+
+ return HAL_OK;
+ }
}
else
{
@@ -1342,33 +1417,35 @@
* @brief Erases the specified memory area of the given MMC card.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc Pointer to MMC handle
- * @param BlockStartAdd Start Block address
- * @param BlockEndAdd End Block address
+ * @param hmmc: Pointer to MMC handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if(BlockEndAdd < BlockStartAdd)
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ if(end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
-
- if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr))
+
+ if(end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Check if the card command class supports erase command */
if(((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE) == 0U)
{
@@ -1378,58 +1455,57 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
if((SDIO_GetResponse(hmmc->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
- /* Check the Card capacity in term of Logical number of blocks */
- if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+
+ if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
- BlockStartAdd *= 512U;
- BlockEndAdd *= 512U;
+ start_add *= 512U;
+ end_add *= 512U;
}
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd);
+ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd);
+ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
-
+
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -1440,79 +1516,51 @@
/**
* @brief This function handles MMC card interrupt request.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t context = hmmc->Context;
+
/* Check for SDIO interrupt flags */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DATAEND) != RESET)
+ if((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND);
-
-#ifdef SDIO_STA_STBITERR
+ MMC_Read_IT(hmmc);
+ }
+
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND);
+
+#if defined(SDIO_STA_STBITERR)
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
#else /* SDIO_STA_STBITERR not defined */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR);
-#endif
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT |\
+ SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\
+ SDIO_IT_RXFIFOHF);
+#endif /* SDIO_STA_STBITERR */
- if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ hmmc->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);
+
+ if((context & MMC_CONTEXT_DMA) != 0U)
{
- if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
-
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- hmmc->State = HAL_MMC_STATE_READY;
- if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
- {
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->RxCpltCallback(hmmc);
-#else
- HAL_MMC_RxCpltCallback(hmmc);
-#endif
- }
- else
- {
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->TxCpltCallback(hmmc);
-#else
- HAL_MMC_TxCpltCallback(hmmc);
-#endif
- }
- }
- else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
- {
- if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
- {
- errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- hmmc->ErrorCode |= errorstate;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
- }
- }
- if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
{
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the MMC DCTRL register */
@@ -1520,127 +1568,121 @@
hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
-#else
+#else
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
}
+ else if((context & MMC_CONTEXT_IT) != 0U)
+ {
+ /* Stop Transfer for Write Multi blocks or Read Multi blocks */
+ if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
+ HAL_MMC_ErrorCallback(hmmc);
+#endif
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->RxCpltCallback(hmmc);
+#else
+ HAL_MMC_RxCpltCallback(hmmc);
+#endif
+ }
+ else
+ {
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->TxCpltCallback(hmmc);
+#else
+ HAL_MMC_TxCpltCallback(hmmc);
+#endif
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXFIFOHE) != RESET)
+
+ else if((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_TXFIFOHE);
-
MMC_Write_IT(hmmc);
}
-
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXFIFOHF) != RESET)
- {
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_RXFIFOHF);
-
- MMC_Read_IT(hmmc);
- }
-
-#ifdef SDIO_STA_STBITERR
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
+
+#if defined(SDIO_STA_STBITERR)
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET)
+#else /* SDIO_STA_STBITERR not defined */
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET)
+#endif /* SDIO_STA_STBITERR */
{
/* Set Error code */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL) != RESET)
{
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_STBITERR) != RESET)
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
}
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ }
+#if defined(SDIO_STA_STBITERR)
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_STBITERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+#endif /* SDIO_STA_STBITERR */
+#if defined(SDIO_STA_STBITERR)
/* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);
+
+ /* Disable all interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR */
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
/* Disable all interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
-
- if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
- {
- /* Abort the MMC DMA Streams */
- if(hmmc->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
- {
- MMC_DMATxAbort(hmmc->hdmatx);
- }
- }
- else if(hmmc->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
- {
- MMC_DMARxAbort(hmmc->hdmarx);
- }
- }
- else
- {
- hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- hmmc->State = HAL_MMC_STATE_READY;
- HAL_MMC_AbortCallback(hmmc);
- }
- }
- else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+#endif /* SDIO_STA_STBITERR */
+
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+
+ if((context & MMC_CONTEXT_IT) != 0U)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
- }
-#else /* SDIO_STA_STBITERR not defined */
- else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR) != RESET)
- {
- /* Set Error code */
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
- }
- if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
- {
- hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
- }
-
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- /* Disable all interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+ else if((context & MMC_CONTEXT_DMA) != 0U)
{
/* Abort the MMC DMA Streams */
if(hmmc->hdmatx != NULL)
@@ -1667,30 +1709,28 @@
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
#endif
}
}
- else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ else
{
- /* Set the MMC state to ready to be able to start again the process */
- hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->ErrorCallback(hmmc);
-#else
- HAL_MMC_ErrorCallback(hmmc);
-#endif
+ /* Nothing to do */
}
}
-#endif /* SDIO_STA_STBITERR */
+
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
* @brief return the MMC state
- * @param hmmc Pointer to mmc handle
+ * @param hmmc: Pointer to mmc handle
* @retval HAL state
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
@@ -1700,7 +1740,7 @@
/**
* @brief Return the MMC error code
-* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains
+* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval MMC Error Code
*/
@@ -1711,10 +1751,10 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval None
*/
- __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
+__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
@@ -1726,14 +1766,14 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hmmc Pointer MMC handle
+ * @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_RxCpltCallback can be implemented in the user file
*/
@@ -1741,47 +1781,47 @@
/**
* @brief MMC error callbacks
- * @param hmmc Pointer MMC handle
+ * @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
* @brief MMC Abort callbacks
- * @param hmmc Pointer MMC handle
+ * @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_MMC_ErrorCallback can be implemented in the user file
- */
+ the HAL_MMC_AbortCallback can be implemented in the user file
+ */
}
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User MMC Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (surcharged) predefined callback
* @param hmmc : MMC handle
- * @param CallbackID : ID of the callback to be registered
+ * @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
- * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
- * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
@@ -1798,7 +1838,7 @@
/* Process locked */
__HAL_LOCK(hmmc);
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@@ -1823,7 +1863,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1841,7 +1881,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1850,7 +1890,7 @@
else
{
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1862,16 +1902,16 @@
/**
* @brief Unregister a User MMC Callback
- * MMC Callback is redirected to the weak (surcharged) predefined callback
+ * MMC Callback is redirected to the weak (surcharged) predefined callback
* @param hmmc : MMC handle
- * @param CallbackID : ID of the callback to be unregistered
+ * @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
- * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
- * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
@@ -1880,7 +1920,7 @@
/* Process locked */
__HAL_LOCK(hmmc);
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
@@ -1905,7 +1945,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1923,7 +1963,7 @@
break;
default :
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1932,7 +1972,7 @@
else
{
/* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1943,20 +1983,19 @@
}
#endif
-
/**
* @}
*/
/** @addtogroup MMC_Exported_Functions_Group3
- * @brief management functions
+ * @brief management functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to control the MMC card
+ This subsection provides a set of functions allowing to control the MMC card
operations and get the related information
@endverbatim
@@ -1966,79 +2005,31 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hmmc Pointer to MMC handle
- * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that
- * contains all CID register parameters
+ * @param hmmc: Pointer to MMC handle
+ * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
+ * contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (uint8_t)((hmmc->CID[0U] & 0xFF000000U) >> 24U);
- pCID->ManufacturerID = tmp;
-
- /* Byte 1 */
- tmp = (uint8_t)((hmmc->CID[0U] & 0x00FF0000U) >> 16U);
- pCID->OEM_AppliID = tmp << 8U;
-
- /* Byte 2 */
- tmp = (uint8_t)((hmmc->CID[0U] & 0x000000FF00U) >> 8U);
- pCID->OEM_AppliID |= tmp;
-
- /* Byte 3 */
- tmp = (uint8_t)(hmmc->CID[0U] & 0x000000FFU);
- pCID->ProdName1 = tmp << 24U;
-
- /* Byte 4 */
- tmp = (uint8_t)((hmmc->CID[1U] & 0xFF000000U) >> 24U);
- pCID->ProdName1 |= tmp << 16U;
-
- /* Byte 5 */
- tmp = (uint8_t)((hmmc->CID[1U] & 0x00FF0000U) >> 16U);
- pCID->ProdName1 |= tmp << 8U;
-
- /* Byte 6 */
- tmp = (uint8_t)((hmmc->CID[1U] & 0x0000FF00U) >> 8U);
- pCID->ProdName1 |= tmp;
-
- /* Byte 7 */
- tmp = (uint8_t)(hmmc->CID[1U] & 0x000000FFU);
- pCID->ProdName2 = tmp;
-
- /* Byte 8 */
- tmp = (uint8_t)((hmmc->CID[2U] & 0xFF000000U) >> 24U);
- pCID->ProdRev = tmp;
-
- /* Byte 9 */
- tmp = (uint8_t)((hmmc->CID[2U] & 0x00FF0000U) >> 16U);
- pCID->ProdSN = tmp << 24U;
-
- /* Byte 10 */
- tmp = (uint8_t)((hmmc->CID[2U] & 0x0000FF00U) >> 8U);
- pCID->ProdSN |= tmp << 16U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hmmc->CID[2U] & 0x000000FFU);
- pCID->ProdSN |= tmp << 8U;
-
- /* Byte 12 */
- tmp = (uint8_t)((hmmc->CID[3U] & 0xFF000000U) >> 24U);
- pCID->ProdSN |= tmp;
-
- /* Byte 13 */
- tmp = (uint8_t)((hmmc->CID[3U] & 0x00FF0000U) >> 16U);
- pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
- pCID->ManufactDate = (tmp & 0x0FU) << 8U;
-
- /* Byte 14 */
- tmp = (uint8_t)((hmmc->CID[3U] & 0x0000FF00U) >> 8U);
- pCID->ManufactDate |= tmp;
-
- /* Byte 15 */
- tmp = (uint8_t)(hmmc->CID[3U] & 0x000000FFU);
- pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
+ pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
+
+ pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
+
+ pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
+
+ pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
+
+ pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
+
+ pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
+
+ pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
+
+ pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
+
+ pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
+
pCID->Reserved2 = 1U;
return HAL_OK;
@@ -2047,123 +2038,102 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hmmc Pointer to MMC handle
- * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that
- * contains all CSD register parameters
+ * @param hmmc: Pointer to MMC handle
+ * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
+ * contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (hmmc->CSD[0U] & 0xFF000000U) >> 24U;
- pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
- pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
- pCSD->Reserved1 = tmp & 0x03U;
-
- /* Byte 1 */
- tmp = (hmmc->CSD[0U] & 0x00FF0000U) >> 16U;
- pCSD->TAAC = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (hmmc->CSD[0U] & 0x0000FF00U) >> 8U;
- pCSD->NSAC = (uint8_t)tmp;
-
- /* Byte 3 */
- tmp = hmmc->CSD[0U] & 0x000000FFU;
- pCSD->MaxBusClkFrec = (uint8_t)tmp;
-
- /* Byte 4 */
- tmp = (hmmc->CSD[1U] & 0xFF000000U) >> 24U;
- pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
-
- /* Byte 5 */
- tmp = (hmmc->CSD[1U] & 0x00FF0000U) >> 16U;
- pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
- pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
-
- /* Byte 6 */
- tmp = (hmmc->CSD[1U] & 0x0000FF00U) >> 8U;
- pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
- pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
- pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
- pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
- pCSD->Reserved2 = 0; /*!< Reserved */
-
- pCSD->DeviceSize = (tmp & 0x03U) << 10U;
-
- /* Byte 7 */
- tmp = (uint8_t)(hmmc->CSD[1U] & 0x000000FFU);
- pCSD->DeviceSize |= (tmp) << 2U;
-
- /* Byte 8 */
- tmp = (uint8_t)((hmmc->CSD[2U] & 0xFF000000U) >> 24U);
- pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
-
- pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
- pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
-
- /* Byte 9 */
- tmp = (uint8_t)((hmmc->CSD[2U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
- pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
- pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
- /* Byte 10 */
- tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8U);
- pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
-
+ pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
+
+ pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
+
+ pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
+
+ pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
+
+ pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
+
+ pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
+
+ pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
+
+ pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
+
+ pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
+
+ pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
+
+ pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
+
+ pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
+
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
+ pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
+
+ pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
+
+ pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
+
+ pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
+
+ pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
+
+ pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
+
hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
- hmmc->MmcCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
- hmmc->MmcCard.BlockSize = 1U << (pCSD->RdBlockLen);
-
- hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
+ hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
hmmc->MmcCard.LogBlockSize = 512U;
- pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
- pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hmmc->CSD[2U] & 0x000000FFU);
- pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
- pCSD->WrProtectGrSize = (tmp & 0x7FU);
-
- /* Byte 12 */
- tmp = (uint8_t)((hmmc->CSD[3U] & 0xFF000000U) >> 24U);
- pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
- pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
- pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
- pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
-
- /* Byte 13 */
- tmp = (uint8_t)((hmmc->CSD[3U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
- pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
- pCSD->Reserved3 = 0U;
- pCSD->ContentProtectAppli = (tmp & 0x01U);
-
- /* Byte 14 */
- tmp = (uint8_t)((hmmc->CSD[3U] & 0x0000FF00U) >> 8U);
- pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
- pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
- pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
- pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
- pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
- pCSD->ECC = (tmp & 0x03U);
-
- /* Byte 15 */
- tmp = (uint8_t)(hmmc->CSD[3U] & 0x000000FFU);
- pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
- pCSD->Reserved4 = 1U;
-
+ pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
+
+ pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
+
+ pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
+
+ pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
+
+ pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
+
+ pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
+
+ pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
+
+ pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
+
+ pCSD->Reserved3 = 0;
+
+ pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
+
+ pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
+
+ pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
+
+ pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
+
+ pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
+
+ pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
+
+ pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
+
+ pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
+
+ pCSD->Reserved4 = 1;
+
return HAL_OK;
}
/**
* @brief Gets the MMC card info.
- * @param hmmc Pointer to MMC handle
- * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that
- * will contain the MMC card status information
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
+ * will contain the MMC card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
@@ -2175,15 +2145,15 @@
pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
-
+
return HAL_OK;
}
/**
- * @brief Enables wide bus operation for the requested card if supported by
+ * @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hmmc Pointer to MMC handle
- * @param WideMode Specifies the MMC card wide bus mode
+ * @param hmmc: Pointer to MMC handle
+ * @param WideMode: Specifies the MMC card wide bus mode
* This parameter can be one of the following values:
* @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
@@ -2194,15 +2164,15 @@
{
__IO uint32_t count = 0U;
SDIO_InitTypeDef Init;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
uint32_t response = 0U, busy = 0U;
-
+
/* Check the parameters */
assert_param(IS_SDIO_BUS_WIDE(WideMode));
-
+
/* Chnage Satte */
hmmc->State = HAL_MMC_STATE_BUSY;
-
+
/* Update Clock for Bus mode update */
Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
@@ -2211,8 +2181,8 @@
Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO*/
- SDIO_Init(hmmc->Instance, Init);
-
+ (void)SDIO_Init(hmmc->Instance, Init);
+
if(WideMode == SDIO_BUS_WIDE_8B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
@@ -2242,53 +2212,55 @@
/* WideMode is not a valid argument*/
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
}
-
+
/* Check for switch error and violation of the trial number of sending CMD 13 */
while(busy == 0U)
{
- if(count++ == SDMMC_MAX_TRIAL)
+ if(count == SDMMC_MAX_TRIAL)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
return HAL_ERROR;
}
-
+ count++;
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
-
+
/* Get command response */
response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
-
+
/* Get operating voltage*/
busy = (((response >> 7U) == 1U) ? 0U : 1U);
}
-
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_DATATIMEOUT;
while((response & 0x00000100U) == 0U)
{
- if(count-- == 0U)
+ if(count == 0U)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
return HAL_ERROR;
}
-
+ count--;
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
-
+
/* Get command response */
response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
}
-
+
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
@@ -2305,55 +2277,54 @@
Init.BusWide = WideMode;
Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
Init.ClockDiv = hmmc->Init.ClockDiv;
- SDIO_Init(hmmc->Instance, Init);
+ (void)SDIO_Init(hmmc->Instance, Init);
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
-
+
return HAL_OK;
}
-
/**
* @brief Gets the current mmc card data state.
- * @param hmmc pointer to MMC handle
+ * @param hmmc: pointer to MMC handle
* @retval Card state
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
{
- HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t cardstate;
+ uint32_t errorstate;
uint32_t resp1 = 0U;
-
+
errorstate = MMC_SendStatus(hmmc, &resp1);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
- cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
-
- return cardstate;
+ cardstate = ((resp1 >> 9U) & 0x0FU);
+
+ return (HAL_MMC_CardStateTypeDef)cardstate;
}
/**
* @brief Abort the current transfer and disable the MMC.
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
-
+
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
/* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
+
if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
{
/* Disable the MMC DMA request */
@@ -2362,16 +2333,26 @@
/* Abort the MMC DMA Tx Stream */
if(hmmc->hdmatx != NULL)
{
- HAL_DMA_Abort(hmmc->hdmatx);
+ if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ }
}
/* Abort the MMC DMA Rx Stream */
if(hmmc->hdmarx != NULL)
{
- HAL_DMA_Abort(hmmc->hdmarx);
+ if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ }
}
}
-
+
hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Initialize the MMC operation */
+ hmmc->Context = MMC_CONTEXT_NONE;
+
CardState = HAL_MMC_GetCardState(hmmc);
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
@@ -2386,21 +2367,21 @@
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
-
+
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
+
/* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
+
if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
{
/* Disable the MMC DMA request */
@@ -2431,6 +2412,7 @@
{
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
+
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
@@ -2441,29 +2423,33 @@
}
else
{
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
}
-
+
return HAL_OK;
}
/**
* @}
*/
-
+
/**
* @}
*/
-
-/* Private function ----------------------------------------------------------*/
+
+/* Private function ----------------------------------------------------------*/
/** @addtogroup MMC_Private_Functions
* @{
*/
/**
* @brief DMA MMC transmit process complete callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -2476,13 +2462,13 @@
/**
* @brief DMA MMC receive process complete callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send stop command in multiblock write */
if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA))
@@ -2491,7 +2477,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
@@ -2504,11 +2490,11 @@
hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
@@ -2517,44 +2503,50 @@
/**
* @brief DMA MMC communication error callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMAError(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
HAL_MMC_CardStateTypeDef CardState;
+ uint32_t RxErrorCode, TxErrorCode;
- if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+ /* if DMA error is FIFO error ignore it */
+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
- /* Clear All flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
-
- /* Disable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
- CardState = HAL_MMC_GetCardState(hmmc);
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ RxErrorCode = hmmc->hdmarx->ErrorCode;
+ TxErrorCode = hmmc->hdmatx->ErrorCode;
+ if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
{
- hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ /* Disable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ CardState = HAL_MMC_GetCardState(hmmc);
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+
+ hmmc->State= HAL_MMC_STATE_READY;
}
- hmmc->State= HAL_MMC_STATE_READY;
- }
-
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
- hmmc->ErrorCallback(hmmc);
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->ErrorCallback(hmmc);
#else
- HAL_MMC_ErrorCallback(hmmc);
+ HAL_MMC_ErrorCallback(hmmc);
#endif
-
+ }
}
/**
* @brief DMA MMC Tx Abort callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
@@ -2579,11 +2571,15 @@
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
else
{
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
@@ -2595,7 +2591,7 @@
/**
* @brief DMA MMC Rx Abort callback
- * @param hdma DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
@@ -2620,11 +2616,15 @@
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
else
{
-#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
@@ -2634,25 +2634,24 @@
}
}
-
/**
* @brief Initializes the mmc card.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval MMC Card error state
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardCSDTypeDef CSD;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint16_t mmc_rca = 1;
-
+ uint32_t errorstate;
+ uint16_t mmc_rca = 1U;
+
/* Check the power State */
- if(SDIO_GetPowerState(hmmc->Instance) == 0U)
+ if(SDIO_GetPowerState(hmmc->Instance) == 0U)
{
/* Power off */
return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
}
-
+
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -2667,7 +2666,7 @@
hmmc->CID[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
}
-
+
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* MMC Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
@@ -2675,10 +2674,10 @@
{
return errorstate;
}
-
+
/* Get the MMC card RCA */
hmmc->MmcCard.RelCardAdd = mmc_rca;
-
+
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -2693,22 +2692,25 @@
hmmc->CSD[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
hmmc->CSD[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
}
-
+
/* Get the Card Class */
hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U);
-
+
/* Get CSD parameters */
- HAL_MMC_GetCardCSD(hmmc, &CSD);
+ if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
+ {
+ return hmmc->ErrorCode;
+ }
/* Select the Card */
- errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- return errorstate;
- }
+ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
/* Configure SDIO peripheral interface */
- SDIO_Init(hmmc->Instance, hmmc->Init);
+ (void)SDIO_Init(hmmc->Instance, hmmc->Init);
/* All cards are initialized */
return HAL_MMC_ERROR_NONE;
@@ -2718,15 +2720,15 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores MMC information that will be needed in future
* in the MMC handle.
- * @param hmmc Pointer to MMC handle
+ * @param hmmc: Pointer to MMC handle
* @retval error state
*/
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
{
__IO uint32_t count = 0U;
uint32_t response = 0U, validvoltage = 0U;
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -2740,133 +2742,157 @@
{
return HAL_MMC_ERROR_INVALID_VOLTRANGE;
}
-
+
/* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
}
-
+
/* Get command response */
response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
-
+
/* Get operating voltage*/
validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
}
-
+
/* When power routine is finished and command returns valid voltage */
- if ((response & eMMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE)
+ if (((response & (0xFF000000U)) >> 24U) == 0xC0U)
{
- /* When voltage range of the card is within 2.7V and 3.6V */
- hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD;
+ hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
}
else
{
- /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */
- hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD;
+ hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
}
-
+
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Turns the SDIO output signals off.
- * @param hmmc Pointer to MMC handle
- * @retval HAL status
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
*/
-static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
+static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
{
/* Set Power State to OFF */
- SDIO_PowerState_OFF(hmmc->Instance);
-
- return HAL_OK;
+ (void)SDIO_PowerState_OFF(hmmc->Instance);
}
/**
* @brief Returns the current card's status.
- * @param hmmc Pointer to MMC handle
- * @param pCardStatus pointer to the buffer that will contain the MMC card
- * status (Card Status register)
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardStatus: pointer to the buffer that will contain the MMC card
+ * status (Card Status register)
* @retval error state
*/
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
{
- uint32_t errorstate = HAL_MMC_ERROR_NONE;
-
+ uint32_t errorstate;
+
if(pCardStatus == NULL)
{
return HAL_MMC_ERROR_PARAM;
}
-
+
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
-
+
/* Get MMC card status */
*pCardStatus = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
-
+
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
+static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count;
- uint32_t* tmp;
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
- tmp = (uint32_t*)hmmc->pRxBuffPtr;
-
- /* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ tmp = hmmc->pRxBuffPtr;
+ dataremaining = hmmc->RxXferSize;
+
+ if (dataremaining > 0U)
{
- *(tmp + count) = SDIO_ReadFIFO(hmmc->Instance);
+ /* Read data from SDIO Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = SDIO_ReadFIFO(hmmc->Instance);
+ *tmp = (uint8_t)(data & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ }
+
+ hmmc->pRxBuffPtr = tmp;
+ hmmc->RxXferSize = dataremaining;
}
-
- hmmc->pRxBuffPtr += 8U;
-
- return HAL_OK;
}
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
+static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hmmc->pTxBuffPtr;
-
- /* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
+
+ tmp = hmmc->pTxBuffPtr;
+ dataremaining = hmmc->TxXferSize;
+
+ if (dataremaining > 0U)
{
- SDIO_WriteFIFO(hmmc->Instance, (tmp + count));
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tmp);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 8U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 16U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 24U);
+ tmp++;
+ dataremaining--;
+ (void)SDIO_WriteFIFO(hmmc->Instance, &data);
+ }
+
+ hmmc->pTxBuffPtr = tmp;
+ hmmc->TxXferSize = dataremaining;
}
-
- hmmc->pTxBuffPtr += 8U;
-
- return HAL_OK;
}
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* SDIO */
#endif /* HAL_MMC_MODULE_ENABLED */
diff --git a/Src/stm32f4xx_hal_nand.c b/Src/stm32f4xx_hal_nand.c
index 6a1fb91..3404d19 100644
--- a/Src/stm32f4xx_hal_nand.c
+++ b/Src/stm32f4xx_hal_nand.c
@@ -882,12 +882,13 @@
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- /* Get tick */
- tickstart = HAL_GetTick();
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
@@ -1010,12 +1011,12 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
+ {
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -1546,12 +1547,12 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
+ {
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
diff --git a/Src/stm32f4xx_hal_qspi.c b/Src/stm32f4xx_hal_qspi.c
index 1fb0743..b143e35 100644
--- a/Src/stm32f4xx_hal_qspi.c
+++ b/Src/stm32f4xx_hal_qspi.c
@@ -318,9 +318,6 @@
assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
}
- /* Process locked */
- __HAL_LOCK(hqspi);
-
if(hqspi->State == HAL_QSPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -401,9 +398,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hqspi);
-
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
diff --git a/Src/stm32f4xx_hal_rcc.c b/Src/stm32f4xx_hal_rcc.c
index 7fe1db6..1857df2 100644
--- a/Src/stm32f4xx_hal_rcc.c
+++ b/Src/stm32f4xx_hal_rcc.c
@@ -220,7 +220,7 @@
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart;
+ uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
@@ -531,7 +531,24 @@
}
else
{
- return HAL_ERROR;
+ /* Check if there is a request to disable the PLL used as System clock source */
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Do not return HAL_ERROR if request repeats the current configuration */
+ pll_config = RCC->CFGR;
+ if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
+ (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
+ {
+ return HAL_ERROR;
+ }
+ }
}
}
return HAL_OK;
@@ -693,7 +710,7 @@
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings */
- HAL_InitTick (TICK_INT_PRIORITY);
+ HAL_InitTick (uwTickPrio);
return HAL_OK;
}
diff --git a/Src/stm32f4xx_hal_rcc_ex.c b/Src/stm32f4xx_hal_rcc_ex.c
index 2b4e04c..0d3aacc 100644
--- a/Src/stm32f4xx_hal_rcc_ex.c
+++ b/Src/stm32f4xx_hal_rcc_ex.c
@@ -2175,7 +2175,8 @@
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
factor is common parameters for both peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
- (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
@@ -2227,6 +2228,17 @@
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
}
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
+ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+ {
+ /* Check for Parameters */
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+ /* Configure the PLLI2S multiplication and division factors */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+ }
+
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
/* Get tick */
@@ -2472,7 +2484,7 @@
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
break;
}
- /* Clock not enabled for I2S */
+ /* Clock not enabled for I2S*/
default:
{
frequency = 0U;
@@ -3292,7 +3304,7 @@
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
- if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ if(HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
diff --git a/Src/stm32f4xx_hal_rng.c b/Src/stm32f4xx_hal_rng.c
index fca4240..47c313c 100644
--- a/Src/stm32f4xx_hal_rng.c
+++ b/Src/stm32f4xx_hal_rng.c
@@ -313,44 +313,44 @@
{
switch (CallbackID)
{
- case HAL_RNG_ERROR_CB_ID :
- hrng->ErrorCallback = pCallback;
- break;
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = pCallback;
+ break;
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else if (HAL_RNG_STATE_RESET == hrng->State)
{
switch (CallbackID)
{
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -388,44 +388,44 @@
{
switch (CallbackID)
{
- case HAL_RNG_ERROR_CB_ID :
- hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else if (HAL_RNG_STATE_RESET == hrng->State)
{
switch (CallbackID)
{
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -631,7 +631,7 @@
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
{
- if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+ if (HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
{
return hrng->RandomNumber;
}
@@ -697,13 +697,13 @@
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
{
/* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
/* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
rngclockerror = 1U;
}
else
diff --git a/Src/stm32f4xx_hal_rtc.c b/Src/stm32f4xx_hal_rtc.c
index f7fe5f1..cae7b9c 100644
--- a/Src/stm32f4xx_hal_rtc.c
+++ b/Src/stm32f4xx_hal_rtc.c
@@ -105,10 +105,12 @@
*** Callback registration ***
=============================================
+ [..]
The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+ [..]
Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback.
@@ -118,9 +120,11 @@
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@@ -135,6 +139,7 @@
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+ [..]
By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions :
examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
@@ -144,6 +149,7 @@
If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
@@ -152,6 +158,7 @@
using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
or @ref HAL_RTC_Init() function.
+ [..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -1572,10 +1579,11 @@
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
{
- if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
+ /* Get the AlarmA interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
+ /* Get the pending status of the AlarmA Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
{
/* AlarmA callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -1584,15 +1592,16 @@
HAL_RTC_AlarmAEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the Alarm interrupt pending bit */
+ /* Clear the AlarmA interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
}
}
- if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
+ /* Get the AlarmB interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
+ /* Get the pending status of the AlarmB Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET)
{
/* AlarmB callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -1601,7 +1610,7 @@
HAL_RTCEx_AlarmBEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the Alarm interrupt pending bit */
+ /* Clear the AlarmB interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
}
}
diff --git a/Src/stm32f4xx_hal_rtc_ex.c b/Src/stm32f4xx_hal_rtc_ex.c
index 5b25ed7..8e07b4e 100644
--- a/Src/stm32f4xx_hal_rtc_ex.c
+++ b/Src/stm32f4xx_hal_rtc_ex.c
@@ -499,10 +499,11 @@
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
- if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
+ /* Get the TimeStamp interrupt source enable status */
+ if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
+ /* Get the pending status of the TIMESTAMP Interrupt */
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != (uint32_t)RESET)
{
/* TIMESTAMP callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -516,11 +517,11 @@
}
}
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
+ /* Get the Tamper1 interrupt source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != (uint32_t)RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET)
+ /* Get the pending status of the Tamper1 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -534,11 +535,11 @@
}
}
- /* Get the status of the Interrupt */
- if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
+ /* Get the Tamper2 interrupt source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != (uint32_t)RESET)
{
- /* Get the TAMPER Interrupt enable bit and pending bit */
- if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
+ /* Get the pending status of the Tamper2 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != (uint32_t)RESET)
{
/* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -551,6 +552,7 @@
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
}
}
+
/* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
@@ -998,27 +1000,29 @@
/**
* @brief This function handles Wake Up Timer interrupt request.
+ * @note Unlike alarm interrupt line (shared by AlarmA and AlarmB) and tamper
+ * interrupt line (shared by timestamp and tampers) wakeup timer
+ * interrupt line is exclusive to the wakeup timer.
+ * There is no need in this case to check on the interrupt enable
+ * status via __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE().
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
- if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
+ /* Get the pending status of the WAKEUPTIMER Interrupt */
+ if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != (uint32_t)RESET)
{
- /* Get the status of the Interrupt */
- if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
- {
- /* WAKEUPTIMER callback */
+ /* WAKEUPTIMER callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- hrtc->WakeUpTimerEventCallback(hrtc);
+ hrtc->WakeUpTimerEventCallback(hrtc);
#else
- HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the WAKEUPTIMER interrupt pending bit */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
- }
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
diff --git a/Src/stm32f4xx_hal_sai.c b/Src/stm32f4xx_hal_sai.c
index 5d181e1..e94c1a1 100644
--- a/Src/stm32f4xx_hal_sai.c
+++ b/Src/stm32f4xx_hal_sai.c
@@ -141,12 +141,13 @@
*** Callback registration ***
=============================
-
+ [..]
The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
+ Use functions HAL_SAI_RegisterCallback() to register a user callback.
- Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
+ [..]
+ Function HAL_SAI_RegisterCallback() allows to register following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
(+) TxCpltCallback : SAI transmit complete.
@@ -154,13 +155,16 @@
(+) ErrorCallback : SAI error.
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
+ [..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
- Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
+ [..]
+ Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
+ [..]
This function allows to reset following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
@@ -170,23 +174,26 @@
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
- By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+ [..]
+ By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
- examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
+ examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
- and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+ [..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
- or @ref HAL_SAI_Init function.
+ using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
+ or HAL_SAI_Init function.
+ [..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -240,7 +247,6 @@
/** @defgroup SAI_Private_Constants SAI Private Constants
* @{
*/
-#define SAI_FIFO_SIZE 8U
#define SAI_DEFAULT_TIMEOUT 4U /* 4ms */
/**
* @}
@@ -466,6 +472,9 @@
}
}
+ /* Check the SAI Block master clock divider parameter */
+ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
+
/* Compute CKSTR bits of SAI CR1 according to ClockStrobing and AudioMode */
if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))
{
@@ -498,6 +507,7 @@
default:
break;
}
+
/* SAI CR1 Configuration */
hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\
@@ -1453,6 +1463,12 @@
return HAL_ERROR;
}
+ /* Enable the interrupts for error handling */
+ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
+
+ /* Enable SAI Rx DMA Request */
+ hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
+
/* Check if the SAI is already enabled */
if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)
{
@@ -1460,12 +1476,6 @@
__HAL_SAI_ENABLE(hsai);
}
- /* Enable the interrupts for error handling */
- __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
-
- /* Enable SAI Rx DMA Request */
- hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
-
/* Process Unlocked */
__HAL_UNLOCK(hsai);
@@ -1612,6 +1622,9 @@
/* SAI AFSDET interrupt occurred ----------------------------------*/
else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
{
+ /* Clear the SAI AFSDET flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
+
/* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
@@ -1652,6 +1665,9 @@
/* SAI LFSDET interrupt occurred ----------------------------------*/
else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
{
+ /* Clear the SAI LFSDET flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
+
/* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
@@ -1692,6 +1708,9 @@
/* SAI WCKCFG interrupt occurred ----------------------------------*/
else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
{
+ /* Clear the SAI WCKCFG flag */
+ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
+
/* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
@@ -1929,19 +1948,16 @@
return HAL_ERROR;
}
- switch(protocol)
+ if (protocol == SAI_I2S_STANDARD)
{
- case SAI_I2S_STANDARD :
hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
- break;
- case SAI_I2S_MSBJUSTIFIED :
- case SAI_I2S_LSBJUSTIFIED :
+ }
+ else
+ {
+ /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
- break;
- default :
- return HAL_ERROR;
}
/* Frame definition */
@@ -2018,16 +2034,14 @@
hsai->SlotInit.SlotNumber = nbslot;
hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
- switch(protocol)
+ if (protocol == SAI_PCM_SHORT)
{
- case SAI_PCM_SHORT :
- hsai->FrameInit.ActiveFrameLength = 1U;
- break;
- case SAI_PCM_LONG :
- hsai->FrameInit.ActiveFrameLength = 13U;
- break;
- default :
- return HAL_ERROR;
+ hsai->FrameInit.ActiveFrameLength = 1;
+ }
+ else
+ {
+ /* SAI_PCM_LONG */
+ hsai->FrameInit.ActiveFrameLength = 13;
}
switch(datasize)
@@ -2339,7 +2353,7 @@
{
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
hsai->XferCount = 0U;
@@ -2384,7 +2398,8 @@
static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
/* Disable Rx DMA Request */
hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);
diff --git a/Src/stm32f4xx_hal_sd.c b/Src/stm32f4xx_hal_sd.c
index 9753e4e..d2a88d7 100644
--- a/Src/stm32f4xx_hal_sd.c
+++ b/Src/stm32f4xx_hal_sd.c
@@ -3,161 +3,165 @@
* @file stm32f4xx_hal_sd.c
* @author MCD Application Team
* @brief SD card HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + SD card Control functions
- *
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- This driver implements a high level communication layer for read and write from/to
- this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
- the user in HAL_SD_MspInit() function (MSP layer).
- Basically, the MSP layer configuration should be the same as we provide in the
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
+ the user in HAL_SD_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
- This driver is a generic layered driver for SDIO memories which uses the HAL
- SDIO driver functions to interface with SD and uSD cards devices.
+ This driver is a generic layered driver for SDIO memories which uses the HAL
+ SDIO driver functions to interface with SD and uSD cards devices.
It is used as follows:
-
- (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
- (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
+
+ (#)Initialize the SDIO low level resources by implementing the HAL_SD_MspInit() API:
+ (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
(##) SDIO pins configuration for SD card
- (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
- (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+ (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
and HAL_SD_WriteBlocks_DMA() APIs).
- (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
- (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDIO and DMA interrupt priorities using functions
HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
(+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
(+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
and __HAL_SD_CLEAR_IT()
(##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
and HAL_SD_WriteBlocks_IT() APIs).
- (+++) Configure the SDIO interrupt priorities using function
- HAL_NVIC_SetPriority();
+ (+++) Configure the SDIO interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
(+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
and __HAL_SD_CLEAR_IT()
- (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+ (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
-
+
*** SD Card Initialization and configuration ***
- ================================================
+ ================================================
[..]
- To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- SDIO IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+ SDIO Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
- (#) Initialize the SDIO peripheral interface with defaullt configuration.
- The initialization process is done at 400KHz. You can change or adapt
- this frequency by adjusting the "ClockDiv" field.
+ (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+ type (Standard Capacity or High Capacity). You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
The SD Card frequency (SDIO_CK) is computed as follows:
-
+
SDIO_CK = SDIOCLK / (ClockDiv + 2)
-
- In initialization mode and according to the SD Card standard,
+
+ In initialization mode and according to the SD Card standard,
make sure that the SDIO_CK frequency doesn't exceed 400KHz.
- This phase of initialization is done through SDIO_Init() and
+ This phase of initialization is done through SDIO_Init() and
SDIO_PowerState_ON() SDIO low level APIs.
(#) Initialize the SD card. The API used is HAL_SD_InitCard().
- This phase allows the card initialization and identification
+ This phase allows the card initialization and identification
and check the SD Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with SD standard.
- This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+ This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
-
- (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
- frequency is set to 24MHz. You can change or adapt this frequency by adjusting
- the "ClockDiv" field.
- In transfer mode and according to the SD Card standard, make sure that the
+
+ (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+ frequency by adjusting the "ClockDiv" field.
+ In transfer mode and according to the SD Card standard, make sure that the
SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
- To be able to use a frequency higher than 24MHz, you should use the SDIO
- peripheral in bypass mode. Refer to the corresponding reference manual
+ To be able to use a frequency higher than 24MHz, you should use the SDIO
+ peripheral in bypass mode. Refer to the corresponding reference manual
for more details.
-
+
(#) Select the corresponding SD Card according to the address read with the step 2.
-
+
(#) Configure the SD Card in wide bus mode: 4-bits data.
-
+
*** SD Card Read operation ***
==============================
- [..]
- (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ [..]
+ (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the DMA transfer process through the SD Rx interrupt event.
(+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Rx interrupt event.
-
+
*** SD Card Write operation ***
- ===============================
- [..]
- (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ ===============================
+ [..]
+ (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
- You could also check the DMA transfer process through the SD Tx interrupt event.
+ You could also check the DMA transfer process through the SD Tx interrupt event.
(+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
- This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ This function support only 512-bytes block length (the block size should be
+ chosen as 512 bytes).
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Tx interrupt event.
-
+
*** SD card status ***
- ======================
+ ======================
[..]
- (+) The SD Status contains status bits that are related to the SD Memory
+ (+) The SD Status contains status bits that are related to the SD Memory
Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
*** SD card information ***
- ===========================
+ ===========================
[..]
(+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
It returns useful information about the SD card such as block size, card type,
@@ -165,13 +169,11 @@
*** SD card CSD register ***
============================
- [..]
(+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
Some of the CSD parameters are useful for card initialization and identification.
*** SD card CID register ***
============================
- [..]
(+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
Some of the CSD parameters are useful for card initialization and identification.
@@ -179,7 +181,7 @@
==================================
[..]
Below the list of most used macros in SD HAL driver.
-
+
(+) __HAL_SD_ENABLE : Enable the SD device
(+) __HAL_SD_DISABLE : Disable the SD device
(+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
@@ -189,9 +191,8 @@
(+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
(+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
- [..]
- (@) You can refer to the SD HAL driver header file for more useful macros
-
+ (@) You can refer to the SD HAL driver header file for more useful macros
+
*** Callback registration ***
=============================================
[..]
@@ -222,7 +223,7 @@
By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -232,11 +233,11 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
+ using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
or @ref HAL_SD_Init function.
When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
@@ -249,40 +250,36 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+#if defined(SDIO)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @addtogroup SD
+/** @addtogroup SD
* @{
*/
#ifdef HAL_SD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup SD_Private_Defines
* @{
*/
-
+
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -291,15 +288,15 @@
* @{
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
-static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);
-static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SD_DMAError(DMA_HandleTypeDef *hdma);
@@ -315,13 +312,13 @@
*/
/** @addtogroup SD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to initialize/de-initialize the SD
card device to be ready for use.
@@ -330,9 +327,9 @@
*/
/**
- * @brief Initializes the SD according to the specified parameters in the
+ * @brief Initializes the SD according to the specified parameters in the
SD_HandleTypeDef and create the associated handle.
- * @param hsd Pointer to the SD handle
+ * @param hsd: Pointer to the SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
@@ -356,7 +353,7 @@
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_SD_STATE_RESET only */
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
@@ -373,20 +370,23 @@
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SD_MspInit(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize the Card parameters */
- HAL_SD_InitCard(hsd);
+ if (HAL_SD_InitCard(hsd) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Initialize the error code */
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
/* Initialize the SD operation */
hsd->Context = SD_CONTEXT_NONE;
-
+
/* Initialize the SD state */
hsd->State = HAL_SD_STATE_READY;
@@ -395,14 +395,15 @@
/**
* @brief Initializes the SD Card.
- * @param hsd Pointer to SD handle
- * @note This function initializes the SD card. It could be used when a card
+ * @param hsd: Pointer to SD handle
+ * @note This function initializes the SD card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
+ HAL_StatusTypeDef status;
SD_InitTypeDef Init;
/* Default SDIO peripheral configuration for SD card initialization */
@@ -414,21 +415,21 @@
Init.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO peripheral interface with default configuration */
- SDIO_Init(hsd->Instance, Init);
+ status = SDIO_Init(hsd->Instance, Init);
+ if(status != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Disable SDIO Clock */
- __HAL_SD_DISABLE(hsd);
-
+ __HAL_SD_DISABLE(hsd);
+
/* Set Power State to ON */
- SDIO_PowerState_ON(hsd->Instance);
-
+ (void)SDIO_PowerState_ON(hsd->Instance);
+
/* Enable SDIO Clock */
__HAL_SD_ENABLE(hsd);
-
- /* Required power up waiting time before starting the SD initialization
- sequence */
- HAL_Delay(2U);
-
+
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -452,7 +453,7 @@
/**
* @brief De-Initializes the SD card.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
@@ -462,16 +463,16 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
hsd->State = HAL_SD_STATE_BUSY;
-
- /* Set SD power state to off */
+
+ /* Set SD power state to off */
SD_PowerOFF(hsd);
-
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
if(hsd->MspDeInitCallback == NULL)
{
hsd->MspDeInitCallback = HAL_SD_MspDeInit;
@@ -482,41 +483,41 @@
#else
/* De-Initialize the MSP layer */
HAL_SD_MspDeInit(hsd);
-#endif
-
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_RESET;
-
+
return HAL_OK;
}
/**
* @brief Initializes the SD MSP.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_MspInit could be implemented in the user file
*/
}
/**
* @brief De-Initialize SD MSP.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_MspDeInit could be implemented in the user file
*/
}
@@ -526,14 +527,14 @@
*/
/** @addtogroup SD_Exported_Functions_Group2
- * @brief Data transfer functions
+ * @brief Data transfer functions
*
-@verbatim
+@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to manage the data
+ This subsection provides a set of functions allowing to manage the data
transfer from/to SD card.
@endverbatim
@@ -541,124 +542,140 @@
*/
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd Pointer to SD handle
- * @param pData pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of SD blocks to read
- * @param Timeout Specify timeout value
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of SD blocks to read
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
+
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = NumberOfBlocks * BLOCKSIZE;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ (void)SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Read block(s) in polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
/* Poll on SDIO flags */
-#ifdef SDIO_STA_STBITERR
- while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
+ dataremaining = config.DataLength;
+#if defined(SDIO_STA_STBITERR)
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
#endif /* SDIO_STA_STBITERR */
{
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))
{
/* Read data from SDIO Rx FIFO */
for(count = 0U; count < 8U; count++)
{
- *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+ data = SDIO_ReadFIFO(hsd->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
/* Send stop transmission command in case of multiblock read */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
@@ -669,11 +686,12 @@
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
}
-
+
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
{
@@ -681,6 +699,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
@@ -689,6 +708,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
@@ -697,30 +717,47 @@
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
- /* Empty FIFO if there is still any data */
- while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
+ else
{
- *tempbuff = SDIO_ReadFIFO(hsd->Instance);
+ /* Nothing to do */
+ }
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))
+ {
+ data = SDIO_ReadFIFO(hsd->Instance);
+ *tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+ *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+ tempbuff++;
+ dataremaining--;
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
-
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -735,21 +772,22 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd Pointer to SD handle
- * @param pData pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of SD blocks to write
- * @param Timeout Specify timeout value
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of SD blocks to write
+ * @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U;
- uint32_t *tempbuff = (uint32_t *)pData;
-
+ uint32_t count, data, dataremaining;
+ uint32_t add = BlockAdd;
+ uint8_t *tempbuff = pData;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
@@ -758,98 +796,112 @@
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- /* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
- }
- else
- {
- hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
+ (void)SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
/* Write block(s) in polling mode */
-#ifdef SDIO_STA_STBITERR
+ dataremaining = config.DataLength;
+#if defined(SDIO_STA_STBITERR)
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
#else /* SDIO_STA_STBITERR not defined */
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
#endif /* SDIO_STA_STBITERR */
{
- if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))
{
/* Write data to SDIO Tx FIFO */
for(count = 0U; count < 8U; count++)
{
- SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
+ data = (uint32_t)(*tempbuff);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 8U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 16U);
+ tempbuff++;
+ dataremaining--;
+ data |= ((uint32_t)(*tempbuff) << 24U);
+ tempbuff++;
+ dataremaining--;
+ (void)SDIO_WriteFIFO(hsd->Instance, &data);
}
- tempbuff += 8U;
}
-
- if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
-
+
/* Send stop transmission command in case of multiblock write */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
- {
+ {
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
@@ -857,14 +909,15 @@
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
}
-
+
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
{
@@ -872,14 +925,16 @@
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
@@ -888,14 +943,19 @@
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
+ else
+ {
+ /* Nothing to do */
+ }
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -906,102 +966,104 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Rx
+ * @note You could also check the IT transfer process through the SD Rx
* interrupt event.
- * @param hsd Pointer to SD handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
- hsd->pRxBuffPtr = (uint32_t *)pData;
+
+ hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-
-#ifdef SDIO_STA_STBITERR
+
+#if defined(SDIO_STA_STBITERR)
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
#endif /* SDIO_STA_STBITERR */
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
+ (void)SDIO_ConfigData(hsd->Instance, &config);
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
-
+
/* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
-
+
/* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
+
return HAL_OK;
}
else
@@ -1011,103 +1073,105 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed in interrupt mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the IT transfer process through the SD Tx
- * interrupt event.
- * @param hsd Pointer to SD handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @note You could also check the IT transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
- hsd->pTxBuffPtr = (uint32_t *)pData;
+
+ hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
-
+
/* Enable transfer interrupts */
-#ifdef SDIO_STA_STBITERR
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
+#if defined(SDIO_STA_STBITERR)
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
#endif /* SDIO_STA_STBITERR */
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
-
- /* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
+ (void)SDIO_ConfigData(hsd->Instance, &config);
+
return HAL_OK;
}
else
@@ -1117,115 +1181,126 @@
}
/**
- * @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Rx
+ * @note You could also check the DMA transfer process through the SD Rx
* interrupt event.
- * @param hsd Pointer SD handle
- * @param pData Pointer to the buffer that will contain the received data
- * @param BlockAdd Block Address from where data is to be read
- * @param NumberOfBlocks Number of blocks to read.
+ * @param hsd: Pointer SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
-#ifdef SDIO_STA_STBITERR
+
+#if defined(SDIO_STA_STBITERR)
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
#endif /* SDIO_STA_STBITERR */
-
+
/* Set the DMA transfer complete callback */
hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
-
+
/* Set the DMA error callback */
hsd->hdmarx->XferErrorCallback = SD_DMAError;
-
+
/* Set the DMA Abort callback */
hsd->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Enable SD DMA transfer */
- __HAL_SD_DMA_ENABLE(hsd);
-
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
- {
- BlockAdd *= 512U;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ /* Enable the DMA Channel */
+ if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
{
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
+ __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- /* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
- {
- hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Multi Block command */
- errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
- }
else
{
- hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Read Single Block command */
- errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
- }
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
+ /* Enable SD DMA transfer */
+ __HAL_SD_DMA_ENABLE(hsd);
- return HAL_OK;
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ add *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ (void)SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
}
else
{
@@ -1234,116 +1309,132 @@
}
/**
- * @brief Writes block(s) to a specified address in a card. The Data transfer
- * is managed by DMA mode.
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @note You could also check the DMA transfer process through the SD Tx
+ * @note You could also check the DMA transfer process through the SD Tx
* interrupt event.
- * @param hsd Pointer to SD handle
- * @param pData Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd Block Address where data will be written
- * @param NumberOfBlocks Number of blocks to write
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t add = BlockAdd;
+
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-
- /* Enable SD Error interrupts */
-#ifdef SDIO_STA_STBITERR
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+
+ /* Enable SD Error interrupts */
+#if defined(SDIO_STA_STBITERR)
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
- __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
#endif /* SDIO_STA_STBITERR */
-
+
/* Set the DMA transfer complete callback */
hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
-
+
/* Set the DMA error callback */
hsd->hdmatx->XferErrorCallback = SD_DMAError;
-
+
/* Set the DMA Abort callback */
hsd->hdmatx->XferAbortCallback = NULL;
-
+
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockAdd *= 512U;
+ add *= 512U;
}
-
- /* Set Block Size for Card */
+
+ /* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
-
- /* Write Multi Block command */
- errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
-
+
/* Write Single Block command */
- errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
-
+
/* Enable SDIO DMA transfer */
__HAL_SD_DMA_ENABLE(hsd);
-
+
/* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
-
- /* Configure the SD DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = BLOCKSIZE * NumberOfBlocks;
- config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
- return HAL_OK;
+ if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
+ {
+#if defined(SDIO_STA_STBITERR)
+ __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
+#endif /* SDIO_STA_STBITERR */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ (void)SDIO_ConfigData(hsd->Instance, &config);
+
+ return HAL_OK;
+ }
}
else
{
@@ -1355,33 +1446,35 @@
* @brief Erases the specified memory area of the given SD card.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd Pointer to SD handle
- * @param BlockStartAdd Start Block address
- * @param BlockEndAdd End Block address
+ * @param hsd: Pointer to SD handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t start_add = BlockStartAdd;
+ uint32_t end_add = BlockEndAdd;
+
if(hsd->State == HAL_SD_STATE_READY)
{
- hsd->ErrorCode = HAL_DMA_ERROR_NONE;
-
- if(BlockEndAdd < BlockStartAdd)
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+ if(end_add < start_add)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
-
- if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
+
+ if(end_add > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_BUSY;
-
+
/* Check if the card command class supports erase command */
if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
{
@@ -1391,62 +1484,62 @@
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Get start and end block for high capacity cards */
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
- BlockStartAdd *= 512U;
- BlockEndAdd *= 512U;
+ start_add *= 512U;
+ end_add *= 512U;
}
-
+
/* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD32 SD_ERASE_GRP_START with argument as addr */
- errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
+ errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
/* Send CMD33 SD_ERASE_GRP_END with argument as addr */
- errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
+ errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
}
-
+
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
+
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
else
@@ -1457,218 +1550,178 @@
/**
* @brief This function handles SD card interrupt request.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+ uint32_t context = hsd->Context;
+
/* Check for SDIO interrupt flags */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DATAEND) != RESET)
+ if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
-
-#ifdef SDIO_STA_STBITERR
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+ SD_Read_IT(hsd);
+ }
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
+
+#if defined(SDIO_STA_STBITERR)
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\
+ SDIO_IT_RXFIFOHF | SDIO_IT_STBITERR);
#else /* SDIO_STA_STBITERR not defined */
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-#endif
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\
+ SDIO_IT_RXFIFOHF);
+#endif /* SDIO_STA_STBITERR */
+
+ hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);
- if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ if((context & SD_CONTEXT_IT) != 0U)
{
- if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
-
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
- if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
+ hsd->Context = SD_CONTEXT_NONE;
+ if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->RxCpltCallback(hsd);
#else
HAL_SD_RxCpltCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
else
{
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
-#else
+#else
HAL_SD_TxCpltCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+ else if((context & SD_CONTEXT_DMA) != 0U)
{
- if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
+ if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
{
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the SD DCTRL register */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
+
hsd->State = HAL_SD_STATE_READY;
-
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
-#else
+#else
HAL_SD_TxCpltCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
-
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXFIFOHE) != RESET)
+
+ else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_TXFIFOHE);
-
SD_Write_IT(hsd);
}
-
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXFIFOHF) != RESET)
- {
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXFIFOHF);
-
- SD_Read_IT(hsd);
- }
-
-#ifdef SDIO_STA_STBITERR
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
+
+#if defined(SDIO_STA_STBITERR)
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET)
+#else /* SDIO_STA_STBITERR not defined */
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET)
+#endif /* SDIO_STA_STBITERR */
{
/* Set Error code */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET)
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET)
{
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_STBITERR) != RESET)
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
}
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ }
+#if defined(SDIO_STA_STBITERR)
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+#endif /* SDIO_STA_STBITERR */
+#if defined(SDIO_STA_STBITERR)
/* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);
+
/* Disable all interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
-
- if((hsd->Context & SD_CONTEXT_DMA) != RESET)
- {
- /* Abort the SD DMA Streams */
- if(hsd->hdmatx != NULL)
- {
- /* Set the DMA Tx abort callback */
- hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
- {
- SD_DMATxAbort(hsd->hdmatx);
- }
- }
- else if(hsd->hdmarx != NULL)
- {
- /* Set the DMA Rx abort callback */
- hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
- /* Abort DMA in IT mode */
- if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
- {
- SD_DMARxAbort(hsd->hdmarx);
- }
- }
- else
- {
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->AbortCpltCallback(hsd);
-#else
- HAL_SD_AbortCallback(hsd);
-#endif
- }
- }
- else if((hsd->Context & SD_CONTEXT_IT) != RESET)
- {
- /* Set the SD state to ready to be able to start again the process */
- hsd->State = HAL_SD_STATE_READY;
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->ErrorCallback(hsd);
-#else
- HAL_SD_ErrorCallback(hsd);
-#endif
- }
- }
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
#else /* SDIO_STA_STBITERR not defined */
- else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR) != RESET)
- {
- /* Set Error code */
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
- }
- if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET)
- {
- hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
- }
-
/* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
/* Disable all interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+#endif /* SDIO_STA_STBITERR */
+
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+ if((context & SD_CONTEXT_IT) != 0U)
{
- /* Abort the SD DMA Streams */
- if(hsd->hdmatx != NULL)
+ /* Set the SD state to ready to be able to start again the process */
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->ErrorCallback(hsd);
+#else
+ HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+ }
+ else if((context & SD_CONTEXT_DMA) != 0U)
+ {
+ /* Abort the SD DMA channel */
+ if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Tx abort callback */
hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
@@ -1678,7 +1731,7 @@
SD_DMATxAbort(hsd->hdmatx);
}
}
- else if(hsd->hdmarx != NULL)
+ else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Rx abort callback */
hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
@@ -1692,22 +1745,28 @@
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- else if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ else
{
- /* Set the SD state to ready to be able to start again the process */
- hsd->State = HAL_SD_STATE_READY;
- HAL_SD_ErrorCallback(hsd);
+ /* Nothing to do */
}
}
-#endif
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
* @brief return the SD state
- * @param hsd Pointer to sd handle
+ * @param hsd: Pointer to sd handle
* @retval HAL state
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
@@ -1717,7 +1776,7 @@
/**
* @brief Return the SD error code
-* @param hsd Pointer to a SD_HandleTypeDef structure that contains
+* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval SD Error Code
*/
@@ -1728,10 +1787,10 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
- __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
@@ -1743,14 +1802,14 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hsd Pointer SD handle
+ * @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_RxCpltCallback can be implemented in the user file
*/
@@ -1758,51 +1817,51 @@
/**
* @brief SD error callbacks
- * @param hsd Pointer SD handle
+ * @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
* @brief SD Abort callbacks
- * @param hsd Pointer SD handle
+ * @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SD_ErrorCallback can be implemented in the user file
- */
+ the HAL_SD_AbortCallback can be implemented in the user file
+ */
}
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User SD Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (surcharged) predefined callback
* @param hsd : SD handle
- * @param CallbackId : Id of the callback to be registered
+ * @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
* @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
* @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
* @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
- * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
- * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1815,10 +1874,10 @@
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_TX_CPLT_CB_ID :
hsd->TxCpltCallback = pCallback;
@@ -1840,7 +1899,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1848,7 +1907,7 @@
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = pCallback;
@@ -1858,7 +1917,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1867,7 +1926,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1879,28 +1938,28 @@
/**
* @brief Unregister a User SD Callback
- * SD Callback is redirected to the weak (surcharged) predefined callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
* @param hsd : SD handle
- * @param CallbackId : Id of the callback to be unregistered
+ * @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
* @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
* @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
* @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
- * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
- * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hsd);
-
+
if(hsd->State == HAL_SD_STATE_READY)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_TX_CPLT_CB_ID :
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
@@ -1922,7 +1981,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1930,7 +1989,7 @@
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
- switch (CallbackId)
+ switch (CallbackID)
{
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = HAL_SD_MspInit;
@@ -1940,7 +1999,7 @@
break;
default :
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1949,7 +2008,7 @@
else
{
/* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1958,21 +2017,21 @@
__HAL_UNLOCK(hsd);
return status;
}
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SD_Exported_Functions_Group3
- * @brief management functions
+ * @brief management functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to control the SD card
+ This subsection provides a set of functions allowing to control the SD card
operations and get the related information
@endverbatim
@@ -1982,79 +2041,31 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hsd Pointer to SD handle
- * @param pCID Pointer to a HAL_SD_CIDTypeDef structure that
- * contains all CID register parameters
+ * @param hsd: Pointer to SD handle
+ * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
+ * contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U);
- pCID->ManufacturerID = tmp;
-
- /* Byte 1 */
- tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U);
- pCID->OEM_AppliID = tmp << 8U;
-
- /* Byte 2 */
- tmp = (uint8_t)((hsd->CID[0U] & 0x000000FF00U) >> 8U);
- pCID->OEM_AppliID |= tmp;
-
- /* Byte 3 */
- tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU);
- pCID->ProdName1 = tmp << 24U;
-
- /* Byte 4 */
- tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U);
- pCID->ProdName1 |= tmp << 16;
-
- /* Byte 5 */
- tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U);
- pCID->ProdName1 |= tmp << 8U;
-
- /* Byte 6 */
- tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U);
- pCID->ProdName1 |= tmp;
-
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU);
- pCID->ProdName2 = tmp;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U);
- pCID->ProdRev = tmp;
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U);
- pCID->ProdSN = tmp << 24U;
-
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U);
- pCID->ProdSN |= tmp << 16U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU);
- pCID->ProdSN |= tmp << 8U;
-
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U);
- pCID->ProdSN |= tmp;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U);
- pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
- pCID->ManufactDate = (tmp & 0x0FU) << 8U;
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U);
- pCID->ManufactDate |= tmp;
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU);
- pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
+ pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+ pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+ pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+ pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+ pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+ pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+ pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+ pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+ pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
pCID->Reserved2 = 1U;
return HAL_OK;
@@ -2063,244 +2074,171 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hsd Pointer to SD handle
- * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that
- * contains all CSD register parameters
+ * @param hsd: Pointer to SD handle
+ * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
{
- uint32_t tmp = 0U;
-
- /* Byte 0 */
- tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U;
- pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
- pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
- pCSD->Reserved1 = tmp & 0x03U;
-
- /* Byte 1 */
- tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U;
- pCSD->TAAC = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U;
- pCSD->NSAC = (uint8_t)tmp;
-
- /* Byte 3 */
- tmp = hsd->CSD[0U] & 0x000000FFU;
- pCSD->MaxBusClkFrec = (uint8_t)tmp;
-
- /* Byte 4 */
- tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U;
- pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
-
- /* Byte 5 */
- tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U;
- pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
- pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
-
- /* Byte 6 */
- tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U;
- pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
- pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
- pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
- pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
- pCSD->Reserved2 = 0U; /*!< Reserved */
-
+ pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+ pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+ pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+ pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+ pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+ pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+ pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+ pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+ pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+ pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+ pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
+
+ pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
if(hsd->SdCard.CardType == CARD_SDSC)
{
- pCSD->DeviceSize = (tmp & 0x03U) << 10U;
-
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
- pCSD->DeviceSize |= (tmp) << 2U;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
- pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
-
- pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
- pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
- pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
- pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
- pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
-
- hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
- hsd->SdCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
- hsd->SdCard.BlockSize = 1U << (pCSD->RdBlockLen);
+ pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+ pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+ pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+ pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+ pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+ hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+ hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
hsd->SdCard.LogBlockSize = 512U;
}
else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
{
/* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
- pCSD->DeviceSize = (tmp & 0x3FU) << 16U;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
-
- pCSD->DeviceSize |= (tmp << 8U);
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
-
- pCSD->DeviceSize |= (tmp);
-
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
-
- hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1U) * 1024U);
- hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512U;
+ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+ hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+ hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+ hsd->SdCard.BlockSize = 512U;
+ hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
}
else
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
-
- pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
- pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
-
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU);
- pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
- pCSD->WrProtectGrSize = (tmp & 0x7FU);
-
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U);
- pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
- pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
- pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
- pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U);
- pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
- pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
- pCSD->Reserved3 = 0U;
- pCSD->ContentProtectAppli = (tmp & 0x01U);
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U);
- pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
- pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
- pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
- pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
- pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
- pCSD->ECC = (tmp & 0x03U);
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU);
- pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
- pCSD->Reserved4 = 1U;
-
+
+ pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+ pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+ pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+ pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+ pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+ pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+ pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+ pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+ pCSD->Reserved3 = 0;
+
+ pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+ pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+ pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+ pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+ pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+ pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+ pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+ pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
+ pCSD->Reserved4 = 1;
+
return HAL_OK;
}
/**
* @brief Gets the SD status info.
- * @param hsd Pointer to SD handle
- * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that
- * will contain the SD card status information
+ * @param hsd: Pointer to SD handle
+ * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
{
- uint32_t tmp = 0U;
- uint32_t sd_status[16U];
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t sd_status[16];
+ uint32_t errorstate;
+
errorstate = SD_SendSDStatus(hsd, sd_status);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
else
{
- /* Byte 0 */
- tmp = (sd_status[0U] & 0xC0U) >> 6U;
- pStatus->DataBusWidth = (uint8_t)tmp;
-
- /* Byte 0 */
- tmp = (sd_status[0U] & 0x20U) >> 5U;
- pStatus->SecuredMode = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (sd_status[0U] & 0x00FF0000U) >> 16U;
- pStatus->CardType = (uint16_t)(tmp << 8U);
-
- /* Byte 3 */
- tmp = (sd_status[0U] & 0xFF000000U) >> 24U;
- pStatus->CardType |= (uint16_t)tmp;
-
- /* Byte 4 */
- tmp = (sd_status[1U] & 0xFFU);
- pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24U);
-
- /* Byte 5 */
- tmp = (sd_status[1U] & 0xFF00U) >> 8U;
- pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16U);
-
- /* Byte 6 */
- tmp = (sd_status[1U] & 0xFF0000U) >> 16U;
- pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8U);
-
- /* Byte 7 */
- tmp = (sd_status[1U] & 0xFF000000U) >> 24U;
- pStatus->ProtectedAreaSize |= (uint32_t)tmp;
-
- /* Byte 8 */
- tmp = (sd_status[2U] & 0xFFU);
- pStatus->SpeedClass = (uint8_t)tmp;
-
- /* Byte 9 */
- tmp = (sd_status[2U] & 0xFF00U) >> 8U;
- pStatus->PerformanceMove = (uint8_t)tmp;
-
- /* Byte 10 */
- tmp = (sd_status[2U] & 0xF00000U) >> 20U;
- pStatus->AllocationUnitSize = (uint8_t)tmp;
-
- /* Byte 11 */
- tmp = (sd_status[2U] & 0xFF000000U) >> 24U;
- pStatus->EraseSize = (uint16_t)(tmp << 8U);
-
- /* Byte 12 */
- tmp = (sd_status[3U] & 0xFFU);
- pStatus->EraseSize |= (uint16_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[3U] & 0xFC00U) >> 10U;
- pStatus->EraseTimeout = (uint8_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[3U] & 0x0300U) >> 8U;
- pStatus->EraseOffset = (uint8_t)tmp;
+ pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+ pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+ pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+ pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) |
+ ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+ pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+ pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+ pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+ pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+ pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+ pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
}
-
+
return HAL_OK;
}
/**
* @brief Gets the SD card info.
- * @param hsd Pointer to SD handle
- * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that
- * will contain the SD card status information
+ * @param hsd: Pointer to SD handle
+ * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
@@ -2313,15 +2251,15 @@
pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
-
+
return HAL_OK;
}
/**
- * @brief Enables wide bus operation for the requested card if supported by
+ * @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hsd Pointer to SD handle
- * @param WideMode Specifies the SD card wide bus mode
+ * @param hsd: Pointer to SD handle
+ * @param WideMode: Specifies the SD card wide bus mode
* This parameter can be one of the following values:
* @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
@@ -2331,15 +2269,15 @@
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
{
SDIO_InitTypeDef Init;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
/* Check the parameters */
assert_param(IS_SDIO_BUS_WIDE(WideMode));
-
- /* Chnage Satte */
+
+ /* Change State */
hsd->State = HAL_SD_STATE_BUSY;
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
if(WideMode == SDIO_BUS_WIDE_8B)
{
@@ -2348,13 +2286,13 @@
else if(WideMode == SDIO_BUS_WIDE_4B)
{
errorstate = SD_WideBus_Enable(hsd);
-
+
hsd->ErrorCode |= errorstate;
}
else if(WideMode == SDIO_BUS_WIDE_1B)
{
errorstate = SD_WideBus_Disable(hsd);
-
+
hsd->ErrorCode |= errorstate;
}
else
@@ -2362,13 +2300,13 @@
/* WideMode is not a valid argument*/
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
}
- }
+ }
else
{
/* MMC Card does not support this feature */
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
-
+
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
@@ -2385,73 +2323,89 @@
Init.BusWide = WideMode;
Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
Init.ClockDiv = hsd->Init.ClockDiv;
- SDIO_Init(hsd->Instance, Init);
+ (void)SDIO_Init(hsd->Instance, Init);
}
/* Change State */
hsd->State = HAL_SD_STATE_READY;
-
+
return HAL_OK;
}
-
/**
* @brief Gets the current sd card data state.
- * @param hsd pointer to SD handle
+ * @param hsd: pointer to SD handle
* @retval Card state
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
{
- HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t cardstate;
+ uint32_t errorstate;
uint32_t resp1 = 0;
-
+
errorstate = SD_SendStatus(hsd, &resp1);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
}
- cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
-
- return cardstate;
+ cardstate = ((resp1 >> 9U) & 0x0FU);
+
+ return (HAL_SD_CardStateTypeDef)cardstate;
}
/**
* @brief Abort the current transfer and disable the SD.
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypeDef CardState;
-
+ uint32_t context = hsd->Context;
+
/* DIsable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
+
/* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+ CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
+
+ if ((context & SD_CONTEXT_DMA) != 0U)
{
/* Disable the SD DMA request */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Abort the SD DMA Tx Stream */
- if(hsd->hdmatx != NULL)
+
+ /* Abort the SD DMA Tx channel */
+ if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
- HAL_DMA_Abort(hsd->hdmatx);
+ if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ }
}
- /* Abort the SD DMA Rx Stream */
- if(hsd->hdmarx != NULL)
+ /* Abort the SD DMA Rx channel */
+ else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
- HAL_DMA_Abort(hsd->hdmarx);
+ if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ }
+ }
+ else
+ {
+ /* Nothing to do */
}
}
-
+
hsd->State = HAL_SD_STATE_READY;
+
+ /* Initialize the SD operation */
+ hsd->Context = SD_CONTEXT_NONE;
+
CardState = HAL_SD_GetCardState(hsd);
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
@@ -2466,51 +2420,58 @@
/**
* @brief Abort the current transfer and disable the SD (IT mode).
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypeDef CardState;
-
- /* DIsable All interrupts */
+ uint32_t context = hsd->Context;
+
+ /* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
+
+ CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
+
+ if ((context & SD_CONTEXT_DMA) != 0U)
{
/* Disable the SD DMA request */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
- /* Abort the SD DMA Tx Stream */
- if(hsd->hdmatx != NULL)
+
+ /* Abort the SD DMA Tx channel */
+ if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
- hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
{
hsd->hdmatx = NULL;
}
}
- /* Abort the SD DMA Rx Stream */
- if(hsd->hdmarx != NULL)
+ /* Abort the SD DMA Rx channel */
+ else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
- hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
{
hsd->hdmarx = NULL;
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
-
/* No transfer ongoing on both DMA channels*/
- if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
+ else
{
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
@@ -2521,53 +2482,53 @@
}
else
{
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->AbortCpltCallback(hsd);
#else
HAL_SD_AbortCallback(hsd);
-#endif
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
-
+
return HAL_OK;
}
/**
* @}
*/
-
+
/**
* @}
*/
-
-/* Private function ----------------------------------------------------------*/
+
+/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
*/
/**
- * @brief DMA SD transmit process complete callback
- * @param hdma DMA handle
+ * @brief DMA SD transmit process complete callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
-
+
/* Enable DATAEND Interrupt */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
}
/**
- * @brief DMA SD receive process complete callback
- * @param hdma DMA handle
+ * @brief DMA SD receive process complete callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
/* Send stop command in multiblock write */
if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
{
@@ -2582,15 +2543,16 @@
#endif
}
}
-
+
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the SD DCTRL register */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
-
+
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->RxCpltCallback(hsd);
@@ -2600,151 +2562,146 @@
}
/**
- * @brief DMA SD communication error callback
- * @param hdma DMA handle
+ * @brief DMA SD communication error callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMAError(DMA_HandleTypeDef *hdma)
+static void SD_DMAError(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
-
- if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+ uint32_t RxErrorCode, TxErrorCode;
+
+ /* if DMA error is FIFO error ignore it */
+ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
- /* Clear All flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* Disable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
- SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
-
- hsd->ErrorCode |= HAL_SD_ERROR_DMA;
- CardState = HAL_SD_GetCardState(hsd);
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ RxErrorCode = hsd->hdmarx->ErrorCode;
+ TxErrorCode = hsd->hdmatx->ErrorCode;
+ if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
{
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Disable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ CardState = HAL_SD_GetCardState(hsd);
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+
+ hsd->State= HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
}
-
- hsd->State= HAL_SD_STATE_READY;
- }
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->ErrorCallback(hsd);
#else
- HAL_SD_ErrorCallback(hsd);
+ HAL_SD_ErrorCallback(hsd);
#endif
-}
-
-/**
- * @brief DMA SD Tx Abort callback
- * @param hdma DMA handle
- * @retval None
- */
-static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- HAL_SD_CardStateTypeDef CardState;
-
- if(hsd->hdmatx != NULL)
- {
- hsd->hdmatx = NULL;
- }
-
- /* All DMA channels are aborted */
- if(hsd->hdmarx == NULL)
- {
- CardState = HAL_SD_GetCardState(hsd);
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->AbortCpltCallback(hsd);
-#else
- HAL_SD_AbortCallback(hsd);
-#endif
- }
- else
- {
-#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->ErrorCallback(hsd);
-#else
- HAL_SD_ErrorCallback(hsd);
-#endif
- }
- }
}
}
/**
- * @brief DMA SD Rx Abort callback
- * @param hdma DMA handle
+ * @brief DMA SD Tx Abort callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
-
- if(hsd->hdmarx != NULL)
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
- hsd->hdmarx = NULL;
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
}
-
- /* All DMA channels are aborted */
- if(hsd->hdmatx == NULL)
+
+ if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
{
- CardState = HAL_SD_GetCardState(hsd);
- hsd->ErrorCode = HAL_SD_ERROR_NONE;
- hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
- {
- hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
-
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
- {
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->AbortCpltCallback(hsd);
+ hsd->AbortCpltCallback(hsd);
#else
- HAL_SD_AbortCallback(hsd);
+ HAL_SD_AbortCallback(hsd);
#endif
- }
- else
- {
+ }
+ else
+ {
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
- hsd->ErrorCallback(hsd);
+ hsd->ErrorCallback(hsd);
#else
- HAL_SD_ErrorCallback(hsd);
+ HAL_SD_ErrorCallback(hsd);
#endif
- }
- }
}
}
+/**
+ * @brief DMA SD Rx Abort callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ HAL_SD_CardStateTypeDef CardState;
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->Context = SD_CONTEXT_NONE;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+
+ if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
+ {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
+ HAL_SD_AbortCallback(hsd);
+#endif
+ }
+ else
+ {
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
+ HAL_SD_ErrorCallback(hsd);
+#endif
+ }
+}
/**
* @brief Initializes the sd card.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval SD Card error state
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
{
HAL_SD_CardCSDTypeDef CSD;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint16_t sd_rca = 1U;
-
+
/* Check the power State */
- if(SDIO_GetPowerState(hsd->Instance) == 0U)
+ if(SDIO_GetPowerState(hsd->Instance) == 0U)
{
/* Power off */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hsd->Instance);
@@ -2761,8 +2718,8 @@
hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
}
}
-
- if(hsd->SdCard.CardType != CARD_SECURED)
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
@@ -2772,11 +2729,11 @@
return errorstate;
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Get the SD card RCA */
hsd->SdCard.RelCardAdd = sd_rca;
-
+
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2792,12 +2749,15 @@
hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
}
}
-
+
/* Get the Card Class */
hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
-
+
/* Get CSD parameters */
- HAL_SD_GetCardCSD(hsd, &CSD);
+ if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
@@ -2806,8 +2766,8 @@
return errorstate;
}
- /* Configure SDIO peripheral interface */
- SDIO_Init(hsd->Instance, hsd->Init);
+ /* Configure SDIO peripheral interface */
+ (void)SDIO_Init(hsd->Instance, hsd->Init);
/* All cards are initialized */
return HAL_SD_ERROR_NONE;
@@ -2817,138 +2777,126 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores SD information that will be needed in future
* in the SD handle.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
__IO uint32_t count = 0U;
uint32_t response = 0U, validvoltage = 0U;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->SdCard.CardVersion = CARD_V1_X;
-
- /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while(validvoltage == 0U)
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
- }
-
- /* Get command response */
- response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ return errorstate;
}
- /* Card type is SDSC */
- hsd->SdCard.CardType = CARD_SDSC;
+
}
else
{
hsd->SdCard.CardVersion = CARD_V2_X;
-
- /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while(validvoltage == 0U)
+ }
+
+ if( hsd->SdCard.CardVersion == CARD_V2_X)
+ {
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
- {
- return HAL_SD_ERROR_INVALID_VOLTRANGE;
- }
-
- /* SEND CMD55 APP_CMD with RCA as 0 */
- errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- return errorstate;
- }
-
- /* Get command response */
- response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- /* Get operating voltage*/
- validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
- }
-
- if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
- {
- hsd->SdCard.CardType = CARD_SDHC_SDXC;
- }
- else
- {
- hsd->SdCard.CardType = CARD_SDSC;
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
}
-
+ /* SD CARD */
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+ while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+ {
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Send CMD41 */
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+ count++;
+ }
+
+ if(count >= SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
+
+ if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ {
+ hsd->SdCard.CardType = CARD_SDHC_SDXC;
+ }
+ else
+ {
+ hsd->SdCard.CardType = CARD_SDSC;
+ }
+
+
return HAL_SD_ERROR_NONE;
}
/**
* @brief Turns the SDIO output signals off.
- * @param hsd Pointer to SD handle
- * @retval HAL status
+ * @param hsd: Pointer to SD handle
+ * @retval None
*/
-static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
{
/* Set Power State to OFF */
- SDIO_PowerState_OFF(hsd->Instance);
-
- return HAL_OK;
+ (void)SDIO_PowerState_OFF(hsd->Instance);
}
/**
* @brief Send Status info command.
- * @param hsd pointer to SD handle
- * @param pSDstatus Pointer to the buffer that will contain the SD card status
+ * @param hsd: pointer to SD handle
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status
* SD Status register)
* @retval error state
*/
static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count = 0U;
-
+ uint32_t count;
+ uint32_t *pData = pSDstatus;
+
/* Check SD response */
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Set block size for card if it is not equal to current block size for card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2956,7 +2904,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
+
/* Send CMD55 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2964,16 +2912,16 @@
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
- /* Configure the SD DPSM (Data Path State Machine) */
+
+ /* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 64U;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
+ (void)SDIO_ConfigData(hsd->Instance, &config);
+
/* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2981,7 +2929,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
-
+
/* Get status data */
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
{
@@ -2989,18 +2937,17 @@
{
for(count = 0U; count < 8U; count++)
{
- *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
+ *pData = SDIO_ReadFIFO(hsd->Instance);
+ pData++;
}
-
- pSDstatus += 8U;
}
-
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
@@ -3013,88 +2960,92 @@
{
return HAL_SD_ERROR_RX_OVERRUN;
}
+ else
+ {
+ /* Nothing to do */
+ }
while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
{
- *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
- pSDstatus++;
-
+ *pData = SDIO_ReadFIFO(hsd->Instance);
+ pData++;
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
/* Clear all the static status flags*/
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
return HAL_SD_ERROR_NONE;
}
/**
* @brief Returns the current card's status.
- * @param hsd Pointer to SD handle
- * @param pCardStatus pointer to the buffer that will contain the SD card
- * status (Card Status register)
+ * @param hsd: Pointer to SD handle
+ * @param pCardStatus: pointer to the buffer that will contain the SD card
+ * status (Card Status register)
* @retval error state
*/
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
{
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
if(pCardStatus == NULL)
{
return HAL_SD_ERROR_PARAM;
}
-
+
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Get SD card status */
*pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
+
return HAL_SD_ERROR_NONE;
}
/**
* @brief Enables the SDIO wide bus mode.
- * @param hsd pointer to SD handle
+ * @param hsd: pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
uint32_t scr[2U] = {0U, 0U};
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* If requested card supports wide bus operation */
if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3109,43 +3060,43 @@
/**
* @brief Disables the SDIO wide bus mode.
- * @param hsd Pointer to SD handle
+ * @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
uint32_t scr[2U] = {0U, 0U};
- uint32_t errorstate = HAL_SD_ERROR_NONE;
-
+ uint32_t errorstate;
+
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
-
+
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* If requested card supports 1 bit mode operation */
if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
return HAL_SD_ERROR_NONE;
}
else
@@ -3153,32 +3104,33 @@
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
}
-
-
+
+
/**
* @brief Finds the SD card SCR register value.
- * @param hsd Pointer to SD handle
- * @param pSCR pointer to the buffer that will contain the SCR value
+ * @param hsd: Pointer to SD handle
+ * @param pSCR: pointer to the buffer that will contain the SCR value
* @retval error state
*/
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
SDIO_DataInitTypeDef config;
- uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t index = 0U;
uint32_t tempscr[2U] = {0U, 0U};
-
+ uint32_t *scr = pSCR;
+
/* Set Block Size To 8 Bytes */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3189,15 +3141,15 @@
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
- SDIO_ConfigData(hsd->Instance, &config);
-
+ (void)SDIO_ConfigData(hsd->Instance, &config);
+
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
errorstate = SDMMC_CmdSendSCR(hsd->Instance);
- if(errorstate != HAL_OK)
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
+
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
{
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
@@ -3205,42 +3157,43 @@
*(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
index++;
}
-
+
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
-
+
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-
+
return HAL_SD_ERROR_DATA_TIMEOUT;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-
+
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-
+
return HAL_SD_ERROR_RX_OVERRUN;
}
else
{
/* No error flag set */
/* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- *(pSCR + 1U) = ((tempscr[0U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0U] & SDMMC_8TO15BITS) << 8U) |\
- ((tempscr[0U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0U] & SDMMC_24TO31BITS) >> 24U);
-
- *(pSCR) = ((tempscr[1U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1U] & SDMMC_8TO15BITS) << 8U) |\
- ((tempscr[1U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1U] & SDMMC_24TO31BITS) >> 24U);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+ *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+ ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+ scr++;
+ *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+
}
return HAL_SD_ERROR_NONE;
@@ -3248,60 +3201,86 @@
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count = 0U;
- uint32_t* tmp;
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
- tmp = (uint32_t*)hsd->pRxBuffPtr;
-
- /* Read data from SDIO Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ tmp = hsd->pRxBuffPtr;
+ dataremaining = hsd->RxXferSize;
+
+ if (dataremaining > 0U)
{
- *(tmp + count) = SDIO_ReadFIFO(hsd->Instance);
+ /* Read data from SDIO Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = SDIO_ReadFIFO(hsd->Instance);
+ *tmp = (uint8_t)(data & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+ tmp++;
+ dataremaining--;
+ }
+
+ hsd->pRxBuffPtr = tmp;
+ hsd->RxXferSize = dataremaining;
}
-
- hsd->pRxBuffPtr += 8U;
-
- return HAL_OK;
}
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hsd pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count = 0U;
- uint32_t* tmp;
-
- tmp = (uint32_t*)hsd->pTxBuffPtr;
-
- /* Write data to SDIO Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ uint32_t count, data, dataremaining;
+ uint8_t* tmp;
+
+ tmp = hsd->pTxBuffPtr;
+ dataremaining = hsd->TxXferSize;
+
+ if (dataremaining > 0U)
{
- SDIO_WriteFIFO(hsd->Instance, (tmp + count));
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ data = (uint32_t)(*tmp);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 8U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 16U);
+ tmp++;
+ dataremaining--;
+ data |= ((uint32_t)(*tmp) << 24U);
+ tmp++;
+ dataremaining--;
+ (void)SDIO_WriteFIFO(hsd->Instance, &data);
+ }
+
+ hsd->pTxBuffPtr = tmp;
+ hsd->TxXferSize = dataremaining;
}
-
- hsd->pTxBuffPtr += 8U;
-
- return HAL_OK;
}
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
#endif /* HAL_SD_MODULE_ENABLED */
/**
@@ -3312,4 +3291,6 @@
* @}
*/
+#endif /* SDIO */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f4xx_hal_smartcard.c b/Src/stm32f4xx_hal_smartcard.c
index 6b79f9a..2de2bb0 100644
--- a/Src/stm32f4xx_hal_smartcard.c
+++ b/Src/stm32f4xx_hal_smartcard.c
@@ -1570,7 +1570,7 @@
}
/* SMARTCARD Over-Run interrupt occurred -------------------------------*/
- if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
}
@@ -2269,6 +2269,7 @@
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t tmpreg = 0x00U;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
@@ -2335,17 +2336,20 @@
#if defined(USART6)
if((hsc->Instance == USART1) || (hsc->Instance == USART6))
{
- hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
}
#else
if(hsc->Instance == USART1)
{
- hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
}
#endif /* USART6 */
else
{
- hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
}
}
diff --git a/Src/stm32f4xx_hal_smbus.c b/Src/stm32f4xx_hal_smbus.c
index 6e7c508..46ac031 100644
--- a/Src/stm32f4xx_hal_smbus.c
+++ b/Src/stm32f4xx_hal_smbus.c
@@ -92,7 +92,7 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterXXXCallback()
@@ -110,9 +110,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback().
-
+ [..]
Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
@@ -127,9 +127,9 @@
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
-
+ [..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback().
-
+ [..]
By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_SMBUS_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
@@ -138,7 +138,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
+ [..]
Callbacks can be registered/unregistered in @ref HAL_SMBUS_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_SMBUS_STATE_READY or @ref HAL_SMBUS_STATE_RESET state,
@@ -146,7 +146,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
or @ref HAL_SMBUS_Init() function.
-
+ [..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
diff --git a/Src/stm32f4xx_hal_spi.c b/Src/stm32f4xx_hal_spi.c
index fbe57f4..d166674 100644
--- a/Src/stm32f4xx_hal_spi.c
+++ b/Src/stm32f4xx_hal_spi.c
@@ -65,16 +65,16 @@
Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
Function HAL_SPI_RegisterCallback() allows to register following callbacks:
- (+) TxCpltCallback : SPI Tx Completed callback
- (+) RxCpltCallback : SPI Rx Completed callback
- (+) TxRxCpltCallback : SPI TxRx Completed callback
- (+) TxHalfCpltCallback : SPI Tx Half Completed callback
- (+) RxHalfCpltCallback : SPI Rx Half Completed callback
- (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (+) ErrorCallback : SPI Error callback
- (+) AbortCpltCallback : SPI Abort callback
- (+) MspInitCallback : SPI Msp Init callback
- (+) MspDeInitCallback : SPI Msp DeInit callback
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
@@ -84,17 +84,18 @@
HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
- (+) TxCpltCallback : SPI Tx Completed callback
- (+) RxCpltCallback : SPI Rx Completed callback
- (+) TxRxCpltCallback : SPI TxRx Completed callback
- (+) TxHalfCpltCallback : SPI Tx Half Completed callback
- (+) RxHalfCpltCallback : SPI Rx Half Completed callback
- (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (+) ErrorCallback : SPI Error callback
- (+) AbortCpltCallback : SPI Abort callback
- (+) MspInitCallback : SPI Msp Init callback
- (+) MspDeInitCallback : SPI Msp DeInit callback
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+ [..]
By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
@@ -104,6 +105,7 @@
If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
@@ -112,7 +114,8 @@
using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
or HAL_SPI_Init() function.
- When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ [..]
+ When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -268,8 +271,8 @@
*/
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -489,7 +492,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -699,8 +703,8 @@
*/
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -1642,7 +1646,8 @@
hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@@ -1754,7 +1759,8 @@
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@@ -1875,7 +1881,8 @@
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@@ -1896,7 +1903,8 @@
hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@@ -1936,11 +1944,12 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
- __IO uint32_t count, resetcount;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
@@ -1963,8 +1972,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -1981,8 +1989,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2015,8 +2022,7 @@
break;
}
count--;
- }
- while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
}
}
@@ -2083,12 +2089,13 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
uint32_t abortcplt ;
- __IO uint32_t count, resetcount;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
@@ -2112,8 +2119,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2130,8 +2136,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2347,7 +2352,8 @@
}
/* SPI in Error Treatment --------------------------------------------------*/
- if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
+ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
+ || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
{
/* SPI Overrun error interrupt occurred ----------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
@@ -2944,8 +2950,7 @@
break;
}
count--;
- }
- while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Check if an Abort process is still ongoing */
if (hspi->hdmarx != NULL)
@@ -3546,8 +3551,7 @@
break;
}
count--;
- }
- while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
@@ -3702,8 +3706,7 @@
break;
}
count--;
- }
- while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
@@ -3760,8 +3763,7 @@
break;
}
count--;
- }
- while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
diff --git a/Src/stm32f4xx_hal_tim.c b/Src/stm32f4xx_hal_tim.c
index 99004f4..eb98d57 100644
--- a/Src/stm32f4xx_hal_tim.c
+++ b/Src/stm32f4xx_hal_tim.c
@@ -98,18 +98,22 @@
*** Callback registration ***
=============================================
+ [..]
The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
+ [..]
Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
+ [..]
Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
+ [..]
These functions allow to register/unregister following callbacks:
(+) Base_MspInitCallback : TIM Base Msp Init Callback.
(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
@@ -139,15 +143,18 @@
(+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
(+) BreakCallback : TIM Break Callback.
+ [..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+ [..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init / DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+ [..]
Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
Exception done MspInit / MspDeInit that can be registered / unregistered
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
@@ -155,6 +162,7 @@
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+ [..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -213,7 +221,7 @@
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig);
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
@@ -224,8 +232,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- *
+ * @brief Time Base functions
+ *
@verbatim
==============================================================================
##### Time Base functions #####
@@ -479,11 +487,11 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -556,8 +564,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- *
+ * @brief TIM Output Compare functions
+ *
@verbatim
==============================================================================
##### TIM Output Compare functions #####
@@ -922,16 +930,16 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
- uint32_t tmpsmcr;
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1129,8 +1137,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- *
+ * @brief TIM PWM functions
+ *
@verbatim
==============================================================================
##### TIM PWM functions #####
@@ -1502,11 +1510,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1703,8 +1711,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- *
+ * @brief TIM Input Capture functions
+ *
@verbatim
==============================================================================
##### TIM Input Capture functions #####
@@ -2050,11 +2058,11 @@
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2238,8 +2246,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- *
+ * @brief TIM One Pulse functions
+ *
@verbatim
==============================================================================
##### TIM One Pulse functions #####
@@ -2552,8 +2560,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- *
+ * @brief TIM Encoder functions
+ *
@verbatim
==============================================================================
##### TIM Encoder functions #####
@@ -2605,8 +2613,8 @@
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -2955,16 +2963,17 @@
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3138,8 +3147,8 @@
* @}
*/
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief TIM IRQ handler management
- *
+ * @brief TIM IRQ handler management
+ *
@verbatim
==============================================================================
##### IRQ handler management #####
@@ -3339,8 +3348,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief TIM Peripheral Control functions
- *
+ * @brief TIM Peripheral Control functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -3656,9 +3665,14 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
@@ -3805,11 +3819,11 @@
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -3852,7 +3866,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3868,7 +3883,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3884,7 +3900,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3900,7 +3917,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3916,7 +3934,8 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3932,7 +3951,8 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4055,8 +4075,8 @@
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -4064,11 +4084,11 @@
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4366,7 +4386,7 @@
/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
{
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@@ -4653,9 +4673,9 @@
htim->State = HAL_TIM_STATE_BUSY;
- if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@@ -4683,7 +4703,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -4694,9 +4714,9 @@
htim->State = HAL_TIM_STATE_BUSY;
- if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@@ -4786,8 +4806,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
+ * @brief TIM Callbacks functions
+ *
@verbatim
==============================================================================
##### TIM Callbacks functions #####
@@ -4990,7 +5010,8 @@
* @param pCallback pointer to the callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -5441,8 +5462,8 @@
*/
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief TIM Peripheral State functions
- *
+ * @brief TIM Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
@@ -6121,7 +6142,7 @@
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef *sSlaveConfig)
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;
diff --git a/Src/stm32f4xx_hal_tim_ex.c b/Src/stm32f4xx_hal_tim_ex.c
index fa2f8f1..99a13c0 100644
--- a/Src/stm32f4xx_hal_tim_ex.c
+++ b/Src/stm32f4xx_hal_tim_ex.c
@@ -72,7 +72,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
-*/
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -396,11 +396,11 @@
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -708,11 +708,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -1116,11 +1116,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -1464,7 +1464,8 @@
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1519,7 +1520,8 @@
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1575,7 +1577,8 @@
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1630,7 +1633,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@@ -1651,16 +1654,19 @@
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
@@ -1676,6 +1682,9 @@
* @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@@ -1886,7 +1895,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
diff --git a/Src/stm32f4xx_hal_uart.c b/Src/stm32f4xx_hal_uart.c
index d7e2cf5..eaf4114 100644
--- a/Src/stm32f4xx_hal_uart.c
+++ b/Src/stm32f4xx_hal_uart.c
@@ -325,7 +325,9 @@
/* Check the parameters */
if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
{
- /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
+ /* The hardware flow control is available only for USART1, USART2, USART3 and USART6.
+ Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5.
+ */
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
}
@@ -1009,10 +1011,13 @@
/**
* @brief Sends an amount of data in blocking mode.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
@@ -1040,6 +1045,10 @@
huart->TxXferSize = Size;
huart->TxXferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
while (huart->TxXferCount > 0U)
{
huart->TxXferCount--;
@@ -1078,9 +1087,6 @@
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1091,10 +1097,13 @@
/**
* @brief Receives an amount of data in blocking mode.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration
* @retval HAL status
*/
@@ -1123,6 +1132,9 @@
huart->RxXferSize = Size;
huart->RxXferCount = Size;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
{
@@ -1167,9 +1179,6 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1180,10 +1189,13 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1222,10 +1234,13 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1269,11 +1284,14 @@
}
/**
- * @brief Sends an amount of data in non blocking mode.
+ * @brief Sends an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1333,11 +1351,14 @@
}
/**
- * @brief Receives an amount of data in non blocking mode.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be received
+ * @brief Receives an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
* @retval HAL status
*/
@@ -2037,7 +2058,7 @@
}
/* UART Over-Run interrupt occurred --------------------------------------*/
- if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
@@ -3040,6 +3061,7 @@
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
uint32_t tmpreg;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
@@ -3072,39 +3094,57 @@
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
{
/*-------------------------- USART BRR Configuration ---------------------*/
-#if defined(USART6)
+#if defined(USART6) && defined(UART9) && defined(UART10)
+ if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
+ {
+ pclk = HAL_RCC_GetPCLK2Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
+ }
+#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
{
- huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
}
#else
if (huart->Instance == USART1)
{
- huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
}
#endif /* USART6 */
else
{
- huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
}
}
else
{
/*-------------------------- USART BRR Configuration ---------------------*/
-#if defined(USART6)
+#if defined(USART6) && defined(UART9) && defined(UART10)
+ if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
+ {
+ pclk = HAL_RCC_GetPCLK2Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
+ }
+#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
{
- huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
if (huart->Instance == USART1)
{
- huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#endif /* USART6 */
else
{
- huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
}
diff --git a/Src/stm32f4xx_hal_usart.c b/Src/stm32f4xx_hal_usart.c
index 655b80d..a65ea79 100644
--- a/Src/stm32f4xx_hal_usart.c
+++ b/Src/stm32f4xx_hal_usart.c
@@ -734,11 +734,14 @@
/**
* @brief Simplex Send an amount of data in blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param Timeout Timeout duration
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
@@ -759,7 +762,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
- /* Init tickstart for timeout managment */
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->TxXferSize = Size;
@@ -815,11 +818,15 @@
/**
* @brief Full-Duplex Receive an amount of data in blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pRxData Pointer to data buffer
- * @param Size Amount of data to be received
- * @param Timeout Timeout duration
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -839,7 +846,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment */
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -919,12 +926,15 @@
}
/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData Pointer to data transmitted buffer
- * @param pRxData Pointer to data received buffer
- * @param Size Amount of data to be sent
+ * @brief Full-Duplex Send and Receive an amount of data in full-duplex mode (blocking mode).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData Pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent (same amount to be received).
* @param Timeout Timeout duration
* @retval HAL status
*/
@@ -945,7 +955,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment */
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -1035,10 +1045,13 @@
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
*/
@@ -1085,10 +1098,14 @@
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pRxData Pointer to data buffer
- * @param Size Amount of data to be received
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1130,12 +1147,15 @@
}
/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData Pointer to data transmitted buffer
- * @param pRxData Pointer to data received buffer
- * @param Size Amount of data to be received
+ * @brief Full-Duplex Send and Receive an amount of data in full-duplex mode (non-blocking).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData Pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -1183,11 +1203,14 @@
}
/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @brief Simplex Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1245,11 +1268,14 @@
}
/**
- * @brief Full-Duplex Receive an amount of data in non-blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pRxData Pointer to data buffer
- * @param Size Amount of data to be received
+ * @brief Full-Duplex Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
* @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
@@ -1337,12 +1363,15 @@
}
/**
- * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @param pTxData Pointer to data transmitted buffer
- * @param pRxData Pointer to data received buffer
- * @param Size Amount of data to be received
+ * @brief Full-Duplex Transmit Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData Pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData Pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received/sent.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
@@ -1763,7 +1792,7 @@
}
/* USART Over-Run interrupt occurred -----------------------------------*/
- if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
@@ -2689,6 +2718,7 @@
static void USART_SetConfig(USART_HandleTypeDef *husart)
{
uint32_t tmpreg = 0x00U;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
@@ -2741,20 +2771,29 @@
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/
-#if defined(USART6)
+#if defined(USART6) && defined(UART9) && defined(UART10)
+ if ((husart->Instance == USART1) || (husart->Instance == USART6) || (husart->Instance == UART9) || (husart->Instance == UART10))
+ {
+ pclk = HAL_RCC_GetPCLK2Freq();
+ husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
+ }
+#elif defined(USART6)
if((husart->Instance == USART1) || (husart->Instance == USART6))
{
- husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
}
#else
if(husart->Instance == USART1)
{
- husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
- }
-#endif /* USART6 */
+ pclk = HAL_RCC_GetPCLK2Freq();
+ husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
+ }
+#endif /* USART6 || UART9 || UART10 */
else
{
- husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
}
}
diff --git a/Src/stm32f4xx_hal_wwdg.c b/Src/stm32f4xx_hal_wwdg.c
index 0c43ba7..60d41b9 100644
--- a/Src/stm32f4xx_hal_wwdg.c
+++ b/Src/stm32f4xx_hal_wwdg.c
@@ -32,17 +32,19 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
- max timeout before reset: ~73.14µs
- (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
- max timeout before reset: ~599.18ms
+ (++) Counter min (T[5;0] = 0x00) @42MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 97.52µs
+ (++) Counter max (T[5;0] = 0x3F) @42MHz (PCLK1) with prescaler dividing by 8:
+ max timeout before reset: approximately 49.93ms
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
+
*** Common driver usage ***
===========================
+
+ [..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
@@ -59,9 +61,10 @@
HAL_WWDG_Refresh() function. This operation must occur only when
the counter is lower than the refresh window value already programmed.
- [..]
*** Callback registration ***
=============================
+
+ [..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
@ref HAL_WWDG_RegisterCallback() to register a user callback.
@@ -80,13 +83,15 @@
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
+ [..]
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
- corresponding legacy weak (surcharged) functions:
+ corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
+ [..]
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** WWDG HAL driver macros list ***
@@ -138,8 +143,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
@@ -178,12 +183,12 @@
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers */
- if(hwwdg->EwiCallback == NULL)
+ if (hwwdg->EwiCallback == NULL)
{
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
}
- if(hwwdg->MspInitCallback == NULL)
+ if (hwwdg->MspInitCallback == NULL)
{
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
}
@@ -242,13 +247,13 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
status = HAL_ERROR;
}
else
{
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = pCallback;
@@ -270,7 +275,7 @@
/**
* @brief Unregister a WWDG Callback
- * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
* @param hwwdg WWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -282,7 +287,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
@@ -306,8 +311,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
diff --git a/Src/stm32f4xx_ll_adc.c b/Src/stm32f4xx_ll_adc.c
index 8acb231..7992694 100644
--- a/Src/stm32f4xx_ll_adc.c
+++ b/Src/stm32f4xx_ll_adc.c
@@ -709,8 +709,7 @@
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
- ADC_REG_InitStruct->SequencerLength
- | ADC_REG_InitStruct->SequencerDiscont
+ ADC_REG_InitStruct->SequencerDiscont
);
}
else
@@ -719,8 +718,7 @@
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
- ADC_REG_InitStruct->SequencerLength
- | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
);
}
diff --git a/Src/stm32f4xx_ll_gpio.c b/Src/stm32f4xx_ll_gpio.c
index eba14b0..bfdcb1e 100644
--- a/Src/stm32f4xx_ll_gpio.c
+++ b/Src/stm32f4xx_ll_gpio.c
@@ -211,35 +211,39 @@
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
-
+
/* Configure the port pins */
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
{
/* Get current io position */
currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
-
+
if (currentpin)
{
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
+
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
-
+
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
}
-
+
/* Pull-up Pull down resistor configuration*/
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
+
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
{
/* Check Alternate parameter */
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
-
+
/* Speed mode configuration */
if (POSITION_VAL(currentpin) < 0x00000008U)
{
@@ -250,19 +254,13 @@
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
return (SUCCESS);
}
diff --git a/Src/stm32f4xx_ll_lptim.c b/Src/stm32f4xx_ll_lptim.c
index 2c05217..cbc2037 100644
--- a/Src/stm32f4xx_ll_lptim.c
+++ b/Src/stm32f4xx_ll_lptim.c
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief LPTIM LL module driver.
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
@@ -172,14 +173,6 @@
}
/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
* @brief Disable the LPTIM instance
* @rmtoll CR ENABLE LL_LPTIM_Disable
* @param LPTIMx Low-Power Timer instance
@@ -207,11 +200,11 @@
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -232,11 +225,11 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -249,7 +242,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@@ -264,11 +258,13 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
+
/* Restore LPTIM source kernel clock */
LL_RCC_SetLPTIMClockSource(tmpclksource);
}
@@ -286,6 +282,14 @@
* @}
*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#endif /* LPTIM1 */
/**
diff --git a/Src/stm32f4xx_ll_rcc.c b/Src/stm32f4xx_ll_rcc.c
index 37c130a..ea18adc 100644
--- a/Src/stm32f4xx_ll_rcc.c
+++ b/Src/stm32f4xx_ll_rcc.c
@@ -185,7 +185,7 @@
*/
ErrorStatus LL_RCC_DeInit(void)
{
- uint32_t vl_mask = 0U;
+ __IO uint32_t vl_mask;
/* Set HSION bit */
LL_RCC_HSI_Enable();
@@ -197,10 +197,12 @@
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
- vl_mask = 0xFFFFFFFFU;
+ /* Read CR register */
+ vl_mask = LL_RCC_ReadReg(CR);
- /* Reset HSEON, PLLSYSON bits */
- CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
+ /* Reset HSEON, HSEBYP, PLLON, CSSON bits */
+ CLEAR_BIT(vl_mask,
+ (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
#if defined(RCC_PLLSAI_SUPPORT)
/* Reset PLLSAION bit */
@@ -212,7 +214,7 @@
CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
#endif /* RCC_PLLI2S_SUPPORT */
- /* Write new mask in CR register */
+ /* Write new value in CR register */
LL_RCC_WriteReg(CR, vl_mask);
/* Set HSITRIM bits to the reset value*/
diff --git a/Src/stm32f4xx_ll_sdmmc.c b/Src/stm32f4xx_ll_sdmmc.c
index 2b3f067..4f23a45 100644
--- a/Src/stm32f4xx_ll_sdmmc.c
+++ b/Src/stm32f4xx_ll_sdmmc.c
@@ -15,7 +15,7 @@
==============================================================================
##### SDMMC peripheral features #####
==============================================================================
- [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
+ [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
devices.
@@ -29,8 +29,7 @@
(+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
Rev1.1)
(+) Data transfer up to 48 MHz for the 8 bit mode
- (+) Data and command output enable signals to control external bidirectional drivers.
-
+ (+) Data and command output enable signals to control external bidirectional drivers
##### How to use this driver #####
==============================================================================
@@ -44,8 +43,8 @@
functionalities of the external device.
[..]
- (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL
- (PLL48CLK). Before start working with SDMMC peripheral make sure that the
+ (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+ PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
PLL is well configured.
The SDMMC peripheral uses two clock signals:
(++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
@@ -57,13 +56,13 @@
(+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
peripheral.
- (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
- function and disable it using the function SDIO_PowerState_ON(SDIOx).
+ (+) Enable the Power ON State using the SDIO_PowerState_ON()
+ function and disable it using the function SDIO_PowerState_OFF().
(+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
- (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hSDIO, IT)
- and __SDIO_DISABLE_IT(hSDIO, IT) if you need to use interrupt mode.
+ (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT()
+ and __SDIO_DISABLE_IT() if you need to use interrupt mode.
(+) When using the DMA mode
(++) Configure the DMA in the MSP layer of the external device
@@ -89,7 +88,7 @@
SDIO_GetResponse() function.
(+) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(),
+ data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
*** Read Operations ***
@@ -151,7 +150,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -159,6 +158,8 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+#if defined(SDIO)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -169,11 +170,6 @@
*/
#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -209,13 +205,13 @@
/**
* @brief Initializes the SDMMC according to the specified
* parameters in the SDMMC_InitTypeDef and create the associated handle.
- * @param SDIOx Pointer to SDMMC register base
- * @param Init SDMMC initialization structure
+ * @param SDIOx: Pointer to SDMMC register base
+ * @param Init: SDMMC initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
@@ -263,7 +259,7 @@
/**
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
@@ -274,8 +270,8 @@
/**
* @brief Write data (word) to Tx FIFO in blocking mode (polling)
- * @param SDIOx Pointer to SDMMC register base
- * @param pWriteData pointer to data to write
+ * @param SDIOx: Pointer to SDMMC register base
+ * @param pWriteData: pointer to data to write
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
@@ -307,33 +303,37 @@
/**
* @brief Set SDMMC Power state to ON.
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
{
/* Set power state to ON */
SDIOx->POWER = SDIO_POWER_PWRCTRL;
+
+ /* 1ms: required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(2);
return HAL_OK;
}
/**
* @brief Set SDMMC Power state to OFF.
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
{
/* Set power state to OFF */
- SDIOx->POWER = 0x00000000U;
+ SDIOx->POWER = (uint32_t)0x00000000;
return HAL_OK;
}
/**
* @brief Get SDMMC Power state.
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval Power status of the controller. The returned value can be one of the
* following values:
* - 0x00: Power OFF
@@ -348,14 +348,14 @@
/**
* @brief Configure the SDMMC command path according to the specified parameters in
* SDIO_CmdInitTypeDef structure and send the command
- * @param SDIOx Pointer to SDMMC register base
- * @param Command pointer to a SDIO_CmdInitTypeDef structure that contains
+ * @param SDIOx: Pointer to SDMMC register base
+ * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains
* the configuration information for the SDMMC command
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
@@ -380,7 +380,7 @@
/**
* @brief Return the command index of last command for which response received
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval Command index of the last command response received
*/
uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
@@ -391,24 +391,24 @@
/**
* @brief Return the response received from the card for the last command
- * @param SDIOx Pointer to SDMMC register base
- * @param Response Specifies the SDMMC response register.
+ * @param SDIOx: Pointer to SDMMC register base
+ * @param Response: Specifies the SDMMC response register.
* This parameter can be one of the following values:
* @arg SDIO_RESP1: Response Register 1
- * @arg SDIO_RESP1: Response Register 2
- * @arg SDIO_RESP1: Response Register 3
- * @arg SDIO_RESP1: Response Register 4
+ * @arg SDIO_RESP2: Response Register 2
+ * @arg SDIO_RESP3: Response Register 3
+ * @arg SDIO_RESP4: Response Register 4
* @retval The Corresponding response register value
*/
uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
{
- __IO uint32_t tmp = 0U;
+ uint32_t tmp;
/* Check the parameters */
assert_param(IS_SDIO_RESP(Response));
/* Get the response */
- tmp = (uint32_t)&(SDIOx->RESP1) + Response;
+ tmp = (uint32_t)(&(SDIOx->RESP1)) + Response;
return (*(__IO uint32_t *) tmp);
}
@@ -416,14 +416,14 @@
/**
* @brief Configure the SDMMC data path according to the specified
* parameters in the SDIO_DataInitTypeDef.
- * @param SDIOx Pointer to SDMMC register base
- * @param Data pointer to a SDIO_DataInitTypeDef structure
+ * @param SDIOx: Pointer to SDIO register base
+ * @param Data : pointer to a SDIO_DataInitTypeDef structure
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
@@ -453,7 +453,7 @@
/**
* @brief Returns number of remaining data bytes to be transferred.
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval Number of remaining data bytes to be transferred
*/
uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
@@ -463,7 +463,7 @@
/**
* @brief Get the FIFO data
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval Data received
*/
uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
@@ -473,8 +473,8 @@
/**
* @brief Sets one of the two options of inserting read wait interval.
- * @param SDIOx Pointer to SDMMC register base
- * @param SDIO_ReadWaitMode SDMMC Read Wait operation mode.
+ * @param SDIOx: Pointer to SDIO register base
+ * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
* This parameter can be:
* @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
* @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
@@ -512,13 +512,13 @@
/**
* @brief Send the Data Block Lenght command and check the response
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
@@ -526,7 +526,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
@@ -536,13 +536,13 @@
/**
* @brief Send the Read Single Block command and check the response
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
@@ -550,7 +550,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
@@ -560,13 +560,13 @@
/**
* @brief Send the Read Multi Block command and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
@@ -574,7 +574,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
@@ -584,13 +584,13 @@
/**
* @brief Send the Write Single Block command and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
@@ -598,7 +598,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
@@ -608,13 +608,13 @@
/**
* @brief Send the Write Multi Block command and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
@@ -622,7 +622,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
@@ -632,13 +632,13 @@
/**
* @brief Send the Start Address Erase command for SD and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
@@ -646,7 +646,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
@@ -656,13 +656,13 @@
/**
* @brief Send the End Address Erase command for SD and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
@@ -670,7 +670,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
@@ -680,13 +680,13 @@
/**
* @brief Send the Start Address Erase command and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
@@ -694,7 +694,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
@@ -704,13 +704,13 @@
/**
* @brief Send the End Address Erase command and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
@@ -718,7 +718,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
@@ -728,13 +728,13 @@
/**
* @brief Send the Erase command and check the response
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = 0U;
@@ -742,7 +742,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
@@ -752,13 +752,13 @@
/**
* @brief Send the Stop Transfer command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD12 STOP_TRANSMISSION */
sdmmc_cmdinit.Argument = 0U;
@@ -766,24 +766,24 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, 100000000U);
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT);
return errorstate;
}
/**
* @brief Send the Select Deselect command and check the response.
- * @param SDIOx Pointer to SDIO register base
- * @param addr Address of the card to be selected
+ * @param SDIOx: Pointer to SDIO register base
+ * @param addr: Address of the card to be selected
* @retval HAL status
*/
uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD7 SDMMC_SEL_DESEL_CARD */
sdmmc_cmdinit.Argument = (uint32_t)Addr;
@@ -791,7 +791,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
@@ -801,20 +801,20 @@
/**
* @brief Send the Go Idle State command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
sdmmc_cmdinit.Response = SDIO_RESPONSE_NO;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdError(SDIOx);
@@ -824,13 +824,13 @@
/**
* @brief Send the Operating Condition command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD8 to verify SD card interface operating condition */
/* Argument: - [31:12]: Reserved (shall be set to '0')
@@ -842,7 +842,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp7(SDIOx);
@@ -854,20 +854,21 @@
* @brief Send the Application command to verify that that the next command
* is an application specific com-mand rather than a standard command
* and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = (uint32_t)Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
/* If there is a HAL_ERROR, it is a MMC card, else
@@ -881,20 +882,21 @@
/**
* @brief Send the command asking the accessed card to send its operating
* condition register (OCR)
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType)
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType;
+ sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp3(SDIOx);
@@ -904,20 +906,21 @@
/**
* @brief Send the Bus Width command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
+ * @param BusWidth: BusWidth
* @retval HAL status
*/
uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
@@ -927,13 +930,13 @@
/**
* @brief Send the Send SCR command and check the response.
- * @param SDIOx Pointer to SDMMC register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD51 SD_APP_SEND_SCR */
sdmmc_cmdinit.Argument = 0U;
@@ -941,7 +944,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
@@ -951,13 +954,13 @@
/**
* @brief Send the Send CID command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD2 ALL_SEND_CID */
sdmmc_cmdinit.Argument = 0U;
@@ -965,7 +968,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDIOx);
@@ -975,21 +978,22 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD9 SEND_CSD */
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDIOx);
@@ -999,13 +1003,14 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
+ * @param pRCA: Card RCA
* @retval HAL status
*/
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
/* Send CMD3 SD_CMD_SET_REL_ADDR */
sdmmc_cmdinit.Argument = 0U;
@@ -1013,7 +1018,7 @@
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
@@ -1023,20 +1028,21 @@
/**
* @brief Send the Status command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
+ * @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
@@ -1046,20 +1052,20 @@
/**
* @brief Send the Status register command and check the response.
- * @param SDIOx Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = 0U;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
@@ -1070,21 +1076,21 @@
/**
* @brief Sends host capacity support information and activates the card's
* initialization process. Send SDMMC_CMD_SEND_OP_COND command
- * @param SDIOx Pointer to SDIO register base
- * @parame Argument Argument used for the command
+ * @param SDIOx: Pointer to SDIO register base
+ * @parame Argument: Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
sdmmc_cmdinit.Argument = Argument;
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp3(SDIOx);
@@ -1094,21 +1100,23 @@
/**
* @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
- * @param SDIOx Pointer to SDIO register base
- * @parame Argument Argument used for the command
+ * @param SDIOx: Pointer to SDIO register base
+ * @parame Argument: Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
SDIO_CmdInitTypeDef sdmmc_cmdinit;
- uint32_t errorstate = SDMMC_ERROR_NONE;
+ uint32_t errorstate;
- sdmmc_cmdinit.Argument = Argument;
+ /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+ /* CMD Response: R1 */
+ sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+ (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
@@ -1127,13 +1135,13 @@
/**
* @brief Checks for error conditions for CMD0.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
{
/* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
+ The SDIO_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
@@ -1146,20 +1154,21 @@
}while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
/* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
return SDMMC_ERROR_NONE;
}
/**
* @brief Checks for error conditions for R1 response.
- * @param hsd SD handle
- * @param SD_CMD The sent command index
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
{
uint32_t response_r1;
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
@@ -1171,9 +1180,10 @@
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDIOx->STA;
+ }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
@@ -1186,6 +1196,13 @@
return SDMMC_ERROR_CMD_CRC_FAIL;
}
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
@@ -1193,9 +1210,6 @@
return SDMMC_ERROR_CMD_CRC_FAIL;
}
- /* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
-
/* We have received response, retrieve it for analysis */
response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
@@ -1283,13 +1297,14 @@
/**
* @brief Checks for error conditions for R2 (CID or CSD) response.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
{
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
+ The SDIO_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
@@ -1298,8 +1313,9 @@
{
return SDMMC_ERROR_TIMEOUT;
}
-
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+ sta_reg = SDIOx->STA;
+ }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
{
@@ -1317,7 +1333,7 @@
{
/* No error flag set */
/* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
}
return SDMMC_ERROR_NONE;
@@ -1325,13 +1341,14 @@
/**
* @brief Checks for error conditions for R3 (OCR) response.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
{
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
+ The SDIO_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
@@ -1340,9 +1357,10 @@
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDIOx->STA;
+ }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
@@ -1350,10 +1368,9 @@
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
else
-
{
/* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
}
return SDMMC_ERROR_NONE;
@@ -1361,18 +1378,19 @@
/**
* @brief Checks for error conditions for R6 (RCA) response.
- * @param hsd SD handle
- * @param SD_CMD The sent command index
- * @param pRCA Pointer to the variable that will contain the SD card relative
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @param pRCA: Pointer to the variable that will contain the SD card relative
* address RCA
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
{
uint32_t response_r1;
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
+ The SDIO_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
@@ -1381,9 +1399,10 @@
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDIOx->STA;
+ }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
@@ -1396,6 +1415,10 @@
return SDMMC_ERROR_CMD_CRC_FAIL;
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
@@ -1404,7 +1427,7 @@
}
/* Clear all the static flags */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
/* We have received response, retrieve it. */
response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
@@ -1431,11 +1454,12 @@
/**
* @brief Checks for error conditions for R7 response.
- * @param hsd SD handle
+ * @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
{
+ uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDIO_CMDTIMEOUT is expressed in ms */
register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
@@ -1446,16 +1470,28 @@
{
return SDMMC_ERROR_TIMEOUT;
}
+ sta_reg = SDIOx->STA;
+ }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
- }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
-
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
{
/* Card is SD V2.0 compliant */
- __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
+ else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
{
@@ -1471,15 +1507,7 @@
* @}
*/
-/**
- * @}
- */
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
-
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
/**
* @}
*/
@@ -1488,4 +1516,6 @@
* @}
*/
+#endif /* SDIO */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f4xx_ll_spi.c b/Src/stm32f4xx_ll_spi.c
index 5d2902b..dfbdabe 100644
--- a/Src/stm32f4xx_ll_spi.c
+++ b/Src/stm32f4xx_ll_spi.c
@@ -60,41 +60,41 @@
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
* @{
*/
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
- || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
- || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
- || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
- || ((__VALUE__) == LL_SPI_MSB_FIRST))
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
- || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
@@ -330,36 +330,36 @@
* @{
*/
-#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
- || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
- || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
- || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
- && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
- || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
- || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
/**
* @}
*/
@@ -399,7 +399,9 @@
*/
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
{
- uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t i2sdiv = 2U;
+ uint32_t i2sodd = 0U;
+ uint32_t packetlength = 1U;
uint32_t tmp;
uint32_t sourceclock;
ErrorStatus status = ERROR;
diff --git a/Src/stm32f4xx_ll_tim.c b/Src/stm32f4xx_ll_tim.c
index f99d29f..bee919b 100644
--- a/Src/stm32f4xx_ll_tim.c
+++ b/Src/stm32f4xx_ll_tim.c
@@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F4xx_LL_Driver
* @{
@@ -46,89 +46,89 @@
* @{
*/
#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
- || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
- || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
- || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
- || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
/**
* @}
*/
@@ -669,7 +669,7 @@
* @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
* depending on the LOCK configuration, it can be necessary to configure all of
* them during the first write access to the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @param TIMx Timer Instance
* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
@@ -717,7 +717,7 @@
*/
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
- * @brief Private functions
+ * @brief Private functions
* @{
*/
/**
diff --git a/Src/stm32f4xx_ll_usart.c b/Src/stm32f4xx_ll_usart.c
index dab4fdd..1c3dd0c 100644
--- a/Src/stm32f4xx_ll_usart.c
+++ b/Src/stm32f4xx_ll_usart.c
@@ -346,13 +346,13 @@
#if defined(UART9)
else if (USARTx == UART9)
{
- periphclk = rcc_clocks.PCLK1_Frequency;
+ periphclk = rcc_clocks.PCLK2_Frequency;
}
#endif /* UART9 */
#if defined(UART10)
else if (USARTx == UART10)
{
- periphclk = rcc_clocks.PCLK1_Frequency;
+ periphclk = rcc_clocks.PCLK2_Frequency;
}
#endif /* UART10 */
else
