Release v1.1.1
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 887d64b..cdc70e3 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -236,12 +236,12 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4)
-#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
-#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -306,8 +306,17 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
#endif /* STM32L4 */
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#endif
+
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -365,6 +374,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
#endif /* STM32H7 */
/**
@@ -460,7 +472,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -564,7 +578,14 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#endif
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
@@ -735,6 +756,66 @@
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+ * set/reset crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
/**
* @}
*/
@@ -874,7 +955,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -933,7 +1014,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -965,6 +1046,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -1358,6 +1449,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1380,6 +1495,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
/**
* @}
*/
@@ -1409,16 +1531,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1437,6 +1561,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@@ -1509,14 +1640,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@@ -3112,9 +3243,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3242,7 +3372,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3350,22 +3480,22 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3606,12 +3736,12 @@
* @{
*/
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
@@ -3620,9 +3750,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32L4)
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif
+#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_cryp.h b/Inc/stm32g4xx_hal_cryp.h
index ef5305f..a9f0b2e 100644
--- a/Inc/stm32g4xx_hal_cryp.h
+++ b/Inc/stm32g4xx_hal_cryp.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -64,9 +64,10 @@
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
- uint32_t HeaderSize; /*!< The size of header buffer in word */
+ uint32_t HeaderSize; /*!< The size of header buffer */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
- uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
Vector only once and to skip configuration for consecutive processings.
This parameter can be a value of @ref CRYP_Configuration_Skip */
@@ -182,10 +183,12 @@
uint32_t Key_saved[8]; /*!< copy of key registers */
- uint32_t Size_saved; /*!< copy of input buffer size */
+ uint16_t Size_saved; /*!< copy of input buffer size */
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
+ uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
+
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
@@ -263,6 +266,17 @@
* @}
*/
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+ * @{
+ */
+
+#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
+
+/**
+ * @}
+ */
+
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
@@ -565,6 +579,13 @@
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
+ (((((ALGO) == CRYP_AES_CTR)) && \
+ ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
+ (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
+ (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
+ ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_cryp_ex.h b/Inc/stm32g4xx_hal_cryp_ex.h
index 30817da..0708eb2 100644
--- a/Inc/stm32g4xx_hal_cryp_ex.h
+++ b/Inc/stm32g4xx_hal_cryp_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_fmac.h b/Inc/stm32g4xx_hal_fmac.h
index b6e21d7..1f289dd 100644
--- a/Inc/stm32g4xx_hal_fmac.h
+++ b/Inc/stm32g4xx_hal_fmac.h
@@ -2,8 +2,7 @@
******************************************************************************
* @file stm32g4xx_hal_fmac.h
* @author MCD Application Team
- * @brief This file contains all the functions prototypes for the FMAC firmware
- * library.
+ * @brief Header for stm32g4xx_hal_fmac.c module
******************************************************************************
* @attention
*
@@ -135,7 +134,7 @@
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/**
- * @brief FMAC Callback ID structure definition
+ * @brief FMAC Callback ID enumeration definition
*/
typedef enum
{
@@ -165,31 +164,31 @@
{
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
Ignored if InputBufferSize is set to 0 (previous configuration kept).
- NB: the buffers can overlap or even coincide exactly. */
+ Note: the buffers can overlap or even coincide exactly. */
- uint8_t InputBufferSize; /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
- in the buffer is inferior to this threshold.
+ in the buffer is lower than this threshold.
This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
Ignored if CoeffBufferSize is set to 0 (previous configuration kept).
- NB: the buffers can overlap or even coincide exactly. */
+ Note: the buffers can overlap or even coincide exactly. */
- uint8_t CoeffBufferSize; /*!< Number of 16-bit addresses allocated to the coefficient buffer.
+ uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
0 if a previous configuration should be kept. */
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
Ignored if OuputBufferSize is set to 0 (previous configuration kept).
- NB: the buffers can overlap or even coincide exactly. */
+ Note: the buffers can overlap or even coincide exactly. */
- uint8_t OutputBufferSize; /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
- in the buffer is inferior to this threshold.
+ in the buffer is lower than this threshold.
This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
@@ -202,13 +201,15 @@
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
- uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None.
+ uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
- uint32_t Clip; /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded).
+ uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping
+ is done when the clipping feature is disabled and saturation is done when the
+ clipping feature is enabled.
This parameter can be a value of @ref FMAC_Clip_State. */
uint32_t Filter; /*!< Filter type.
@@ -237,17 +238,17 @@
/** @defgroup FMAC_Error_Code FMAC Error code
* @{
*/
-#define HAL_FMAC_ERROR_NONE 0x00000000UL /*!< No error */
-#define HAL_FMAC_ERROR_SAT 0x00000001UL /*!< Saturation error */
-#define HAL_FMAC_ERROR_UNFL 0x00000002UL /*!< Underflow error */
-#define HAL_FMAC_ERROR_OVFL 0x00000004UL /*!< Overflow error */
-#define HAL_FMAC_ERROR_DMA 0x00000008UL /*!< DMA error */
-#define HAL_FMAC_ERROR_RESET 0x00000010UL /*!< Reset error */
-#define HAL_FMAC_ERROR_PARAM 0x00000020UL /*!< Parameter error */
+#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
+#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
+#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
+#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
+#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
+#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
-#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040UL /*!< Invalid Callback error */
+#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
-#define HAL_FMAC_ERROR_TIMEOUT 0x00000080UL /*!< Timeout error */
+#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
/**
* @}
@@ -256,11 +257,11 @@
/** @defgroup FMAC_Functions FMAC Functions
* @{
*/
-#define FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
-#define FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
-#define FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
-#define FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
-#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
+#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
+#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
+#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
+#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
+#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
/**
* @}
*/
@@ -269,15 +270,15 @@
* @{
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
*/
-#define FMAC_THRESHOLD_1 0x00000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
+#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */
-#define FMAC_THRESHOLD_2 0x01000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
+#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */
-#define FMAC_THRESHOLD_4 0x02000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
+#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */
-#define FMAC_THRESHOLD_8 0x03000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
+#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */
-#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFUL /*!< The configured threshold value shouldn't be changed */
+#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
/**
* @}
*/
@@ -286,7 +287,7 @@
* @{
*/
#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
-#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through the FMAC DMA */
+#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
/**
@@ -296,7 +297,7 @@
/** @defgroup FMAC_Clip_State FMAC Clip State
* @{
*/
-#define FMAC_CLIP_DISABLED 0x00000000UL /*!< Clipping disabled */
+#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
/**
* @}
@@ -326,52 +327,13 @@
* @}
*/
-/** @defgroup FMAC_DMAR DMA Read Request Enable bit
- * @{
- */
-#define FMAC_DMA_REN FMAC_CR_DMAREN /*!< DMA Read Requests Enable */
-/**
- * @}
- */
-
-/** @defgroup FMAC_DMAW DMA Write Request Enable bit
- * @{
- */
-#define FMAC_DMA_WEN FMAC_CR_DMAWEN /*!< DMA Write Channel Enable */
-/**
- * @}
- */
-
-/** @defgroup FMAC_DMAS DMA START bit
- * @{
- */
-#define FMAC_START FMAC_PARAM_START /*!< DMA Start */
-/**
- * @}
- */
-
-/** @defgroup FMAC_TimeOut_Value FMAC polling-based communications time-out value
- * @{
- */
-#define HAL_FMAC_TIMEOUT_VALUE 1000UL /*!< FMAC polling-based communications time-out value */
-/**
- * @}
- */
-
-/** @defgroup FMAC_Reset_TimeOut_Value FMAC reset time-out value
- * @{
- */
-#define HAL_FMAC_RESET_TIMEOUT_VALUE 500UL /*!< FMAC reset time-out value */
-/**
- * @}
- */
-
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* External variables --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
* @{
*/
@@ -391,10 +353,10 @@
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
/**
- * @brief Enable the FMAC interrupt when result is ready
+ * @brief Enable the specified FMAC interrupt
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC Interrupt.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_IT_RIEN Read interrupt enable
* @arg @ref FMAC_IT_WIEN Write interrupt enable
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
@@ -409,7 +371,7 @@
* @brief Disable the FMAC interrupt
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC Interrupt.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_IT_RIEN Read interrupt enable
* @arg @ref FMAC_IT_WIEN Write interrupt enable
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
@@ -423,7 +385,7 @@
/** @brief Check whether the specified FMAC interrupt occurred or not.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to check.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
@@ -445,7 +407,7 @@
/** @brief Check whether the specified FMAC status flag is set or not.
* @param __HANDLE__ FMAC handle.
* @param __FLAG__ FMAC flag to check.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
@@ -482,7 +444,6 @@
* @}
*/
-/* Private macros --------------------------------------------------------*/
/** @addtogroup FMAC_Private_Macros
* @{
*/
@@ -499,7 +460,7 @@
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
/**
- * @brief Verify the FMAC load function.
+ * @brief Verify the FMAC load function used for input data, output data or coefficients.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
@@ -508,7 +469,7 @@
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
/**
- * @brief Verify the FMAC load function.
+ * @brief Verify the FMAC load function used with N values as input or output data.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
@@ -516,7 +477,7 @@
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
/**
- * @brief Verify the FMAC load function.
+ * @brief Verify the FMAC load function used with N + M values as coefficients.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
@@ -592,6 +553,19 @@
((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
/**
+ * @brief Check whether the threshold is applicable.
+ * @param __SIZE__ Size of the matching buffer.
+ * @param __WM__ Watermark value.
+ * @param __ACCESS__ Access to the buffer (polling, it, dma, none).
+ * @retval THRESHOLD
+ */
+#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
+ ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \
+ ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+
+/**
* @}
*/
@@ -623,8 +597,8 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
-HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize);
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
diff --git a/Inc/stm32g4xx_hal_gpio_ex.h b/Inc/stm32g4xx_hal_gpio_ex.h
index cda1636..4f26da2 100644
--- a/Inc/stm32g4xx_hal_gpio_ex.h
+++ b/Inc/stm32g4xx_hal_gpio_ex.h
@@ -82,6 +82,7 @@
#endif /* TIM5 */
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
#endif /* TIM20 */
@@ -214,6 +215,7 @@
* @brief AF 9 selection
*/
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
#define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
@@ -245,6 +247,7 @@
#define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */
#endif /* FDCAN3 */
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
@@ -252,7 +255,8 @@
* @brief AF 12 selection
*/
#define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
-#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#if defined(HRTIM1)
#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
diff --git a/Inc/stm32g4xx_hal_hrtim.h b/Inc/stm32g4xx_hal_hrtim.h
index 086ec4f..1e8a85e 100644
--- a/Inc/stm32g4xx_hal_hrtim.h
+++ b/Inc/stm32g4xx_hal_hrtim.h
@@ -1244,8 +1244,8 @@
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer C */
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
@@ -1268,7 +1268,7 @@
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
@@ -1336,8 +1336,8 @@
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer C */
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
@@ -1360,7 +1360,7 @@
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
@@ -2368,7 +2368,7 @@
* @{
* @brief Constants defining the DLL calibration periods (in micro seconds)
*/
-#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
+#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
#define HRTIM_CALIBRATIONRATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
#define HRTIM_CALIBRATIONRATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
#define HRTIM_CALIBRATIONRATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
@@ -3361,47 +3361,66 @@
((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
-#define IS_HRTIM_EVENTSRC(EVENTSRC)\
- (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \
- ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \
- ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \
- ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \
- ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \
- ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \
- ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \
- ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \
- ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ) || \
- ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ) || \
- ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ) || \
- ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ) || \
- ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ) || \
- ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ) || \
- ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ) || \
- ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ) || \
- ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ) || \
- ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1))
+#define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC) \
+ ((((EVENT) == HRTIM_EVENT_1) && \
+ (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \
+ ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_2) && \
+ (((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \
+ ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_3) && \
+ (((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \
+ ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_4) && \
+ (((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_5) && \
+ (((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_6) && \
+ (((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_7) && \
+ (((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \
+ ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_8) && \
+ (((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_9) && \
+ (((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \
+ ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \
+ ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_10) && \
+ (((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \
+ ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \
+ ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \
+ ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1))))
#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
@@ -3627,26 +3646,19 @@
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F))
#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
- (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
- ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \
+ (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3))
-#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
- ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
- || \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)))
+#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
+ ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
+ || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+ || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+ || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+ || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+ || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)))
#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
diff --git a/Inc/stm32g4xx_hal_i2c_ex.h b/Inc/stm32g4xx_hal_i2c_ex.h
index 68a443d..ca04b72 100644
--- a/Inc/stm32g4xx_hal_i2c_ex.h
+++ b/Inc/stm32g4xx_hal_i2c_ex.h
@@ -123,6 +123,9 @@
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
+
+
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_lptim.h b/Inc/stm32g4xx_hal_lptim.h
index e3bfd55..8ebd8c0 100644
--- a/Inc/stm32g4xx_hal_lptim.h
+++ b/Inc/stm32g4xx_hal_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM HAL module.
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -411,6 +412,8 @@
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
+ * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
+ * check for TIMEOUT.
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
@@ -447,6 +450,7 @@
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* @retval None
+ * @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
@@ -455,6 +459,7 @@
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value
* @retval None
+ * @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
@@ -503,6 +508,7 @@
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
@@ -519,6 +525,7 @@
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
+ * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
@@ -572,6 +579,10 @@
* @{
*/
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -579,7 +590,14 @@
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -628,12 +646,26 @@
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -651,9 +683,19 @@
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @addtogroup LPTIM_Group5
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+/**
+ * @}
+ */
/**
* @}
@@ -745,7 +787,7 @@
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
((__TRIG__) == LPTIM_TRIGSOURCE_9))
-#endif /* STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */
+#endif /* STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
@@ -807,7 +849,7 @@
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
-void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_opamp.h b/Inc/stm32g4xx_hal_opamp.h
index 8f185c0..3f52fdf 100644
--- a/Inc/stm32g4xx_hal_opamp.h
+++ b/Inc/stm32g4xx_hal_opamp.h
@@ -172,8 +172,8 @@
*/
typedef enum
{
- HAL_OPAMP_MSP_INIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */
- HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */
+ HAL_OPAMP_MSPINIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */
+ HAL_OPAMP_MSPDEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */
HAL_OPAMP_ALL_CB_ID = 0x03UL /*!< OPAMP All ID */
} HAL_OPAMP_CallbackIDTypeDef;
diff --git a/Inc/stm32g4xx_hal_pcd.h b/Inc/stm32g4xx_hal_pcd.h
index ce60a8a..4cc6d0b 100644
--- a/Inc/stm32g4xx_hal_pcd.h
+++ b/Inc/stm32g4xx_hal_pcd.h
@@ -196,7 +196,7 @@
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
diff --git a/Inc/stm32g4xx_hal_rcc_ex.h b/Inc/stm32g4xx_hal_rcc_ex.h
index 899dbf7..0f5eb75 100644
--- a/Inc/stm32g4xx_hal_rcc_ex.h
+++ b/Inc/stm32g4xx_hal_rcc_ex.h
@@ -1355,6 +1355,7 @@
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
diff --git a/Inc/stm32g4xx_hal_smbus.h b/Inc/stm32g4xx_hal_smbus.h
index c3abdb6..f9a9f31 100644
--- a/Inc/stm32g4xx_hal_smbus.h
+++ b/Inc/stm32g4xx_hal_smbus.h
@@ -132,7 +132,11 @@
* @brief SMBUS handle Structure definition
* @{
*/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
typedef struct __SMBUS_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
@@ -326,6 +330,7 @@
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
@@ -582,11 +587,12 @@
((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
diff --git a/Inc/stm32g4xx_hal_tim.h b/Inc/stm32g4xx_hal_tim.h
index fcf0950..abe7596 100644
--- a/Inc/stm32g4xx_hal_tim.h
+++ b/Inc/stm32g4xx_hal_tim.h
@@ -174,7 +174,7 @@
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -186,7 +186,7 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -316,6 +316,26 @@
} HAL_TIM_StateTypeDef;
/**
+ * @brief TIM Channel States definition
+ */
+typedef enum
+{
+ HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
+ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
+ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+ * @brief DMA Burst States definition
+ */
+typedef enum
+{
+ HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
+ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
+ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
* @brief HAL Active channel structures definition
*/
typedef enum
@@ -338,13 +358,16 @@
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
+ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
+ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@@ -554,6 +577,15 @@
* @}
*/
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+ * @{
+ */
+#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
+/**
+ * @}
+ */
+
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
@@ -647,6 +679,15 @@
* @}
*/
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@@ -1182,25 +1223,49 @@
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
+ } while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@@ -1427,6 +1492,31 @@
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Get update interrupt flag (UIF) copy status.
+ * @param __COUNTER__ Counter value.
+ * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+ */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
@@ -1445,6 +1535,8 @@
/**
* @brief Set the TIM Counter Register value on runtime.
+ * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+ * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
@@ -1804,6 +1896,9 @@
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+ ((__MODE__) == TIM_UIFREMAP_ENALE))
+
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
@@ -1826,6 +1921,9 @@
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@@ -2046,22 +2144,6 @@
((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
#if defined (TIM5) && defined(TIM20)
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR9) || \
- ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
@@ -2077,22 +2159,6 @@
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))
#elif defined (TIM5)
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_ETRF))
-
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
@@ -2106,21 +2172,6 @@
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))
#else
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR10) || \
- ((__SELECTION__) == TIM_TS_ITR11) || \
- ((__SELECTION__) == TIM_TS_ETRF))
-
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
@@ -2150,15 +2201,15 @@
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@@ -2215,6 +2266,50 @@
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
+ (__HANDLE__)->ChannelState[5])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
+ } while(0)
+
+#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
+ (__HANDLE__)->ChannelNState[3])
+
+#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
+ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
+ (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
+ } while(0)
+
/**
* @}
*/
@@ -2440,6 +2535,11 @@
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@@ -2459,7 +2559,6 @@
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
diff --git a/Inc/stm32g4xx_hal_tim_ex.h b/Inc/stm32g4xx_hal_tim_ex.h
index 2db8481..ef0b3e4 100644
--- a/Inc/stm32g4xx_hal_tim_ex.h
+++ b/Inc/stm32g4xx_hal_tim_ex.h
@@ -1839,6 +1839,7 @@
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_usart.h b/Inc/stm32g4xx_hal_usart.h
index 4e94aa4..99d3701 100644
--- a/Inc/stm32g4xx_hal_usart.h
+++ b/Inc/stm32g4xx_hal_usart.h
@@ -226,6 +226,7 @@
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@@ -350,6 +351,7 @@
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
+#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
@@ -404,6 +406,7 @@
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
+#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
@@ -460,6 +463,7 @@
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
+ * @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
@@ -480,6 +484,7 @@
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
* @retval None
*/
@@ -630,6 +635,7 @@
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
diff --git a/Inc/stm32g4xx_hal_usart_ex.h b/Inc/stm32g4xx_hal_usart_ex.h
index be45e60..96a67cd 100644
--- a/Inc/stm32g4xx_hal_usart_ex.h
+++ b/Inc/stm32g4xx_hal_usart_ex.h
@@ -46,7 +46,7 @@
* @{
*/
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
@@ -169,7 +169,6 @@
} \
} while(0U)
-
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__ USART frame length.
diff --git a/Inc/stm32g4xx_hal_wwdg.h b/Inc/stm32g4xx_hal_wwdg.h
index 0299d7f..575a1e3 100644
--- a/Inc/stm32g4xx_hal_wwdg.h
+++ b/Inc/stm32g4xx_hal_wwdg.h
@@ -303,6 +303,6 @@
}
#endif
-#endif /* __STM32G4xx_HAL_WWDG_H */
+#endif /* STM32G4xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32g4xx_ll_adc.h b/Inc/stm32g4xx_ll_adc.h
index f6870c9..8bcd9ca 100644
--- a/Inc/stm32g4xx_ll_adc.h
+++ b/Inc/stm32g4xx_ll_adc.h
@@ -2734,11 +2734,13 @@
}
/**
- * @brief Set parameter common to several ADC: measurement path to internal
- * channels (VrefInt, temperature sensor, ...).
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Configure all paths (overwrite current configuration).
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * The values not selected are removed from configuration.
* @note Stabilization time of measurement path to internal channel:
* After enabling internal paths, before starting ADC conversion,
* a delay is required for internal voltage reference and
@@ -2768,6 +2770,65 @@
}
/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Add paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Remove paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
+ * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
+ * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
* @brief Get parameter common to several ADC: measurement path to internal
* channels (VrefInt, temperature sensor, ...).
* @note One or several values can be selected.
diff --git a/Inc/stm32g4xx_ll_fmac.h b/Inc/stm32g4xx_ll_fmac.h
index b3f3371..5d860c8 100644
--- a/Inc/stm32g4xx_ll_fmac.h
+++ b/Inc/stm32g4xx_ll_fmac.h
@@ -38,20 +38,6 @@
* @{
*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup FMAC_LL_Private_Macros FMAC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -63,11 +49,11 @@
* @brief Flag defines which can be used with LL_FMAC_ReadReg function
* @{
*/
-#define LL_FMAC_SR_SAT FMAC_SR_SAT
-#define LL_FMAC_SR_UNFL FMAC_SR_UNFL
-#define LL_FMAC_SR_OVFL FMAC_SR_OVFL
-#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL
-#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY
+#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
+#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
+#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
+#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
+#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
/**
* @}
*/
@@ -76,11 +62,11 @@
* @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
* @{
*/
-#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN
-#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN
-#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN
-#define LL_FMAC_CR_WIEN FMAC_CR_WIEN
-#define LL_FMAC_CR_RIEN FMAC_CR_RIEN
+#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
+#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
+#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
+#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
+#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
/**
* @}
*/
@@ -89,10 +75,10 @@
* @brief Watermark defines that can be used for buffer full (input) or buffer empty (output)
* @{
*/
-#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000UL /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
-#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000UL /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
-#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000UL /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
-#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000UL /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
+#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
+#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
+#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
+#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
/**
* @}
*/
@@ -100,11 +86,20 @@
/** @defgroup FMAC_LL_EC_FUNC FMAC functions
* @{
*/
-#define LL_FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
-#define LL_FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
-#define LL_FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
-#define LL_FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
-#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
+#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
+#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
+#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
+#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
+#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing
+ * @{
+ */
+#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */
+#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */
/**
* @}
*/
@@ -113,7 +108,8 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* External variables --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
* @{
*/
@@ -177,7 +173,7 @@
* @brief Return X1 full watermark.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark
* @param FMACx FMAC instance
- * @retval Returned value can be one of the following values:
+ * @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
@@ -192,7 +188,8 @@
* @brief Configure X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize
* @param FMACx FMAC instance
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -204,7 +201,7 @@
* @brief Return X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
* @param FMACx FMAC instance
- * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @retval uint8_t Number of 16-bit words allocated to the input buffer (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
{
@@ -215,7 +212,8 @@
* @brief Configure X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+ * @param Base Base address of the input buffer (X1) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -227,7 +225,7 @@
* @brief Return X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+ * @retval uint8_t Base address of the input buffer (X1) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
{
@@ -238,7 +236,8 @@
* @brief Configure X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize
* @param FMACx FMAC instance
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -250,7 +249,7 @@
* @brief Return X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
* @param FMACx FMAC instance
- * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
{
@@ -261,7 +260,8 @@
* @brief Configure X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+ * @param Base Base address of the coefficient buffer (X2) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -273,7 +273,7 @@
* @brief Return X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+ * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
{
@@ -300,7 +300,7 @@
* @brief Return Y empty watermark.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark
* @param FMACx FMAC instance
- * @retval Returned value can be one of the following values:
+ * @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
@@ -315,7 +315,8 @@
* @brief Configure Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize
* @param FMACx FMAC instance
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -327,7 +328,7 @@
* @brief Return Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
* @param FMACx FMAC instance
- * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @retval uint8_t Number of 16-bit words allocated to the output buffer (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
{
@@ -338,7 +339,8 @@
* @brief Configure Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+ * @param Base Base address of the output buffer (Y) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -350,7 +352,7 @@
* @brief Return Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+ * @retval uint8_t Base address of the output buffer (Y) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
{
@@ -383,7 +385,7 @@
* @brief Check the state of FMAC processing.
* @rmtoll PARAM START LL_FMAC_IsEnabledStart
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
{
@@ -411,7 +413,7 @@
* @brief Return function.
* @rmtoll PARAM FUNC LL_FMAC_GetFunction
* @param FMACx FMAC instance
- * @retval Returned value can be one of the following values:
+ * @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
@@ -427,7 +429,8 @@
* @brief Configure input parameter R.
* @rmtoll PARAM R LL_FMAC_SetParamR
* @param FMACx FMAC instance
- * @param Param 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @param Param Parameter R (gain, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
@@ -439,7 +442,7 @@
* @brief Return input parameter R.
* @rmtoll PARAM R LL_FMAC_GetParamR
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
{
@@ -450,7 +453,8 @@
* @brief Configure input parameter Q.
* @rmtoll PARAM Q LL_FMAC_SetParamQ
* @param FMACx FMAC instance
- * @param Param 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+ * @param Param Parameter Q (vector length, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
@@ -462,7 +466,7 @@
* @brief Return input parameter Q.
* @rmtoll PARAM Q LL_FMAC_GetParamQ
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+ * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
{
@@ -473,23 +477,24 @@
* @brief Configure input parameter P.
* @rmtoll PARAM P LL_FMAC_SetParamP
* @param FMACx FMAC instance
- * @param Param 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+ * @param Param Parameter P (vector length, number of filter taps, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
{
- MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param) << FMAC_PARAM_P_Pos);
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param));
}
/**
* @brief Return input parameter P.
* @rmtoll PARAM P LL_FMAC_GetParamP
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+ * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
{
- return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P) >> FMAC_PARAM_P_Pos);
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
}
/**
@@ -512,21 +517,10 @@
}
/**
- * @brief Interrupt the FMAC reset.
- * @rmtoll CR RESET LL_FMAC_DisableReset
- * @param FMACx FMAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_FMAC_DisableReset(FMAC_TypeDef *FMACx)
-{
- CLEAR_BIT(FMACx->CR, FMAC_CR_RESET);
-}
-
-/**
* @brief Check the state of the FMAC reset.
* @rmtoll CR RESET LL_FMAC_IsEnabledReset
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
{
@@ -567,7 +561,7 @@
* @brief Check Clipping State.
* @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
{
@@ -608,7 +602,7 @@
* @brief Check FMAC DMA write channel request state.
* @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
@@ -641,7 +635,7 @@
* @brief Check FMAC DMA read channel request state.
* @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
{
@@ -682,7 +676,7 @@
* @brief Check FMAC saturation error interrupt state.
* @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
{
@@ -715,7 +709,7 @@
* @brief Check FMAC underflow error interrupt state.
* @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
{
@@ -748,7 +742,7 @@
* @brief Check FMAC overflow error interrupt state.
* @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
{
@@ -781,7 +775,7 @@
* @brief Check FMAC write interrupt state.
* @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
{
@@ -814,7 +808,7 @@
* @brief Check FMAC read interrupt state.
* @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
{
@@ -833,7 +827,7 @@
* @brief Check FMAC saturation error flag state.
* @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
{
@@ -844,7 +838,7 @@
* @brief Check FMAC underflow error flag state.
* @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
{
@@ -855,7 +849,7 @@
* @brief Check FMAC overflow error flag state.
* @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
{
@@ -866,7 +860,7 @@
* @brief Check FMAC X1 buffer full flag state.
* @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
{
@@ -877,7 +871,7 @@
* @brief Check FMAC Y buffer empty flag state.
* @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
{
@@ -896,7 +890,8 @@
* @brief Write 16-bit input data for the FMAC processing.
* @rmtoll WDATA WDATA LL_FMAC_WriteData
* @param FMACx FMAC instance
- * @param InData 0x0000 .. 0xFFFF: 16-bit value to be provided as input data for FMAC processing.
+ * @param InData 16-bit value to be provided as input data for FMAC processing.
+ * This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
@@ -908,7 +903,7 @@
* @brief Return 16-bit output data of FMAC processing.
* @rmtoll RDATA RDATA LL_FMAC_ReadData
* @param FMACx FMAC instance
- * @retval 0x0000 .. 0xFFFF: 16-bit output data of FMAC processing.
+ * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
*/
__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
{
@@ -934,8 +929,10 @@
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
- * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @param Base Base address of the input buffer (X1) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
@@ -949,8 +946,10 @@
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n
* X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @param Base Base address of the coefficient buffer (X2) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
@@ -970,8 +969,10 @@
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
- * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @param Base Base address of the output buffer (Y) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
@@ -988,16 +989,21 @@
* PARAM Q LL_FMAC_ConfigFunc\n
* PARAM R LL_FMAC_ConfigFunc
* @param FMACx FMAC instance
- * @param Start 0x00 .. 0x01: Enable or disable FMAC processing.
+ * @param Start This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_PROCESSING_STOP
+ * @arg @ref LL_FMAC_PROCESSING_START
* @param Function This parameter can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
- * @param ParamP 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
- * @param ParamQ 0x00 .. 0xFF: Parameter Q (vector length, etc.).
- * @param ParamR 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @param ParamP Parameter P (vector length, number of filter taps, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param ParamQ Parameter Q (vector length, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param ParamR Parameter R (gain, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
diff --git a/Inc/stm32g4xx_ll_hrtim.h b/Inc/stm32g4xx_ll_hrtim.h
index 9865f1e..94c135f 100644
--- a/Inc/stm32g4xx_ll_hrtim.h
+++ b/Inc/stm32g4xx_ll_hrtim.h
@@ -1248,7 +1248,7 @@
#define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
#define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
#define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
- | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
+ | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
/**
* @}
*/
@@ -1379,9 +1379,8 @@
#define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
#define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
-
/* Timer Events mapping for Timer A */
-#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its ictive state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
@@ -8038,7 +8037,7 @@
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
- * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+ * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
@@ -8544,7 +8543,7 @@
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
- * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+ * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
diff --git a/Inc/stm32g4xx_ll_lptim.h b/Inc/stm32g4xx_ll_lptim.h
index 7874903..f669da6 100644
--- a/Inc/stm32g4xx_ll_lptim.h
+++ b/Inc/stm32g4xx_ll_lptim.h
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of LPTIM LL module.
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -301,7 +301,6 @@
* @}
*/
-
/**
* @}
*/
@@ -383,7 +382,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@@ -436,7 +435,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
/**
@@ -487,7 +486,7 @@
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
* @note After a write to the LPTIMx_ARR register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the ARROK flag be set, will
+ * is completed. Any successive write before the ARROK flag is set, will
* lead to unpredictable results.
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
@@ -515,7 +514,7 @@
* @brief Set the compare value
* @note After a write to the LPTIMx_CMP register a new write operation to the
* same register can only be performed when the previous write operation
- * is completed. Any successive write before the CMPOK flag be set, will
+ * is completed. Any successive write before the CMPOK flag is set, will
* lead to unpredictable results.
* @rmtoll CMP CMP LL_LPTIM_SetCompare
* @param LPTIMx Low-Power Timer instance
@@ -703,7 +702,7 @@
/**
* @brief Set LPTIM input 1 source (default GPIO).
- * @rmtoll OR IN1 LL_LPTIM_SetInput1Src
+ * @rmtoll OR IN1 LL_LPTIM_SetInput1Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
@@ -716,12 +715,12 @@
*/
__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
- WRITE_REG(LPTIMx->OR, Src);
+ MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN1, Src);
}
/**
* @brief Set LPTIM input 2 source (default GPIO).
- * @rmtoll OR IN2 LL_LPTIM_SetInput2Src
+ * @rmtoll OR IN2 LL_LPTIM_SetInput2Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
@@ -733,7 +732,7 @@
*/
__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
- WRITE_REG(LPTIMx->OR, Src);
+ MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN2, Src);
}
/**
@@ -783,7 +782,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@@ -1061,7 +1060,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@@ -1091,7 +1090,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@@ -1106,14 +1105,14 @@
}
/**
- * @brief Inform application whether a autoreload match interrupt has occured.
+ * @brief Inform application whether a autoreload match interrupt has occurred.
* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@@ -1135,7 +1134,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@@ -1157,7 +1156,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@@ -1179,7 +1178,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@@ -1201,7 +1200,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@@ -1223,7 +1222,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@@ -1264,7 +1263,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@@ -1297,7 +1296,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@@ -1330,7 +1329,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@@ -1363,7 +1362,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@@ -1392,11 +1391,11 @@
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@@ -1425,11 +1424,11 @@
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@@ -1458,11 +1457,11 @@
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
diff --git a/Inc/stm32g4xx_ll_pwr.h b/Inc/stm32g4xx_ll_pwr.h
index 5133b0c..1b246cf 100644
--- a/Inc/stm32g4xx_ll_pwr.h
+++ b/Inc/stm32g4xx_ll_pwr.h
@@ -470,50 +470,48 @@
#if defined(PWR_CR3_UCPD_DBDIS)
/**
- * @brief Enable (write 0) USB Type-C dead battery pull-down behavior
- * on UCPD1_CC1 and UCPD1_CC2 pins.
- * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
- * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
- * in all cases, either to stop this pull-down or to hand over control to the UCPD1
- * (which should therefore be initialized before doing the disable).
- * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_EnableUSBDeadBattery
+ * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
+ * on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+ * to disable it in all cases, either to stop this pull-down or to hand over
+ * control to the UCPD (which should therefore be initialized before doing the disable).
+ * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
* @retval None
*/
-__STATIC_INLINE void LL_PWR_EnableUSBDeadBattery(void)
+__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
}
/**
- * @brief Disable (write 1) USB Type-C dead battery pull-down behavior
- * on UCPD1_CC1 and UCPD1_CC2 pins.
- * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
- * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
- * in all cases, either to stop this pull-down or to hand over control to the UCPD1
- * (which should therefore be initialized before doing the disable).
- * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_DisableUSBDeadBattery
+ * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
+ * on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+ * to disable it in all cases, either to stop this pull-down or to hand over
+ * control to the UCPD (which should therefore be initialized before doing the disable).
+ * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
* @retval None
*/
-__STATIC_INLINE void LL_PWR_DisableUSBDeadBattery(void)
+__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
{
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
}
/**
- * @brief Check USB Type-C dead battery pull-down behavior
- * on UCPD1_CC1 and UCPD1_CC2 pins.
- * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
- * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
- * in all cases, either to stop this pull-down or to hand over control to the UCPD1
- * (which should therefore be initialized before doing the disable).
- * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_IsEnabledUSBDeadBattery
- * @retval State of bit.
+ * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
+ * on UCPD CC1 and CC2 pins.
+ * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
+ * to disable it in all cases, either to stop this pull-down or to hand over
+ * control to the UCPD (which should therefore be initialized before doing the disable).
+ * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
+ * @retval State of feature (1 : enabled; 0 : disabled).
*/
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBDeadBattery(void)
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
{
-
- return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS))?1UL:0UL);
-
+ return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
}
#endif /* PWR_CR3_UCPD_DBDIS */
@@ -753,28 +751,6 @@
return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
}
-#if defined (PWR_CR3_UCPD_DBDIS)
-/**
- * @brief Enable USB Type-C and Power Delivery Dead Battery disable
- * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableDeadBatteryPD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableDeadBatteryPD(void)
-{
- SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
-}
-
-/**
- * @brief Disable USB Type-C and Power Delivery Dead Battery disable
- * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableDeadBatteryPD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableDeadBatteryPD(void)
-{
- CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
-}
-#endif /* PWR_CR3_UCPD_DBDIS */
-
#if defined(PWR_CR3_UCPD_STDBY)
/**
* @brief Enable USB Type-C and Power Delivery standby mode.
@@ -1613,6 +1589,12 @@
/* Old functions name kept for legacy purpose, to be replaced by the */
/* current functions name. */
#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
+#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
+#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
+#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
+#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
+#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_rtc.h b/Inc/stm32g4xx_ll_rtc.h
index 3a52e9b..b8ce443 100644
--- a/Inc/stm32g4xx_ll_rtc.h
+++ b/Inc/stm32g4xx_ll_rtc.h
@@ -3180,15 +3180,14 @@
*/
__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
- register uint32_t tmp = 0U;
+ register __IO uint32_t *tmp;
UNUSED(RTCx);
- tmp = (uint32_t)(&(TAMP->BKP0R));
- tmp += (BackupRegister * 4U);
+ tmp = &(TAMP->BKP0R) + BackupRegister;
/* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
+ *tmp = Data;
}
/**
@@ -3205,15 +3204,14 @@
*/
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
- register uint32_t tmp = 0U;
+ const register __IO uint32_t *tmp;
UNUSED(RTCx);
- tmp = (uint32_t)(&(TAMP->BKP0R));
- tmp += (BackupRegister * 4U);
+ tmp = &(TAMP->BKP0R) + BackupRegister;
/* Read the specified register */
- return (*(__IO uint32_t *)tmp);
+ return *tmp;
}
/**
diff --git a/Inc/stm32g4xx_ll_spi.h b/Inc/stm32g4xx_ll_spi.h
index 159aba1..3163b20 100644
--- a/Inc/stm32g4xx_ll_spi.h
+++ b/Inc/stm32g4xx_ll_spi.h
@@ -1314,7 +1314,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
- return (uint32_t) &(SPIx->DR);
+ return (uint32_t) & (SPIx->DR);
}
/**
diff --git a/Inc/stm32g4xx_ll_system.h b/Inc/stm32g4xx_ll_system.h
index 2f3202c..0178140 100644
--- a/Inc/stm32g4xx_ll_system.h
+++ b/Inc/stm32g4xx_ll_system.h
@@ -305,7 +305,7 @@
*/
#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
-#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.8V) */
+#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_tim.h b/Inc/stm32g4xx_ll_tim.h
index 89b84cd..17e395c 100644
--- a/Inc/stm32g4xx_ll_tim.h
+++ b/Inc/stm32g4xx_ll_tim.h
@@ -126,48 +126,9 @@
#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
/* Generic bit definitions for TIMx_AF1 register */
-#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */
-#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */
-#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */
-#define TIMx_AF1_BKCOMP3E TIM1_AF1_BKCMP3E /*!< BRK COMP3 enable */
-#define TIMx_AF1_BKCOMP4E TIM1_AF1_BKCMP4E /*!< BRK COMP4 enable */
-#if defined(COMP5)
-#define TIMx_AF1_BKCOMP5E TIM1_AF1_BKCMP5E /*!< BRK COMP5 enable */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIMx_AF1_BKCOMP6E TIM1_AF1_BKCMP6E /*!< BRK COMP6 enable */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIMx_AF1_BKCOMP7E TIM1_AF1_BKCMP7E /*!< BRK COMP7 enable */
-#endif /* COMP7 */
#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
-#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */
-#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */
-#define TIMx_AF1_BKCOMP3P TIM1_AF1_BKCMP3P /*!< BRK COMP3 input polarity */
-#define TIMx_AF1_BKCOMP4P TIM1_AF1_BKCMP4P /*!< BRK COMP4 input polarity */
#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
-/* Generic bit definitions for TIMx_AF2 register */
-#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */
-#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */
-#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */
-#define TIMx_AF2_BK2COMP3E TIM1_AF2_BK2CMP3E /*!< BRK2 COMP3 enable */
-#define TIMx_AF2_BK2COMP4E TIM1_AF2_BK2CMP4E /*!< BRK2 COMP4 enable */
-#if defined(COMP5)
-#define TIMx_AF2_BK2COMP5E TIM1_AF2_BK2CMP5E /*!< BRK2 COMP5 enable */
-#endif /* COMP5 */
-#if defined(COMP6)
-#define TIMx_AF2_BK2COMP6E TIM1_AF2_BK2CMP6E /*!< BRK2 COMP6 enable */
-#endif /* COMP6 */
-#if defined(COMP7)
-#define TIMx_AF2_BK2COMP7E TIM1_AF2_BK2CMP7E /*!< BRK2 COMP7 enable */
-#endif /* COMP7 */
-#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */
-#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */
-#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */
-#define TIMx_AF2_BK2COMP3P TIM1_AF2_BK2CMP3P /*!< BRK2 COMP3 input polarity */
-#define TIMx_AF2_BK2COMP4P TIM1_AF2_BK2CMP4P /*!< BRK2 COMP4 input polarity */
-
/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
#define DT_DELAY_1 ((uint8_t)0x7F)
@@ -273,13 +234,14 @@
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@@ -2318,7 +2280,7 @@
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
@@ -2363,6 +2325,16 @@
}
/**
+ * @brief Indicate whether update interrupt flag (UIF) copy is set.
+ * @param Counter Counter value
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+{
+ return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
* @brief Enable dithering.
* @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
diff --git a/Inc/stm32g4xx_ll_ucpd.h b/Inc/stm32g4xx_ll_ucpd.h
index dfeddc2..c96ee99 100644
--- a/Inc/stm32g4xx_ll_ucpd.h
+++ b/Inc/stm32g4xx_ll_ucpd.h
@@ -126,8 +126,7 @@
#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
-#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGEND /*!< Enable Rx message received */
-#define LL_UCPD_IMR_RXERR UCPD_IMR_RXMSGENDIE /*!< Enable Rx error */
+#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE /*!< Enable Rx message received */
#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
diff --git a/Inc/stm32g4xx_ll_usart.h b/Inc/stm32g4xx_ll_usart.h
index 4f1af73..b7d85d9 100644
--- a/Inc/stm32g4xx_ll_usart.h
+++ b/Inc/stm32g4xx_ll_usart.h
@@ -2651,7 +2651,8 @@
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
@@ -2687,7 +2688,8 @@
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
@@ -2727,7 +2729,8 @@
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
@@ -2765,7 +2768,8 @@
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
+ - SCEN and IREN bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
@@ -2805,7 +2809,8 @@
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
+ - IREN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
@@ -2848,7 +2853,8 @@
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
+ - SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
@@ -2886,7 +2892,8 @@
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
diff --git a/Inc/stm32g4xx_ll_utils.h b/Inc/stm32g4xx_ll_utils.h
index f8cd1b9..5543fce 100644
--- a/Inc/stm32g4xx_ll_utils.h
+++ b/Inc/stm32g4xx_ll_utils.h
@@ -288,6 +288,7 @@
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
diff --git a/Inc/stm32g4xx_ll_wwdg.h b/Inc/stm32g4xx_ll_wwdg.h
index 11966b8..6e31436 100644
--- a/Inc/stm32g4xx_ll_wwdg.h
+++ b/Inc/stm32g4xx_ll_wwdg.h
@@ -326,6 +326,6 @@
}
#endif
-#endif /* __STM32G4xx_LL_WWDG_H */
+#endif /* STM32G4xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/README.md b/README.md
index f21006a..80e9b21 100644
--- a/README.md
+++ b/README.md
@@ -36,6 +36,9 @@
------------- | --------------- | ---------- | -------------------------------------
Tag v1.0.0 | Tag v1.0.0 | Tag v5.4.0_cm4 | Tag v1.0.0 (and following, if any, till next new tag)
Tag v1.1.0 | Tag v1.1.0 | Tag v5.4.0_cm4 | Tag v1.1.0 (and following, if any, till next new tag)
+Tag v1.1.1 | Tag v1.1.1 | Tag v5.4.0_cm4 | Tag v1.2.0 (and following, if any, till next new tag)
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32g4xx_hal_driver/blob/master/Release_Notes.html).
The full **STM32CubeG4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG4).
diff --git a/Release_Notes.html b/Release_Notes.html
index ca18495..8250d70 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -5,7 +5,7 @@
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for STM32G4xx HAL Drivers</title>
- <style type="text/css">
+ <style>
code{white-space: pre-wrap;}
span.smallcaps{font-variant: small-caps;}
span.underline{text-decoration: underline;}
@@ -46,10 +46,217 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.1.0 / 28-June-2019</label>
+<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.1 / 14-February-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance Release</h3>
+<ul>
+<li><p>General updates to fix known defects and enhancements implementation</p></li>
+<li><p><strong>HAL/LL CRYP</strong> update</p>
+<ul>
+<li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.1_R6, 10.3, 10.4_a, 10.6, 12.1, 13.5 15.7</li>
+<li>Perform a new check mechanism on the cryp buffer size in Encryption et Decryption API
+<ul>
+<li>Add IS_CRYP_BUFFERSIZE() macro</li>
+</ul></li>
+<li>Clean up the HAL_CRYP_Resume() API to avoid infinite loop due to an early interruption during resumption process
+<ul>
+<li>Remove __HAL_CRYP_ENABLE_IT() and __HAL_CRYP_ENABLE() API .</li>
+</ul></li>
+<li>Add new parameter in the CRYP_HandleTypeDef structure
+<ul>
+<li>Add SizesSum_saved to save the SizesSum when processing is suspended</li>
+<li>Update the HAL_CRYP_Suspend() and HAL_CRYP_Resume() API by adding this new parameter</li>
+</ul></li>
+<li>Add missing interruptions re-enabling operations following an all flags clear-up in the CRYP_PhaseProcessingResume() API</li>
+<li>Support AAD with all possible byte sizes, not only multiple of 4 bytes
+<ul>
+<li>Update CRYP_GCMCCM_SetHeaderPhase() API</li>
+<li>Add new parameter HeaderWidthUnit in the CRYP_ConfigTypeDef structure which contains the Cryp Header Width Unit</li>
+<li>Add new definition of the CRYP Header size Unit
+<ul>
+<li>CRYP_HEADERWIDTHUNIT_WORD</li>
+<li>CRYP_HEADERWIDTHUNIT_BYTE</li>
+</ul></li>
+</ul></li>
+<li>Support data encryption and decryption with length not only multiple of 16 bytes
+<ul>
+<li>Update IS_CRYP_BUFFERSIZE() macro</li>
+<li>Update AES functions : CRYP_AES_ProcessData() / CRYP_AES_IT() / CRYP_AESCCM_Process() / CRYP_AESGCM_Process_DMA()</li>
+<li>Update CRYP_GCMCCM_SetPayloadPhase_IT() API</li>
+</ul></li>
+</ul></li>
+<li><p><strong>HAL/LL FMAC</strong> update</p>
+<ul>
+<li>General updates to comply to internal coding rules.</li>
+</ul></li>
+<li><p><strong>HAL GPIO</strong> update</p>
+<ul>
+<li>Update the GPIO initialization sequence in HAL_GPIO_Init() API to avoid unwanted glitches on GPIO pins.</li>
+<li>Add missing GPIO Alternate Function definitions:
+<ul>
+<li>GPIO_AF2_TIM16, GPIO_AF9_TIM8, GPIO_AF11_TIM8, GPIO_AF12_TIM1.</li>
+</ul></li>
+</ul></li>
+<li><p><strong>HAL HRTIM</strong> update</p>
+<ul>
+<li>Update HAL_HRTIM_WaveformCompareConfig() to clear HRTIM_TIMxCR.DELCMP bitfield when the auto-delayed protection mode is disabled.</li>
+<li>Correct some “HRTIM_OUTPUTSET_TIMxx” constant names which are not compliant with Timer Events Mapping specified in the reference manual
+<ul>
+<li>Remove HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1, HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 , HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 and HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2</li>
+<li>Add HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 and HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 , HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 and HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2</li>
+<li>Update HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 and HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 definitions</li>
+</ul></li>
+<li>Update HAL_HRTIM_DLLCalibrationStart() and HAL_HRTIM_DLLCalibrationStart_IT() API by setting HRTIM state ready to avoid some unstable behavior of the TIMER E.</li>
+<li>Add new check field in the IS_HRTIM_EVENTSRC() macro to check also on EVENT</li>
+<li>Add a new check in the HAL_HRTIM_EventConfig() API on event and event source thru the IS_HRTIM_EVENTSRC() macro</li>
+<li>Remove UPDGAT bits reset from the HRTIM_TimingUnitWaveform_Control() API</li>
+<li>Add a lock and unlock handle process in the HAL_HRTIM_SimpleOCChannelConfig() API</li>
+</ul></li>
+<li><p><strong>HAL I2C</strong> update</p>
+<ul>
+<li>Update HAL I2C processes to report ErrorCode when wrong I2C start conditionoccurs
+<ul>
+<li>Add new ErrorCode define: HAL_I2C_WRONG_START</li>
+<li>Set ErrorCode parameter in I2C handle to HAL_I2C_WRONG_START</li>
+</ul></li>
+<li>Update I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).
+<ul>
+<li>Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks</li>
+</ul></li>
+<li>Fix HAL I2C slave interrupt handling issue with I2C sequential transfers.
+<ul>
+<li>Update I2C_Slave_ISR_IT() and I2C_Slave_ISR_DMA() APIs to check on STOP condition and handle it before clearing the ADDR flag</li>
+</ul></li>
+</ul></li>
+<li><p><strong>HAL LPTIM</strong> update</p>
+<ul>
+<li>Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API
+<ul>
+<li>Add LPTIM_WaitForFlag() API to wait for flag set.</li>
+<li>Perform new checks on HAL_LPTIM_STATE_TIMEOUT.</li>
+</ul></li>
+<li>Apply digital filter for external clock for all LPTIM clock source.
+<ul>
+<li>Update HAL_LPTIM_Init() API</li>
+</ul></li>
+<li>Correct the input1source and input2source selection
+<ul>
+<li>Update LL_LPTIM_SetInput1Src and LL_LPTIM_SetInput2Src
+<ul>
+<li>Remove WRITE_REG and replace it by MODIFY_REG</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><p><strong>HAL/LL RTC</strong> update</p>
+<ul>
+<li>Update API HAL_RTC_SetAlarm_IT() to allow changing alarm time “on the fly” simply by calling the API again.</li>
+<li>Update API LL_RTC_BKP_SetRegister() and API LL_RTC_BKP_GetRegister() to comply to rules 2.2 and 13.2 of MISRAC-2012.</li>
+</ul></li>
+<li><p><strong>HAL SPI</strong> update</p>
+<ul>
+<li>Update the “Rx DMA transfer complete callback” to disable the Tx DMA request only in case of full-duplex mode and not it in half-duplex mode.</li>
+</ul></li>
+<li><p><strong>HAL TIM</strong> update</p>
+<ul>
+<li>Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
+<ul>
+<li>Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.</li>
+<li>Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.</li>
+<li>Update HAL_TIM_Encoder_Init() API
+<ul>
+<li>Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.</li>
+</ul></li>
+</ul></li>
+<li>Provide new API to set and clear UIFREMAP
+<ul>
+<li>Add new definition for TIM Update Interrupt Flag Remap
+<ul>
+<li>TIM_UIFREMAP_DISABLE</li>
+<li>TIM_UIFREMAP_ENABLE</li>
+</ul></li>
+<li>Add new macro in HAL driver to enable and desable the Update Interrupt Flag Remap
+<ul>
+<li>__HAL_TIM_UIFREMAP_ENABLE()</li>
+<li>__HAL_TIM_UIFREMAP_DISABLE()/__HAL_TIM_GET_UIFCPY macro</li>
+</ul></li>
+<li>Add new mecanism to check whether the update interrupt flag (UIF) copy is set or not
+<ul>
+<li>Add the __HAL_TIM_GET_UIFCPY() macro in the HAL driver</li>
+<li>Add LL_TIM_IsActiveUIFCPY() API in the LL driver</li>
+</ul></li>
+<li>Add new macro to check on the Update Interrupt Flag Remap mode
+<ul>
+<li>IS_TIM_UIFREMAP_MODE()</li>
+</ul></li>
+</ul></li>
+<li>Remove useless TIM trigger selector</li>
+<li>Fix bug when using multiple DMA request to different channels of same timer
+<ul>
+<li>Introduce DMA burst state managment mechanism
+<ul>
+<li>Add a new stucture for DMA Burst States definition : HAL_TIM_DMABurstStateTypeDef</li>
+<li>Update __HAL_TIM_RESET_HANDLE_STATE to support DMABurstState</li>
+<li>Add a new API HAL_TIM_DMABurstState() to get the actual state of a DMA burst operation</li>
+<li>Add DMABurstState, the DMA burst operation state, in the TIM_HandleTypeDef structure</li>
+<li>Add new API TIM_DMAErrorCCxN() for TIM DMA error callback (complementary channel)</li>
+<li>Add new API TIM_DMADelayPulseNCplt() for TIM DMA Delay Pulse complete callback (complementary channel)</li>
+</ul></li>
+</ul></li>
+<li>Implement TIM channel state managment mechanism
+<ul>
+<li>Add new macro
+<ul>
+<li>TIM_CHANNEL_STATE_SET_ALL and TIM_CHANNEL_N_STATE_SET_ALL</li>
+<li>TIM_CHANNEL_STATE_SET and TIM_CHANNEL_N_STATE_SET</li>
+<li>TIM_CHANNEL_STATE_GET and TIM_CHANNEL_N_STATE_GET</li>
+</ul></li>
+<li>Add new API HAL_TIM_GetActiveChannel()</li>
+<li>Add new API HAL_TIM_GetChannelState() to get actual state of the TIM channel</li>
+<li>Add a new stucture for TIM channel States definition : HAL_TIM_ChannelStateTypeDef</li>
+<li>Update __HAL_TIM_RESET_HANDLE_STATE to support ChannelState and ChannelNState</li>
+<li>Add a new element in the TIM_HandleTypeDef structure : ChannelState to manage TIM channel operation stat.</li>
+<li>Add a new element in the TIM_HandleTypeDef structure : ChannelNState to manage TIM complementary channel operation state</li>
+</ul></li>
+</ul></li>
+<li><p><strong>HAL/LL USART</strong> update</p>
+<ul>
+<li>Add support to the Receiver Timeout Interrupt in the HAL_USART_IRQHandler</li>
+<li>Fix wrong value for SlaveMode field in USART handle after HAL_USARTEx_DisableSlaveMode() call
+<ul>
+<li>Set USART_SLAVEMODE_DISABLE instead of USART_SLAVEMODE_ENABLE</li>
+</ul></li>
+</ul></li>
+<li><p><strong>HAL USB</strong> update</p>
+<ul>
+<li>Improve USB endpoint out re-enabling with double-buffer mode.</li>
+</ul></li>
+<li><p><strong>LL UTILS</strong> update</p>
+<ul>
+<li>API UTILS_SetFlashLatency() renamed LL_SetFlashLatency() and set exportable.</li>
+<li>API LL_PLL_ConfigSystemClock_HSI() and API LL_PLL_ConfigSystemClock_HSE() updated to set back the AHB prescaler to 1 after it has been temporarily set to 2 to avoid undershoot when configuring PLL at high frequencies.</li>
+</ul></li>
+</ul>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
+<li>System Workbench STM32 (SW4STM32) toolchain V2.9.0</li>
+</ul>
+<h2 id="supported-devices">Supported Devices</h2>
+<ul>
+<li>STM32G431/41xx</li>
+<li>STM32G471xx</li>
+<li>STM32G473/<strong>83xx</strong></li>
+<li>STM32G474/84xx</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-1">Maintenance Release</h3>
<p>Maintenance release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
<h2 id="contents">Contents</h2>
<table>
@@ -132,13 +339,13 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices">Supported Devices</h2>
+<h2 id="supported-devices-1">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -150,16 +357,16 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 12-April-2019</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-1">Supported Devices</h2>
+<h2 id="supported-devices-2">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
diff --git a/Src/stm32g4xx_hal.c b/Src/stm32g4xx_hal.c
index e8a8b2a..3fad0e0 100644
--- a/Src/stm32g4xx_hal.c
+++ b/Src/stm32g4xx_hal.c
@@ -49,11 +49,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32G4xx HAL Driver version number $VERSION$
+ * @brief STM32G4xx HAL Driver version number V1.1.1
*/
#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
-#define __STM32G4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32G4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
@@ -352,15 +352,25 @@
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
{
HAL_StatusTypeDef status = HAL_OK;
+ uint32_t prevTickFreq;
+
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
+ uwTickFreq = Freq;
+
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
- if (status == HAL_OK)
+
+ if (status != HAL_OK)
{
- uwTickFreq = Freq;
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
}
}
diff --git a/Src/stm32g4xx_hal_adc.c b/Src/stm32g4xx_hal_adc.c
index 191cfc8..868a6f3 100644
--- a/Src/stm32g4xx_hal_adc.c
+++ b/Src/stm32g4xx_hal_adc.c
@@ -325,9 +325,9 @@
#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
when no regular conversion is on-going */
-
+
/* Timeout values for ADC operations (enable settling time, */
/* disable settling time, ...). */
/* Values defined to be higher than worst cases: low clock frequency, */
diff --git a/Src/stm32g4xx_hal_cryp.c b/Src/stm32g4xx_hal_cryp.c
index 9eced79..b815b70 100644
--- a/Src/stm32g4xx_hal_cryp.c
+++ b/Src/stm32g4xx_hal_cryp.c
@@ -155,83 +155,24 @@
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
(#) structure of message construction in GCM is defined as below :
(##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
-
- ICB
- +-------------------------------------------------------+
- | Initialization vector (IV) | Counter |
- |----------------|----------------|-----------|---------|
- 127 95 63 31 0
-
-
- Bit Number Register Contents
- ---------- --------------- -----------
- 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
- 95 ...64 CRYP_IV1L[31:0] B0[95:64]
- 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
- 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
-
-
-
(##) The authenticated header A (also knows as Additional Authentication Data AAD)
this part of the message is only authenticated, not encrypted.
(##) The plaintext message P is both authenticated and encrypted as ciphertext.
GCM standard specifies that ciphertext has same bit length as the plaintext.
(##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
(on 64 bits)
- GCM last block definition
- +-------------------------------------------------------------------+
- | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
- |-----------|--------------------|-----------|----------------------|
- | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
- |-----------|--------------------|-----------|----------------------|
+
+ [..] A more detailed description of the GCM message structure is available below.
[..] This section describe The AES Counter with Cipher Block Chaining-Message
Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
(#) Specific parameters for CCM :
- (##) B0 block : According to NIST Special Publication 800-38C,
- The first block B0 is formatted as follows, where l(m) is encoded in
- most-significant-byte first order:
-
- Octet Number Contents
- ------------ ---------
- 0 Flags
- 1 ... 15-q Nonce N
- 16-q ... 15 Q
-
- the Flags field is formatted as follows:
-
- Bit Number Contents
- ---------- ----------------------
- 7 Reserved (always zero)
- 6 Adata
- 5 ... 3 (t-2)/2
- 2 ... 0 [q-1]3
-
- - Q: a bit string representation of the octet length of P (plaintext)
- - q The octet length of the binary representation of the octet length of the payload
- - A nonce (N), n The octet length of the where n+q=15.
- - Flags: most significant octet containing four flags for control information,
- - t The octet length of the MAC.
- (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
- the associated data length expressed in bytes (a) defined as below:
- - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
- - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
- - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
+ (##) B0 block : follows NIST Special Publication 800-38C,
+ (##) B1 block (header)
(##) CTRx block : control blocks
- - Generation of CTR1 from first block B0 information :
- equal to B0 with first 5 bits zeroed and most significant bits storing octet
- length of P also zeroed, then incremented by one
- Bit Number Register Contents
- ---------- --------------- -----------
- 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
- bit 0 that is set to 1
- 95 ...64 CRYP_IV1L[31:0] B0[95:64]
- 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
- 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
-
- - Generation of CTR0: same as CTR1 with bit[0] set to zero.
+ [..] A detailed description of the CCM message structure is available below.
(#) Four phases are performed in CCM for CRYP1 peripheral:
(##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
@@ -340,7 +281,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -981,11 +922,15 @@
*/
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
{
+ HAL_CRYP_STATETypeDef state;
+
/* Request suspension */
HAL_CRYP_ProcessSuspend(hcryp);
- while ((HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_SUSPENDED) && \
- (HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_READY));
+ do
+ {
+ state = HAL_CRYP_GetState(hcryp);
+ } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
{
@@ -1019,7 +964,8 @@
hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
hcryp->Phase_saved = hcryp->Phase;
hcryp->State_saved = hcryp->State;
- hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? hcryp->Size /4 : hcryp->Size);
+ hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size);
+ hcryp->SizesSum_saved = hcryp->SizesSum;
hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
@@ -1049,6 +995,12 @@
*/
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
{
+ /* Check the CRYP handle allocation */
+ if (hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
+
if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
{
/* CRYP was not suspended */
@@ -1075,16 +1027,14 @@
hcryp->Init.pInitVect = hcryp->IV_saved;
}
__HAL_CRYP_DISABLE(hcryp);
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void) HAL_CRYP_Init(hcryp);
}
else /* Authentication algorithms case */
{
/* Restore low-priority block CRYP handle parameters */
hcryp->Phase = hcryp->Phase_saved;
hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
+ hcryp->SizesSum = hcryp->SizesSum_saved;
/* Disable AES and write-back SUSPxR registers */;
__HAL_CRYP_DISABLE(hcryp);
@@ -1094,8 +1044,6 @@
hcryp->Instance->CR = hcryp->CR_saved;
CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
- __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- __HAL_CRYP_ENABLE(hcryp);
/* At the same time, set handle state back to READY to be able to resume the AES calculations
without the processing APIs returning HAL_BUSY when called. */
@@ -1157,6 +1105,81 @@
* @{
*/
+/* GCM message structure additional details
+
+ ICB
+ +-------------------------------------------------------+
+ | Initialization vector (IV) | Counter |
+ |----------------|----------------|-----------|---------|
+ 127 95 63 31 0
+
+
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
+
+
+
+ GCM last block definition
+ +-------------------------------------------------------------------+
+ | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
+ |-----------|--------------------|-----------|----------------------|
+ | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
+ |-----------|--------------------|-----------|----------------------|
+
+*/
+
+/* CCM message blocks description
+
+ (##) B0 block : According to NIST Special Publication 800-38C,
+ The first block B0 is formatted as follows, where l(m) is encoded in
+ most-significant-byte first order:
+
+ Octet Number Contents
+ ------------ ---------
+ 0 Flags
+ 1 ... 15-q Nonce N
+ 16-q ... 15 Q
+
+ the Flags field is formatted as follows:
+
+ Bit Number Contents
+ ---------- ----------------------
+ 7 Reserved (always zero)
+ 6 Adata
+ 5 ... 3 (t-2)/2
+ 2 ... 0 [q-1]3
+
+ - Q: a bit string representation of the octet length of P (plaintext)
+ - q The octet length of the binary representation of the octet length of the payload
+ - A nonce (N), n The octet length of the where n+q=15.
+ - Flags: most significant octet containing four flags for control information,
+ - t The octet length of the MAC.
+ (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
+ the associated data length expressed in bytes (a) defined as below:
+ - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
+ - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
+ - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
+ (##) CTRx block : control blocks
+ - Generation of CTR1 from first block B0 information :
+ equal to B0 with first 5 bits zeroed and most significant bits storing octet
+ length of P also zeroed, then incremented by one
+
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
+ bit 0 that is set to 1
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
+
+ - Generation of CTR0: same as CTR1 with bit[0] set to zero.
+
+*/
+
/**
* @brief Encryption mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
@@ -1171,6 +1194,12 @@
{
uint32_t algo;
HAL_StatusTypeDef status;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1265,6 +1294,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1358,6 +1393,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1374,8 +1415,8 @@
hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{
- hcryp->CrypInCount = hcryp->CrypInCount_saved;
- hcryp->CrypOutCount = hcryp->CrypOutCount_saved;
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
}
else
{
@@ -1462,6 +1503,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1478,8 +1525,8 @@
hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{
- hcryp->CrypInCount = hcryp->CrypInCount_saved;
- hcryp->CrypOutCount = hcryp->CrypOutCount_saved;
+ hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
+ hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
}
else
{
@@ -1566,6 +1613,12 @@
HAL_StatusTypeDef status;
uint32_t algo;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -1686,6 +1739,12 @@
{
HAL_StatusTypeDef status;
uint32_t algo;
+#ifdef USE_FULL_ASSERT
+ uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
+
+ /* Check input buffer size */
+ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
+#endif
if (hcryp->State == HAL_CRYP_STATE_READY)
{
@@ -2684,7 +2743,8 @@
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
@@ -2721,19 +2781,17 @@
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i= 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
}
/**
@@ -2746,24 +2804,23 @@
*/
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i= 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable Computation Complete flag and errors interrupts */
@@ -2900,7 +2957,7 @@
uint32_t tickstart;
uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
uint32_t npblb;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t index;
uint32_t lastwordsize;
uint32_t incount; /* Temporary CrypInCount Value */
@@ -3079,9 +3136,11 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
hcryp->CrypOutCount++;
}
}
@@ -3428,7 +3487,7 @@
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -3608,9 +3667,11 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
@@ -3641,7 +3702,7 @@
uint32_t loopcounter;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4] ; /* Temporary CrypOutBuff */
uint32_t incount; /* Temporary CrypInCount Value */
uint32_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
@@ -3813,9 +3874,11 @@
for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[loopcounter] = hcryp->Instance->DOUTR;
+ }
+ for (loopcounter = 0U; loopcounter<lastwordsize; loopcounter++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter];
hcryp->CrypOutCount++;
}
}
@@ -4138,7 +4201,7 @@
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -4317,9 +4380,11 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
@@ -4343,29 +4408,28 @@
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t i;
/***************************** Payload phase *******************************/
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i= 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size))
@@ -4491,10 +4555,21 @@
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t loopcounter;
+ uint32_t size_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
/***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ size_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ size_in_bytes = hcryp->Init.HeaderSize;
+ }
- if ((hcryp->Init.HeaderSize != 0U))
+ if ((size_in_bytes != 0U))
{
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
@@ -4502,10 +4577,11 @@
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
+ if ((size_in_bytes % 16U) == 0U)
{
- /* HeaderSize %4, no padding */
- for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ /* No padding */
+ for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -4536,8 +4612,8 @@
}
else
{
- /*Write header block in the IN FIFO without last block */
- for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ /* Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -4565,17 +4641,35 @@
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while (loopcounter < 4U)
+ /* If the header size is a multiple of words */
+ if ((size_in_bytes % 4U) == 0U)
{
- /*Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeroes */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[size_in_bytes % 4U];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
@@ -5006,7 +5100,7 @@
__IO uint32_t count = 0U;
/* In case of GCM payload phase encryption, check that suspension can be carried out */
- if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0))
+ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U))
{
/* Wait for BUSY flag to be cleared */
@@ -5144,21 +5238,21 @@
if (KeySize == CRYP_KEYSIZE_256B)
{
hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
}
hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr);
- keyaddr+=4;
+ keyaddr+=4U;
hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr);
}
@@ -5170,9 +5264,19 @@
*/
static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
{
- uint32_t loopcounter = 0U;
- uint32_t lastwordsize =0;
- uint32_t npblb = 0U ;
+ uint32_t loopcounter;
+ uint16_t lastwordsize;
+ uint16_t npblb;
+ uint32_t cr_temp;
+
+
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR | CRYP_CCF_CLEAR);
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
/* Case of header phase resumption =================================================*/
if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
@@ -5183,7 +5287,7 @@
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U))
+ if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
{
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
@@ -5212,73 +5316,77 @@
}
}
/* Case of payload phase resumption =================================================*/
- else if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
+ else
{
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- if ((hcryp->Size/4) - (hcryp->CrypInCount) >= 4U)
+ if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
{
- /* Write the input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
- hcryp->CrypInCount++;
- if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
- {
- /* Call output transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- else /* Last block of payload < 128bit*/
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = ((hcryp->Size/16U)+1U)*16U- (hcryp->Size);
- if((((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
- (((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb<< 20U);
- }
- /* Number of valid words (lastwordsize) in last block */
- if (npblb % 4U ==0U)
- {
- lastwordsize = (16U-npblb)/4U;
- }
- else
- {
- lastwordsize = (16U-npblb)/4U +1U;
- }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Last block optionally pad the data with zeros*/
- for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ {
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- while(loopcounter < 4U )
+ else /* Last block of payload < 128bit*/
{
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size);
+ cr_temp = hcryp->Instance->CR;
+ if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
+ (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
+
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
}
}
diff --git a/Src/stm32g4xx_hal_cryp_ex.c b/Src/stm32g4xx_hal_cryp_ex.c
index dde23a6..100d7b5 100644
--- a/Src/stm32g4xx_hal_cryp_ex.c
+++ b/Src/stm32g4xx_hal_cryp_ex.c
@@ -9,7 +9,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -99,10 +99,17 @@
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tickstart;
+ /* Assume first Init.HeaderSize is in words */
uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
- uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
+ uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
+ /* Correct headerlength if Init.HeaderSize is actually in bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
+ {
+ headerlength /= 4U;
+ }
+
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
diff --git a/Src/stm32g4xx_hal_fmac.c b/Src/stm32g4xx_hal_fmac.c
index f5816bb..988428a 100644
--- a/Src/stm32g4xx_hal_fmac.c
+++ b/Src/stm32g4xx_hal_fmac.c
@@ -9,7 +9,20 @@
* + Peripheral Control functions
* + Callback functions
* + IRQ handler management
- * + Peripheral State functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
*
* @verbatim
================================================================================
@@ -18,17 +31,18 @@
[..]
The FMAC HAL driver can be used as follows:
- (#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit():
- (++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE().
+ (#) Initialize the FMAC low level resources by implementing the @ref HAL_FMAC_MspInit():
+ (++) Enable the FMAC interface clock using @ref __HAL_RCC_FMAC_CLK_ENABLE().
(++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT):
- (+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority().
- (+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ().
- (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
+ (+++) Configure the FMAC interrupt priority using @ref HAL_NVIC_SetPriority().
+ (+++) Enable the FMAC IRQ handler using @ref HAL_NVIC_EnableIRQ().
+ (+++) In FMAC IRQ handler, call @ref HAL_FMAC_IRQHandler().
(++) In case of using DMA to control data transfer (e.g. access configured
as FMAC_BUFFER_ACCESS_DMA):
- (+++) Enable the DMA1 interface clock using __HAL_RCC_DMA1_CLK_ENABLE().
- (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
- (+++) If the initialisation of the internal buffers (coefficients, input,
+ (+++) Enable the DMA interface clock using @ref __HAL_RCC_DMA1_CLK_ENABLE()
+ or @ref __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
+ (+++) Enable the DMAMUX1 interface clock using @ref __HAL_RCC_DMAMUX1_CLK_ENABLE().
+ (+++) If the initialization of the internal buffers (coefficients, input,
output) is done via DMA, configure and enable one DMA channel for
managing data transfer from memory to memory (preload channel).
(+++) If the input buffer is accessed via DMA, configure and enable one
@@ -38,16 +52,16 @@
one DMA channel for managing data transfer from peripheral to
memory (output channel).
(+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s)
- using __HAL_LINKDMA().
+ using @ref __HAL_LINKDMA().
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority()
- and HAL_NVIC_EnableIRQ().
+ interrupt on the enabled DMA channel(s) using @ref HAL_NVIC_SetPriority()
+ and @ref HAL_NVIC_EnableIRQ().
- (#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function
- resorts to HAL_FMAC_MspInit() for low-level initialization.
+ (#) Initialize the FMAC HAL using @ref HAL_FMAC_Init(). This function
+ resorts to @ref HAL_FMAC_MspInit() for low-level initialization.
- (#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig()
- or HAL_FMAC_FilterConfig_DMA().
+ (#) Configure the FMAC processing (filter) using @ref HAL_FMAC_FilterConfig()
+ or @ref HAL_FMAC_FilterConfig_DMA().
This function:
(++) Defines the memory area within the FMAC internal memory
(input, coefficients, output) and the associated threshold (input, output).
@@ -60,61 +74,61 @@
(++) Enable the error interruptions in the input access and/or the output
access is done through IT/DMA. If an error occurs, the interruption
will be triggered in loop. In order to recover, the user will have
- to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
- Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
+ to reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init.
+ Optionally, he can also disable the interrupt using @ref __HAL_FMAC_DISABLE_IT;
the error status will be kept, but no more interrupt will be triggered.
(++) Write the provided coefficients into the internal memory using polling
- mode (HAL_FMAC_FilterConfig()) or DMA (HAL_FMAC_FilterConfig_DMA()).
- In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
+ mode ( @ref HAL_FMAC_FilterConfig() ) or DMA ( @ref HAL_FMAC_FilterConfig_DMA() ).
+ In the DMA case, @ref HAL_FMAC_FilterConfigCallback() is called when
the handling is over.
(#) Optionally, the user can enable the error interruption related to
- saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the
+ saturation by calling @ref __HAL_FMAC_ENABLE_IT. This helps in debugging the
filter. If a saturation occurs, the interruption will be triggered in loop.
In order to recover, the user will have to:
- (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
- he wishes to continue all the same.
- (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
+ (++) Disable the interruption by calling @ref __HAL_FMAC_DISABLE_IT if
+ the user wishes to continue all the same.
+ (++) Reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init.
(#) Optionally, preload input (FIR, IIR) and output (IIR) data using
- HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA().
- In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when
+ @ref HAL_FMAC_FilterPreload() or @ref HAL_FMAC_FilterPreload_DMA().
+ In the DMA case, @ref HAL_FMAC_FilterPreloadCallback() is called when
the handling is over.
This step is optional as the filter can be started without preloaded
data.
- (#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart().
+ (#) Start the FMAC processing (filter) using @ref HAL_FMAC_FilterStart().
This function also configures the output buffer that will be filled from
the circular internal output buffer. The function returns immediately
without updating the provided buffer. The IP processing will be active until
- HAL_FMAC_FilterStop() is called.
+ @ref HAL_FMAC_FilterStop() is called.
- (#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback()
+ (#) If the input internal buffer is accessed via DMA, @ref HAL_FMAC_HalfGetDataCallback()
will be called to indicate that half of the input buffer has been handled.
- (#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback()
+ (#) If the input internal buffer is accessed via DMA or interrupt, @ref HAL_FMAC_GetDataCallback()
will be called to require new input data. It will be provided through
- HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
+ @ref HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
- (#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback()
+ (#) If the output internal buffer is accessed via DMA, @ref HAL_FMAC_HalfOutputDataReadyCallback()
will be called to indicate that half of the output buffer has been handled.
(#) If the output internal buffer is accessed via DMA or interrupt,
- HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
- buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer()
+ @ref HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
+ buffer. It will be provided through @ref HAL_FMAC_ConfigFilterOutputBuffer()
if the DMA isn't in circular mode.
- (#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData().
+ (#) In all modes except none, provide new input data to be processed via @ref HAL_FMAC_AppendFilterData().
This function should only be called once the previous input data has been handled
(the preloaded input data isn't concerned).
(#) In all modes except none, provide a new output buffer to be filled via
- HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
+ @ref HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
user's output buffer has been filled.
- (#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData().
+ (#) In polling mode, handle the input and output data using @ref HAL_FMAC_PollFilterData().
This function:
- (++) Write the user's input data (provided via HAL_FMAC_AppendFilterData())
+ (++) Write the user's input data (provided via @ref HAL_FMAC_AppendFilterData())
into the FMAC input memory area.
(++) Read the FMAC output memory area and write it into the user's output buffer.
It will return either when:
@@ -124,10 +138,10 @@
The user will have to use the updated input and output sizes to keep track
of them.
- (#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop().
+ (#) Stop the FMAC processing (filter) using @ref HAL_FMAC_FilterStop().
- (#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
- resorts to HAL_FMAC_MspDeInit() for low-level de-initialization.
+ (#) Call @ref HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
+ resorts to @ref HAL_FMAC_MspDeInit() for low-level de-initialization.
##### Callback registration #####
==================================
@@ -170,7 +184,7 @@
[..]
By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_FMAC_TxCpltCallback(), @ref HAL_FMAC_RxHalfCpltCallback().
+ examples @ref GetDataCallback(), @ref OutputDataReadyCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init()
and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
@@ -194,18 +208,6 @@
@endverbatim
*
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -218,11 +220,10 @@
*/
/** @defgroup FMAC FMAC
- * @brief FMAC HAL driver modules
+ * @brief FMAC HAL driver module
* @{
*/
-/* External variables --------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup FMAC_Private_Constants FMAC Private Constants
@@ -230,12 +231,28 @@
*/
#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
+#define MAX_PRELOAD_INDEX 0xFFU
#define PRELOAD_ACCESS_DMA 0x00U
#define PRELOAD_ACCESS_POLLING 0x01U
#define POLLING_DISABLED 0U
#define POLLING_ENABLED 1U
#define POLLING_NOT_STOPPED 0U
#define POLLING_STOPPED 1U
+/* FMAC polling-based communications time-out value */
+#define HAL_FMAC_TIMEOUT_VALUE 1000U
+/* FMAC reset time-out value */
+#define HAL_FMAC_RESET_TIMEOUT_VALUE 500U
+/* DMA Read Requests Enable */
+#define FMAC_DMA_REN FMAC_CR_DMAREN
+/* DMA Write Channel Enable */
+#define FMAC_DMA_WEN FMAC_CR_DMAWEN
+/* FMAC Execution Enable */
+#define FMAC_START FMAC_PARAM_START
+
+/**
+ * @}
+ */
+
/**
* @}
@@ -295,40 +312,27 @@
((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
/**
- * @brief Get the threshold matching the watermak.
+ * @brief Get the threshold matching the watermark.
* @param __WM__ Watermark value.
* @retval THRESHOLD
*/
-#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) ((__WM__ == FMAC_THRESHOLD_1)? 1U: \
- (__WM__ == FMAC_THRESHOLD_2)? 2U: \
- (__WM__ == FMAC_THRESHOLD_4)? 4U:8U)
-
-/**
- * @brief Check whether the threshold is applicable.
- * @param __SIZE__ Size of the matching buffer.
- * @param __WM__ Watermark value.
- * @param __ACCESS__ Access to the buffer (polling, it, dma, none).
- * @retval THRESHOLD
- */
-#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
- ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
- ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
- ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \
- ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U)
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
-
+/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
-static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
uint8_t PreloadAccess);
static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess);
@@ -348,7 +352,7 @@
static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
/** @defgroup FMAC_Exported_Functions FMAC Exported Functions
* @{
@@ -366,6 +370,8 @@
(+) DeInitialize the FMAC peripheral
(+) Initialize the FMAC MSP (MCU Specific Package)
(+) De-Initialize the FMAC MSP
+ (+) Register a User FMAC Callback
+ (+) Unregister a FMAC CallBack
[..]
@@ -376,10 +382,12 @@
/**
* @brief Initialize the FMAC peripheral and the associated handle.
* @param hfmac pointer to a FMAC_HandleTypeDef structure.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
{
+ HAL_StatusTypeDef status;
+
/* Check the FMAC handle allocation */
if (hfmac == NULL)
{
@@ -391,7 +399,7 @@
if (hfmac->State == HAL_FMAC_STATE_RESET)
{
- /* Allocate lock resource and initialize it */
+ /* Initialize lock resource */
hfmac->Lock = HAL_UNLOCKED;
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
@@ -418,36 +426,36 @@
}
/* Reset pInput and pOutput */
- hfmac->FilterParam = 0UL;
+ hfmac->FilterParam = 0U;
FMAC_ResetDataPointers(hfmac);
/* Reset FMAC unit (internal pointers) */
if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
{
/* Update FMAC error code and FMAC peripheral state */
- hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hfmac);
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+ hfmac->State = HAL_FMAC_STATE_READY;
- return HAL_TIMEOUT;
+ status = HAL_OK;
}
- /* Update FMAC error code and FMAC peripheral state */
- hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
- hfmac->State = HAL_FMAC_STATE_READY;
-
- /* Process Unlocked */
__HAL_UNLOCK(hfmac);
- return HAL_OK;
+ return status;
}
/**
* @brief De-initialize the FMAC peripheral.
* @param hfmac pointer to a FMAC structure.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
{
@@ -467,7 +475,7 @@
hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
/* Reset pInput and pOutput */
- hfmac->FilterParam = 0UL;
+ hfmac->FilterParam = 0U;
FMAC_ResetDataPointers(hfmac);
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
@@ -485,10 +493,9 @@
/* Change FMAC peripheral state */
hfmac->State = HAL_FMAC_STATE_RESET;
- /* Release Lock */
+ /* Always release Lock in case of de-initialization */
__HAL_UNLOCK(hfmac);
- /* Return function status */
return HAL_OK;
}
@@ -524,8 +531,8 @@
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/**
- * @brief Register a User FMAC Callback
- * to be used instead of the weak predefined callback.
+ * @brief Register a User FMAC Callback.
+ * @note The User FMAC Callback is to be used instead of the weak predefined callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param CallbackID ID of the callback to be registered.
@@ -540,13 +547,19 @@
* @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
* @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
* @param pCallback pointer to the Callback function.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
pFMAC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
if (pCallback == NULL)
{
/* Update the error code */
@@ -554,10 +567,9 @@
return HAL_ERROR;
}
- /* Process locked */
__HAL_LOCK(hfmac);
- if (HAL_FMAC_STATE_READY == hfmac->State)
+ if (hfmac->State == HAL_FMAC_STATE_READY)
{
switch (CallbackID)
{
@@ -606,7 +618,7 @@
break;
}
}
- else if (HAL_FMAC_STATE_RESET == hfmac->State)
+ else if (hfmac->State == HAL_FMAC_STATE_RESET)
{
switch (CallbackID)
{
@@ -636,7 +648,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
__HAL_UNLOCK(hfmac);
return status;
@@ -644,7 +655,7 @@
/**
* @brief Unregister a FMAC CallBack.
- * FMAC callback is redirected to the weak predefined callback.
+ * @note The FMAC callback is redirected to the weak predefined callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module
* @param CallbackID ID of the callback to be unregistered.
@@ -658,16 +669,21 @@
* @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
* @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
* @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
__HAL_LOCK(hfmac);
- if (HAL_FMAC_STATE_READY == hfmac->State)
+ if (hfmac->State == HAL_FMAC_STATE_READY)
{
switch (CallbackID)
{
@@ -716,7 +732,7 @@
break;
}
}
- else if (HAL_FMAC_STATE_RESET == hfmac->State)
+ else if (hfmac->State == HAL_FMAC_STATE_RESET)
{
switch (CallbackID)
{
@@ -746,7 +762,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
__HAL_UNLOCK(hfmac);
return status;
@@ -777,38 +792,40 @@
*/
/**
- * @brief Configure the FMAC filter according to the parameters
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
* specified in the FMAC_FilterConfigTypeDef structure.
* The provided data will be loaded using polling mode.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
-HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
{
- return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_POLLING));
+ return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING));
}
/**
- * @brief Configure the FMAC filter according to the parameters
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
* specified in the FMAC_FilterConfigTypeDef structure.
* The provided data will be loaded using DMA.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
-HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
{
- return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_DMA));
+ return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA));
}
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
- * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* The provided data will be loaded using polling mode.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
@@ -820,10 +837,10 @@
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
- * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize)
@@ -833,7 +850,7 @@
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
- * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* The provided data will be loaded using DMA.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
@@ -845,10 +862,10 @@
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
- * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize)
@@ -866,21 +883,21 @@
* If it is set to NULL, the output will not be read and it will be up to
* an external IP to empty the output buffer.
* @param pOutputSize pointer to the size of the output buffer. The number of read data will be written here.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
{
- uint32_t tmpcr = 0UL;
+ uint32_t tmpcr = 0U;
HAL_StatusTypeDef status;
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check that a valid configuration was done previously */
- if (hfmac->FilterParam == 0UL)
+ if (hfmac->FilterParam == 0U)
{
return HAL_ERROR;
}
@@ -935,34 +952,27 @@
/* Reset the busy flag (do not overwrite the possible write and read flag) */
hfmac->State = HAL_FMAC_STATE_READY;
-
- /* Return function status */
- return status;
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_BUSY;
}
+
+ return status;
}
/**
- * @brief Provide a new input buffer that will be loaded into the FMAC
- * input memory area.
+ * @brief Provide a new input buffer that will be loaded into the FMAC input memory area.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput New input vector (additional input data).
* @param pInputSize Size of the input vector (if all the data can't be
* written, it will be updated with the number of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
{
- /* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef status;
/* Check the function parameters */
if ((pInput == NULL) || (pInputSize == NULL))
@@ -974,6 +984,12 @@
return HAL_ERROR;
}
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the FMAC configuration */
if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE)
{
@@ -990,33 +1006,29 @@
if (hfmac->WrState == HAL_FMAC_STATE_READY)
{
/* Register the new input buffer */
- return (FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize));
+ status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize);
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_BUSY;
}
+
+ return status;
}
/**
- * @brief Provide a new output buffer to be filled with the data
- * computed by FMAC unit.
+ * @brief Provide a new output buffer to be filled with the data computed by FMAC unit.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pOutput New output vector.
* @param pOutputSize Size of the output vector (if the vector can't
* be entirely filled, pOutputSize will be updated with the number
* of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
{
- /* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef status;
/* Check the function parameters */
if ((pOutput == NULL) || (pOutputSize == NULL))
@@ -1028,6 +1040,12 @@
return HAL_ERROR;
}
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the FMAC configuration */
if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
{
@@ -1044,18 +1062,20 @@
if (hfmac->RdState == HAL_FMAC_STATE_READY)
{
/* Register the new output buffer */
- return (FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize));
+ status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_BUSY;
}
+
+ return status;
}
/**
- * @brief Write the previously provided user's input data and
- * fill the previously provided user's output buffer,
+ * @brief Handle the input and/or output data in polling mode
+ * @note This function writes the previously provided user's input data and
+ * fills the previously provided user's output buffer,
* according to the existing FMAC configuration (polling mode only).
* The function returns when the input data has been handled or
* when the output data is filled. The possible unused data isn't
@@ -1065,7 +1085,7 @@
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param Timeout timeout value.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
{
@@ -1074,9 +1094,10 @@
uint8_t inpollingover = POLLING_NOT_STOPPED;
uint8_t outpolling;
uint8_t outpollingover = POLLING_NOT_STOPPED;
+ HAL_StatusTypeDef status;
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
{
return HAL_ERROR;
}
@@ -1161,41 +1182,40 @@
/* Reset the busy flag (do not overwrite the possible write and read flag) */
hfmac->State = HAL_FMAC_STATE_READY;
- /* Return function status */
if ((HAL_GetTick() - tickstart) >= Timeout)
{
- return HAL_TIMEOUT;
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ status = HAL_TIMEOUT;
}
else
{
- return HAL_OK;
+ status = HAL_OK;
}
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_BUSY;
}
+
+ return status;
}
/**
* @brief Stop the FMAC processing.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
{
-
- /* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef status;
/* Check handle state is ready */
if (hfmac->State == HAL_FMAC_STATE_READY)
{
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
/* Set the START bit to 0 (stop the previously configured filter) */
CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START);
@@ -1218,20 +1238,25 @@
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Reset the data pointers */
+ FMAC_ResetDataPointers(hfmac);
+
+ status = HAL_OK;
}
- /* Reset the data pointers */
- FMAC_ResetDataPointers(hfmac);
-
- /* Return function status */
- return HAL_OK;
+ /* Reset the busy flag */
+ hfmac->State = HAL_FMAC_STATE_READY;
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_BUSY;
}
+
+ return status;
}
/**
@@ -1397,7 +1422,7 @@
/* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U))
{
/* Read some data if possible (Y size is used as a pseudo timeout in order
to not get stuck too long under IT if FMAC keeps on processing input
@@ -1424,7 +1449,7 @@
/* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U))
{
/* Write some data if possible (X1 size is used as a pseudo timeout in order
to not get stuck too long under IT if FMAC keep on processing input
@@ -1451,21 +1476,21 @@
/* Check if the overflow error interrupt is enabled and if overflow error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
}
/* Check if the underflow error interrupt is enabled and if underflow error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
}
/* Check if the saturation error interrupt is enabled and if saturation error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
}
@@ -1486,29 +1511,30 @@
* @}
*/
-/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions.
+/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions
+ * @brief Peripheral State and Error functions.
*
@verbatim
==============================================================================
- ##### Peripheral State functions #####
+ ##### Peripheral State and Error functions #####
==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
+ [..] This subsection provides functions allowing to
+ (+) Check the FMAC state
+ (+) Get error code
@endverbatim
* @{
*/
/**
- * @brief Return the FMAC handle state.
+ * @brief Return the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @retval HAL state
+ * @retval HAL_FMAC_StateTypeDef FMAC state
*/
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
{
- /* Return FMAC handle state */
+ /* Return FMAC state */
return hfmac->State;
}
@@ -1517,7 +1543,7 @@
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @note The returned error is a bit-map combination of possible errors.
- * @retval Error bit-map
+ * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
*/
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
{
@@ -1545,7 +1571,7 @@
/**
* @brief Perform a reset of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
{
@@ -1558,10 +1584,11 @@
SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
/* Wait until flag is reset */
- while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0UL)
+ while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
{
if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
{
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
return HAL_TIMEOUT;
}
}
@@ -1573,7 +1600,7 @@
/**
* @brief Reset the data pointers of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval None
*/
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
{
@@ -1584,7 +1611,7 @@
/**
* @brief Reset the input data pointers of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval None
*/
static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
@@ -1597,7 +1624,7 @@
/**
* @brief Reset the output data pointers of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval None
*/
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
@@ -1608,15 +1635,17 @@
}
/**
- * @brief Configure the FMAC filter according to the parameters
- specified in the FMAC_FilterConfigTypeDef structure.
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
+ * specified in the FMAC_FilterConfigTypeDef structure.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
- * @retval HAL status
+ * @param PreloadAccess access mode used for the preload (polling or DMA).
+ * @retval HAL_StatusTypeDef HAL status
*/
-static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
uint8_t PreloadAccess)
{
uint32_t tickstart;
@@ -1626,193 +1655,190 @@
#endif /* USE_FULL_ASSERT */
/* Check the parameters */
- assert_param(IS_FMAC_THRESHOLD(sConfig->InputThreshold));
- assert_param(IS_FMAC_THRESHOLD(sConfig->OutputThreshold));
- assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->InputAccess));
- assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->OutputAccess));
- assert_param(IS_FMAC_CLIP_STATE(sConfig->Clip));
- assert_param(IS_FMAC_FILTER_FUNCTION(sConfig->Filter));
- assert_param(IS_FMAC_PARAM_P(sConfig->Filter, sConfig->P));
- assert_param(IS_FMAC_PARAM_Q(sConfig->Filter, sConfig->Q));
- assert_param(IS_FMAC_PARAM_R(sConfig->Filter, sConfig->R));
+ assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold));
+ assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold));
+ assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess));
+ assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess));
+ assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip));
+ assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter));
+ assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P));
+ assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q));
+ assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R));
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check handle state is ready */
- if (hfmac->State == HAL_FMAC_STATE_READY)
+ if (hfmac->State != HAL_FMAC_STATE_READY)
{
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_BUSY;
+ return HAL_BUSY;
+ }
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
- /* Indicate that there is no valid configuration done */
- hfmac->FilterParam = 0UL;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
- if (sConfig->InputBufferSize != 0U)
- {
- MODIFY_REG(hfmac->Instance->X1BUFCFG, \
- (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
- (((((uint32_t)(sConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
- ((((uint32_t)(sConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE)));
- }
+ /* Indicate that there is no valid configuration done */
+ hfmac->FilterParam = 0U;
- /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
- if (sConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
- {
- /* Check the parameter */
- assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), sConfig->InputThreshold, sConfig->InputAccess));
+ /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
+ if (pConfig->InputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
+ (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
+ ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE)));
+ }
- MODIFY_REG(hfmac->Instance->X1BUFCFG, \
- FMAC_X1BUFCFG_FULL_WM, \
- ((sConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
- }
+ /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
+ if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess));
- /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
- if (sConfig->CoeffBufferSize != 0U)
- {
- MODIFY_REG(hfmac->Instance->X2BUFCFG, \
- (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
- (((((uint32_t)(sConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
- ((((uint32_t)(sConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE)));
- }
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ FMAC_X1BUFCFG_FULL_WM, \
+ ((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
+ }
- /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
- if (sConfig->OutputBufferSize != 0U)
- {
- MODIFY_REG(hfmac->Instance->YBUFCFG, \
- (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \
- (((((uint32_t)(sConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \
- ((((uint32_t)(sConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
- }
+ /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
+ if (pConfig->CoeffBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X2BUFCFG, \
+ (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
+ (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
+ ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE)));
+ }
- /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
- if (sConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
- {
- /* Check the parameter */
- assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), sConfig->OutputThreshold, sConfig->OutputAccess));
+ /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
+ if (pConfig->OutputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \
+ (((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \
+ ((((uint32_t)(pConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
+ }
- MODIFY_REG(hfmac->Instance->YBUFCFG, \
- FMAC_YBUFCFG_EMPTY_WM, \
- ((sConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
- }
+ /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
+ if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess));
- /* CR: Configure the clip feature */
- tmpcr = sConfig->Clip & FMAC_CR_CLIPEN;
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ FMAC_YBUFCFG_EMPTY_WM, \
+ ((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
+ }
- /* CR: If IT or DMA will be used, enable error interrupts.
- * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
- if ((sConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) ||
- (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
- {
- tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
- }
+ /* FMAC_CR: Configure the clip feature */
+ tmpcr = pConfig->Clip & FMAC_CR_CLIPEN;
- /* CR: write the value */
- WRITE_REG(hfmac->Instance->CR, tmpcr);
+ /* FMAC_CR: If IT or DMA will be used, enable error interrupts.
+ * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
+ if ((pConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) ||
+ (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
+ {
+ tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
+ }
- /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
- hfmac->InputAccess = sConfig->InputAccess;
- hfmac->OutputAccess = sConfig->OutputAccess;
+ /* FMAC_CR: write the value */
+ WRITE_REG(hfmac->Instance->CR, tmpcr);
- /* Check whether the configured X2 is big enough for the filter */
+ /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
+ hfmac->InputAccess = pConfig->InputAccess;
+ hfmac->OutputAccess = pConfig->OutputAccess;
+
+ /* Check whether the configured X2 is big enough for the filter */
#if defined(USE_FULL_ASSERT)
- x2size = FMAC_GET_X2_SIZE(hfmac);
+ x2size = FMAC_GET_X2_SIZE(hfmac);
#endif /* USE_FULL_ASSERT */
- assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= sConfig->P)) || \
- ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)sConfig->P + (uint32_t)sConfig->Q))));
+ assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \
+ ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
- /* Build the PARAM value that will be used when starting the filter */
- hfmac->FilterParam = (FMAC_PARAM_START | sConfig->Filter | \
- ((((uint32_t)(sConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
- ((((uint32_t)(sConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
- ((((uint32_t)(sConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
+ /* Build the PARAM value that will be used when starting the filter */
+ hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \
+ ((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
+ ((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
+ ((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
- /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
- if ((sConfig->pCoeffB != NULL) && (sConfig->CoeffBSize != 0U))
+ /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
+ if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U))
+ {
+ /* FIR/IIR: The provided coefficients should match X2 size */
+ assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size);
+ /* FIR/IIR: The size of pCoeffB should match the parameter P */
+ assert_param(pConfig->CoeffBSize >= pConfig->P);
+ /* pCoeffA should be provided for IIR but not for FIR */
+ /* IIR : if pCoeffB is provided, pCoeffA should also be there */
+ /* IIR: The size of pCoeffA should match the parameter Q */
+ assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
+ (pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) ||
+ ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
+ (pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) &&
+ (pConfig->CoeffASize >= pConfig->Q)));
+
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
+ ((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
+ FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
{
- /* FIR/IIR: The provided coefficients should match X2 size */
- assert_param(((uint32_t)sConfig->CoeffASize + (uint32_t)sConfig->CoeffBSize) <= x2size);
- /* FIR/IIR: The size of pCoeffB should match the parameter P */
- assert_param(sConfig->CoeffBSize >= sConfig->P);
- /* pCoeffA should be provided for IIR but not for FIR */
- /* IIR : if pCoeffB is provided, pCoeffA should also be there */
- /* IIR: The size of pCoeffA should match the parameter Q */
- assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
- (sConfig->pCoeffA == NULL) && (sConfig->CoeffASize == 0U)) ||
- ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
- (sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U) &&
- (sConfig->CoeffASize >= sConfig->Q)));
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize);
- /* Write number of values to be loaded, the data load function and start the operation */
- WRITE_REG(hfmac->Instance->PARAM, \
- (((uint32_t)(sConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
- ((uint32_t)(sConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
- FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
-
- if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ /* Load pCoeffA if needed */
+ if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U))
{
/* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffB), sConfig->CoeffBSize);
-
- /* Load pCoeffA if needed */
- if ((sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U))
- {
- /* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffA), sConfig->CoeffASize);
- }
-
- /* Wait for the end of the writing */
- if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
- {
- hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
-
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_READY;
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize);
}
- else
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
{
- hfmac->pInput = sConfig->pCoeffA;
- hfmac->InputCurrentSize = sConfig->CoeffASize;
-
- /* Set the FMAC DMA transfer complete callback */
- hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
- hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
- /* Set the DMA error callback */
- hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
- /* Enable the DMA stream managing FMAC preload data write */
- return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)sConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
- sConfig->CoeffBSize));
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
}
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
}
else
{
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_READY;
+ hfmac->pInput = pConfig->pCoeffA;
+ hfmac->InputCurrentSize = pConfig->CoeffASize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
+ pConfig->CoeffBSize));
}
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
}
- /* Return function status */
return HAL_OK;
}
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
- * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput Preloading of the first elements of the input buffer (X1).
@@ -1823,24 +1849,26 @@
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
- * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * @param PreloadAccess access mode used for the preload (polling or DMA).
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
{
uint32_t tickstart;
+ HAL_StatusTypeDef status;
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check that a valid configuration was done previously */
- if (hfmac->FilterParam == 0UL)
+ if (hfmac->FilterParam == 0U)
{
return HAL_ERROR;
}
@@ -1858,122 +1886,126 @@
}
/* Check handle state is ready */
- if (hfmac->State == HAL_FMAC_STATE_READY)
+ if (hfmac->State != HAL_FMAC_STATE_READY)
{
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_BUSY;
+ return HAL_BUSY;
+ }
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
- /* Preload the input buffer if required */
- if ((pInput != NULL) && (InputSize != 0U))
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Preload the input buffer if required */
+ if ((pInput != NULL) && (InputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
{
- /* Write number of values to be loaded, the data load function and start the operation */
- WRITE_REG(hfmac->Instance->PARAM, \
- (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
- if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
{
- /* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
-
- /* Wait for the end of the writing */
- if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
- {
- hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
}
- else
- {
- hfmac->pInput = pOutput;
- hfmac->InputCurrentSize = OutputSize;
-
- /* Set the FMAC DMA transfer complete callback */
- hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
- hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
- /* Set the DMA error callback */
- hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
- /* Enable the DMA stream managing FMAC preload data write */
- return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
- }
- }
-
- /* Preload the output buffer if required */
- if ((pOutput != NULL) && (OutputSize != 0U))
- {
- /* Write number of values to be loaded, the data load function and start the operation */
- WRITE_REG(hfmac->Instance->PARAM, \
- (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
-
- if (PreloadAccess == PRELOAD_ACCESS_POLLING)
- {
- /* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
-
- /* Wait for the end of the writing */
- if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
- {
- hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- else
- {
- hfmac->pInput = NULL;
- hfmac->InputCurrentSize = 0U;
-
- /* Set the FMAC DMA transfer complete callback */
- hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
- hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
- /* Set the DMA error callback */
- hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
- /* Enable the DMA stream managing FMAC preload data write */
- return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
- }
- }
-
- /* Update the error codes */
- if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
- {
- hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
- }
- if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
- {
- hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
- }
-
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_READY;
-
- /* Return function status */
- if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
- {
- return HAL_OK;
}
else
{
- return HAL_ERROR;
+ hfmac->pInput = pOutput;
+ hfmac->InputCurrentSize = OutputSize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
}
}
+
+ /* Preload the output buffer if required */
+ if ((pOutput != NULL) && (OutputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
+ }
+ }
+
+ /* Update the error codes */
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
+ }
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
+ }
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Return function status */
+ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
+ {
+ status = HAL_OK;
+ }
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_ERROR;
}
+ return status;
}
/**
* @brief Write data into FMAC internal memory through WDATA and increment input buffer pointer.
- * This function is only used with preload functions.
+ * @note This function is only used with preload functions.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param ppData pointer to pointer to the data buffer.
* @param Size size of the data buffer.
- * @retval none
+ * @retval None
*/
static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
{
@@ -1992,17 +2024,16 @@
* @param hfmac FMAC handle.
* @param Tickstart Tick start value.
* @param Timeout Timeout duration.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag changes */
- while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
if ((HAL_GetTick() - Tickstart) > Timeout)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hfmac);
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
return HAL_TIMEOUT;
}
@@ -2011,14 +2042,13 @@
}
/**
- * @brief Register the new input buffer, update DMA configuration
- * if needed and change the FMAC state.
+ * @brief Register the new input buffer, update DMA configuration if needed and change the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput New input vector (additional input data).
* @param pInputSize Size of the input vector (if all the data can't be
* written, it will be updated with the number of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
uint16_t *pInputSize)
@@ -2051,20 +2081,18 @@
hfmac->pInputSize = pInputSize;
}
- /* Return function status */
return HAL_OK;
}
/**
- * @brief Register the new output buffer, update DMA configuration
- * if needed and change the FMAC state.
+ * @brief Register the new output buffer, update DMA configuration if needed and change the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pOutput New output vector.
* @param pOutputSize Size of the output vector (if the vector can't
* be entirely filled, pOutputSize will be updated with the number
* of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
uint16_t *pOutputSize)
@@ -2073,7 +2101,7 @@
hfmac->OutputCurrentSize = 0U;
/* Check whether a valid pointer was provided */
- if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0UL))
+ if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U))
{
/* The user will have to provide a valid configuration later */
hfmac->pOutput = NULL;
@@ -2110,7 +2138,6 @@
hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
}
- /* Return function status */
return HAL_OK;
}
@@ -2119,7 +2146,7 @@
* @param hfmac FMAC handle.
* @param MaxSizeToRead Maximum number of data to read (this serves as a timeout
* if FMAC continuously writes into the output buffer).
- * @retval HAL status
+ * @retval None
*/
static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
{
@@ -2128,7 +2155,7 @@
uint32_t tmpvalue;
/* Check if there is data to read */
- if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0UL)
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U)
{
return;
}
@@ -2157,7 +2184,7 @@
*(hfmac->pOutput) = (int16_t)tmpvalue;
hfmac->pOutput++;
hfmac->OutputCurrentSize++;
- } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0UL);
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U);
/* Y buffer empty flag has just be raised, read the threshold */
threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U;
@@ -2183,7 +2210,7 @@
* @param hfmac FMAC handle.
* @param MaxSizeToWrite Maximum number of data to write (this serves as a timeout
* if FMAC continuously empties the input buffer).
- * @retval HAL status
+ * @retval None
*/
static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
{
@@ -2191,7 +2218,7 @@
uint16_t threshold;
/* Check if there is room in FMAC */
- if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0UL)
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U)
{
return;
}
@@ -2219,7 +2246,7 @@
WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
hfmac->pInput++;
hfmac->InputCurrentSize++;
- } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0UL);
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U);
/* X1 buffer full flag has just be raised, read the threshold */
threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U;
@@ -2348,7 +2375,7 @@
else
{
/* Wait for the end of the writing */
- for (index = 0U; index < 0xFFU; index++)
+ for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
{
if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
{
@@ -2356,8 +2383,8 @@
}
}
- /* If 'START' is still set, there was an error: set FMAC handle state to error */
- if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ /* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
}
@@ -2400,16 +2427,16 @@
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Wait for the end of the X1 writing */
- for (index = 0U; index < 0xFFU; index++)
+ for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
{
- if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0UL)
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
{
break;
}
}
/* If 'START' is still set, there was an error: set FMAC handle state to error */
- if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
@@ -2445,7 +2472,6 @@
/* nothing to do */
}
- /* Return function status */
if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
{
/* Change the FMAC state */
diff --git a/Src/stm32g4xx_hal_gpio.c b/Src/stm32g4xx_hal_gpio.c
index 3a8dfd3..23a445e 100644
--- a/Src/stm32g4xx_hal_gpio.c
+++ b/Src/stm32g4xx_hal_gpio.c
@@ -188,26 +188,6 @@
if (iocurrent != 0x00u)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3U];
- temp &= ~(0xFU << ((position & 0x07U) * 4U));
- temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
- GPIOx->AFR[position >> 3U] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- GPIOx->MODER = temp;
-
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@@ -233,6 +213,26 @@
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
+ /* In case of Alternate function mode selection */
+ if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ temp &= ~(0xFU << ((position & 0x07U) * 4U));
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = temp;
+
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@@ -334,16 +334,16 @@
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
/* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
-
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
-
- /* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
+ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u));
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position);
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
}
position++;
diff --git a/Src/stm32g4xx_hal_hrtim.c b/Src/stm32g4xx_hal_hrtim.c
index 7aa48e8..c4e6745 100644
--- a/Src/stm32g4xx_hal_hrtim.c
+++ b/Src/stm32g4xx_hal_hrtim.c
@@ -793,6 +793,9 @@
SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
}
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
return HAL_OK;
}
@@ -843,6 +846,9 @@
SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
}
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
return HAL_OK;
}
@@ -1393,6 +1399,9 @@
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_BUSY;
@@ -1491,6 +1500,9 @@
default:
{
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+
hhrtim->State = HAL_HRTIM_STATE_ERROR;
/* Process Unlocked */
@@ -1513,6 +1525,9 @@
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
return HAL_OK;
}
@@ -2059,6 +2074,9 @@
}
default:
{
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+
hhrtim->State = HAL_HRTIM_STATE_ERROR;
/* Process Unlocked */
@@ -3422,6 +3440,9 @@
default:
{
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+
hhrtim->State = HAL_HRTIM_STATE_ERROR;
/* Process Unlocked */
@@ -3888,6 +3909,7 @@
{
/* Check parameters */
assert_param(IS_HRTIM_EVENT(Event));
+ assert_param(IS_HRTIM_EVENTSRC(Event, pEventCfg->Source));
assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
@@ -9398,9 +9420,6 @@
{
uint32_t hrtim_timcr2;
- /* UPDGAT bitfield must be reset before programming a new value */
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
-
/* Configure timing unit (Timer A to Timer F) */
hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
diff --git a/Src/stm32g4xx_hal_i2c.c b/Src/stm32g4xx_hal_i2c.c
index bd3eac9..de47309 100644
--- a/Src/stm32g4xx_hal_i2c.c
+++ b/Src/stm32g4xx_hal_i2c.c
@@ -223,12 +223,12 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
-
+ [..]
Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@@ -243,9 +243,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
-
+ [..]
Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
@@ -262,9 +262,9 @@
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
-
+ [..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
-
+ [..]
By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
@@ -273,7 +273,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
+ [..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@@ -281,7 +281,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
or @ref HAL_I2C_Init() function.
-
+ [..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (0x00000001U)
-#define I2C_XFER_RX_IT (0x00000002U)
-#define I2C_XFER_LISTEN_IT (0x00000004U)
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
-#define I2C_XFER_ERROR_IT (0x00000011U)
-#define I2C_XFER_CPLT_IT (0x00000012U)
-#define I2C_XFER_RELOAD_IT (0x00000012U)
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -410,6 +410,9 @@
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@@ -3200,7 +3203,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3285,7 +3288,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3446,7 +3449,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -3531,7 +3534,7 @@
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
- if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
@@ -4251,9 +4254,21 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@@ -4737,6 +4752,13 @@
/* Process locked */
__HAL_LOCK(hi2c);
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, tmpITFlags);
+ }
+
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@@ -4788,9 +4810,6 @@
{
if (hi2c->XferCount > 0U)
{
- /* Remove RXNE flag on temporary variable as read done */
- tmpITFlags &= ~I2C_FLAG_RXNE;
-
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@@ -4844,13 +4863,6 @@
/* Nothing to do */
}
- /* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, tmpITFlags);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5004,10 +5016,18 @@
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
+ HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
+ }
+
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
@@ -5075,8 +5095,24 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hi2c->State;
+
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@@ -5092,11 +5128,6 @@
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
- {
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
- }
else
{
/* Nothing to do */
@@ -5370,9 +5401,27 @@
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@@ -5427,19 +5476,36 @@
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ __IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -5448,12 +5514,17 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ /* Fetch Last receive data if any */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmpreg = (uint8_t)hi2c->Instance->RXDR;
+ UNUSED(tmpreg);
+ }
+
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@@ -5467,6 +5538,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5501,6 +5573,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5547,12 +5620,26 @@
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -5566,6 +5653,9 @@
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@@ -5573,6 +5663,9 @@
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@@ -5609,7 +5702,6 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -5632,6 +5724,7 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5647,6 +5740,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5661,6 +5755,7 @@
else
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5734,6 +5829,7 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -5753,7 +5849,6 @@
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@@ -5768,16 +5863,19 @@
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ tmppreviousstate = hi2c->PreviousState;
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
- if (hi2c->hdmatx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5793,13 +5891,20 @@
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
/* Abort DMA RX transfer if any */
- else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
- if (hi2c->hdmarx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5815,10 +5920,28 @@
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
- else if (hi2c->State == HAL_I2C_STATE_ABORT)
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Error callback treatment.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5832,6 +5955,8 @@
}
else
{
+ hi2c->PreviousState = I2C_STATE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -6042,30 +6167,16 @@
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if (hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->hdmatx != NULL)
{
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AbortCpltCallback(hi2c);
-#else
- HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmatx->XferAbortCallback = NULL;
}
- else
+ if (hi2c->hdmarx != NULL)
{
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ErrorCallback(hi2c);
-#else
- HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmarx->XferAbortCallback = NULL;
}
+
+ I2C_TreatErrorCallback(hi2c);
}
/**
@@ -6342,19 +6453,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -6380,7 +6491,7 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@@ -6434,19 +6545,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
diff --git a/Src/stm32g4xx_hal_i2s.c b/Src/stm32g4xx_hal_i2s.c
index 8d497e3..565480a 100644
--- a/Src/stm32g4xx_hal_i2s.c
+++ b/Src/stm32g4xx_hal_i2s.c
@@ -261,7 +261,7 @@
uint32_t i2sodd;
uint32_t packetlength;
uint32_t tmp;
- uint32_t i2sclk;
+ uint32_t i2sclk = 0U;
/* Check the I2S handle allocation */
if (hi2s == NULL)
diff --git a/Src/stm32g4xx_hal_lptim.c b/Src/stm32g4xx_hal_lptim.c
index d51539d..e4f887f 100644
--- a/Src/stm32g4xx_hal_lptim.c
+++ b/Src/stm32g4xx_hal_lptim.c
@@ -143,7 +143,7 @@
@endverbatim
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -152,7 +152,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -173,13 +174,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Constants
+ * @{
+ */
#define TIMEOUT 1000UL /* Timeout is 1s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
/* Exported functions --------------------------------------------------------*/
@@ -226,16 +235,19 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@@ -269,13 +281,17 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
}
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
@@ -289,18 +305,28 @@
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ /* Glitch filters for internal triggers and external inputs are configured
+ * only if an internal clock source is provided to the LPTIM
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ /* Configure the active edge or edges used by the counter only if LPTIM is
+ * clocked by an external clock source
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ }
+
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge |
- hlptim->Init.Trigger.SampleTime);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge);
}
/* Write to LPTIMx CFGR */
@@ -343,6 +369,11 @@
/* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
if (hlptim->MspDeInitCallback == NULL)
{
@@ -451,12 +482,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -483,6 +532,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -512,6 +566,41 @@
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -534,12 +623,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -566,6 +649,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -617,12 +705,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -649,6 +755,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -678,6 +789,41 @@
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -700,12 +846,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -732,6 +872,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -783,12 +928,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -815,6 +978,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -844,6 +1012,41 @@
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the pulse value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -866,12 +1069,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the pulse value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
-
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
@@ -898,6 +1095,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -963,9 +1165,18 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -992,6 +1203,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@@ -1039,6 +1255,29 @@
/* Set ENC bit to enable the encoder interface */
hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable "switch to down direction" interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
@@ -1048,9 +1287,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1077,6 +1313,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@@ -1120,12 +1361,30 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1152,6 +1411,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@@ -1189,18 +1453,47 @@
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
+ /* Load the Timeout value in the compare register */
+ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
+
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Compare match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
- /* Load the Timeout value in the compare register */
- __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1230,6 +1523,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@@ -1271,9 +1569,18 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1300,6 +1607,11 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -1335,6 +1647,29 @@
hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
}
+ /* Enable the Peripheral */
+ __HAL_LPTIM_ENABLE(hlptim);
+
+ /* Clear flag */
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
+ /* Load the period value in the autoreload register */
+ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
+
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable the Peripheral */
+ __HAL_LPTIM_DISABLE(hlptim);
+
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@@ -1344,9 +1679,6 @@
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
- /* Load the period value in the autoreload register */
- __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
-
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
@@ -1376,12 +1708,16 @@
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
+ if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+
/* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-
/* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
@@ -1979,15 +2315,39 @@
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
+ * @brief LPTimer Wait for flag set
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @param flag The lptim flag
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+{
+ HAL_StatusTypeDef result = HAL_OK;
+ uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ result = HAL_TIMEOUT;
+ }
+ }
+ while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+
+ return result;
+}
+
+/**
* @brief Disable LPTIM HW instance.
- * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
* @retval None
*/
-void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
{
uint32_t tmpclksource = 0;
uint32_t tmpIER;
@@ -2000,95 +2360,91 @@
/*********** Save LPTIM Config ***********/
/* Save LPTIM source clock */
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
- tmpIER = lptim->Instance->IER;
- tmpCFGR = lptim->Instance->CFGR;
- tmpCMP = lptim->Instance->CMP;
- tmpARR = lptim->Instance->ARR;
- tmpOR = lptim->Instance->OR;
+ tmpIER = hlptim->Instance->IER;
+ tmpCFGR = hlptim->Instance->CFGR;
+ tmpCMP = hlptim->Instance->CMP;
+ tmpARR = hlptim->Instance->ARR;
+ tmpOR = hlptim->Instance->OR;
/*********** Reset LPTIM ***********/
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_FORCE_RESET();
- __HAL_RCC_LPTIM1_RELEASE_RESET();
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
+ default:
+ break;
}
/*********** Restore LPTIM Config ***********/
- uint32_t Ref_Time;
- uint32_t Time_Elapsed;
-
if ((tmpCMP != 0UL) || (tmpARR != 0UL))
{
/* Force LPTIM source kernel clock from APB */
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
{
/* Restore CMP register (LPTIM should be enabled first) */
- lptim->Instance->CR |= LPTIM_CR_ENABLE;
- lptim->Instance->CMP = tmpCMP;
- /* Polling on CMP write ok status after above restore operation */
- Ref_Time = HAL_GetTick();
- do
- {
- Time_Elapsed = HAL_GetTick() - Ref_Time;
- } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT));
+ hlptim->Instance->CR |= LPTIM_CR_ENABLE;
+ hlptim->Instance->CMP = tmpCMP;
- __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK);
+ /* Wait for the completion of the write operation to the LPTIM_CMP register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
+ {
+ hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
+ }
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
}
if (tmpARR != 0UL)
{
/* Restore ARR register (LPTIM should be enabled first) */
- lptim->Instance->CR |= LPTIM_CR_ENABLE;
- lptim->Instance->ARR = tmpARR;
- /* Polling on ARR write ok status after above restore operation */
- Ref_Time = HAL_GetTick();
- do
- {
- Time_Elapsed = HAL_GetTick() - Ref_Time;
- } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT));
+ hlptim->Instance->CR |= LPTIM_CR_ENABLE;
+ hlptim->Instance->ARR = tmpARR;
- __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK);
+ /* Wait for the completion of the write operation to the LPTIM_ARR register */
+ if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
+ {
+ hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
+ }
+
+ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
}
/* Restore LPTIM source kernel clock */
- switch ((uint32_t)lptim->Instance)
+ switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
+ default:
+ break;
}
}
/* Restore configuration registers (LPTIM should be disabled first) */
- lptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
- lptim->Instance->IER = tmpIER;
- lptim->Instance->CFGR = tmpCFGR;
- lptim->Instance->OR = tmpOR;
+ hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
+ hlptim->Instance->IER = tmpIER;
+ hlptim->Instance->CFGR = tmpCFGR;
+ hlptim->Instance->OR = tmpOR;
__enable_irq();
}
diff --git a/Src/stm32g4xx_hal_opamp.c b/Src/stm32g4xx_hal_opamp.c
index d77d4a0..23a7d72 100644
--- a/Src/stm32g4xx_hal_opamp.c
+++ b/Src/stm32g4xx_hal_opamp.c
@@ -1048,8 +1048,8 @@
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
- * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MspInit callback ID
- * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MspDeInit callback ID
+ * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID
+ * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
@@ -1070,10 +1070,10 @@
{
switch (CallbackId)
{
- case HAL_OPAMP_MSP_INIT_CB_ID :
+ case HAL_OPAMP_MSPINIT_CB_ID :
hopamp->MspInitCallback = pCallback;
break;
- case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ case HAL_OPAMP_MSPDEINIT_CB_ID :
hopamp->MspDeInitCallback = pCallback;
break;
default :
@@ -1086,10 +1086,10 @@
{
switch (CallbackId)
{
- case HAL_OPAMP_MSP_INIT_CB_ID :
+ case HAL_OPAMP_MSPINIT_CB_ID :
hopamp->MspInitCallback = pCallback;
break;
- case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ case HAL_OPAMP_MSPDEINIT_CB_ID :
hopamp->MspDeInitCallback = pCallback;
break;
default :
@@ -1115,8 +1115,8 @@
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MSP Init Callback ID
- * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MSP DeInit Callback ID
+ * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MSP Init Callback ID
+ * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MSP DeInit Callback ID
* @arg @ref HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks
* @retval status
*/
@@ -1132,10 +1132,10 @@
{
switch (CallbackId)
{
- case HAL_OPAMP_MSP_INIT_CB_ID :
+ case HAL_OPAMP_MSPINIT_CB_ID :
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
break;
- case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ case HAL_OPAMP_MSPDEINIT_CB_ID :
hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
break;
case HAL_OPAMP_ALL_CB_ID :
@@ -1152,10 +1152,10 @@
{
switch (CallbackId)
{
- case HAL_OPAMP_MSP_INIT_CB_ID :
+ case HAL_OPAMP_MSPINIT_CB_ID :
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
break;
- case HAL_OPAMP_MSP_DEINIT_CB_ID :
+ case HAL_OPAMP_MSPDEINIT_CB_ID :
hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
break;
default :
diff --git a/Src/stm32g4xx_hal_pcd.c b/Src/stm32g4xx_hal_pcd.c
index c435ac6..8589764 100644
--- a/Src/stm32g4xx_hal_pcd.c
+++ b/Src/stm32g4xx_hal_pcd.c
@@ -1050,21 +1050,18 @@
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
{
/* Force low-power mode in the macrocell */
- hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
- hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U)
- {
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->SuspendCallback(hpcd);
+ hpcd->SuspendCallback(hpcd);
#else
- HAL_PCD_SuspendCallback(hpcd);
+ HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- }
}
/* Handle LPM Interrupt */
@@ -1074,8 +1071,8 @@
if (hpcd->LPM_State == LPM_L0)
{
/* Force suspend and low-power mode before going to L1 state*/
- hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
- hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE;
+ hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
hpcd->LPM_State = LPM_L1;
hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
@@ -1680,8 +1677,8 @@
{
/* DIR = 0 */
- /* DIR = 0 => IN int */
- /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
ep = &hpcd->IN_ep[0];
@@ -1705,20 +1702,20 @@
{
/* DIR = 1 */
- /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
if ((wEPVal & USB_EP_SETUP) != 0U)
{
- /* Get SETUP Packet*/
+ /* Get SETUP Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
ep->pmaadress, (uint16_t)ep->xfer_count);
- /* SETUP bit kept frozen while CTR_RX = 1*/
+ /* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Process SETUP Packet*/
@@ -1733,7 +1730,7 @@
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- /* Get Control Data OUT Packet*/
+ /* Get Control Data OUT Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
@@ -1743,7 +1740,7 @@
ep->xfer_buff += ep->xfer_count;
- /* Process Control Data OUT Packet*/
+ /* Process Control Data OUT Packet */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
@@ -1758,7 +1755,7 @@
}
else
{
- /* Decode and service non control endpoints interrupt */
+ /* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
@@ -1768,7 +1765,7 @@
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
ep = &hpcd->OUT_ep[epindex];
- /* OUT double Buffering*/
+ /* OUT double Buffering */
if (ep->doublebuffer == 0U)
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
@@ -1779,9 +1776,12 @@
}
else
{
+ /* free EP OUT Buffer */
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
- /*read from endpoint BUF0Addr buffer*/
+ /* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
@@ -1790,17 +1790,15 @@
}
else
{
- /*read from endpoint BUF1Addr buffer*/
+ /* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
- /* free EP OUT Buffer */
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
}
- /*multi-packet on the NON control OUT endpoint*/
+ /* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
ep->xfer_buff += count;
@@ -1827,7 +1825,7 @@
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- /*multi-packet on the NON control IN endpoint*/
+ /* multi-packet on the NON control IN endpoint */
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
ep->xfer_buff += ep->xfer_count;
diff --git a/Src/stm32g4xx_hal_rtc.c b/Src/stm32g4xx_hal_rtc.c
index b9a295c..879efa6 100644
--- a/Src/stm32g4xx_hal_rtc.c
+++ b/Src/stm32g4xx_hal_rtc.c
@@ -1198,7 +1198,7 @@
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
- else /* format BCD */
+ else /* Format BCD */
{
if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U)
{
@@ -1420,6 +1420,7 @@
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
+
/* Configure the Alarm A or Alarm B Sub Second registers */
subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
@@ -1430,7 +1431,8 @@
if (sAlarm->Alarm == RTC_ALARM_A)
{
/* Disable the Alarm A interrupt */
- CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE);
+ CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
+
/* Clear flag alarm A */
WRITE_REG(RTC->SCR, RTC_SCR_CALRAF);
__HAL_RTC_ALARM_EXTI_CLEAR_IT();
@@ -1462,7 +1464,8 @@
else
{
/* Disable the Alarm B interrupt */
- CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE);
+ CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
+
/* Clear flag alarm B */
WRITE_REG(RTC->SCR, RTC_SCR_CALRBF);
__HAL_RTC_ALARM_EXTI_CLEAR_IT();
@@ -1499,6 +1502,7 @@
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
diff --git a/Src/stm32g4xx_hal_smbus.c b/Src/stm32g4xx_hal_smbus.c
index 829b12b..e6631cf 100644
--- a/Src/stm32g4xx_hal_smbus.c
+++ b/Src/stm32g4xx_hal_smbus.c
@@ -89,12 +89,12 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
to register an interrupt callback.
-
+ [..]
Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@@ -106,9 +106,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
-
+ [..]
Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
@@ -122,9 +122,9 @@
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
-
+ [..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
-
+ [..]
By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
@@ -133,7 +133,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
-
+ [..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@@ -141,7 +141,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
or @ref HAL_SMBUS_Init() function.
-
+ [..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -203,18 +203,18 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
*/
@@ -1801,7 +1801,7 @@
* @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint16_t DevAddress;
@@ -2085,7 +2085,7 @@
* @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint8_t TransferDirection;
uint16_t SlaveAddrCode;
@@ -2341,7 +2341,7 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
uint32_t tmpisr = 0UL;
@@ -2381,7 +2381,7 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
uint32_t tmpisr = 0UL;
uint32_t tmpstate = hsmbus->State;
@@ -2453,7 +2453,7 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
{
uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
@@ -2554,7 +2554,7 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2603,7 +2603,7 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2620,7 +2620,7 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
{
/* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
/* it request implicitly to generate a restart condition */
diff --git a/Src/stm32g4xx_hal_spi.c b/Src/stm32g4xx_hal_spi.c
index fa5e3ea..a7e8cd6 100644
--- a/Src/stm32g4xx_hal_spi.c
+++ b/Src/stm32g4xx_hal_spi.c
@@ -2278,7 +2278,8 @@
break;
}
count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2295,7 +2296,8 @@
break;
}
count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2440,7 +2442,8 @@
break;
}
count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2457,7 +2460,8 @@
break;
}
count--;
- } while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -3051,8 +3055,17 @@
}
#endif /* USE_SPI_CRC */
- /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ /* Check if we are in Master RX 2 line mode */
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* Normal case */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
/* Check the end of the transaction */
if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
@@ -4171,7 +4184,8 @@
break;
}
count--;
- } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
@@ -4212,7 +4226,8 @@
break;
}
count--;
- } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{
@@ -4243,7 +4258,8 @@
break;
}
count--;
- } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
diff --git a/Src/stm32g4xx_hal_tim.c b/Src/stm32g4xx_hal_tim.c
index 58aa3e6..250b60c 100644
--- a/Src/stm32g4xx_hal_tim.c
+++ b/Src/stm32g4xx_hal_tim.c
@@ -205,7 +205,7 @@
/* Private define ------------------------------------------------------------*/
#define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup TIM_Private_Functions
@@ -227,6 +227,7 @@
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
@@ -312,6 +313,13 @@
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -345,6 +353,13 @@
HAL_TIM_Base_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -397,6 +412,12 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
@@ -407,9 +428,6 @@
__HAL_TIM_ENABLE(htim);
}
- /* Change the TIM state*/
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -424,13 +442,10 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Set the TIM state */
- htim->State = HAL_TIM_STATE_BUSY;
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the TIM state*/
+ /* Set the TIM state */
htim->State = HAL_TIM_STATE_READY;
/* Return function status */
@@ -449,6 +464,15 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Check the TIM state */
+ if (htim->State != HAL_TIM_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
@@ -472,12 +496,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
+
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
/* Return function status */
return HAL_OK;
}
@@ -496,6 +524,7 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+ /* Set the TIM state */
if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
@@ -513,7 +542,7 @@
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
/* Set the DMA Period elapsed callbacks */
@@ -561,7 +590,7 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
+ /* Set the TIM state */
htim->State = HAL_TIM_STATE_READY;
/* Return function status */
@@ -644,6 +673,13 @@
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -677,6 +713,13 @@
HAL_TIM_OC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -736,6 +779,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -786,6 +838,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -808,6 +863,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -924,6 +988,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -948,11 +1015,12 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -960,12 +1028,12 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -1138,8 +1206,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1221,6 +1289,13 @@
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -1254,6 +1329,13 @@
HAL_TIM_PWM_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1313,6 +1395,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -1363,8 +1454,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1387,6 +1478,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -1503,6 +1603,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1527,11 +1630,12 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1539,12 +1643,12 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -1716,8 +1820,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1799,6 +1903,13 @@
/* Init the base time for the input capture */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -1832,6 +1943,13 @@
HAL_TIM_IC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1885,10 +2003,23 @@
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
@@ -1925,6 +2056,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1943,10 +2078,23 @@
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM channel state */
+ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2050,6 +2198,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2070,16 +2222,21 @@
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2087,12 +2244,13 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -2252,8 +2410,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -2290,6 +2449,9 @@
* requires a timer reset to avoid unexpected direction
* due to DIR bit readonly in center aligned mode.
* Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @note When the timer instance is initialized in One Pulse mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
* @param htim TIM One Pulse handle
* @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
@@ -2345,6 +2507,15 @@
/* Configure the OPM Mode */
htim->Instance->CR1 |= OnePulseMode;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -2378,6 +2549,15 @@
HAL_TIM_OnePulse_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2428,9 +2608,29 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2485,6 +2685,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2500,9 +2706,29 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Prevent unused argument(s) compilation warning */
UNUSED(OutputChannel);
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2568,6 +2794,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -2606,6 +2838,9 @@
* @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
* Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
* using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @note When the timer instance is initialized in Encoder mode, timer
+ * channels 1 and channel 2 are reserved and cannot be used for other
+ * purpose.
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
@@ -2623,15 +2858,15 @@
}
/* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -2703,6 +2938,15 @@
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -2737,6 +2981,15 @@
HAL_TIM_Encoder_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2788,8 +3041,58 @@
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
/* Enable the encoder interface channels */
switch (Channel)
@@ -2833,7 +3136,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2862,6 +3165,20 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -2878,8 +3195,58 @@
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@@ -2929,7 +3296,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2960,8 +3327,19 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
return HAL_OK;
@@ -2983,27 +3361,95 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length)
{
- /* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Set the TIM channel(s) state */
+ if (Channel == TIM_CHANNEL_1)
{
- return HAL_BUSY;
- }
- else if (htim->State == HAL_TIM_STATE_READY)
- {
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
- return HAL_ERROR;
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData1 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ return HAL_ERROR;
+ }
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((pData2 == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
}
}
else
{
- /* nothing to do */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ {
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
switch (Channel)
@@ -3101,6 +3547,7 @@
default:
break;
}
+
/* Return function status */
return HAL_OK;
}
@@ -3118,7 +3565,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -3153,8 +3600,19 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM channel(s) state */
+ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+ {
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
return HAL_OK;
@@ -3475,8 +3933,6 @@
/* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3543,8 +3999,6 @@
break;
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3575,8 +4029,6 @@
/* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
if (Channel == TIM_CHANNEL_1)
{
/* TI1 Configuration */
@@ -3640,8 +4092,6 @@
htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -3675,8 +4125,6 @@
/* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3785,8 +4233,6 @@
break;
}
- htim->State = HAL_TIM_STATE_READY;
-
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -4025,11 +4471,11 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4037,7 +4483,7 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -4174,8 +4620,6 @@
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4240,6 +4684,9 @@
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
}
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Return function status */
return status;
}
@@ -4357,11 +4804,11 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4369,7 +4816,7 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -4507,8 +4954,6 @@
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4573,6 +5018,9 @@
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
}
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Return function status */
return status;
}
@@ -5958,6 +6406,54 @@
}
/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM handle
+ * @retval Active channel
+ */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+{
+ return htim->Channel;
+}
+
+/**
+ * @brief Return actual state of the TIM channel.
+ * @param htim TIM handle
+ * @param Channel TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval TIM Channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+ return channel_state;
+}
+
+/**
+ * @brief Return actual state of a DMA burst operation.
+ * @param htim TIM handle
+ * @retval DMA burst state
+ */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+ return htim->DMABurstState;
+}
+
+/**
* @}
*/
@@ -5978,13 +6474,38 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
@@ -5996,23 +6517,41 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else
{
@@ -6037,8 +6576,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -6078,23 +6615,45 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
}
else
{
@@ -6119,8 +6678,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -6160,7 +6717,10 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
@@ -6178,8 +6738,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedHalfCpltCallback(htim);
#else
@@ -6196,7 +6754,10 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
+ if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ }
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
@@ -6214,8 +6775,6 @@
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State = HAL_TIM_STATE_READY;
-
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerHalfCpltCallback(htim);
#else
diff --git a/Src/stm32g4xx_hal_tim_ex.c b/Src/stm32g4xx_hal_tim_ex.c
index a6a5057..049bb12 100644
--- a/Src/stm32g4xx_hal_tim_ex.c
+++ b/Src/stm32g4xx_hal_tim_ex.c
@@ -62,7 +62,7 @@
(#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
@@ -109,9 +109,11 @@
*/
/* End of private constants --------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Exported functions --------------------------------------------------------*/
@@ -142,6 +144,9 @@
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @note When the timer instance is initialized in Hall Sensor Interface mode,
+ * timer channels 1 and channel 2 are reserved and cannot be used for
+ * other purpose.
* @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
@@ -227,6 +232,15 @@
htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+ /* Initialize the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@@ -260,6 +274,15 @@
HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+ /* Change the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -307,12 +330,31 @@
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -343,6 +385,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -355,10 +403,29 @@
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ /* Check the TIM channels state */
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -397,6 +464,12 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -411,29 +484,36 @@
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM channel state */
+ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
+
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@@ -482,9 +562,14 @@
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -532,6 +617,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@@ -575,6 +669,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -598,6 +695,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -721,6 +827,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -746,24 +855,25 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
switch (Channel)
@@ -771,11 +881,11 @@
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
@@ -790,11 +900,11 @@
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
@@ -809,11 +919,11 @@
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
@@ -828,11 +938,11 @@
case TIM_CHANNEL_4:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
@@ -929,8 +1039,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -988,6 +1098,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@@ -1030,6 +1149,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1053,6 +1175,15 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ /* Check the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -1176,6 +1307,9 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1201,35 +1335,37 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ /* Set the TIM complementary channel state */
+ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if (((uint32_t)pData == 0U) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
- /* nothing to do */
+ return HAL_ERROR;
}
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
@@ -1244,11 +1380,11 @@
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
@@ -1263,11 +1399,11 @@
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
@@ -1282,11 +1418,11 @@
case TIM_CHANNEL_4:
{
/* Set the DMA compare callbacks */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
@@ -1383,8 +1519,8 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
- /* Change the htim state */
- htim->State = HAL_TIM_STATE_READY;
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1424,11 +1560,27 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
+ HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
- /* Enable the complementary One Pulse output */
+ /* Check the TIM channels state */
+ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1449,12 +1601,14 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
- /* Disable the complementary One Pulse output */
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1462,6 +1616,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1478,17 +1636,33 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+ HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
+ HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+ /* Check the TIM channels state */
+ if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- /* Enable the complementary One Pulse output */
+ /* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1509,6 +1683,8 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@@ -1518,8 +1694,9 @@
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- /* Disable the complementary One Pulse output */
+ /* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1527,6 +1704,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
+ /* Set the TIM channels state */
+ TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+
/* Return function status */
return HAL_OK;
}
@@ -1840,7 +2021,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@@ -1873,16 +2054,19 @@
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- /* Reset the MSM Bit */
- tmpsmcr &= ~TIM_SMCR_MSM;
- /* Set master mode */
- tmpsmcr |= sMasterConfig->MasterSlaveMode;
-
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- /* Update TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
@@ -3126,6 +3310,28 @@
}
/**
+ * @brief Return actual state of the TIM complementary channel.
+ * @param htim TIM handle
+ * @param ChannelN TIM Complementary channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @retval TIM Complementary channel state
+ */
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
+{
+ HAL_TIM_ChannelStateTypeDef channel_state;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
+
+ channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
+
+ return channel_state;
+}
+/**
* @}
*/
@@ -3178,6 +3384,103 @@
/**
+ * @brief TIM DMA Delay Pulse complete callback (complementary channel).
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA error callback (complementary channel)
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
diff --git a/Src/stm32g4xx_hal_timebase_tim_template.c b/Src/stm32g4xx_hal_timebase_tim_template.c
index 8ee6ddc..2d9d126 100644
--- a/Src/stm32g4xx_hal_timebase_tim_template.c
+++ b/Src/stm32g4xx_hal_timebase_tim_template.c
@@ -74,6 +74,7 @@
uint32_t uwAPB1Prescaler;
uint32_t uwPrescalerValue;
uint32_t pFLatency;
+ HAL_StatusTypeDef status;
/* Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U);
@@ -116,14 +117,29 @@
TimHandle.Init.Prescaler = uwPrescalerValue;
TimHandle.Init.ClockDivision = 0;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
- if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ status = HAL_TIM_Base_Init(&TimHandle);
+ if (status == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
- return HAL_TIM_Base_Start_IT(&TimHandle);
+ status = HAL_TIM_Base_Start_IT(&TimHandle);
+ if (status == HAL_OK)
+ {
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ /* Configure the TIM IRQ priority */
+ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
}
/* Return function status */
- return HAL_ERROR;
+ return status;
}
/**
diff --git a/Src/stm32g4xx_hal_usart.c b/Src/stm32g4xx_hal_usart.c
index c9449d8..6020bf2 100644
--- a/Src/stm32g4xx_hal_usart.c
+++ b/Src/stm32g4xx_hal_usart.c
@@ -317,7 +317,8 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
@@ -2091,7 +2092,7 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -2146,6 +2147,14 @@
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
/* USART SPI slave underrun error interrupt occurred -------------------------*/
if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
diff --git a/Src/stm32g4xx_hal_usart_ex.c b/Src/stm32g4xx_hal_usart_ex.c
index 6da75be..9a429d1 100644
--- a/Src/stm32g4xx_hal_usart_ex.c
+++ b/Src/stm32g4xx_hal_usart_ex.c
@@ -57,10 +57,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
-/* UART RX FIFO depth */
+/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
-/* UART TX FIFO depth */
+/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
@@ -243,7 +243,7 @@
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
- husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+ husart->SlaveMode = USART_SLAVEMODE_DISABLE;
husart->State = HAL_USART_STATE_READY;
diff --git a/Src/stm32g4xx_hal_wwdg.c b/Src/stm32g4xx_hal_wwdg.c
index 92f8ec5..cb3b07c 100644
--- a/Src/stm32g4xx_hal_wwdg.c
+++ b/Src/stm32g4xx_hal_wwdg.c
@@ -32,10 +32,10 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
- max timeout before reset: ~73.14µs
- (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
- max timeout before reset: ~599.18ms
+ (++) Counter min (T[5;0] = 0x00) @170MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 24.09µs
+ (++) Counter max (T[5;0] = 0x3F) @170MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: approximately 197.38ms
==============================================================================
##### How to use this driver #####
diff --git a/Src/stm32g4xx_ll_adc.c b/Src/stm32g4xx_ll_adc.c
index 531b7d8..19fce32 100644
--- a/Src/stm32g4xx_ll_adc.c
+++ b/Src/stm32g4xx_ll_adc.c
@@ -942,7 +942,7 @@
CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
/* Reset register OFR4 */
CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
-
+
/* Reset registers JDR1, JDR2, JDR3, JDR4 */
/* Note: bits in access mode read only, no direct reset applicable */
diff --git a/Src/stm32g4xx_ll_fmac.c b/Src/stm32g4xx_ll_fmac.c
index 2ad6787..7491be4 100644
--- a/Src/stm32g4xx_ll_fmac.c
+++ b/Src/stm32g4xx_ll_fmac.c
@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32g4xx_ll_fmac.c
* @author MCD Application Team
- * @brief FMAC LL module driver.
+ * @brief Header for stm32g4xx_ll_fmac.c module
******************************************************************************
* @attention
*
@@ -37,41 +37,13 @@
* @{
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup FMAC_LL_Private_Macros
- * @{
- */
-
-/** @brief Check if the watermark value is a valid one.
- * @param __VALUE__ Watermak value.
- * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
- */
-#define IS_LL_FMAC_WM(__VALUE__) (((__VALUE__) == LL_FMAC_WM_0_THRESHOLD_1) \
- || ((__VALUE__) == LL_FMAC_WM_1_THRESHOLD_2) \
- || ((__VALUE__) == LL_FMAC_WM_2_THRESHOLD_4) \
- || ((__VALUE__) == LL_FMAC_WM_3_THRESHOLD_8))
-
-/** @brief Check if the function ID is a valid one.
- * @param __VALUE__ Function ID.
- * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
- */
-#define IS_LL_FMAC_FUNC(__VALUE__) (((__VALUE__) == LL_FMAC_FUNC_LOAD_X1) \
- || ((__VALUE__) == LL_FMAC_FUNC_LOAD_X2) \
- || ((__VALUE__) == LL_FMAC_FUNC_LOAD_Y) \
- || ((__VALUE__) == LL_FMAC_FUNC_CONVO_FIR) \
- || ((__VALUE__) == LL_FMAC_FUNC_IIR_DIRECT_FORM_1))
-
-
-/**
- * @}
- */
-
+/* Private variables ---------------------------------------------------------*/
+/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
/** @addtogroup FMAC_LL_Exported_Functions
* @{
*/
@@ -83,7 +55,7 @@
/**
* @brief Initialize FMAC peripheral registers to their default reset values.
* @param FMACx FMAC Instance
- * @retval An ErrorStatus enumeration value:
+ * @retval ErrorStatus enumeration value:
* - SUCCESS: FMAC registers are initialized
* - ERROR: FMAC registers are not initialized
*/
diff --git a/Src/stm32g4xx_ll_lptim.c b/Src/stm32g4xx_ll_lptim.c
index a04a458..c7de8d3 100644
--- a/Src/stm32g4xx_ll_lptim.c
+++ b/Src/stm32g4xx_ll_lptim.c
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief LPTIM LL module driver.
******************************************************************************
- * @attention
+ * @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
@@ -13,7 +13,8 @@
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
- * ******************************************************************************
+ *
+ ******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
@@ -172,14 +173,6 @@
}
/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
* @brief Disable the LPTIM instance
* @rmtoll CR ENABLE LL_LPTIM_Disable
* @param LPTIMx Low-Power Timer instance
@@ -207,11 +200,11 @@
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -232,11 +225,11 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -249,7 +242,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@@ -264,11 +258,13 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
+
/* Restore LPTIM source kernel clock */
LL_RCC_SetLPTIMClockSource(tmpclksource);
}
@@ -286,6 +282,14 @@
* @}
*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/**
diff --git a/Src/stm32g4xx_ll_tim.c b/Src/stm32g4xx_ll_tim.c
index e3e5f49..f6f42da 100644
--- a/Src/stm32g4xx_ll_tim.c
+++ b/Src/stm32g4xx_ll_tim.c
@@ -320,7 +320,7 @@
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**
diff --git a/Src/stm32g4xx_ll_usb.c b/Src/stm32g4xx_ll_usb.c
index f2cef5a..9c371fd 100644
--- a/Src/stm32g4xx_ll_usb.c
+++ b/Src/stm32g4xx_ll_usb.c
@@ -83,7 +83,7 @@
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
- uint16_t winterruptmask;
+ uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
@@ -92,7 +92,7 @@
USB_CNTR_RESETM | USB_CNTR_L1REQM;
/* Set interrupt mask */
- USBx->CNTR |= winterruptmask;
+ USBx->CNTR |= (uint16_t)winterruptmask;
return HAL_OK;
}
@@ -105,7 +105,7 @@
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
- uint16_t winterruptmask;
+ uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
@@ -114,7 +114,7 @@
USB_CNTR_RESETM | USB_CNTR_L1REQM;
/* Clear interrupt mask */
- USBx->CNTR &= ~winterruptmask;
+ USBx->CNTR &= (uint16_t)(~winterruptmask);
return HAL_OK;
}
@@ -155,13 +155,13 @@
/* Init Device */
/*CNTR_FRES = 1*/
- USBx->CNTR = USB_CNTR_FRES;
+ USBx->CNTR = (uint16_t)USB_CNTR_FRES;
/*CNTR_FRES = 0*/
- USBx->CNTR = 0;
+ USBx->CNTR = 0U;
/*Clear pending interrupts*/
- USBx->ISTR = 0;
+ USBx->ISTR = 0U;
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
@@ -270,7 +270,7 @@
break;
}
- PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);
+ PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
@@ -591,13 +591,13 @@
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
{
/* disable all interrupts and force USB reset */
- USBx->CNTR = USB_CNTR_FRES;
+ USBx->CNTR = (uint16_t)USB_CNTR_FRES;
/* clear interrupt status register */
- USBx->ISTR = 0;
+ USBx->ISTR = 0U;
/* switch-off device */
- USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
+ USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
return HAL_OK;
}
@@ -614,7 +614,7 @@
if (address == 0U)
{
/* set device address and enable function */
- USBx->DADDR = USB_DADDR_EF;
+ USBx->DADDR = (uint16_t)USB_DADDR_EF;
}
return HAL_OK;
@@ -628,7 +628,7 @@
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
/* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
- USBx->BCDR |= USB_BCDR_DPPU;
+ USBx->BCDR |= (uint16_t)USB_BCDR_DPPU;
return HAL_OK;
}
@@ -771,7 +771,7 @@
*/
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
{
- USBx->CNTR |= USB_CNTR_RESUME;
+ USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
return HAL_OK;
}
@@ -783,7 +783,7 @@
*/
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
{
- USBx->CNTR &= ~(USB_CNTR_RESUME);
+ USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
return HAL_OK;
}
diff --git a/Src/stm32g4xx_ll_utils.c b/Src/stm32g4xx_ll_utils.c
index ea78949..f6cbb92 100644
--- a/Src/stm32g4xx_ll_utils.c
+++ b/Src/stm32g4xx_ll_utils.c
@@ -142,7 +142,6 @@
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_PLL_IsBusy(void);
/**
@@ -269,6 +268,118 @@
}
/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param HCLKFrequency HCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
+{
+ uint32_t timeout;
+ uint32_t getlatency;
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 or greater than max clock */
+ if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY9_FREQ))
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+ {
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY8_FREQ)
+ {
+ /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */
+ latency = LL_FLASH_LATENCY_8;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY7_FREQ)
+ {
+ /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */
+ latency = LL_FLASH_LATENCY_7;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY6_FREQ)
+ {
+ /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */
+ latency = LL_FLASH_LATENCY_6;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ)
+ {
+ /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
+ latency = LL_FLASH_LATENCY_5;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
+ {
+ /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
+ latency = LL_FLASH_LATENCY_4;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
+ {
+ /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
+ latency = LL_FLASH_LATENCY_3;
+ }
+ else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
+ {
+ /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
+ {
+ /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+ }
+ else /* SCALE2 */
+ {
+ if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
+ {
+ /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
+ {
+ /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+ }
+
+ if (status != ERROR)
+ {
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ timeout = 2U;
+ do
+ {
+ /* Wait for Flash latency to be updated */
+ getlatency = LL_FLASH_GetLatency();
+ timeout--;
+ } while ((getlatency != latency) && (timeout > 0U));
+
+ if(getlatency != latency)
+ {
+ status = ERROR;
+ }
+ }
+ }
+
+ return status;
+}
+
+/**
* @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
@@ -289,7 +400,7 @@
{
ErrorStatus status;
uint32_t pllfreq;
- uint32_t hpre = 0U;
+ uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
/* Check if one of the PLL is enabled */
if(UTILS_PLL_IsBusy() == SUCCESS)
@@ -314,10 +425,10 @@
/* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
if(pllfreq > 80000000U)
{
- hpre = UTILS_ClkInitStruct->AHBCLKDivider;
- if(hpre == LL_RCC_SYSCLK_DIV_1)
+ if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
{
UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
}
}
@@ -325,10 +436,16 @@
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
/* Apply definitive AHB prescaler value if necessary */
- if((status == SUCCESS) && (hpre != 0U))
+ if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
{
- UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if (status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
}
}
else
@@ -365,7 +482,7 @@
{
ErrorStatus status;
uint32_t pllfreq;
- uint32_t hpre = 0U;
+ uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
@@ -405,10 +522,10 @@
/* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
if(pllfreq > 80000000U)
{
- hpre = UTILS_ClkInitStruct->AHBCLKDivider;
- if(hpre == LL_RCC_SYSCLK_DIV_1)
+ if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
{
UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
+ hpre = LL_RCC_SYSCLK_DIV_2;
}
}
@@ -416,10 +533,16 @@
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
/* Apply definitive AHB prescaler value if necessary */
- if((status == SUCCESS) && (hpre != 0U))
+ if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
{
- UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(pllfreq);
+ if (status == SUCCESS)
+ {
+ UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_SetSystemCoreClock(pllfreq);
+ }
}
}
else
@@ -442,103 +565,6 @@
/** @addtogroup UTILS_LL_Private_Functions
* @{
*/
-/**
- * @brief Update number of Flash wait states in line with new frequency and current
- voltage range.
- * @param HCLK_Frequency HCLK frequency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
- */
-static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
-{
- ErrorStatus status = SUCCESS;
-
- uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
-
- /* Frequency cannot be equal to 0 */
- if(HCLK_Frequency == 0U)
- {
- status = ERROR;
- }
- else
- {
- if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
- {
- if(HCLK_Frequency > UTILS_SCALE1_LATENCY8_FREQ)
- {
- /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */
- latency = LL_FLASH_LATENCY_8;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
- {
- /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */
- latency = LL_FLASH_LATENCY_7;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ)
- {
- /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */
- latency = LL_FLASH_LATENCY_6;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)
- {
- /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
- latency = LL_FLASH_LATENCY_5;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
- {
- /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
- latency = LL_FLASH_LATENCY_4;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
- {
- /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
- latency = LL_FLASH_LATENCY_3;
- }
- else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
- {
- /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
- {
- /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
- }
- }
- else /* SCALE2 */
- {
- if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
- {
- /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
- {
- /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
- }
- }
-
- LL_FLASH_SetLatency(latency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
- }
- return status;
-}
/**
* @brief Function to check that PLL can be modified
@@ -617,7 +643,7 @@
if(SystemCoreClock < hclk_frequency)
{
/* Set FLASH latency to highest latency */
- status = UTILS_SetFlashLatency(hclk_frequency);
+ status = LL_SetFlashLatency(hclk_frequency);
}
/* Update system clock configuration */
@@ -648,7 +674,7 @@
if(SystemCoreClock > hclk_frequency)
{
/* Set FLASH latency to lowest latency */
- status = UTILS_SetFlashLatency(hclk_frequency);
+ status = LL_SetFlashLatency(hclk_frequency);
}
/* Update SystemCoreClock variable */
