Release v1.10.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index e57e823..93a925d 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -384,6 +383,7 @@
#endif /* STM32H7 */
+
/**
* @}
*/
@@ -596,24 +596,24 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@@ -774,49 +774,6 @@
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-/** @brief Constants defining the events that can be selected to configure the
- * set/reset crossbar of a timer output
- */
-#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
-#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
-#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
-#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
-#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
-#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
-#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
-#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
-#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
-
-#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
-#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
-#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
-#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
-#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
-#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
-#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
-#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
-#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
-
-/** @brief Constants defining the event filtering applied to external events
- * by a timer
- */
-#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
@@ -969,6 +926,11 @@
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
/**
* @}
@@ -980,15 +942,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
- #define I2S_IT_TXE I2S_IT_TXP
- #define I2S_IT_RXNE I2S_IT_RXP
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
- #define I2S_FLAG_TXE I2S_FLAG_TXP
- #define I2S_FLAG_RXNE I2S_FLAG_RXP
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
@@ -1023,7 +985,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1123,16 +1085,16 @@
#if defined(STM32H7)
- #define SPI_FLAG_TXE SPI_FLAG_TXP
- #define SPI_FLAG_RXNE SPI_FLAG_RXP
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
- #define SPI_IT_TXE SPI_IT_TXP
- #define SPI_IT_RXNE SPI_IT_RXP
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
- #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
- #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
- #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
- #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
@@ -1459,7 +1421,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@@ -1481,7 +1443,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1495,7 +1457,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1503,7 +1466,8 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
@@ -1526,9 +1490,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
@@ -1538,7 +1502,8 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
@@ -1563,9 +1528,9 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
@@ -1620,9 +1585,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@@ -1871,15 +1836,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@@ -2090,8 +2055,8 @@
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
@@ -2147,7 +2112,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
- #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
@@ -2284,7 +2249,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -3252,7 +3218,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3381,7 +3347,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3401,19 +3367,19 @@
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
@@ -3597,6 +3563,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal.h b/Inc/stm32h7xx_hal.h
index 8f9946f..95a44bf 100644
--- a/Inc/stm32h7xx_hal.h
+++ b/Inc/stm32h7xx_hal.h
@@ -69,10 +69,10 @@
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
@@ -1093,10 +1093,14 @@
void HAL_EnableDomain2DBGStandbyMode(void);
void HAL_DisableDomain2DBGStandbyMode(void);
#endif /*DUAL_CORE*/
+#if defined(DBGMCU_CR_DBG_STOPD3)
void HAL_EnableDomain3DBGStopMode(void);
void HAL_DisableDomain3DBGStopMode(void);
+#endif /*DBGMCU_CR_DBG_STOPD3*/
+#if defined(DBGMCU_CR_DBG_STANDBYD3)
void HAL_EnableDomain3DBGStandbyMode(void);
void HAL_DisableDomain3DBGStandbyMode(void);
+#endif /*DBGMCU_CR_DBG_STANDBYD3*/
void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
#if defined(DUAL_CORE)
diff --git a/Inc/stm32h7xx_hal_adc.h b/Inc/stm32h7xx_hal_adc.h
index 5be1e1a..155aaa7 100644
--- a/Inc/stm32h7xx_hal_adc.h
+++ b/Inc/stm32h7xx_hal_adc.h
@@ -128,11 +128,11 @@
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
- Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
- to free the IRQ vector sequencer.
- Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
- use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
- (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
+ and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group,
+ use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
@@ -163,7 +163,7 @@
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
- uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
+ uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
This parameter can be a value of @ref ADC_ConversionDataManagement.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups
@@ -266,7 +266,7 @@
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE.*/
#if defined(ADC_VER_V5_V90)
- uint32_t OffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data.
+ uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.
This parameter can be a value of @ref ADCEx_OffsetSign.
Note:
- This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
@@ -380,7 +380,7 @@
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
@@ -533,7 +533,7 @@
* @{
*/
#define ADC3_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -1773,7 +1773,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -1821,7 +1821,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
diff --git a/Inc/stm32h7xx_hal_adc_ex.h b/Inc/stm32h7xx_hal_adc_ex.h
index b86c259..ae18507 100644
--- a/Inc/stm32h7xx_hal_adc_ex.h
+++ b/Inc/stm32h7xx_hal_adc_ex.h
@@ -122,7 +122,7 @@
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
#if defined(ADC_VER_V5_V90)
- uint32_t InjectedOffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data.
+ uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.
This parameter can be a value of @ref ADCEx_OffsetSign.
Note:
- This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
@@ -295,7 +295,7 @@
/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
* @{
*/
-#define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is substracted */
+#define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */
#define ADC3_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */
/**
* @}
@@ -415,7 +415,7 @@
* @{
*/
#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
-#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
+#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
/**
* @}
*/
@@ -441,7 +441,7 @@
* Usage of this macro is not the Standard way of multimode
* configuration and can lead to have HAL ADC handles status
* misaligned. Usage of this macro must be limited to cases
- * mentionned above.
+ * mentioned above.
* @param __HANDLE__ ADC handle.
* @retval None
*/
@@ -1207,7 +1207,10 @@
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
- ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 ))
/**
* @brief Verify the ADC oversampling triggered mode.
diff --git a/Inc/stm32h7xx_hal_cec.h b/Inc/stm32h7xx_hal_cec.h
index 9b138ba..e4ff48d 100644
--- a/Inc/stm32h7xx_hal_cec.h
+++ b/Inc/stm32h7xx_hal_cec.h
@@ -121,7 +121,7 @@
* b6 Error information
* 0 : No Error
* 1 : Error
- * b5 IP initilisation status
+ * b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b4-b3 (not used)
@@ -138,7 +138,7 @@
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
+ * b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
diff --git a/Inc/stm32h7xx_hal_conf_template.h b/Inc/stm32h7xx_hal_conf_template.h
index 10ed9ea..05bf9c5 100644
--- a/Inc/stm32h7xx_hal_conf_template.h
+++ b/Inc/stm32h7xx_hal_conf_template.h
@@ -108,7 +108,7 @@
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for HSE start up, in ms */
+ #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -166,7 +166,7 @@
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (0x0FUL) /*!< tick interrupt priority */
#define USE_RTOS 0
-#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
+#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 1U /*!< use CRC in SPI */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
diff --git a/Inc/stm32h7xx_hal_cordic.h b/Inc/stm32h7xx_hal_cordic.h
index 1fb9208..04e2d79 100644
--- a/Inc/stm32h7xx_hal_cordic.h
+++ b/Inc/stm32h7xx_hal_cordic.h
@@ -198,15 +198,21 @@
#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
-#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
-#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
-#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
+ |CORDIC_CSR_PRECISION_0))
/**
* @}
*/
@@ -257,7 +263,8 @@
*/
#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
32-bit data input (Q1.31 format), or two 16-bit
- data input (Q1.15 format) packed in one 32 bits Data */
+ data input (Q1.15 format) packed in one 32 bits
+ Data */
#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
(Q1.31 format) */
/**
@@ -268,8 +275,9 @@
* @{
*/
#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
- 32-bit data ouput (Q1.31 format), or two 16-bit
- data output (Q1.15 format) packed in one 32 bits Data */
+ 32-bit data output (Q1.31 format), or two 16-bit
+ data output (Q1.15 format) packed in one 32 bits
+ Data */
#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
(Q1.31 format) */
/**
@@ -329,9 +337,9 @@
*/
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+ (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
@@ -346,7 +354,7 @@
* @retval None
*/
#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
+ (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
/**
* @brief Disable the CORDIC interrupt
@@ -357,7 +365,7 @@
* @retval None
*/
#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
+ (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified CORDIC interrupt occurred or not.
Dummy macro as no interrupt status flag.
@@ -383,7 +391,7 @@
* @retval SET (flag is set) or RESET (flag is reset)
*/
#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
+ ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear specified CORDIC status flag. Dummy macro as no
flag can be cleared.
@@ -403,7 +411,7 @@
* @retval FlagStatus
*/
#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
+ (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
/**
* @}
@@ -527,7 +535,8 @@
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, pCORDIC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
+ pCORDIC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
/**
* @}
@@ -539,10 +548,14 @@
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
-HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc);
-HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection);
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t DMADirection);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_cryp.h b/Inc/stm32h7xx_hal_cryp.h
index fc24fbf..619c862 100644
--- a/Inc/stm32h7xx_hal_cryp.h
+++ b/Inc/stm32h7xx_hal_cryp.h
@@ -61,9 +61,10 @@
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
- uint32_t HeaderSize; /*!< The size of header buffer in word */
+ uint32_t HeaderSize; /*!< The size of header buffer */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
- uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t DataWidthUnit; /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to configure Key and Initialization
Vector only once and to skip configuration for consecutive processing.
This parameter can be a value of @ref CRYP_Configuration_Skip */
@@ -216,6 +217,17 @@
* @}
*/
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+ * @{
+ */
+
+#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
+
+/**
+ * @}
+ */
+
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
diff --git a/Inc/stm32h7xx_hal_dac.h b/Inc/stm32h7xx_hal_dac.h
index e248dd4..fb2ff1b 100644
--- a/Inc/stm32h7xx_hal_dac.h
+++ b/Inc/stm32h7xx_hal_dac.h
@@ -79,17 +79,17 @@
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -391,7 +391,8 @@
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
diff --git a/Inc/stm32h7xx_hal_def.h b/Inc/stm32h7xx_hal_def.h
index d59c8c1..f7e3c13 100644
--- a/Inc/stm32h7xx_hal_def.h
+++ b/Inc/stm32h7xx_hal_def.h
@@ -107,7 +107,15 @@
}while (0)
#endif /* USE_RTOS */
-#if defined ( __GNUC__ )
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif
+ #ifndef __packed
+ #define __packed __attribute__((packed))
+ #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@@ -118,7 +126,14 @@
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__GNUC__) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@@ -130,7 +145,7 @@
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
- #if defined (__CC_ARM) /* ARM Compiler */
+ #if defined (__CC_ARM) /* ARM Compiler V5 */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@@ -150,9 +165,9 @@
/**
* @brief __RAM_FUNC definition
*/
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+ --------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@@ -179,6 +194,24 @@
#endif
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
+/* ARM V4/V5 and V6 & GNU Compiler
+ -------------------------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32h7xx_hal_dfsdm.h b/Inc/stm32h7xx_hal_dfsdm.h
index 648ef94..189efd0 100644
--- a/Inc/stm32h7xx_hal_dfsdm.h
+++ b/Inc/stm32h7xx_hal_dfsdm.h
@@ -302,8 +302,8 @@
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
* @{
*/
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_dma.h b/Inc/stm32h7xx_hal_dma.h
index 3c1f6fe..7da4420 100644
--- a/Inc/stm32h7xx_hal_dma.h
+++ b/Inc/stm32h7xx_hal_dma.h
@@ -346,11 +346,11 @@
#if defined(HRTIM1)
#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
-#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
-#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
-#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
-#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
-#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */
+#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */
+#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */
+#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */
+#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6*/
#endif /* HRTIM1 */
#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
diff --git a/Inc/stm32h7xx_hal_dma2d.h b/Inc/stm32h7xx_hal_dma2d.h
index ba16bef..d5acb3f 100644
--- a/Inc/stm32h7xx_hal_dma2d.h
+++ b/Inc/stm32h7xx_hal_dma2d.h
@@ -22,7 +22,7 @@
#define STM32H7xx_HAL_DMA2D_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -71,7 +71,8 @@
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
@@ -95,7 +96,8 @@
typedef struct
{
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
@@ -103,9 +105,12 @@
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
- uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
- @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value
+ in case of A8 or A4 color mode.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFF except for the color modes detailed below.
+ @note In case of A8 or A4 color mode (ARGB),
+ this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
@@ -133,46 +138,46 @@
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
-}HAL_DMA2D_StateTypeDef;
+} HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
- DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
+ DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
- DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
+ DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
- void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
+ void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */
- void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
+ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
- void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
+ void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */
- void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
+ void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
- void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
+ void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */
- void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
+ void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
- DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
- HAL_LockTypeDef Lock; /*!< DMA2D lock. */
+ HAL_LockTypeDef Lock; /*!< DMA2D lock. */
- __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
+ __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
- __IO uint32_t ErrorCode; /*!< DMA2D error code. */
+ __IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D Callback pointer definition
*/
-typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
@@ -246,10 +251,10 @@
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
-#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+ with original alpha channel value */
/**
* @}
*/
@@ -340,7 +345,8 @@
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
/**
* @}
*/
@@ -357,7 +363,7 @@
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
-}HAL_DMA2D_CallbackIDTypeDef;
+} HAL_DMA2D_CallbackIDTypeDef;
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -374,10 +380,10 @@
* @retval None
*/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
@@ -483,12 +489,13 @@
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
-HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
-void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
-void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
@@ -502,16 +509,22 @@
*/
/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
@@ -631,14 +644,17 @@
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
-#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
+ || ((LAYER) == DMA2D_FOREGROUND_LAYER))
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
- ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
+#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
+ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
@@ -646,12 +662,18 @@
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
-#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
- ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
- ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
- ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
- ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
- ((INPUT_CM) == DMA2D_INPUT_A4) || ((INPUT_CM) == DMA2D_INPUT_YCBCR))
+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
+ ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
+ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
+ ((INPUT_CM) == DMA2D_INPUT_L8) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL44) || \
+ ((INPUT_CM) == DMA2D_INPUT_AL88) || \
+ ((INPUT_CM) == DMA2D_INPUT_L4) || \
+ ((INPUT_CM) == DMA2D_INPUT_A8) || \
+ ((INPUT_CM) == DMA2D_INPUT_A4) || \
+ ((INPUT_CM) == DMA2D_INPUT_YCBCR))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
@@ -677,11 +699,11 @@
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
- ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
- ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
- ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
- ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_dsi.h b/Inc/stm32h7xx_hal_dsi.h
index a3894ec..06d9ae5 100644
--- a/Inc/stm32h7xx_hal_dsi.h
+++ b/Inc/stm32h7xx_hal_dsi.h
@@ -25,10 +25,11 @@
extern "C" {
#endif
-#if defined(DSI)
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
+#if defined(DSI)
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@@ -922,7 +923,7 @@
/**
* @brief Reset DSI handle state.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None
*/
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
diff --git a/Inc/stm32h7xx_hal_eth.h b/Inc/stm32h7xx_hal_eth.h
index 039dc66..354ce3f 100644
--- a/Inc/stm32h7xx_hal_eth.h
+++ b/Inc/stm32h7xx_hal_eth.h
@@ -89,10 +89,15 @@
*/
typedef struct
{
- uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */
+ uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */
- uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
-
+ uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
+
+ uint32_t* PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
+
+ uint32_t* CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
+
+ uint32_t BuffersInUse; /*<! Buffers in Use */
}ETH_TxDescListTypeDef;
/**
*
@@ -546,7 +551,7 @@
*/
/*
- DMA Tx Normal Desciptor Read Format
+ DMA Tx Normal Descriptor Read Format
-----------------------------------------------------------------------------------------------
TDES0 | Buffer1 or Header Address [31:0] |
-----------------------------------------------------------------------------------------------
@@ -659,7 +664,7 @@
/*
- DMA Tx Context Desciptor
+ DMA Tx Context Descriptor
-----------------------------------------------------------------------------------------------
TDES0 | Timestamp Low |
-----------------------------------------------------------------------------------------------
diff --git a/Inc/stm32h7xx_hal_exti.h b/Inc/stm32h7xx_hal_exti.h
index 18cffec..f31cacf 100644
--- a/Inc/stm32h7xx_hal_exti.h
+++ b/Inc/stm32h7xx_hal_exti.h
@@ -410,33 +410,34 @@
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_PROPERTY(__LINE__) ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
+#define IS_EXTI_PROPERTY(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
#if defined (DUAL_CORE)
-#define IS_EXTI_TARGET(__LINE__) ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \
- (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2) || \
- (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
- (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \
+ (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2) || \
+ (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
+ (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
#else
-#define IS_EXTI_TARGET(__LINE__) ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \
- (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \
+ (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
#endif
-#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
- IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \
- (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
- (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK |\
+ EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
+ IS_EXTI_PROPERTY(__EXTI_LINE__) && IS_EXTI_TARGET(__EXTI_LINE__) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+ (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))
-#define IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
+#define IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
-#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \
- ((__LINE__) == EXTI_TRIGGER_FALLING)|| \
- ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
+ ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)|| \
+ ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING))
-#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00UL)
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00UL)
#if defined(GPIOI)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
diff --git a/Inc/stm32h7xx_hal_flash_ex.h b/Inc/stm32h7xx_hal_flash_ex.h
index 3c4c81a..96119b9 100644
--- a/Inc/stm32h7xx_hal_flash_ex.h
+++ b/Inc/stm32h7xx_hal_flash_ex.h
@@ -1,6 +1,6 @@
/**
******************************************************************************
- * @file stm32H7xx_hal_flash_ex.h
+ * @file stm32h7xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of FLASH HAL module.
******************************************************************************
@@ -276,16 +276,6 @@
* @}
*/
-/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
- * @{
- */
-#define OB_WWDG_SW 0x10U /*!< Software WWDG selected */
-#define OB_WWDG_HW 0x00U /*!< Hardware WWDG selected */
-/**
- * @}
- */
-
-
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
@@ -556,6 +546,7 @@
*/
#endif /* FLASH_OPTSR_NRST_STOP_D2 */
+#if defined (DUAL_BANK)
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
* @{
*/
@@ -564,6 +555,7 @@
/**
* @}
*/
+#endif /* DUAL_BANK */
/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
* @{
@@ -643,19 +635,32 @@
OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
#elif defined (FLASH_OPTSR_VDDMMC_HSLV)
+#if defined (DUAL_BANK)
#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
OB_USER_VDDMMC_HSLV)
+#else
+#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
+ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
+ OB_USER_SECURITY | OB_USER_IOHSLV |\
+ OB_USER_VDDMMC_HSLV)
+#endif /* DUAL_BANK */
#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
OB_USER_SECURITY | OB_USER_IOHSLV |\
OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
-#else
+#else /* Single core */
+#if defined (DUAL_BANK)
#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
+#else
+#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
+ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
+ OB_USER_SECURITY | OB_USER_IOHSLV )
+#endif /* DUAL_BANK */
#endif /* DUAL_CORE */
/**
* @}
@@ -745,10 +750,10 @@
* @{
*/
/**
- * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
+ * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1)
* @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
* @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
- * @retval The FLASH Boot Base Adress
+ * @retval The FLASH Boot Base Address
*/
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
/**
@@ -866,8 +871,6 @@
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
-#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
-
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
@@ -912,7 +915,9 @@
#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
((CONFIG) == OB_SECURE_RDP_ERASE))
+#if defined (DUAL_BANK)
#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
+#endif /* DUAL_BANK */
#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
diff --git a/Inc/stm32h7xx_hal_gfxmmu.h b/Inc/stm32h7xx_hal_gfxmmu.h
index 740f808..8248bed 100644
--- a/Inc/stm32h7xx_hal_gfxmmu.h
+++ b/Inc/stm32h7xx_hal_gfxmmu.h
@@ -69,15 +69,15 @@
typedef struct
{
FunctionalState Activation; /*!< Cache and pre-fetch enable/disable.
- @note: All following parameters are usefull only if cache and pre-fetch are enabled. */
+ @note: All following parameters are useful only if cache and pre-fetch are enabled. */
uint32_t CacheLock; /*!< Locking the cache to a buffer.
This parameter can be a value of @ref GFXMMU_CacheLock. */
uint32_t CacheLockBuffer; /*!< Buffer on which the cache is locked.
This parameter can be a value of @ref GFXMMU_CacheLockBuffer.
- @note: Usefull only when lock of the cache is enabled. */
+ @note: Useful only when lock of the cache is enabled. */
uint32_t CacheForce; /*!< Forcing the cache regardless MPU attributes.
This parameter can be a value of @ref GFXMMU_CacheForce.
- @note: Usefull only when lock of the cache is enabled. */
+ @note: Useful only when lock of the cache is enabled. */
uint32_t OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache.
This parameter can be a value of @ref GFXMMU_OutterBufferability. */
uint32_t OutterCachability; /*!< Cachability of an access generated by the GFXMMU cache.
@@ -94,7 +94,7 @@
FunctionalState Activation; /*!< Interrupts enable/disable */
uint32_t UsedInterrupts; /*!< Interrupts used.
This parameter can be a values combination of @ref GFXMMU_Interrupts.
- @note: Usefull only when interrupts are enabled. */
+ @note: Useful only when interrupts are enabled. */
}GFXMMU_InterruptsTypeDef;
/**
@@ -214,7 +214,7 @@
* @}
*/
-/** @defgroup GFXMMU_OutterBufferability GFXMMU outter bufferability
+/** @defgroup GFXMMU_OutterBufferability GFXMMU outer bufferability
* @{
*/
#define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U /*!< No bufferable */
@@ -223,11 +223,11 @@
* @}
*/
-/** @defgroup GFXMMU_OutterCachability GFXMMU outter cachability
+/** @defgroup GFXMMU_OutterCachability GFXMMU outer cachability
* @{
*/
-#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U /*!< No cachable */
-#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC /*!< Cachable */
+#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U /*!< No cacheable */
+#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC /*!< Cacheable */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_hcd.h b/Inc/stm32h7xx_hal_hcd.h
index fa00ecc..8286262 100644
--- a/Inc/stm32h7xx_hal_hcd.h
+++ b/Inc/stm32h7xx_hal_hcd.h
@@ -33,7 +33,7 @@
* @{
*/
-/** @addtogroup HCD
+/** @addtogroup HCD HCD
* @{
*/
@@ -112,6 +112,10 @@
#define HCD_SPEED_FULL USBH_FSLS_SPEED
#define HCD_SPEED_LOW USBH_FSLS_SPEED
+#define HCD_DEVICE_SPEED_HIGH 0U
+#define HCD_DEVICE_SPEED_FULL 1U
+#define HCD_DEVICE_SPEED_LOW 2U
+
/**
* @}
*/
@@ -143,9 +147,9 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Macros HCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
@@ -214,10 +218,16 @@
* @}
*/
-HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID,
+ pHCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+ pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
@@ -267,6 +277,7 @@
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+
/**
* @}
*/
@@ -277,38 +288,19 @@
/* Private macros ------------------------------------------------------------*/
/** @defgroup HCD_Private_Macros HCD Private Macros
- * @{
- */
-
+ * @{
+ */
/**
* @}
*/
-
/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
- * @{
- */
/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HCD_Private_Functions HCD Private Functions
- * @{
- */
-
+ * @}
+ */
/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
+ * @}
+ */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus
diff --git a/Inc/stm32h7xx_hal_hrtim.h b/Inc/stm32h7xx_hal_hrtim.h
index c2be7a5..798ad82 100644
--- a/Inc/stm32h7xx_hal_hrtim.h
+++ b/Inc/stm32h7xx_hal_hrtim.h
@@ -946,7 +946,7 @@
* @{
* @brief Constants defining the polarity of a timer output
*/
-#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */
+#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */
#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
/**
* @}
diff --git a/Inc/stm32h7xx_hal_i2c.h b/Inc/stm32h7xx_hal_i2c.h
index d510a6d..9962ac1 100644
--- a/Inc/stm32h7xx_hal_i2c.h
+++ b/Inc/stm32h7xx_hal_i2c.h
@@ -495,7 +495,8 @@
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
@@ -521,7 +522,8 @@
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+ (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
@@ -541,7 +543,7 @@
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
@@ -583,7 +585,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+ pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
@@ -598,49 +601,70 @@
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@@ -732,7 +756,8 @@
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
@@ -743,13 +768,15 @@
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+ (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
diff --git a/Inc/stm32h7xx_hal_i2c_ex.h b/Inc/stm32h7xx_hal_i2c_ex.h
index 797cd4c..7909980 100644
--- a/Inc/stm32h7xx_hal_i2c_ex.h
+++ b/Inc/stm32h7xx_hal_i2c_ex.h
@@ -38,7 +38,6 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
@@ -78,24 +77,51 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
-/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
+/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
* @{
*/
-
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+ * @{
+ */
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+ * @{
+ */
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
@@ -111,7 +137,7 @@
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
@@ -146,9 +172,6 @@
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
-
-
-
/**
* @}
*/
@@ -170,14 +193,6 @@
* @}
*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32h7xx_hal_irda.h b/Inc/stm32h7xx_hal_irda.h
index 1a82ca0..869f840 100644
--- a/Inc/stm32h7xx_hal_irda.h
+++ b/Inc/stm32h7xx_hal_irda.h
@@ -78,7 +78,8 @@
/**
* @brief HAL IRDA State definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
+ * @note HAL IRDA State value is a combination of 2 different substates:
+ * gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -89,7 +90,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -106,7 +107,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -250,7 +251,8 @@
Value is allowed for RxState only */
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
+ Value is result of combination (Or) between
+ gState and RxState values */
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
@@ -262,15 +264,15 @@
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
* @{
*/
-#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
+#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
@@ -573,9 +575,14 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((__HANDLE__)->Instance->CR3 |= (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -589,10 +596,14 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -608,8 +619,8 @@
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -623,9 +634,10 @@
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
+ & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
+ & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
diff --git a/Inc/stm32h7xx_hal_iwdg.h b/Inc/stm32h7xx_hal_iwdg.h
index 2157e77..93d3025 100644
--- a/Inc/stm32h7xx_hal_iwdg.h
+++ b/Inc/stm32h7xx_hal_iwdg.h
@@ -87,7 +87,6 @@
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-
/**
* @}
*/
@@ -100,7 +99,6 @@
* @}
*/
-
/**
* @}
*/
@@ -138,7 +136,7 @@
* @{
*/
/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
@@ -147,7 +145,7 @@
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_jpeg.h b/Inc/stm32h7xx_hal_jpeg.h
index 846609a..16176c3 100644
--- a/Inc/stm32h7xx_hal_jpeg.h
+++ b/Inc/stm32h7xx_hal_jpeg.h
@@ -399,7 +399,7 @@
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
- * @retval No retrun
+ * @retval No return
*/
#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
@@ -417,7 +417,7 @@
*
* @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
* located in the same IT enable register (CR register).
- * @retval No retrun
+ * @retval No return
*/
#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)
diff --git a/Inc/stm32h7xx_hal_lptim.h b/Inc/stm32h7xx_hal_lptim.h
index 20fcffa..7275614 100644
--- a/Inc/stm32h7xx_hal_lptim.h
+++ b/Inc/stm32h7xx_hal_lptim.h
@@ -379,10 +379,10 @@
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -532,7 +532,8 @@
* @retval Interrupt status.
*/
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @}
@@ -544,9 +545,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group1
- * @brief Initialization and Configuration functions.
- * @{
- */
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -559,9 +560,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group2
- * @brief Start-Stop operation functions.
- * @{
- */
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -615,9 +616,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group3
- * @brief Read operation functions.
- * @{
- */
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
@@ -627,9 +628,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group4
- * @brief LPTIM IRQ handler and callback functions.
- * @{
- */
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -644,7 +645,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
@@ -652,9 +654,9 @@
*/
/** @addtogroup LPTIM_Group5
- * @brief Peripheral State functions.
- * @{
- */
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
@@ -758,26 +760,26 @@
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
- ((((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
- || \
- (((__INSTANCE__) == LPTIM2) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
- || \
- (((__INSTANCE__) == LPTIM3) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSA) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSB))))
+ ((((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
+ || \
+ (((__INSTANCE__) == LPTIM2) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
+ || \
+ (((__INSTANCE__) == LPTIM3) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSA) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSB))))
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
- ((((__INSTANCE__) == LPTIM1) || \
- ((__INSTANCE__) == LPTIM2)) && \
- (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
+ ((((__INSTANCE__) == LPTIM1) || \
+ ((__INSTANCE__) == LPTIM2)) && \
+ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
/**
* @}
diff --git a/Inc/stm32h7xx_hal_mdma.h b/Inc/stm32h7xx_hal_mdma.h
index afd2aeb..2e5f8e1 100644
--- a/Inc/stm32h7xx_hal_mdma.h
+++ b/Inc/stm32h7xx_hal_mdma.h
@@ -82,7 +82,7 @@
this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
+ It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref MDMA_Source_burst
@note : the burst may be FIXED/INCR based on SourceInc value ,
@@ -90,7 +90,7 @@
BufferTransferLength */
uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers.
- It specifies the amount of data to be transferred in a single non interruptable
+ It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref MDMA_Destination_burst
@note : the burst may be FIXED/INCR based on DestinationInc value ,
@@ -509,7 +509,7 @@
#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
-#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
+#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel request Active flag */
/**
* @}
@@ -549,7 +549,7 @@
* @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
* @arg MDMA_FLAG_BT : Block Transfer complete flag.
* @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
- * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
+ * @arg MDMA_FLAG_CRQA : Channel request Active flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
diff --git a/Inc/stm32h7xx_hal_mmc.h b/Inc/stm32h7xx_hal_mmc.h
index b3dc7cc..db25542 100644
--- a/Inc/stm32h7xx_hal_mmc.h
+++ b/Inc/stm32h7xx_hal_mmc.h
@@ -15,14 +15,14 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_MMC_H
#define STM32H7xx_HAL_MMC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -52,9 +52,9 @@
HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
+ HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
-}HAL_MMC_StateTypeDef;
+} HAL_MMC_StateTypeDef;
/**
* @}
*/
@@ -102,7 +102,7 @@
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-}HAL_MMC_CardInfoTypeDef;
+} HAL_MMC_CardInfoTypeDef;
/**
* @brief MMC handle Structure definition
@@ -142,19 +142,19 @@
uint32_t Ext_CSD[128];
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Read_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Read_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Write_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Write_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
- void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
-#endif
-}MMC_HandleTypeDef;
+ void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+} MMC_HandleTypeDef;
/**
@@ -204,7 +204,7 @@
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-}HAL_MMC_CardCSDTypeDef;
+} HAL_MMC_CardCSDTypeDef;
/**
* @}
*/
@@ -225,7 +225,7 @@
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
-}HAL_MMC_CardCIDTypeDef;
+} HAL_MMC_CardCIDTypeDef;
/**
* @}
*/
@@ -247,7 +247,7 @@
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
-}HAL_MMC_CallbackIDTypeDef;
+} HAL_MMC_CallbackIDTypeDef;
/**
* @}
*/
@@ -255,11 +255,11 @@
/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
* @{
*/
-typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
+typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -282,13 +282,13 @@
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
+/*!< number of transferred bytes does not match the block length */
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
+/*!< command or if there was an attempt to access a locked card */
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
@@ -299,8 +299,8 @@
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
+#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
+/*!< of erase sequence command was received */
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
@@ -313,7 +313,7 @@
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -339,10 +339,12 @@
/**
* @brief
*/
-#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
-#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
+#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
+#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
+#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
+#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
+#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
+#define eMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
@@ -401,22 +403,22 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup MMC_Exported_macros MMC Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/** @brief Reset MMC handle state.
* @param __HANDLE__ MMC Handle.
* @retval None
*/
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @brief Enable the MMC device interrupt.
@@ -630,7 +632,7 @@
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
@@ -642,15 +644,21 @@
* @{
*/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
@@ -662,9 +670,10 @@
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/* MMC callback registering/unregistering */
-HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+ pMMC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -685,6 +694,7 @@
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
/**
* @}
*/
@@ -710,7 +720,8 @@
/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management
* @{
*/
-HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd,
+ uint32_t BlockEndAdd);
HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode);
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT);
@@ -731,7 +742,8 @@
/** @defgroup MMC_Private_Defines MMC Private Defines
* @{
*/
-
+#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61
+#define MMC_EXT_CSD_DATA_SEC_SIZE_POS 8
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_mmc_ex.h b/Inc/stm32h7xx_hal_mmc_ex.h
index b5c9424..256f986 100644
--- a/Inc/stm32h7xx_hal_mmc_ex.h
+++ b/Inc/stm32h7xx_hal_mmc_ex.h
@@ -22,7 +22,7 @@
#define STM32H7xx_HAL_MMC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -50,7 +50,7 @@
MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */
MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */
-}HAL_MMCEx_DMABuffer_MemoryTypeDef;
+} HAL_MMCEx_DMABuffer_MemoryTypeDef;
/**
@@ -60,8 +60,6 @@
/**
* @}
*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
* @{
@@ -70,10 +68,14 @@
/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
-HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
+HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0,
+ uint32_t *pDataBuffer1, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer);
void HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);
diff --git a/Inc/stm32h7xx_hal_nand.h b/Inc/stm32h7xx_hal_nand.h
index ccf984c..3141ec9 100644
--- a/Inc/stm32h7xx_hal_nand.h
+++ b/Inc/stm32h7xx_hal_nand.h
@@ -89,10 +89,10 @@
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
+ for 8 bits addressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
+ for 8 bits addressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
@@ -130,10 +130,10 @@
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
- void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
- void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
-#endif
+ void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
+ void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
+ void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
@@ -145,13 +145,13 @@
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
-}HAL_NAND_CallbackIDTypeDef;
+} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -160,8 +160,8 @@
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
@@ -175,7 +175,7 @@
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -191,7 +191,8 @@
*/
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
@@ -214,15 +215,23 @@
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@@ -230,9 +239,10 @@
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
-HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -277,19 +287,19 @@
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
-#define NAND_CMD_AREA_A 0x00U
-#define NAND_CMD_AREA_B 0x01U
-#define NAND_CMD_AREA_C 0x50U
-#define NAND_CMD_AREA_TRUE1 0x30U
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-#define NAND_CMD_WRITE0 0x80U
-#define NAND_CMD_WRITE_TRUE1 0x10U
-#define NAND_CMD_ERASE0 0x60U
-#define NAND_CMD_ERASE1 0xD0U
-#define NAND_CMD_READID 0x90U
-#define NAND_CMD_STATUS 0x70U
-#define NAND_CMD_LOCK_STATUS 0x7AU
-#define NAND_CMD_RESET 0xFFU
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS 0x00000100UL
@@ -314,7 +324,8 @@
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
diff --git a/Inc/stm32h7xx_hal_nor.h b/Inc/stm32h7xx_hal_nor.h
index 04a3800..d614cb0 100644
--- a/Inc/stm32h7xx_hal_nor.h
+++ b/Inc/stm32h7xx_hal_nor.h
@@ -120,10 +120,12 @@
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+ uint32_t CommandSet; /*!< NOR algorithm command set and control */
+
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
- void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
-#endif
+ void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
+ void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
} NOR_HandleTypeDef;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
@@ -134,13 +136,13 @@
{
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
-}HAL_NOR_CallbackIDTypeDef;
+} HAL_NOR_CallbackIDTypeDef;
/**
* @brief HAL NOR Callback pointer definition
*/
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -162,7 +164,7 @@
} while(0)
#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -177,7 +179,8 @@
*/
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
@@ -196,8 +199,10 @@
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
@@ -205,9 +210,10 @@
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/* NOR callback registering/unregistering */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -251,23 +257,23 @@
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x61)
-#define CFI2_ADDRESS ((uint16_t)0x62)
-#define CFI3_ADDRESS ((uint16_t)0x63)
-#define CFI4_ADDRESS ((uint16_t)0x64)
+#define CFI1_ADDRESS ((uint16_t)0x0061)
+#define CFI2_ADDRESS ((uint16_t)0x0062)
+#define CFI3_ADDRESS ((uint16_t)0x0063)
+#define CFI4_ADDRESS ((uint16_t)0x0064)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0)
-#define NOR_MEMORY_16B ((uint8_t)0x1)
+#define NOR_MEMORY_8B ((uint8_t)0x00)
+#define NOR_MEMORY_16B ((uint8_t)0x01)
/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
-#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
-#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
-#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
+#define NOR_MEMORY_ADRESS1 (0x60000000U)
+#define NOR_MEMORY_ADRESS2 (0x64000000U)
+#define NOR_MEMORY_ADRESS3 (0x68000000U)
+#define NOR_MEMORY_ADRESS4 (0x6C000000U)
/**
* @}
*/
@@ -284,7 +290,7 @@
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
- ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
diff --git a/Inc/stm32h7xx_hal_ospi.h b/Inc/stm32h7xx_hal_ospi.h
index 35da484..6d7471f 100644
--- a/Inc/stm32h7xx_hal_ospi.h
+++ b/Inc/stm32h7xx_hal_ospi.h
@@ -48,52 +48,52 @@
*/
typedef struct
{
- uint32_t FifoThreshold; /* This is the threshold used by the Peripheral to generate the interrupt
- indicating that data are available in reception or free place
- is available in transmission.
- This parameter can be a value between 1 and 32 */
- uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to
- quad mode on two different devices to increase the throughput.
- This parameter can be a value of @ref OSPI_DualQuad */
- uint32_t MemoryType; /* It indicates the external device type connected to the OSPI.
- This parameter can be a value of @ref OSPI_MemoryType */
- uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI,
- it corresponds to the number of address bits required to access
- the external device.
- This parameter can be a value between 1 and 32 */
- uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select
- must remain high between commands.
- This parameter can be a value between 1 and 8 */
- uint32_t FreeRunningClock; /* It enables or not the free running clock.
- This parameter can be a value of @ref OSPI_FreeRunningClock */
- uint32_t ClockMode; /* It indicates the level of clock when the chip select is released.
- This parameter can be a value of @ref OSPI_ClockMode */
- uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration.
- This parameter can be a value of @ref OSPI_WrapSize */
- uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating
- the external clock based on the AHB clock.
- This parameter can be a value between 1 and 256 */
- uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order
- to take in account external signal delays.
- This parameter can be a value of @ref OSPI_SampleShifting */
- uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data.
- This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
- uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and
- defines the boundary of bytes to release the chip select.
- This parameter can be a value between 0 and 31 */
- uint32_t ClkChipSelectHighTime; /* It defines the number of clocks provided on the CLK/nCLK pins when
- the chip select is set to high at the end of a transaction.
- This parameter can be a value between 0 and 7 */
- uint32_t DelayBlockBypass; /* It enables the delay block bypass, so the sampling is not affected
- by the delay block.
- This parameter can be a value of @ref OSPI_DelayBlockBypass */
- uint32_t MaxTran; /* It enables the communication regulation feature. The chip select is
- released every MaxTran+1 bytes when the other OctoSPI request the access
- to the bus.
- This parameter can be a value between 0 and 255 */
- uint32_t Refresh; /* It enables the refresh rate feature. The chip select is released every
- Refresh+1 clock cycles.
- This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt
+ indicating that data are available in reception or free place
+ is available in transmission.
+ This parameter can be a value between 1 and 32 */
+ uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to
+ quad mode on two different devices to increase the throughput.
+ This parameter can be a value of @ref OSPI_DualQuad */
+ uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI.
+ This parameter can be a value of @ref OSPI_MemoryType */
+ uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI,
+ it corresponds to the number of address bits required to access
+ the external device.
+ This parameter can be a value between 1 and 32 */
+ uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select
+ must remain high between commands.
+ This parameter can be a value between 1 and 8 */
+ uint32_t FreeRunningClock; /*!< It enables or not the free running clock.
+ This parameter can be a value of @ref OSPI_FreeRunningClock */
+ uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released.
+ This parameter can be a value of @ref OSPI_ClockMode */
+ uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration.
+ This parameter can be a value of @ref OSPI_WrapSize */
+ uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating
+ the external clock based on the AHB clock.
+ This parameter can be a value between 1 and 256 */
+ uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order
+ to take in account external signal delays.
+ This parameter can be a value of @ref OSPI_SampleShifting */
+ uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data.
+ This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
+ uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and
+ defines the boundary of bytes to release the chip select.
+ This parameter can be a value between 0 and 31 */
+ uint32_t ClkChipSelectHighTime; /*!< It defines the number of clocks provided on the CLK/nCLK pins when
+ the chip select is set to high at the end of a transaction.
+ This parameter can be a value between 0 and 7 */
+ uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected
+ by the delay block.
+ This parameter can be a value of @ref OSPI_DelayBlockBypass */
+ uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is
+ released every MaxTran+1 bytes when the other OctoSPI request the access
+ to the bus.
+ This parameter can be a value between 0 and 255 */
+ uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
+ Refresh+1 clock cycles.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
}OSPI_InitTypeDef;
/**
@@ -103,17 +103,17 @@
typedef struct __OSPI_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
{
- OCTOSPI_TypeDef *Instance; /* OSPI registers base address */
- OSPI_InitTypeDef Init; /* OSPI initialization parameters */
- uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */
- __IO uint32_t XferSize; /* Number of data to transfer */
- __IO uint32_t XferCount; /* Counter of data transferred */
- MDMA_HandleTypeDef *hmdma; /* Handle of the MDMA channel used for the transfer */
- __IO uint32_t State; /* Internal state of the OSPI HAL driver */
- __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */
- uint32_t Timeout; /* Timeout used for the OSPI external device access */
+ OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */
+ OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */
+ uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */
+ __IO uint32_t XferSize; /*!< Number of data to transfer */
+ __IO uint32_t XferCount; /*!< Counter of data transferred */
+ MDMA_HandleTypeDef *hmdma; /*!< Handle of the MDMA channel used for the transfer */
+ __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */
+ __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
+ uint32_t Timeout; /*!< Timeout used for the OSPI external device access */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
@@ -128,7 +128,7 @@
void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}OSPI_HandleTypeDef;
/**
@@ -136,50 +136,50 @@
*/
typedef struct
{
- uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or
- to the registers for the write operation (these registers are only
- used for memory-mapped mode).
- This parameter can be a value of @ref OSPI_OperationType */
- uint32_t FlashId; /* It indicates which external device is selected for this command (it
- applies only if Dualquad is disabled in the initialization structure).
- This parameter can be a value of @ref OSPI_FlashId */
- uint32_t Instruction; /* It contains the instruction to be sent to the device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t InstructionMode; /* It indicates the mode of the instruction.
- This parameter can be a value of @ref OSPI_InstructionMode */
- uint32_t InstructionSize; /* It indicates the size of the instruction.
- This parameter can be a value of @ref OSPI_InstructionSize */
- uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase.
- This parameter can be a value of @ref OSPI_InstructionDtrMode */
- uint32_t Address; /* It contains the address to be sent to the device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t AddressMode; /* It indicates the mode of the address.
- This parameter can be a value of @ref OSPI_AddressMode */
- uint32_t AddressSize; /* It indicates the size of the address.
- This parameter can be a value of @ref OSPI_AddressSize */
- uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase.
- This parameter can be a value of @ref OSPI_AddressDtrMode */
- uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes.
- This parameter can be a value of @ref OSPI_AlternateBytesMode */
- uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes.
- This parameter can be a value of @ref OSPI_AlternateBytesSize */
- uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase.
- This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
- uint32_t DataMode; /* It indicates the mode of the data.
- This parameter can be a value of @ref OSPI_DataMode */
- uint32_t NbData; /* It indicates the number of data transferred with this command.
- This field is only used for indirect mode.
- This parameter can be a value between 1 and 0xFFFFFFFF */
- uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase.
- This parameter can be a value of @ref OSPI_DataDtrMode */
- uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase.
- This parameter can be a value between 0 and 31 */
- uint32_t DQSMode; /* It enables or not the data strobe management.
- This parameter can be a value of @ref OSPI_DQSMode */
- uint32_t SIOOMode; /* It enables or not the SIOO mode.
- This parameter can be a value of @ref OSPI_SIOOMode */
+ uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or
+ to the registers for the write operation (these registers are only
+ used for memory-mapped mode).
+ This parameter can be a value of @ref OSPI_OperationType */
+ uint32_t FlashId; /*!< It indicates which external device is selected for this command (it
+ applies only if Dualquad is disabled in the initialization structure).
+ This parameter can be a value of @ref OSPI_FlashID */
+ uint32_t Instruction; /*!< It contains the instruction to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
+ This parameter can be a value of @ref OSPI_InstructionMode */
+ uint32_t InstructionSize; /*!< It indicates the size of the instruction.
+ This parameter can be a value of @ref OSPI_InstructionSize */
+ uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
+ This parameter can be a value of @ref OSPI_InstructionDtrMode */
+ uint32_t Address; /*!< It contains the address to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AddressMode; /*!< It indicates the mode of the address.
+ This parameter can be a value of @ref OSPI_AddressMode */
+ uint32_t AddressSize; /*!< It indicates the size of the address.
+ This parameter can be a value of @ref OSPI_AddressSize */
+ uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
+ This parameter can be a value of @ref OSPI_AddressDtrMode */
+ uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
+ This parameter can be a value of @ref OSPI_AlternateBytesMode */
+ uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes.
+ This parameter can be a value of @ref OSPI_AlternateBytesSize */
+ uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase.
+ This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
+ uint32_t DataMode; /*!< It indicates the mode of the data.
+ This parameter can be a value of @ref OSPI_DataMode */
+ uint32_t NbData; /*!< It indicates the number of data transferred with this command.
+ This field is only used for indirect mode.
+ This parameter can be a value between 1 and 0xFFFFFFFF */
+ uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
+ This parameter can be a value of @ref OSPI_DataDtrMode */
+ uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase.
+ This parameter can be a value between 0 and 31 */
+ uint32_t DQSMode; /*!< It enables or not the data strobe management.
+ This parameter can be a value of @ref OSPI_DQSMode */
+ uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
+ This parameter can be a value of @ref OSPI_SIOOMode */
}OSPI_RegularCmdTypeDef;
/**
@@ -187,14 +187,14 @@
*/
typedef struct
{
- uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time.
- This parameter can be a value between 0 and 255 */
- uint32_t AccessTime; /* It indicates the number of cycles for the device acces time.
- This parameter can be a value between 0 and 255 */
- uint32_t WriteZeroLatency; /* It enables or not the latency for the write access.
- This parameter can be a value of @ref OSPI_WriteZeroLatency */
- uint32_t LatencyMode; /* It configures the latency mode.
- This parameter can be a value of @ref OSPI_LatencyMode */
+ uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time.
+ This parameter can be a value between 0 and 255 */
+ uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time.
+ This parameter can be a value between 0 and 255 */
+ uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access.
+ This parameter can be a value of @ref OSPI_WriteZeroLatency */
+ uint32_t LatencyMode; /*!< It configures the latency mode.
+ This parameter can be a value of @ref OSPI_LatencyMode */
}OSPI_HyperbusCfgTypeDef;
/**
@@ -202,18 +202,18 @@
*/
typedef struct
{
- uint32_t AddressSpace; /* It indicates the address space accessed by the command.
- This parameter can be a value of @ref OSPI_AddressSpace */
- uint32_t Address; /* It contains the address to be sent tot he device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t AddressSize; /* It indicates the size of the address.
- This parameter can be a value of @ref OSPI_AddressSize */
- uint32_t NbData; /* It indicates the number of data transferred with this command.
- This field is only used for indirect mode.
- This parameter can be a value between 1 and 0xFFFFFFFF
- In case of autopolling mode, this parameter can be any value between 1 and 4 */
- uint32_t DQSMode; /* It enables or not the data strobe management.
- This parameter can be a value of @ref OSPI_DQSMode */
+ uint32_t AddressSpace; /*!< It indicates the address space accessed by the command.
+ This parameter can be a value of @ref OSPI_AddressSpace */
+ uint32_t Address; /*!< It contains the address to be sent tot he device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AddressSize; /*!< It indicates the size of the address.
+ This parameter can be a value of @ref OSPI_AddressSize */
+ uint32_t NbData; /*!< It indicates the number of data transferred with this command.
+ This field is only used for indirect mode.
+ This parameter can be a value between 1 and 0xFFFFFFFF
+ In case of autopolling mode, this parameter can be any value between 1 and 4 */
+ uint32_t DQSMode; /*!< It enables or not the data strobe management.
+ This parameter can be a value of @ref OSPI_DQSMode */
}OSPI_HyperbusCmdTypeDef;
/**
@@ -221,16 +221,16 @@
*/
typedef struct
{
- uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t MatchMode; /* Specifies the method used for determining a match.
- This parameter can be a value of @ref OSPI_MatchMode */
- uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
- This parameter can be a value of @ref OSPI_AutomaticStop */
- uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
- This parameter can be any value between 0 and 0xFFFF */
+ uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t MatchMode; /*!< Specifies the method used for determining a match.
+ This parameter can be a value of @ref OSPI_MatchMode */
+ uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match.
+ This parameter can be a value of @ref OSPI_AutomaticStop */
+ uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases.
+ This parameter can be any value between 0 and 0xFFFF */
}OSPI_AutoPollingTypeDef;
/**
@@ -238,10 +238,10 @@
*/
typedef struct
{
- uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
- This parameter can be a value of @ref OSPI_TimeOutActivation */
- uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
- This parameter can be any value between 0 and 0xFFFF */
+ uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select.
+ This parameter can be a value of @ref OSPI_TimeOutActivation */
+ uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
}OSPI_MemoryMappedTypeDef;
/**
@@ -249,19 +249,19 @@
*/
typedef struct
{
- uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins.
- This parameter can be a value between 1 and 8 */
- uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin.
- This parameter can be a value between 1 and 8 */
- uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin.
- This parameter can be a value between 1 and 8 */
- uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.
- This parameter can be a value of @ref OSPIM_IOPort */
- uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
- This parameter can be a value of @ref OSPIM_IOPort */
- uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected
- if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
- This parameter can be a value between 1 and 256 */
+ uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins.
+ This parameter can be a value between 1 and 8 */
+ uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin.
+ This parameter can be a value between 0 and 8, 0 means that signal not used */
+ uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin.
+ This parameter can be a value between 1 and 8 */
+ uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.
+ This parameter can be a value of @ref OSPIM_IOPort */
+ uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
+ This parameter can be a value of @ref OSPIM_IOPort */
+ uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
+ if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
+ This parameter can be a value between 1 and 256 */
}OSPIM_CfgTypeDef;
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@@ -289,7 +289,7 @@
* @brief HAL OSPI Callback pointer definition
*/
typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
*/
@@ -330,7 +330,7 @@
#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
/**
* @}
*/
@@ -658,6 +658,7 @@
/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port
* @{
*/
+#define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */
#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */
#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */
#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */
@@ -697,7 +698,7 @@
} while(0)
#else
#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/** @brief Enable the OSPI peripheral.
* @param __HANDLE__ specifies the OSPI Handle.
@@ -749,7 +750,8 @@
* @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
+ == (__INTERRUPT__))
/**
* @brief Check whether the selected OSPI flag is set or not.
@@ -764,7 +766,8 @@
* @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
* @retval None
*/
-#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
+#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
+ != 0U) ? SET : RESET)
/** @brief Clears the specified OSPI's flag status.
* @param __HANDLE__ specifies the OSPI Handle.
@@ -808,22 +811,22 @@
void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi);
/* OSPI command configuration functions */
-HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
-HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
/* OSPI indirect mode functions */
-HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData);
-HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData);
-HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData);
-HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
+HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
/* OSPI status flag polling mode functions */
-HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
-HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
+HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
/* OSPI memory-mapped mode functions */
HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
@@ -848,9 +851,10 @@
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/* OSPI callback registering/unregistering */
-HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
-#endif
+HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
+ pOSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
*/
@@ -875,7 +879,7 @@
/** @addtogroup OSPI_Exported_Functions_Group4
* @{
*/
-HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
/**
* @}
@@ -1033,7 +1037,10 @@
#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
-#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
+#define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U)
+
+#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \
+ ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \
diff --git a/Inc/stm32h7xx_hal_otfdec.h b/Inc/stm32h7xx_hal_otfdec.h
index ebd4ea7..3a49ef2 100644
--- a/Inc/stm32h7xx_hal_otfdec.h
+++ b/Inc/stm32h7xx_hal_otfdec.h
@@ -281,7 +281,7 @@
* @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
- #define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified combination of OTFDEC interrupt flags.
* @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
@@ -342,7 +342,8 @@
HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey);
HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode);
-HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey);
HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
@@ -355,7 +356,8 @@
*/
HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec);
uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
-HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config);
+HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config);
/**
* @}
*/
@@ -422,9 +424,9 @@
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY) || \
- ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \
- ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
- ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
+ ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \
+ ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
+ ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
/**
* @brief Verify the OTFDEC region index.
diff --git a/Inc/stm32h7xx_hal_pcd.h b/Inc/stm32h7xx_hal_pcd.h
index 821f8d9..7236566 100644
--- a/Inc/stm32h7xx_hal_pcd.h
+++ b/Inc/stm32h7xx_hal_pcd.h
@@ -187,9 +187,9 @@
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
@@ -199,12 +199,11 @@
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@@ -271,25 +270,41 @@
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_BcdCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_LpmCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -328,16 +343,24 @@
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type);
+
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -403,8 +426,8 @@
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
+ * @{
+ */
/**
* @}
diff --git a/Inc/stm32h7xx_hal_pssi.h b/Inc/stm32h7xx_hal_pssi.h
index 922fafa..cd50234 100644
--- a/Inc/stm32h7xx_hal_pssi.h
+++ b/Inc/stm32h7xx_hal_pssi.h
@@ -232,7 +232,7 @@
#define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */
#define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */
-#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disble */
+#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable */
#define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */
#define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */
diff --git a/Inc/stm32h7xx_hal_pwr_ex.h b/Inc/stm32h7xx_hal_pwr_ex.h
index 563a875..12f557a 100644
--- a/Inc/stm32h7xx_hal_pwr_ex.h
+++ b/Inc/stm32h7xx_hal_pwr_ex.h
@@ -233,13 +233,13 @@
/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
* @{
*/
-#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
+#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */
#if defined (SMPS)
-#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS only */
+#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */
#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
-#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
-#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
+#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
#endif /* defined (SMPS) */
diff --git a/Inc/stm32h7xx_hal_ramecc.h b/Inc/stm32h7xx_hal_ramecc.h
index 56250f8..1046ca8 100644
--- a/Inc/stm32h7xx_hal_ramecc.h
+++ b/Inc/stm32h7xx_hal_ramecc.h
@@ -264,8 +264,8 @@
* @}
*/
-/** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions
- * @brief Error informations functions
+/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions
+ * @brief Error information functions
* @{
*/
uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc);
@@ -278,8 +278,8 @@
* @}
*/
-/** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions
- * @brief Error informations functions
+/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions
+ * @brief Error information functions
* @{
*/
HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc);
diff --git a/Inc/stm32h7xx_hal_rcc.h b/Inc/stm32h7xx_hal_rcc.h
index f4d896d..6a589ee 100644
--- a/Inc/stm32h7xx_hal_rcc.h
+++ b/Inc/stm32h7xx_hal_rcc.h
@@ -7295,9 +7295,9 @@
/**
* @brief Macro to configure the External High Speed oscillator (__HSE__).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
+ * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL),
+ * the application software should wait on HSERDY flag to be set indicating
+ * that HSE clock is stable and can be used to clock the PLL and/or system clock.
* @note HSE state can not be changed if it is used directly or through the
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
@@ -7311,6 +7311,9 @@
* 6 HSE oscillator clock cycles.
* @arg RCC_HSE_ON: turn ON the HSE oscillator.
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+ * @arg RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*)
+ *
+ * (*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
*/
#if defined(RCC_CR_HSEEXT)
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
@@ -8070,6 +8073,16 @@
((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_NONE) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \
+ ((VALUE) == RCC_PLL1VCIRANGE_1) || \
+ ((VALUE) == RCC_PLL1VCIRANGE_2) || \
+ ((VALUE) == RCC_PLL1VCIRANGE_3))
+
+#define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM))
+
+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U)
+
#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
#if !defined(RCC_VER_2_0)
#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
diff --git a/Inc/stm32h7xx_hal_rcc_ex.h b/Inc/stm32h7xx_hal_rcc_ex.h
index cab6039..a08e3db 100644
--- a/Inc/stm32h7xx_hal_rcc_ex.h
+++ b/Inc/stm32h7xx_hal_rcc_ex.h
@@ -2403,7 +2403,11 @@
* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
* @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
*/
+#if defined(RCC_D3CCIPR_I2C4SEL)
#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
+#else
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL)))
+#endif /* RCC_D3CCIPR_I2C4SEL */
#if defined(I2C5)
/** @brief macro to configure the I2C5 clock (I2C5CLK).
@@ -3206,7 +3210,7 @@
MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
#else
#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
- MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+ MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
#endif /* RCC_D2CCIP2R_CECSEL */
/** @brief macro to get the CEC clock source.
@@ -4299,8 +4303,6 @@
#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \
((VALUE) == RCC_PLL3VCOMEDIUM))
-#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
-
#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \
((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \
diff --git a/Inc/stm32h7xx_hal_rng.h b/Inc/stm32h7xx_hal_rng.h
index c8b3608..fc4de1a 100644
--- a/Inc/stm32h7xx_hal_rng.h
+++ b/Inc/stm32h7xx_hal_rng.h
@@ -81,7 +81,7 @@
typedef struct __RNG_HandleTypeDef
#else
typedef struct
-#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
{
RNG_TypeDef *Instance; /*!< Register base address */
@@ -91,7 +91,7 @@
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
- __IO uint32_t ErrorCode; /*!< RNG Error code */
+ __IO uint32_t ErrorCode; /*!< RNG Error code */
uint32_t RandomNumber; /*!< Last Generated RNG Data */
@@ -171,14 +171,14 @@
/** @defgroup RNG_Error_Definition RNG Error Definition
* @{
*/
-#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
+#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
-#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
+#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
@@ -204,7 +204,7 @@
} while(0U)
#else
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @brief Enables the RNG peripheral.
@@ -285,9 +285,9 @@
*/
#if defined (RNG_CR_CONDRST)
-/* Include HASH HAL Extended module */
+/* Include RNG HAL Extended module */
#include "stm32h7xx_hal_rng_ex.h"
-#endif /* CONDRST */
+#endif /* RNG_CR_CONDRST */
/* Exported functions --------------------------------------------------------*/
/** @defgroup RNG_Exported_Functions RNG Exported Functions
* @{
@@ -303,7 +303,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+ pRNG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
@@ -350,8 +351,8 @@
((IT) == RNG_IT_SEI))
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
/**
* @brief Verify the RNG Clock Error Detection mode.
@@ -364,6 +365,16 @@
* @}
*/
+#if defined(RNG_CR_CONDRST)
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private functions
+ * @{
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
+/**
+ * @}
+ */
+#endif /* RNG_CR_CONDRST */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_rng_ex.h b/Inc/stm32h7xx_hal_rng_ex.h
index 4e47abb..1f7fc84 100644
--- a/Inc/stm32h7xx_hal_rng_ex.h
+++ b/Inc/stm32h7xx_hal_rng_ex.h
@@ -32,8 +32,8 @@
* @{
*/
-#if defined (RNG)
-#if defined (RNG_CR_CONDRST)
+#if defined(RNG)
+#if defined(RNG_CR_CONDRST)
/** @defgroup RNGEx RNGEx
* @brief RNG Extension HAL module driver
@@ -71,7 +71,7 @@
*/
/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal
- * programmable divider acting on the incoming RNG clock
+ * programmable divider acting on the incoming RNG clock
* @{
*/
#define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
@@ -184,8 +184,8 @@
/**
- * @}
- */
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
@@ -212,6 +212,11 @@
* @}
*/
+/** @addtogroup RNGEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
+
/**
* @}
*/
@@ -224,7 +229,11 @@
* @}
*/
-#endif /* CONDRST */
+/**
+ * @}
+ */
+
+#endif /* RNG_CR_CONDRST */
#endif /* RNG */
/**
diff --git a/Inc/stm32h7xx_hal_rtc_ex.h b/Inc/stm32h7xx_hal_rtc_ex.h
index 9476718..833ae6f 100644
--- a/Inc/stm32h7xx_hal_rtc_ex.h
+++ b/Inc/stm32h7xx_hal_rtc_ex.h
@@ -638,7 +638,7 @@
* @}
*/
-/** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Ouput Definitions
+/** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Output Definitions
* @{
*/
#if defined(RTC_CR_TAMPOE)
diff --git a/Inc/stm32h7xx_hal_sd.h b/Inc/stm32h7xx_hal_sd.h
index dd06788..83c97ab 100644
--- a/Inc/stm32h7xx_hal_sd.h
+++ b/Inc/stm32h7xx_hal_sd.h
@@ -22,7 +22,7 @@
#define STM32H7xx_HAL_SD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -56,9 +56,9 @@
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */
- HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
+ HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
-}HAL_SD_StateTypeDef;
+} HAL_SD_StateTypeDef;
/**
* @}
*/
@@ -110,7 +110,7 @@
uint32_t CardSpeed; /*!< Specifies the card Speed */
-}HAL_SD_CardInfoTypeDef;
+} HAL_SD_CardInfoTypeDef;
/**
* @brief SD handle Structure definition
@@ -148,22 +148,22 @@
uint32_t CID[4]; /*!< SD card identification number table */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
- void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Read_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Read_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Read_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Write_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Write_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
- void (* DriveTransceiver_1_8V_Callback) (FlagStatus status);
+ void (* DriveTransceiver_1_8V_Callback)(FlagStatus status);
#endif /* USE_SD_TRANSCEIVER */
- void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
- void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-}SD_HandleTypeDef;
+} SD_HandleTypeDef;
/**
* @}
@@ -211,7 +211,7 @@
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-}HAL_SD_CardCSDTypeDef;
+} HAL_SD_CardCSDTypeDef;
/**
* @}
*/
@@ -232,7 +232,7 @@
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
-}HAL_SD_CardCIDTypeDef;
+} HAL_SD_CardCIDTypeDef;
/**
* @}
*/
@@ -255,7 +255,7 @@
__IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */
__IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */
__IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */
-}HAL_SD_CardStatusTypeDef;
+} HAL_SD_CardStatusTypeDef;
/**
* @}
*/
@@ -277,7 +277,7 @@
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
-}HAL_SD_CallbackIDTypeDef;
+} HAL_SD_CallbackIDTypeDef;
/**
* @}
*/
@@ -285,7 +285,7 @@
/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
* @{
*/
-typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
+typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
#endif /* USE_SD_TRANSCEIVER */
@@ -315,13 +315,13 @@
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
+ /*!< number of transferred bytes does not match the block length */
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
+ /*!< command or if there was an attempt to access a locked card */
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
@@ -332,8 +332,8 @@
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
+#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
+ /*!< of erase sequence command was received */
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
@@ -342,7 +342,7 @@
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
@@ -397,9 +397,9 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros SD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/** @brief Reset SD handle state.
* @param __HANDLE__ SD Handle.
* @retval None
@@ -620,10 +620,10 @@
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_SD_Init (SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/**
* @}
@@ -633,23 +633,29 @@
* @{
*/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
-void HAL_SD_IRQHandler (SD_HandleTypeDef *hsd);
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
/* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd);
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
/* Callback to switch in 1.8V mode */
@@ -658,11 +664,12 @@
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* SD callback registering/unregistering */
-HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+ pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);
#if (USE_SD_TRANSCEIVER != 0U)
-HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);
#endif /* USE_SD_TRANSCEIVER */
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
@@ -684,10 +691,10 @@
* @{
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
-HAL_StatusTypeDef HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
@@ -704,7 +711,7 @@
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
-HAL_StatusTypeDef HAL_SD_Abort (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
/**
* @}
diff --git a/Inc/stm32h7xx_hal_sd_ex.h b/Inc/stm32h7xx_hal_sd_ex.h
index 800434e..9c71954 100644
--- a/Inc/stm32h7xx_hal_sd_ex.h
+++ b/Inc/stm32h7xx_hal_sd_ex.h
@@ -22,7 +22,7 @@
#define STM32H7xx_HAL_SD_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -50,17 +50,15 @@
SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */
SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */
-}HAL_SDEx_DMABuffer_MemoryTypeDef;
+} HAL_SDEx_DMABuffer_MemoryTypeDef;
/**
* @}
*/
-
/**
* @}
*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
* @{
@@ -70,10 +68,12 @@
* @{
*/
-HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1,
+ uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
+HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer);
void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);
void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
diff --git a/Inc/stm32h7xx_hal_sdram.h b/Inc/stm32h7xx_hal_sdram.h
index e53ade3..ba189d4 100644
--- a/Inc/stm32h7xx_hal_sdram.h
+++ b/Inc/stm32h7xx_hal_sdram.h
@@ -77,12 +77,12 @@
MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */
- void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */
- void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */
- void (* DmaXferCpltCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SDRAM DMA Xfer Complete callback */
- void (* DmaXferErrorCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SDRAM DMA Xfer Error callback */
-#endif
+ void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */
+ void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */
+ void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */
+ void (* DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma); /*!< SDRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma); /*!< SDRAM DMA Xfer Error callback */
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
} SDRAM_HandleTypeDef;
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
@@ -96,14 +96,14 @@
HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */
HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */
HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */
-}HAL_SDRAM_CallbackIDTypeDef;
+} HAL_SDRAM_CallbackIDTypeDef;
/**
* @brief HAL SDRAM Callback pointer definition
*/
typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
typedef void (*pSDRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -127,7 +127,7 @@
} while(0)
#else
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -161,22 +161,32 @@
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
/* SDRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+ pSDRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback);
-#endif
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+ pSDRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/**
* @}
@@ -188,7 +198,8 @@
/* SDRAM Control functions *****************************************************/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
-HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
diff --git a/Inc/stm32h7xx_hal_smartcard.h b/Inc/stm32h7xx_hal_smartcard.h
index fae3bd4..1c7aee8 100644
--- a/Inc/stm32h7xx_hal_smartcard.h
+++ b/Inc/stm32h7xx_hal_smartcard.h
@@ -52,7 +52,8 @@
where usart_ker_ckpres is the USART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+ This parameter @ref SMARTCARD_Word_Length can only be
+ set to 9 (8 data + 1 parity bits). */
uint32_t StopBits; /*!< Specifies the number of stop bits.
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
@@ -76,13 +77,14 @@
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
- uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
+ is selected. Selecting the single sample method increases
+ the receiver tolerance to clock deviations. This parameter can be a value
+ of @ref SMARTCARD_OneBit_Sampling. */
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
- This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
- by 2 to give the division factor of the source clock frequency */
+ This parameter can be any value from 0x01 to 0x1F. Prescaler value is
+ multiplied by 2 to give the division factor of the source clock frequency */
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
@@ -111,7 +113,7 @@
} SMARTCARD_InitTypeDef;
/**
- * @brief SMARTCARD advanced features initalization structure definition
+ * @brief SMARTCARD advanced features initialization structure definition
*/
typedef struct
{
@@ -141,14 +143,16 @@
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref SMARTCARD_MSB_First */
- uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
- relevant flag is available) or once guard time period has elapsed.
- This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+ uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
+ relevant flag is available) or once guard time period has elapsed.
+ This parameter can be a value
+ of @ref SMARTCARDEx_Transmission_Completion_Indication. */
} SMARTCARD_AdvFeatureInitTypeDef;
/**
* @brief HAL SMARTCARD State definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
+ * @note HAL SMARTCARD State value is a combination of 2 different substates:
+ * gState and RxState (see @ref SMARTCARD_State_Definition).
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -159,7 +163,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -176,7 +180,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -215,7 +219,8 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
- This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
+ This parameter can be a value of
+ @ref SMARTCARDEx_FIFO_mode. */
void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
@@ -227,12 +232,14 @@
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
+ Handle management and also related to Tx operations.
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
@@ -314,23 +321,26 @@
/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
* @{
*/
-#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
-#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
+ is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
+ use. Value is allowed for gState
+ and RxState */
#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
-#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
+ process is ongoing Not to be used for
+ neither gState nor RxState.
+ Value is result of combination (Or)
+ between gState and RxState values */
#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
- Value is allowed for gState only */
+ Value is allowed for gState only */
/**
* @}
*/
@@ -338,15 +348,15 @@
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
* @{
*/
-#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
+#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
@@ -666,7 +676,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
+ * guard time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -679,9 +690,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1UL <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -691,7 +709,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
+ * time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -704,9 +723,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -716,7 +742,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -729,8 +756,10 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
+ (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
+ & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
+ ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -740,7 +769,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -753,9 +783,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x01U)?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x02U)?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) &\
+ (0x01UL << (((uint16_t)(__INTERRUPT__))\
+ & SMARTCARD_IT_MASK))) != 0U)\
+ ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -1293,7 +1330,8 @@
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
- HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
diff --git a/Inc/stm32h7xx_hal_smbus.h b/Inc/stm32h7xx_hal_smbus.h
index c82c44b..426760d 100644
--- a/Inc/stm32h7xx_hal_smbus.h
+++ b/Inc/stm32h7xx_hal_smbus.h
@@ -65,7 +65,7 @@
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
@@ -358,7 +358,8 @@
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
-#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \
+ SMBUS_IT_TXI)
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
@@ -408,10 +409,10 @@
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
#endif
@@ -462,7 +463,8 @@
*
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SMBUS flag is set or not.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -488,7 +490,8 @@
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -539,15 +542,15 @@
*/
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
- ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
- ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
((MASK) == SMBUS_OA2_MASK01) || \
@@ -565,47 +568,49 @@
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
- ((PEC) == SMBUS_PEC_ENABLE))
+ ((PEC) == SMBUS_PEC_ENABLE))
-#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
- ((MODE) == SMBUS_AUTOEND_MODE) || \
- ((MODE) == SMBUS_SOFTEND_MODE) || \
- ((MODE) == SMBUS_SENDPEC_MODE) || \
- ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == SMBUS_SENDPEC_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
- ((REQUEST) == SMBUS_GENERATE_START_READ) || \
- ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
- ((REQUEST) == SMBUS_NO_STARTSTOP))
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
- ((REQUEST) == SMBUS_FIRST_FRAME) || \
- ((REQUEST) == SMBUS_NEXT_FRAME) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
+ (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
@@ -613,7 +618,8 @@
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+ ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
@@ -629,8 +635,8 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
+ * @{
+ */
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
@@ -642,7 +648,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+ pSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
@@ -653,28 +660,33 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
+ * @{
+ */
/* IO operation functions *****************************************************/
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
- * @{
- */
+ * @{
+ */
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
/**
* @}
*/
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
- * @{
- */
+ * @{
+ */
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
@@ -685,8 +697,8 @@
*/
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
@@ -703,8 +715,8 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
+ * @{
+ */
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
diff --git a/Inc/stm32h7xx_hal_spi.h b/Inc/stm32h7xx_hal_spi.h
index c7aa154..fb4e2c5 100644
--- a/Inc/stm32h7xx_hal_spi.h
+++ b/Inc/stm32h7xx_hal_spi.h
@@ -274,7 +274,7 @@
#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */
#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */
#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */
-#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknow error */
+#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */
#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */
diff --git a/Inc/stm32h7xx_hal_sram.h b/Inc/stm32h7xx_hal_sram.h
index d8d44f1..6384026 100644
--- a/Inc/stm32h7xx_hal_sram.h
+++ b/Inc/stm32h7xx_hal_sram.h
@@ -61,7 +61,7 @@
typedef struct __SRAM_HandleTypeDef
#else
typedef struct
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
@@ -76,11 +76,11 @@
MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
- void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
- void (* DmaXferCpltCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SRAM DMA Xfer Complete callback */
- void (* DmaXferErrorCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SRAM DMA Xfer Error callback */
-#endif
+ void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
+ void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
+ void (* DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma); /*!< SRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma); /*!< SRAM DMA Xfer Error callback */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
} SRAM_HandleTypeDef;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
@@ -93,14 +93,14 @@
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
-}HAL_SRAM_CallbackIDTypeDef;
+} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
*/
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -109,8 +109,8 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
@@ -124,7 +124,7 @@
} while(0)
#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
@@ -136,11 +136,12 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
@@ -150,36 +151,46 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @{
- */
+ * @{
+ */
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
-#endif
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
- * @{
- */
+ * @{
+ */
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
@@ -190,8 +201,8 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
+ * @{
+ */
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
diff --git a/Inc/stm32h7xx_hal_tim.h b/Inc/stm32h7xx_hal_tim.h
index aee9f74..2e93e31 100644
--- a/Inc/stm32h7xx_hal_tim.h
+++ b/Inc/stm32h7xx_hal_tim.h
@@ -396,35 +396,35 @@
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
- ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
- ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
+ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
@@ -907,7 +907,7 @@
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
(if none of the break inputs BRK and BRK2 is active) */
/**
* @}
@@ -1066,24 +1066,24 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
@@ -2062,7 +2062,7 @@
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
-
+
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
@@ -2085,7 +2085,7 @@
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
-
+
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
diff --git a/Inc/stm32h7xx_hal_uart.h b/Inc/stm32h7xx_hal_uart.h
index a707583..103cb1b 100644
--- a/Inc/stm32h7xx_hal_uart.h
+++ b/Inc/stm32h7xx_hal_uart.h
@@ -46,51 +46,54 @@
*/
typedef struct
{
- uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate register is computed using the following formula:
- LPUART:
- =======
- Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
- where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
- UART:
- =====
- - If oversampling is 16 or in LIN mode,
- Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
- - If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
- Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
- where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ LPUART:
+ =======
+ Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+ where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+ UART:
+ =====
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck_pres is the UART input clock divided by a prescaler */
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UARTEx_Word_Length. */
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length. */
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits. */
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits. */
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode. */
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode. */
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling. */
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+ to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling. */
- uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
- uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
- This parameter can be a value of @ref UART_ClockPrescaler. */
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
+ This parameter can be a value of @ref UART_ClockPrescaler. */
} UART_InitTypeDef;
@@ -101,7 +104,8 @@
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
Advanced Features may be initialized at the same time .
- This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
+ This parameter can be a value of
+ @ref UART_Advanced_Features_Initialization_Type. */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref UART_Tx_Inv. */
@@ -135,7 +139,8 @@
/**
* @brief HAL UART State definition
- * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
+ * @note HAL UART State value is a combination of 2 different substates:
+ * gState and RxState (see @ref UART_State_Definition).
* - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -146,7 +151,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -163,7 +168,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -191,6 +196,17 @@
} UART_ClockSourceTypeDef;
/**
+ * @brief HAL UART Reception type definition
+ * @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
+ * It is expected to admit following values :
+ * HAL_UART_RECEPTION_STANDARD = 0x00U,
+ * HAL_UART_RECEPTION_TOIDLE = 0x01U,
+ * HAL_UART_RECEPTION_TORTO = 0x02U,
+ * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
+ */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -222,6 +238,8 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -233,11 +251,11 @@
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ and also related to Tx operations. This parameter
+ can be a value of @ref HAL_UART_StateTypeDef */
- __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This
+ parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO uint32_t ErrorCode; /*!< UART Error code */
@@ -253,6 +271,7 @@
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
+ void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
@@ -286,7 +305,9 @@
/**
* @brief HAL UART Callback pointer definition
*/
-typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -313,8 +334,8 @@
#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
+ Not to be used for neither gState nor RxState.Value is result
+ of combination (Or) between gState and RxState values */
#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
@@ -326,16 +347,16 @@
/** @defgroup UART_Error_Definition UART Error Definition
* @{
*/
-#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
-#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
+#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@@ -432,10 +453,14 @@
/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
* @{
*/
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection
+ on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection
+ on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection
+ on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection
+ on 0x55 frame detection */
/**
* @}
*/
@@ -597,8 +622,10 @@
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
-#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
-#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received
+ first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received
+ first enable */
/**
* @}
*/
@@ -624,7 +651,7 @@
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
* @{
*/
-#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
+#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
/**
* @}
*/
@@ -632,9 +659,10 @@
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
* @{
*/
-#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
-#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
-#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
+#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register
+ not empty or RXFIFO is not empty */
/**
* @}
*/
@@ -651,7 +679,8 @@
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB
+ position in CR1 register */
/**
* @}
*/
@@ -659,7 +688,8 @@
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB
+ position in CR1 register */
/**
* @}
*/
@@ -734,28 +764,28 @@
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
-#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
-#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
-#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */
-#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
-#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
-#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */
-#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
-#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
-#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
-#define UART_IT_CM 0x112EU /*!< UART character match interruption */
-#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
-#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */
-#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
-#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
-#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
-#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
+#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
+#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */
+#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
+#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */
+#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
+#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
+#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
+#define UART_IT_CM 0x112EU /*!< UART character match interruption */
+#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
+#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */
+#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
+#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
+#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
+#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
-#define UART_IT_ERR 0x0060U /*!< UART error interruption */
+#define UART_IT_ERR 0x0060U /*!< UART error interruption */
-#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
-#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
-#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
+#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
+#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
+#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
/**
* @}
*/
@@ -779,6 +809,16 @@
* @}
*/
+/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+ * @{
+ */
+#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
+#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
+#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
+#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
+/**
+ * @}
+ */
/**
* @}
@@ -930,10 +970,15 @@
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
@@ -958,9 +1003,15 @@
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+ ((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__ specifies the UART Handle.
@@ -1011,9 +1062,13 @@
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U <<\
+ (((uint16_t)(__INTERRUPT__)) &\
+ UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
@@ -1080,8 +1135,9 @@
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -1098,8 +1154,9 @@
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -1116,8 +1173,9 @@
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -1134,8 +1192,9 @@
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * - macro could only be called when corresponding UART instance is disabled
+ * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+ * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -1170,15 +1229,16 @@
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
-
/** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\
- + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \
+ )
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock.
@@ -1186,8 +1246,8 @@
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\
- + ((__BAUD__)/2U)) / (__BAUD__))
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock.
@@ -1195,8 +1255,8 @@
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\
- + ((__BAUD__)/2U)) / (__BAUD__))
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
+ ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
* @param __HANDLE__ specifies the UART Handle.
@@ -1437,8 +1497,9 @@
* @param __AUTOBAUDRATE__ UART auto Baud rate state.
* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
*/
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
- ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
+ UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
/**
* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
@@ -1514,12 +1575,6 @@
/* Include UART HAL Extended module */
#include "stm32h7xx_hal_uart_ex.h"
-
-/* Prescaler Table used in BRR computation macros.
- Declared as extern here to allow use of private UART macros, outside of HAL UART fonctions */
-extern const uint16_t UARTPrescTable[12];
-
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
@@ -1543,6 +1598,9 @@
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@@ -1581,6 +1639,8 @@
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
/**
* @}
*/
@@ -1626,13 +1686,28 @@
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/**
+ * @}
+ */
+
+/* Private variables -----------------------------------------------------------*/
+/** @defgroup UART_Private_variables UART Private variables
+ * @{
+ */
+/* Prescaler Table used in BRR computation macros.
+ Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+
/**
* @}
diff --git a/Inc/stm32h7xx_hal_uart_ex.h b/Inc/stm32h7xx_hal_uart_ex.h
index a875a00..eb437f3 100644
--- a/Inc/stm32h7xx_hal_uart_ex.h
+++ b/Inc/stm32h7xx_hal_uart_ex.h
@@ -99,12 +99,12 @@
* @brief UART TXFIFO threshold level
* @{
*/
-#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
-#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
+#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
@@ -113,12 +113,12 @@
* @brief UART RXFIFO threshold level
* @{
*/
-#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
-#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
+#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
@@ -174,6 +174,12 @@
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_usart.h b/Inc/stm32h7xx_hal_usart.h
index 15b610e..6092ebe 100644
--- a/Inc/stm32h7xx_hal_usart.h
+++ b/Inc/stm32h7xx_hal_usart.h
@@ -48,11 +48,15 @@
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[15:4] = ((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
- where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.
- @note Oversampling by 8 is systematically applied to achieve high baud rates. */
+ Baud Rate Register[2:0] = (((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where fclk_pres is the USART input clock frequency (fclk)
+ divided by a prescaler.
+ @note Oversampling by 8 is systematically applied to
+ achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
@@ -218,17 +222,17 @@
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */
+#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
+#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@@ -264,15 +268,6 @@
* @}
*/
-/** @defgroup USART_Over_Sampling USART Over Sampling
- * @{
- */
-#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
/** @defgroup USART_Clock USART Clock
* @{
*/
@@ -552,9 +547,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
@@ -574,10 +572,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -600,7 +600,8 @@
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
+ & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
+ USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -622,10 +623,13 @@
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
-
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U <<\
+ (((uint16_t)(__INTERRUPT__)) &\
+ USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
@@ -709,11 +713,12 @@
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
- * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
-#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
- + ((__BAUD__)/2U)) / (__BAUD__))
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
+ (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
@@ -1015,14 +1020,6 @@
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
- * @brief Ensure that USART oversampling is valid.
- * @param __SAMPLING__ USART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == USART_OVERSAMPLING_8))
-
-/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
diff --git a/Inc/stm32h7xx_hal_usart_ex.h b/Inc/stm32h7xx_hal_usart_ex.h
index b698726..7691326 100644
--- a/Inc/stm32h7xx_hal_usart_ex.h
+++ b/Inc/stm32h7xx_hal_usart_ex.h
@@ -45,9 +45,9 @@
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_wwdg.h b/Inc/stm32h7xx_hal_wwdg.h
index c124855..061a62f 100644
--- a/Inc/stm32h7xx_hal_wwdg.h
+++ b/Inc/stm32h7xx_hal_wwdg.h
@@ -56,7 +56,7 @@
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
@@ -68,17 +68,17 @@
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
- void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
- void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
-#endif
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
@@ -87,8 +87,8 @@
*/
typedef enum
{
- HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
- HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
+ HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
@@ -96,7 +96,7 @@
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -268,9 +268,10 @@
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
diff --git a/Inc/stm32h7xx_ll_adc.h b/Inc/stm32h7xx_ll_adc.h
index f7e8c9c..f12b52a 100644
--- a/Inc/stm32h7xx_ll_adc.h
+++ b/Inc/stm32h7xx_ll_adc.h
@@ -371,7 +371,7 @@
/* Internal voltage reference VrefInt */
#if defined(ADC_VER_V5_3)
#define VREFINT_CAL_ADDR ((uint16_t*) (0x8fff810UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
- /* Adress related to STM32H7A3 */
+ /* Address related to STM32H7A3 */
#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#endif /* ADC_VER_V5_3 */
@@ -380,7 +380,7 @@
#if defined(ADC_VER_V5_3)
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
- /* Adresses related to STM32H7A3 */
+ /* Addresses related to STM32H7A3 */
#else /* ADC_VER_V5_90 || ADC_VER_V5_X */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
@@ -444,7 +444,7 @@
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
- @note On this STM32 serie, if ADC group injected is used, some
+ @note On this STM32 series, if ADC group injected is used, some
clock ratio constraints between ADC clock and AHB clock
must be respected. Refer to reference manual.
@@ -527,7 +527,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
@@ -587,7 +587,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
@@ -725,7 +725,7 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
@@ -785,7 +785,7 @@
#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 8 bits */
#else
#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */
- /*!< The resolution setting is managed internaly in the driver:
+ /*!< The resolution setting is managed internally in the driver:
"LL_ADC_RESOLUTION_8B" definition: keep using the "100b" value (corresponding to STM32H74x/5x rev Y).
Rev.V value "111b" is handled through functions "LL_ADC_SetResolution/LL_ADC_GetResolution" with a dedicated check on DBGMCU IDCODE register */
#endif
@@ -801,7 +801,7 @@
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -811,22 +811,22 @@
/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
* @{
*/
-#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC convesion data */
-#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */
+#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */
/**
* @}
*/
@@ -864,7 +864,7 @@
* @{
*/
#define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */
-#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shift is enabled (among ADC selected offset number 1, 2, 3 or 4) */
/**
* @}
*/
@@ -1501,7 +1501,7 @@
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
+/* STM32 series: */
/* - ADC calibration time: maximum delay is 16384/fADC. */
/* (refer to device datasheet, parameter "tCAL") */
/* - ADC enable time: maximum delay is 1 conversion cycle. */
@@ -1532,7 +1532,7 @@
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles */
/* are required between ADC end of calibration and ADC enable. */
/* Wait time can be computed in user application by waiting for the */
/* equivalent number of CPU cycles, by taking into account */
@@ -2388,7 +2388,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 16 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -2439,7 +2439,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 16 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -2611,11 +2611,11 @@
/**
* @brief Set parameter common to several ADC: Clock source and prescaler.
- * @note On this STM32 serie, if ADC group injected is used, some
+ * @note On this STM32 series, if ADC group injected is used, some
* clock ratio constraints between ADC clock and AHB clock
* must be respected.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2693,7 +2693,7 @@
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2766,7 +2766,7 @@
* both calibration factors must be concatenated.
* To perform this processing, use helper macro
* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
@@ -2829,7 +2829,7 @@
* @note This function is intended to set linear calibration parameters
* without having to perform a new calibration using
* @ref LL_ADC_StartCalibration().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
@@ -2904,7 +2904,7 @@
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3041,9 +3041,12 @@
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
- * - Do not use with interruption or DMA since these modes
- * have to clear immediately the EOC flag to free the
- * IRQ vector sequencer.
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@@ -3061,7 +3064,7 @@
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3094,9 +3097,12 @@
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
- * - Do not use with interruption or DMA since these modes
- * have to clear immediately the EOC flag to free the
- * IRQ vector sequencer.
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@@ -3185,7 +3191,7 @@
* to disable state using function LL_ADC_SetOffsetState().
* @note If a channel is mapped on several offsets numbers, only the offset
* with the lowest value is considered for the subtraction.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3468,7 +3474,7 @@
/**
* @brief Set for the ADC selected offset number 1, 2, 3 or 4:
* choose offset saturation mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3532,7 +3538,7 @@
/**
* @brief Set for the ADC selected offset number 1, 2, 3 or 4:
* choose offset sign.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3601,7 +3607,7 @@
* @note This function should be needed only in case of offset to be
* enabled-disabled dynamically, and should not be needed in other cases:
* function LL_ADC_SetOffset() automatically enables the offset.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3681,7 +3687,7 @@
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -3689,7 +3695,7 @@
* function @ref LL_ADC_REG_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3800,7 +3806,7 @@
/**
* @brief Set ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3837,8 +3843,8 @@
* @brief Set ADC sampling mode.
* @note This function set the ADC conversion sampling mode
* @note This mode applies to regular group only.
- * @note Set sampling mode is appied to all conversion of regular group.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note Set sampling mode is applied to all conversion of regular group.
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3893,7 +3899,7 @@
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3985,7 +3991,7 @@
* continuous mode and sequencer discontinuous mode.
* @note It is not possible to enable both ADC auto-injected mode
* and ADC group regular sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -4038,17 +4044,17 @@
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -4135,7 +4141,7 @@
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
@@ -4239,7 +4245,7 @@
* conversions launched successively automatically.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -4275,9 +4281,9 @@
* @brief Set ADC data transfer mode
* @note Conversion data can be either:
* - Available in Data Register
- * - Transfered by DMA in one shot mode
- * - Transfered by DMA in circular mode
- * - Transfered to DFSDM data register
+ * - Transferred by DMA in one shot mode
+ * - Transferred by DMA in circular mode
+ * - Transferred to DFSDM data register
* @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
* @param ADCx ADC instance
* @param DataTransferMode Select Data Management configuration
@@ -4331,7 +4337,7 @@
* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4400,9 +4406,9 @@
* @brief Get ADC data transfer mode
* @note Conversion data can be either:
* - Available in Data Register
- * - Transfered by DMA in one shot mode
- * - Transfered by DMA in circular mode
- * - Transfered to DFSDM data register
+ * - Transferred by DMA in one shot mode
+ * - Transferred by DMA in circular mode
+ * - Transferred to DFSDM data register
* @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
@@ -4426,7 +4432,7 @@
* The default setting of overrun is data preserved.
* Therefore, for compatibility with all devices, parameter
* overrun should be set to data overwritten.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -4468,7 +4474,7 @@
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -4476,7 +4482,7 @@
* function @ref LL_ADC_INJ_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4587,7 +4593,7 @@
/**
* @brief Set ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4627,7 +4633,7 @@
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4704,13 +4710,13 @@
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32H7, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4856,7 +4862,7 @@
* from ADC group regular.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4914,7 +4920,7 @@
* on either groups regular or injected.
* @note A modification of the context mode (bit JQDIS) causes the contexts
* queue to be flushed and the register JSQR is cleared.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4964,13 +4970,13 @@
* @arg @ref LL_ADC_INJ_GetTriggerSource()
* @arg @ref LL_ADC_INJ_GetTriggerEdge()
* @arg @ref LL_ADC_INJ_GetSequencerRanks()
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32H7, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -5198,7 +5204,7 @@
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -5207,7 +5213,7 @@
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5292,7 +5298,7 @@
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -5391,7 +5397,7 @@
* @note For ADC channels configured in differential mode, both inputs
* should be biased at (Vref+)/2 +/-200mV.
* (Vref+ is the analog voltage reference)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @note One or several values can be selected.
@@ -5516,7 +5522,7 @@
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5537,7 +5543,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5667,7 +5673,7 @@
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5688,7 +5694,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5839,7 +5845,7 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5865,7 +5871,7 @@
* on oversampling intermediate computation (after ratio, before shift
* application): intermediate register bitfield [32:7]
* (26 most significant bits).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either ADC groups regular or injected.
@@ -5979,7 +5985,7 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -6047,12 +6053,12 @@
/**
* @brief Set ADC analog watchdog filtering configuration
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
- * @note On this STM32 serie, this feature is only available on first
+ * @note On this STM32 series, this feature is only available on first
* analog watchdog (AWD1)
* @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
* @param ADCx ADC instance
@@ -6081,7 +6087,7 @@
/**
* @brief Get ADC analog watchdog filtering configuration
- * @note On this STM32 serie, this feature is only available on first
+ * @note On this STM32 series, this feature is only available on first
* analog watchdog (AWD1)
* Applicable on ADC3 of devices STM32H72xx and STM32H73xx.
* @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
@@ -6130,7 +6136,7 @@
* the oversampling on ADC group regular is either
* temporary stopped and continued, or resumed from start
* (oversampler buffer reset).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -6184,11 +6190,11 @@
* are done from 1 trigger)
* - discontinuous mode (each conversion of oversampling ratio
* needs a trigger)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
- * @note On this STM32 serie, oversampling discontinuous mode
+ * @note On this STM32 series, oversampling discontinuous mode
* (triggered mode) can be used only when oversampling is
* set on group regular only and in resumed mode.
* @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
@@ -6228,7 +6234,7 @@
* @note This function set the 2 items of oversampling configuration:
* - ratio
* - shift
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -6301,7 +6307,7 @@
*/
/**
* @brief Set ADC boost mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC boost must be configured, without calibration on going, without conversion
* on going on group regular.
@@ -6337,7 +6343,7 @@
/**
* @brief Get ADC boost mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC boost must be configured, without calibration on going, without conversion
* on going on group regular.
@@ -6363,7 +6369,7 @@
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -6442,7 +6448,7 @@
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled
* or enabled without conversion on going on group regular.
@@ -6510,7 +6516,7 @@
* - ADC resolution 10 bits can have maximum delay of 10 cycles.
* - ADC resolution 8 bits can have maximum delay of 8 cycles.
* - ADC resolution 6 bits can have maximum delay of 6 cycles.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -6594,7 +6600,7 @@
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
@@ -6617,7 +6623,7 @@
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
@@ -6645,12 +6651,12 @@
/**
* @brief Enable ADC instance internal voltage regulator.
- * @note On this STM32 serie, after ADC internal voltage regulator enable,
+ * @note On this STM32 series, after ADC internal voltage regulator enable,
* a delay for ADC internal voltage regulator stabilization
* is required before performing a ADC calibration or ADC enable.
* Refer to device datasheet, parameter tADCVREG_STUP.
* Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
@@ -6669,7 +6675,7 @@
/**
* @brief Disable ADC internal voltage regulator.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
@@ -6694,14 +6700,14 @@
/**
* @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
+ * @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled and ADC internal voltage regulator enabled.
* @rmtoll CR ADEN LL_ADC_Enable
@@ -6720,7 +6726,7 @@
/**
* @brief Disable the selected ADC instance.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be not disabled. Must be enabled without conversion on going
* on either groups regular or injected.
@@ -6740,7 +6746,7 @@
/**
* @brief Get the selected ADC instance enable state.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll CR ADEN LL_ADC_IsEnabled
@@ -6766,7 +6772,7 @@
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
- * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * @note On this STM32 series, a minimum number of ADC clock cycles
* are required between ADC end of calibration and ADC enable.
* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
* @note Calibration duration:
@@ -6781,7 +6787,7 @@
* Calibration of linearity is common to both
* single-ended and differential modes
* (calibration run can be performed only once).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
@@ -6827,14 +6833,14 @@
/**
* @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
@@ -6855,7 +6861,7 @@
/**
* @brief Stop ADC group regular conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group regular,
* without ADC disable command on going.
@@ -7022,14 +7028,14 @@
/**
* @brief Start ADC group injected conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group injected,
* without conversion stop command on going on group injected,
@@ -7050,7 +7056,7 @@
/**
* @brief Stop ADC group injected conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group injected,
* without ADC disable command on going.
@@ -7261,7 +7267,7 @@
/**
* @brief Get flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
@@ -7385,7 +7391,7 @@
/**
* @brief Clear flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
diff --git a/Inc/stm32h7xx_ll_bdma.h b/Inc/stm32h7xx_ll_bdma.h
index 9faa900..36910f2 100644
--- a/Inc/stm32h7xx_ll_bdma.h
+++ b/Inc/stm32h7xx_ll_bdma.h
@@ -1090,7 +1090,7 @@
/**
* @brief Configure the Source and Destination addresses.
* @note This API must not be called when the BDMA channel is enabled.
- * @note Each IP using BDMA provides an API to get directly the register adress (LL_PPP_BDMA_GetRegAddr).
+ * @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr).
* @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n
* CMAR MA LL_BDMA_ConfigAddresses
* @param BDMAx BDMA Instance
diff --git a/Inc/stm32h7xx_ll_comp.h b/Inc/stm32h7xx_ll_comp.h
index e75c0bd..beedbac 100644
--- a/Inc/stm32h7xx_ll_comp.h
+++ b/Inc/stm32h7xx_ll_comp.h
@@ -321,7 +321,7 @@
*/
__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
{
- /* Note: On this STM32 serie, window mode can be set only */
+ /* Note: On this STM32 series, window mode can be set only */
/* from COMP instance: COMP2. */
MODIFY_REG(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE, WindowMode);
}
@@ -391,7 +391,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, scaler bridge is configurable:
+ * @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
@@ -489,7 +489,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, scaler bridge is configurable:
+ * @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
diff --git a/Inc/stm32h7xx_ll_cordic.h b/Inc/stm32h7xx_ll_cordic.h
index b46705f..848a5dc 100644
--- a/Inc/stm32h7xx_ll_cordic.h
+++ b/Inc/stm32h7xx_ll_cordic.h
@@ -95,15 +95,21 @@
#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
-#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
-#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
-#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
+ | CORDIC_CSR_PRECISION_0))
/**
* @}
*/
@@ -127,8 +133,9 @@
* @{
*/
#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
- 32-bit data input (Q1.31 format), or two 16-bit
- data input (Q1.15 format) packed in one 32 bits Data */
+ 32-bit data input (Q1.31 format), or two
+ 16-bit data input (Q1.15 format) packed
+ in one 32 bits Data */
#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
(Q1.31 format) */
/**
@@ -139,8 +146,9 @@
* @{
*/
#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
- 32-bit data ouput (Q1.31 format), or two 16-bit
- data output (Q1.15 format) packed in one 32 bits Data */
+ 32-bit data output (Q1.31 format), or two
+ 16-bit data output (Q1.15 format) packed
+ in one 32 bits Data */
#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
(Q1.31 format) */
/**
@@ -240,7 +248,7 @@
* CSR NARGS LL_CORDIC_Configure\n
* CSR NRES LL_CORDIC_Configure\n
* CSR ARGSIZE LL_CORDIC_Configure\n
- * CSR RESSIZE LL_CORDIC_Configure
+ * CSR RESIZE LL_CORDIC_Configure
* @param CORDICx CORDIC instance
* @param Function parameter can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
@@ -292,7 +300,8 @@
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
* @retval None
*/
-__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
+__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale,
+ uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
{
MODIFY_REG(CORDICx->CSR,
CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |
@@ -519,7 +528,7 @@
/**
* @brief Configure width of output data.
- * @rmtoll CSR RESSIZE LL_CORDIC_SetOutSize
+ * @rmtoll CSR RESIZE LL_CORDIC_SetOutSize
* @param CORDICx CORDIC Instance
* @param OutSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
@@ -533,7 +542,7 @@
/**
* @brief Return width of output data.
- * @rmtoll CSR RESSIZE LL_CORDIC_GetOutSize
+ * @rmtoll CSR RESIZE LL_CORDIC_GetOutSize
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
@@ -676,12 +685,12 @@
if (Direction == LL_CORDIC_DMA_REG_DATA_OUT)
{
/* return address of RDATA register */
- data_reg_addr = (uint32_t) & (CORDICx->RDATA);
+ data_reg_addr = (uint32_t) &(CORDICx->RDATA);
}
else
{
/* return address of WDATA register */
- data_reg_addr = (uint32_t) & (CORDICx->WDATA);
+ data_reg_addr = (uint32_t) &(CORDICx->WDATA);
}
return data_reg_addr;
diff --git a/Inc/stm32h7xx_ll_crs.h b/Inc/stm32h7xx_ll_crs.h
index 14218c8..85e0fe7 100644
--- a/Inc/stm32h7xx_ll_crs.h
+++ b/Inc/stm32h7xx_ll_crs.h
@@ -94,7 +94,7 @@
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
-#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
diff --git a/Inc/stm32h7xx_ll_dac.h b/Inc/stm32h7xx_ll_dac.h
index 5870a17..d0c7421 100644
--- a/Inc/stm32h7xx_ll_dac.h
+++ b/Inc/stm32h7xx_ll_dac.h
@@ -53,8 +53,10 @@
/* - channel register offset of data holding register DHRx */
/* - channel register offset of data output register DORx */
/* - channel register offset of sample-and-hold sample time register SHSRx */
-#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
@@ -62,33 +64,54 @@
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 28 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
+ | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
-#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
+#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
+ DORx channel 2 (shifted left of 5 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
-#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
+#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
+ SHSRx channel 2 (shifted left of 6 bits) */
#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
-#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
-#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */
-#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */
+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
+ DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
+ to position 0 */
+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
+ to position 0 */
-#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
-#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
-#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 28 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
+ channel 1 or 2 versus DORx channel 1
+ (shifted left of 5 bits) */
+#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
+ channel 1 or 2 versus SHSRx channel 1
+ (shifted left of 6 bits) */
/* DAC registers bits positions */
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
@@ -96,7 +119,9 @@
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
+ bits (voltage range determined by analog voltage
+ references Vref+ and Vref-, refer to reference manual) */
/**
* @}
@@ -115,7 +140,7 @@
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
-*/
+ */
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
@@ -135,38 +160,50 @@
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
+ internal (SW start) or from external peripheral
+ (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetTriggerSource(). */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- @note If waveform automatic generation mode is disabled, this parameter is discarded.
+ If waveform automatic generation mode is set to noise, this parameter
+ can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle,
+ this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled,
+ this parameter is discarded.
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveNoiseLFSR(),
+ @ref LL_DAC_SetWaveTriangleAmplitude()
depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputBuffer(). */
uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputConnection(). */
- uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
+ uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
+ channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputMode(). */
} LL_DAC_InitTypeDef;
/**
@@ -326,7 +363,7 @@
* @{
*/
#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
-#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
+#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
/**
* @}
*/
@@ -479,22 +516,8 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
*/
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1UL) \
- ? ( \
- LL_DAC_CHANNEL_1 \
- ) \
- : \
- (((__DECIMAL_NB__) == 2UL) \
- ? ( \
- LL_DAC_CHANNEL_2 \
- ) \
- : \
- ( \
- 0UL \
- ) \
- ) \
- )
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
+ (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
/**
* @brief Helper macro to define the DAC conversion data full-scale digital
@@ -519,7 +542,7 @@
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
@@ -531,9 +554,9 @@
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
__DAC_VOLTAGE__,\
__DAC_RESOLUTION__) \
- ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
- )
+((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+)
/**
* @}
@@ -665,12 +688,12 @@
* @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3)
* @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
- * (2) On this STM32 serie, parameter only available on DAC2.
- * (3) On this STM32 serie, parameter not available on all devices.
+ * (2) On this STM32 series, parameter only available on DAC2.
+ * (3) On this STM32 series, parameter not available on all devices.
* Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
- * (4) On this STM32 serie, parameter not available on all devices.
+ * (4) On this STM32 series, parameter not available on all devices.
* Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
* @retval None
*/
@@ -712,12 +735,12 @@
* @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3)
* @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
- * (2) On this STM32 serie, parameter only available on DAC2.
- * (3) On this STM32 serie, parameter not available on all devices.
+ * (2) On this STM32 series, parameter only available on DAC2.
+ * (3) On this STM32 series, parameter not available on all devices.
* Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
- * (4) On this STM32 serie, parameter not available on all devices.
+ * (4) On this STM32 series, parameter not available on all devices.
* Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
*/
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
@@ -914,7 +937,7 @@
* - @ref LL_DAC_SetOutputBuffer()
* - @ref LL_DAC_SetOutputMode()
* - @ref LL_DAC_SetOutputConnection()
- * @note On this STM32 serie, output connection depends on output mode
+ * @note On this STM32 series, output connection depends on output mode
* (normal or sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
@@ -1003,7 +1026,7 @@
/**
* @brief Set the output buffer for the selected DAC channel.
- * @note On this STM32 serie, when buffer is enabled, its offset can be
+ * @note On this STM32 series, when buffer is enabled, its offset can be
* trimmed: factory calibration default values can be
* replaced by user trimming values, using function
* @ref LL_DAC_SetTrimmingValue().
@@ -1046,7 +1069,7 @@
/**
* @brief Set the output connection for the selected DAC channel.
- * @note On this STM32 serie, output connection depends on output mode (normal or
+ * @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
@@ -1076,7 +1099,7 @@
/**
* @brief Get the output connection for the selected DAC channel.
- * @note On this STM32 serie, output connection depends on output mode (normal or
+ * @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
@@ -1121,11 +1144,10 @@
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_SHSR1_TSAMPLE1,
- SampleTime);
+ MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
}
/**
@@ -1141,7 +1163,8 @@
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
}
@@ -1295,7 +1318,8 @@
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
+ * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
@@ -1317,8 +1341,8 @@
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
- ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
@@ -1481,11 +1505,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR12R1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
@@ -1503,11 +1526,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR12L1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
@@ -1525,11 +1547,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR8R1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
@@ -1610,7 +1631,8 @@
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
diff --git a/Inc/stm32h7xx_ll_dma2d.h b/Inc/stm32h7xx_ll_dma2d.h
index 6bfc467..583a04e 100644
--- a/Inc/stm32h7xx_ll_dma2d.h
+++ b/Inc/stm32h7xx_ll_dma2d.h
@@ -66,91 +66,125 @@
uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetMode(). */
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
- This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
uint32_t LineOffset; /*!< Specifies the output line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetLineOffset(). */
uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
- uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
+ uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
- This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
} LL_DMA2D_InitTypeDef;
@@ -160,7 +194,8 @@
typedef struct
{
uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
@@ -230,7 +265,8 @@
- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
- - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
+ - This parameter must be a number between:
+ Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
@@ -267,45 +303,68 @@
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
+ This parameter can be modified afterwards using
+ unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards using,
+ unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
+ - This parameter must be a number between:
+ Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
- This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
+ This parameter can be modified afterwards,
+ using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
} LL_DMA2D_ColorTypeDef;
@@ -396,9 +455,11 @@
* @{
*/
#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
-#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
-#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
+ programmed alpha value */
+#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
+ programmed alpha value with,
+ original alpha channel value */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_ll_dmamux.h b/Inc/stm32h7xx_ll_dmamux.h
index 24cb555..9592307 100644
--- a/Inc/stm32h7xx_ll_dmamux.h
+++ b/Inc/stm32h7xx_ll_dmamux.h
@@ -249,11 +249,11 @@
#define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */
#if defined (HRTIM1)
#define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
-#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6 */
#endif /* HRTIM1 */
#define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */
#define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */
diff --git a/Inc/stm32h7xx_ll_fmc.h b/Inc/stm32h7xx_ll_fmc.h
index 124f5cd..687775a 100644
--- a/Inc/stm32h7xx_ll_fmc.h
+++ b/Inc/stm32h7xx_ll_fmc.h
@@ -116,8 +116,8 @@
#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
+ ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
@@ -150,19 +150,19 @@
#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \
- ((__BANK__) == FMC_SDRAM_BANK2))
+ ((__BANK__) == FMC_SDRAM_BANK2))
#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
- ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
- ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
- ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
+ ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
+ ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
+ ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
- ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
- ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
+ ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
+ ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
- ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
+ ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
- ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
- ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
+ ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
+ ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
/**
@@ -191,62 +191,62 @@
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
- This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
- This parameter can be a value of @ref FMC_Memory_Type */
+ This parameter can be a value of @ref FMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FMC_Burst_Access_Mode */
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FMC_Wait_Timing */
+ This parameter can be a value of @ref FMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
- This parameter can be a value of @ref FMC_Write_Operation */
+ This parameter can be a value of @ref FMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal */
+ This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FMC_Extended_Mode */
+ This parameter can be a value of @ref FMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FMC_AsynchronousWait */
+ This parameter can be a value of @ref FMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
+ This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Continous_Clock */
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Write_FIFO */
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO */
uint32_t PageSize; /*!< Specifies the memory page size.
- This parameter can be a value of @ref FMC_Page_Size */
-}FMC_NORSRAM_InitTypeDef;
+ This parameter can be a value of @ref FMC_Page_Size */
+} FMC_NORSRAM_InitTypeDef;
/**
* @brief FMC NORSRAM Timing parameters structure definition
@@ -256,40 +256,41 @@
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
+ @note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
+ @note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
- NOR Flash memories. */
+ NOR Flash memories. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
+ @note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
- HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and
+ Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
- accesses. */
+ accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
- with synchronous burst mode enable */
+ - It may assume a value between Min_Data = 2 and Max_Data = 17
+ in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FMC_Access_Mode */
-}FMC_NORSRAM_TimingTypeDef;
+ This parameter can be a value of @ref FMC_Access_Mode */
+} FMC_NORSRAM_TimingTypeDef;
/**
* @brief FMC NAND Configuration Structure definition
@@ -297,19 +298,19 @@
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
+ This parameter can be a value of @ref FMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FMC_Wait_feature */
+ This parameter can be any value of @ref FMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FMC_NAND_Data_Width */
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FMC_ECC */
+ This parameter can be any value of @ref FMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FMC_ECC_Page_Size */
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
@@ -318,7 +319,7 @@
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FMC_NAND_InitTypeDef;
+} FMC_NAND_InitTypeDef;
/**
* @brief FMC NAND Timing parameters structure definition
@@ -349,7 +350,7 @@
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-}FMC_NAND_PCC_TimingTypeDef;
+} FMC_NAND_PCC_TimingTypeDef;
/**
@@ -388,7 +389,7 @@
uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
-}FMC_SDRAM_InitTypeDef;
+} FMC_SDRAM_InitTypeDef;
/**
* @brief FMC SDRAM Timing parameters structure definition
@@ -422,7 +423,7 @@
uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
command in number of memory clock cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-}FMC_SDRAM_TimingTypeDef;
+} FMC_SDRAM_TimingTypeDef;
/**
* @brief SDRAM command parameters structure definition
@@ -440,7 +441,7 @@
This parameter can be a value between Min_Data = 1 and Max_Data = 15 */
uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
-}FMC_SDRAM_CommandTypeDef;
+} FMC_SDRAM_CommandTypeDef;
/**
* @}
*/
@@ -457,10 +458,10 @@
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
-#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
-#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
-#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+#define FMC_NORSRAM_BANK1 (0x00000000U)
+#define FMC_NORSRAM_BANK2 (0x00000002U)
+#define FMC_NORSRAM_BANK3 (0x00000004U)
+#define FMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
@@ -468,8 +469,8 @@
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
+#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
+#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
@@ -477,9 +478,9 @@
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
+#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
+#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
+#define FMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
@@ -487,9 +488,9 @@
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
@@ -497,8 +498,8 @@
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
@@ -506,8 +507,8 @@
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
+#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
+#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
@@ -515,8 +516,8 @@
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
+#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
@@ -524,8 +525,8 @@
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
+#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
@@ -533,8 +534,8 @@
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
+#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
+#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
@@ -542,8 +543,8 @@
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
+#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
@@ -551,8 +552,8 @@
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
+#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
@@ -560,8 +561,8 @@
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
@@ -569,11 +570,12 @@
/** @defgroup FMC_Page_Size FMC Page Size
* @{
*/
-#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
-#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
-#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
-#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
-#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
+#define FMC_PAGE_SIZE_NONE (0x00000000U)
+#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
+#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
+#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
+ | FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
/**
* @}
*/
@@ -581,8 +583,8 @@
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
+#define FMC_WRITE_BURST_DISABLE (0x00000000U)
+#define FMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
@@ -590,8 +592,8 @@
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
@@ -599,19 +601,19 @@
/** @defgroup FMC_Write_FIFO FMC Write FIFO
* @{
*/
-#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
-#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
+#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
/**
* @}
*/
- /** @defgroup FMC_Access_Mode FMC Access Mode
+/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
-#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
-#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
-#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+#define FMC_ACCESS_MODE_A (0x00000000U)
+#define FMC_ACCESS_MODE_B (0x10000000U)
+#define FMC_ACCESS_MODE_C (0x20000000U)
+#define FMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
@@ -627,7 +629,7 @@
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+#define FMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
@@ -635,8 +637,8 @@
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
-#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
+#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
@@ -644,7 +646,7 @@
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
@@ -652,8 +654,8 @@
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
-#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
@@ -661,8 +663,8 @@
/** @defgroup FMC_ECC FMC ECC
* @{
*/
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
+#define FMC_NAND_ECC_DISABLE (0x00000000U)
+#define FMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
@@ -670,12 +672,12 @@
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
@@ -690,8 +692,8 @@
/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
* @{
*/
-#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
-#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
+#define FMC_SDRAM_BANK1 (0x00000000U)
+#define FMC_SDRAM_BANK2 (0x00000001U)
/**
* @}
*/
@@ -699,10 +701,10 @@
/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
* @{
*/
-#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
-#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
-#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
-#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
+#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U)
/**
* @}
*/
@@ -710,9 +712,9 @@
/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
* @{
*/
-#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
-#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
-#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
+#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U)
+#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U)
+#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U)
/**
* @}
*/
@@ -720,9 +722,9 @@
/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
* @{
*/
-#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
@@ -730,8 +732,8 @@
/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
* @{
*/
-#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
-#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
+#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U)
/**
* @}
*/
@@ -739,9 +741,9 @@
/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
* @{
*/
-#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
-#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
-#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
+#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U)
+#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U)
+#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U)
/**
* @}
*/
@@ -749,8 +751,8 @@
/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
* @{
*/
-#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
-#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U)
/**
* @}
*/
@@ -758,9 +760,9 @@
/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
* @{
*/
-#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
-#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
-#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
+#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U)
+#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U)
+#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U)
/**
* @}
*/
@@ -768,8 +770,8 @@
/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
* @{
*/
-#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
+#define FMC_SDRAM_RBURST_DISABLE (0x00000000U)
+#define FMC_SDRAM_RBURST_ENABLE (0x00001000U)
/**
* @}
*/
@@ -777,9 +779,9 @@
/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
* @{
*/
-#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
-#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
-#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
+#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U)
+#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U)
+#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U)
/**
* @}
*/
@@ -787,13 +789,13 @@
/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
* @{
*/
-#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
-#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
-#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
-#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
-#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
-#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
-#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
+#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U)
+#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U)
+#define FMC_SDRAM_CMD_PALL (0x00000002U)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U)
+#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U)
/**
* @}
*/
@@ -803,7 +805,7 @@
*/
#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
-#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
+#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U)
/**
* @}
*/
@@ -811,7 +813,7 @@
/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
* @{
*/
-#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
+#define FMC_SDRAM_NORMAL_MODE (0x00000000U)
#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
/**
@@ -826,10 +828,10 @@
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{
*/
-#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
-#define FMC_IT_LEVEL ((uint32_t)0x00000010)
-#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
-#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
+#define FMC_IT_RISING_EDGE (0x00000008U)
+#define FMC_IT_LEVEL (0x00000010U)
+#define FMC_IT_FALLING_EDGE (0x00000020U)
+#define FMC_IT_REFRESH_ERROR (0x00004000U)
/**
* @}
*/
@@ -837,10 +839,10 @@
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @{
*/
-#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
-#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define FMC_FLAG_RISING_EDGE (0x00000001U)
+#define FMC_FLAG_LEVEL (0x00000002U)
+#define FMC_FLAG_FALLING_EDGE (0x00000004U)
+#define FMC_FLAG_FEMPT (0x00000040U)
#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
@@ -855,12 +857,12 @@
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
* @{
*/
- /**
+/**
* @brief Enable the FMC Peripheral.
* @retval None
*/
@@ -882,7 +884,8 @@
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
-#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ |= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
@@ -890,16 +893,17 @@
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ &= ~FMC_BCRx_MBKEN)
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
/**
* @brief Enable the NAND device access.
@@ -1050,10 +1054,15 @@
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
@@ -1077,8 +1086,10 @@
* @{
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
@@ -1089,7 +1100,8 @@
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout);
/**
* @}
*/
@@ -1105,7 +1117,8 @@
* @{
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
+ FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
@@ -1116,9 +1129,11 @@
*/
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
+ FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
-HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
+ uint32_t AutoRefreshNumber);
uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
diff --git a/Inc/stm32h7xx_ll_gpio.h b/Inc/stm32h7xx_ll_gpio.h
index 4b67d6c..cf032aa 100644
--- a/Inc/stm32h7xx_ll_gpio.h
+++ b/Inc/stm32h7xx_ll_gpio.h
@@ -942,7 +942,8 @@
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
- WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
/**
diff --git a/Inc/stm32h7xx_ll_hrtim.h b/Inc/stm32h7xx_ll_hrtim.h
index 69d00fc..36a1235 100644
--- a/Inc/stm32h7xx_ll_hrtim.h
+++ b/Inc/stm32h7xx_ll_hrtim.h
@@ -803,7 +803,7 @@
* @brief Constants defining the registers that can be written during a burst DMA operation.
*/
#define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
-#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
@@ -997,37 +997,37 @@
* @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
*/
#define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */
-#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
-#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */
+#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */
/**
* @}
*/
@@ -1036,7 +1036,7 @@
* @{
* @brief Constants defining the polarity of a timer output.
*/
-#define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is acitve HIGH */
+#define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */
#define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
/**
* @}
@@ -7286,7 +7286,7 @@
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
{
- uint32_t temp; /* MISRAC-2012 compliancy */
+ uint32_t temp; /* MISRAC-2012 compliance */
temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
diff --git a/Inc/stm32h7xx_ll_i2c.h b/Inc/stm32h7xx_ll_i2c.h
index d91b7c2..c698b7a 100644
--- a/Inc/stm32h7xx_ll_i2c.h
+++ b/Inc/stm32h7xx_ll_i2c.h
@@ -360,11 +360,11 @@
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
- ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
- (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
- (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
- (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
- (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
/**
* @}
*/
@@ -583,12 +583,12 @@
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{
/* return address of TXDR register */
- data_reg_addr = (uint32_t) & (I2Cx->TXDR);
+ data_reg_addr = (uint32_t) &(I2Cx->TXDR);
}
else
{
/* return address of RXDR register */
- data_reg_addr = (uint32_t) & (I2Cx->RXDR);
+ data_reg_addr = (uint32_t) &(I2Cx->RXDR);
}
return data_reg_addr;
@@ -1163,7 +1163,7 @@
}
/**
- * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
+ * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
@@ -2090,7 +2090,9 @@
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
}
@@ -2157,7 +2159,7 @@
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
-*/
+ */
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
diff --git a/Inc/stm32h7xx_ll_iwdg.h b/Inc/stm32h7xx_ll_iwdg.h
index cf94fd7..8e22e3d 100644
--- a/Inc/stm32h7xx_ll_iwdg.h
+++ b/Inc/stm32h7xx_ll_iwdg.h
@@ -304,8 +304,8 @@
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
- * SR WVU LL_IWDG_IsReady\n
- * SR RVU LL_IWDG_IsReady
+ * SR RVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
@@ -318,7 +318,6 @@
* @}
*/
-
/**
* @}
*/
diff --git a/Inc/stm32h7xx_ll_lptim.h b/Inc/stm32h7xx_ll_lptim.h
index 2529003..a2ee75c 100644
--- a/Inc/stm32h7xx_ll_lptim.h
+++ b/Inc/stm32h7xx_ll_lptim.h
@@ -100,9 +100,9 @@
* @{
*/
#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
+#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
-#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
@@ -114,13 +114,13 @@
* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
* @{
*/
-#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
-#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
-#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
-#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
-#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
-#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
-#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
+#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
+#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
+#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
+#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
+#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
+#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
+#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
/**
* @}
*/
@@ -155,7 +155,7 @@
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
-#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}
@@ -1370,7 +1370,7 @@
/**
* @brief Enable autoreload register write completed interrupt (ARROKIE).
- * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1381,7 +1381,7 @@
/**
* @brief Disable autoreload register write completed interrupt (ARROKIE).
- * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1392,7 +1392,7 @@
/**
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
- * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1403,7 +1403,7 @@
/**
* @brief Enable direction change to up interrupt (UPIE).
- * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1414,7 +1414,7 @@
/**
* @brief Disable direction change to up interrupt (UPIE).
- * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1425,7 +1425,7 @@
/**
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
- * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1436,7 +1436,7 @@
/**
* @brief Enable direction change to down interrupt (DOWNIE).
- * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1447,7 +1447,7 @@
/**
* @brief Disable direction change to down interrupt (DOWNIE).
- * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1458,7 +1458,7 @@
/**
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
- * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
diff --git a/Inc/stm32h7xx_ll_lpuart.h b/Inc/stm32h7xx_ll_lpuart.h
index 1471bdd..64e17f9 100644
--- a/Inc/stm32h7xx_ll_lpuart.h
+++ b/Inc/stm32h7xx_ll_lpuart.h
@@ -100,36 +100,43 @@
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
- This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
- This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
- This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref LPUART_LL_EC_PARITY.
- This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
- This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
- This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPUART_SetHWFlowCtrl().*/
} LL_LPUART_InitTypeDef;
@@ -147,16 +154,16 @@
* @brief Flags defines which can be used with LL_LPUART_WriteReg function
* @{
*/
-#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
-#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */
-#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
-#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
-#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
-#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
-#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
-#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
@@ -165,27 +172,27 @@
* @brief Flags defines which can be used with LL_LPUART_ReadReg function
* @{
*/
-#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
-#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
-#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
-#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
-#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
-#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
-#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
-#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
-#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
-#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
-#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
-#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
-#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
-#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
-#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
-#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
-#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
-#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
-#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
-#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
-#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
/**
* @}
*/
@@ -194,19 +201,21 @@
* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
* @{
*/
-#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
-#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
-#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
-#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
-#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
-#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
-#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
-#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
-#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
-#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+ interrupt enable */
+#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
+ not full interrupt enable */
+#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
/**
* @}
*/
@@ -227,10 +236,10 @@
/** @defgroup LPUART_LL_EC_DIRECTION Direction
* @{
*/
-#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
/**
* @}
*/
@@ -238,9 +247,9 @@
/** @defgroup LPUART_LL_EC_PARITY Parity Control
* @{
*/
-#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
-#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
@@ -248,8 +257,8 @@
/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
* @{
*/
-#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
-#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
+#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
/**
* @}
*/
@@ -257,9 +266,9 @@
/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
* @{
*/
-#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
/**
* @}
*/
@@ -267,18 +276,27 @@
/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
-#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
-#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
-#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
-#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
-#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
-#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
-#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
-#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
-#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
-#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
-#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -286,8 +304,8 @@
/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
* @{
*/
-#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
*/
@@ -295,8 +313,8 @@
/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
* @{
*/
-#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
/**
* @}
*/
@@ -304,8 +322,8 @@
/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
* @{
*/
-#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
-#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
/**
* @}
*/
@@ -313,8 +331,8 @@
/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
* @{
*/
-#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
-#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
/**
* @}
*/
@@ -322,8 +340,11 @@
/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
* @{
*/
-#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
-#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
+ in positive/direct logic. (1=H, 0=L) */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+ in negative/inverse logic. (1=L, 0=H).
+ The parity bit is also inverted. */
/**
* @}
*/
@@ -331,8 +352,10 @@
/** @defgroup LPUART_LL_EC_BITORDER Bit Order
* @{
*/
-#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
-#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
+ following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+ following the start bit */
/**
* @}
*/
@@ -340,8 +363,8 @@
/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
* @{
*/
-#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
-#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
/**
* @}
*/
@@ -349,10 +372,12 @@
/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
* @{
*/
-#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
+ when there is space in the receive buffer */
+#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
+ when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
/**
* @}
*/
@@ -360,9 +385,9 @@
/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
* @{
*/
-#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
-#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
-#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
/**
* @}
*/
@@ -370,8 +395,8 @@
/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
*/
-#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
-#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
/**
* @}
*/
@@ -379,8 +404,8 @@
/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
-#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
@@ -442,8 +467,9 @@
* @param __BAUDRATE__ Baud Rate value to achieve
* @retval LPUARTDIV value to be used for BRR register filling
*/
-#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
- + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
+ ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
+ * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
/**
* @}
@@ -629,7 +655,8 @@
*/
__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
@@ -1345,7 +1372,10 @@
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t BaudRate)
{
- LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+ if (BaudRate != 0U)
+ {
+ LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+ }
}
/**
diff --git a/Inc/stm32h7xx_ll_mdma.h b/Inc/stm32h7xx_ll_mdma.h
index 18609ad..38d08f2 100644
--- a/Inc/stm32h7xx_ll_mdma.h
+++ b/Inc/stm32h7xx_ll_mdma.h
@@ -279,7 +279,7 @@
/** @defgroup MDMA_LL_EC_WORD_ENDIANNESS Word Endianness
* @{
*/
-#define LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianess preserved for words */
+#define LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianness preserved for words */
#define LL_MDMA_WORD_ENDIANNESS_EXCHANGE MDMA_CCR_WEX /*!< word order exchanged when destination data size is double word */
/**
@@ -289,7 +289,7 @@
/** @defgroup MDMA_LL_EC_HALFWORD_ENDIANNESS Half Word Endianness
* @{
*/
-#define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianess preserved for half words */
+#define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianness preserved for half words */
#define LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE MDMA_CCR_HEX /*!< half word order exchanged when destination data size is word or double word */
/**
@@ -299,7 +299,7 @@
/** @defgroup MDMA_LL_EC_BYTE_ENDIANNESS Byte Endianness
* @{
*/
-#define LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianess preserved for bytes */
+#define LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianness preserved for bytes */
#define LL_MDMA_BYTE_ENDIANNESS_EXCHANGE MDMA_CCR_BEX /*!< byte order exchanged when destination data size is half word , word or double word */
/**
@@ -787,7 +787,7 @@
}
/**
- * @brief Configure Transfer endianness paremeters : Word, Half word and Bytes Endianess.
+ * @brief Configure Transfer endianness parameters : Word, Half word and Bytes Endianness.
* @rmtoll CCR WEX LL_MDMA_ConfigXferEndianness\n
* @rmtoll CCR HEX LL_MDMA_ConfigXferEndianness\n
* @rmtoll CCR BEX LL_MDMA_ConfigXferEndianness
@@ -824,7 +824,7 @@
}
/**
- * @brief Set Words Endianess.
+ * @brief Set Words Endianness.
* @rmtoll CCR WEX LL_MDMA_SetWordEndianness
* @param MDMAx MDMAx Instance
* @param Channel This parameter can be one of the following values:
@@ -857,7 +857,7 @@
}
/**
- * @brief Get Words Endianess.
+ * @brief Get Words Endianness.
* @rmtoll CCR WEX LL_MDMA_GetWordEndianness
* @param MDMAx MDMAx Instance
* @param Channel This parameter can be one of the following values:
@@ -890,7 +890,7 @@
}
/**
- * @brief Set Half Words Endianess.
+ * @brief Set Half Words Endianness.
* @rmtoll CCR HEX LL_MDMA_SetHalfWordEndianness
* @param MDMAx MDMAx Instance
* @param Channel This parameter can be one of the following values:
@@ -923,7 +923,7 @@
}
/**
- * @brief Get Half Words Endianess.
+ * @brief Get Half Words Endianness.
* @rmtoll CCR HEX LL_MDMA_GetHalfWordEndianness
* @param MDMAx MDMAx Instance
* @param Channel This parameter can be one of the following values:
@@ -956,7 +956,7 @@
}
/**
- * @brief Set Bytes Endianess.
+ * @brief Set Bytes Endianness.
* @rmtoll CCR BEX LL_MDMA_SetByteEndianness
* @param MDMAx MDMAx Instance
* @param Channel This parameter can be one of the following values:
@@ -989,7 +989,7 @@
}
/**
- * @brief Get Bytes Endianess.
+ * @brief Get Bytes Endianness.
* @rmtoll CCR BEX LL_MDMA_GetByteEndianness
* @param MDMAx MDMAx Instance
* @param Channel This parameter can be one of the following values:
diff --git a/Inc/stm32h7xx_ll_opamp.h b/Inc/stm32h7xx_ll_opamp.h
index 9808ab1..b6d4d3e 100644
--- a/Inc/stm32h7xx_ll_opamp.h
+++ b/Inc/stm32h7xx_ll_opamp.h
@@ -191,10 +191,10 @@
*/
#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to I/O VINP0
(PB0 for OPAMP1, PE9 for OPAMP2)
- Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
+ Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL_0 /*!< OPAMP non inverting input connected internally to DAC channel
(DAC1_CH1 for OPAMP1, DAC1_CH2 for OPAMP2)
- Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
+ Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#if defined(DAC2)
#define LL_OPAMP_INPUT_NONINVERT_DAC2 OPAMP_CSR_VPSEL_1 /*!< OPAMP non inverting input connected internally to DAC2 channel
(DAC3 only for OPAMP2)*/
@@ -211,12 +211,12 @@
*/
#define LL_OPAMP_INPUT_INVERT_IO0 0x00000000U /*!< OPAMP inverting input connected to I/O VINM0
(PC5 for OPAMP1, PE8 for OPAMP2)
- Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
+ Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to I/0 VINM1
(PA7 for OPAMP1, PG1 for OPAMP2)
- Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
+ Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1 /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias).
- Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
+ Note: On this STM32 series, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
/**
* @}
*/
@@ -751,7 +751,7 @@
/**
* @brief Enable OPAMP instance.
* @note After enable from off state, OPAMP requires a delay
- * to fullfill wake up time specification.
+ * to fulfill wake up time specification.
* Refer to device datasheet, parameter "tWAKEUP".
* @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
* @param OPAMPx OPAMP instance
diff --git a/Inc/stm32h7xx_ll_pwr.h b/Inc/stm32h7xx_ll_pwr.h
index 98602e2..a7f8205 100644
--- a/Inc/stm32h7xx_ll_pwr.h
+++ b/Inc/stm32h7xx_ll_pwr.h
@@ -294,13 +294,13 @@
/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
* @{
*/
-#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
+#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */
#if defined (SMPS)
-#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS */
+#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */
#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
-#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
-#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
#define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
#define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
#endif /* SMPS */
@@ -537,7 +537,7 @@
#if defined (PWR_CR1_AVD_READY)
/**
- * @brief Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready
+ * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready
* @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady
* @retval None
*/
diff --git a/Inc/stm32h7xx_ll_rcc.h b/Inc/stm32h7xx_ll_rcc.h
index ed63ebf..2ab40eb 100644
--- a/Inc/stm32h7xx_ll_rcc.h
+++ b/Inc/stm32h7xx_ll_rcc.h
@@ -64,13 +64,13 @@
--------------------------------------------------------*/
#if defined(RCC_VER_2_0)
-/* Clock source register offset Vs CDCCIPR regsiter */
+/* Clock source register offset Vs CDCCIPR register */
#define CDCCIP 0x0UL
#define CDCCIP1 0x4UL
#define CDCCIP2 0x8UL
#define SRDCCIP 0xCUL
#else
-/* Clock source register offset Vs D1CCIPR regsiter */
+/* Clock source register offset Vs D1CCIPR register */
#define D1CCIP 0x0UL
#define D2CCIP1 0x4UL
#define D2CCIP2 0x8UL
@@ -4594,7 +4594,9 @@
* @brief Set PLL1 P Coefficient
* @note This API shall be called only when PLL1 is disabled.
* @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP
- * @param P parameter can be a value between 2 and 128 (ODD division factor not supportted)
+ * @param P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported)
+ *
+ * (*) : For stm32h72xxx and stm32h73xxx family lines.
*/
__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
{
diff --git a/Inc/stm32h7xx_ll_rng.h b/Inc/stm32h7xx_ll_rng.h
index ab89a18..1b98dd0 100644
--- a/Inc/stm32h7xx_ll_rng.h
+++ b/Inc/stm32h7xx_ll_rng.h
@@ -57,8 +57,8 @@
{
uint32_t ClockErrorDetection; /*!< Clock error detection.
This parameter can be one value of @ref RNG_LL_CED.
-
- This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
+ This parameter can be modified using unitary
+ functions @ref LL_RNG_EnableClkErrorDetect(). */
} LL_RNG_InitTypeDef;
/**
@@ -81,7 +81,7 @@
#if defined(RNG_CR_CONDRST)
/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
- * programmable divider acting on the incoming RNG clock
+ * programmable divider acting on the incoming RNG clock
* @{
*/
#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
@@ -114,7 +114,7 @@
* @}
*/
-#endif/*RNG_CR_CONDRST*/
+#endif /* RNG_CR_CONDRST */
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RNG_ReadReg function
* @{
@@ -645,7 +645,7 @@
/**
* @}
*/
-#endif /*End of RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0*/
+#endif /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
diff --git a/Inc/stm32h7xx_ll_sdmmc.h b/Inc/stm32h7xx_ll_sdmmc.h
index 8b91c6c..fd210d3 100644
--- a/Inc/stm32h7xx_ll_sdmmc.h
+++ b/Inc/stm32h7xx_ll_sdmmc.h
@@ -22,7 +22,7 @@
#define STM32H7xx_LL_SDMMC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -63,10 +63,10 @@
This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
#if (USE_SD_TRANSCEIVER != 0U)
- uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Tranceiver/Switcher.
- This parameter can be a value of @ref SDMMC_LL_TRANCEIVER_PRESENT */
+ uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher.
+ This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */
#endif /* USE_SD_TRANSCEIVER */
-}SDMMC_InitTypeDef;
+} SDMMC_InitTypeDef;
/**
@@ -92,7 +92,7 @@
uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_CPSM_State */
-}SDMMC_CmdInitTypeDef;
+} SDMMC_CmdInitTypeDef;
/**
@@ -117,7 +117,7 @@
uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_DPSM_State */
-}SDMMC_DataInitTypeDef;
+} SDMMC_DataInitTypeDef;
/**
* @}
@@ -135,13 +135,13 @@
#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the */
+ /*!< number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock */
+ /*!< command or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
@@ -152,8 +152,8 @@
#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
+#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out */
+ /*!< of erase sequence command was received */
#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
@@ -172,12 +172,12 @@
#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its */
+ /*!< operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information */
+ /*!< and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
@@ -185,18 +185,18 @@
#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
- (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
- for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
- STOP_TRANSMISSION command. */
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands */
+ /*!< (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
+/*!< for SDHS and SDXC. */
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */
+ /*!< fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by */
+ /*!< STOP_TRANSMISSION command. */
#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */
+ /*!< fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
@@ -205,32 +205,32 @@
#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
- system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
- Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command */
+ /*!< system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. */
+ /*!< Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
- the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
- than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
- for general purpose/application specific commands. */
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by */
+ /*!< the SET_BLOCK_LEN command. */
+#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather */
+ /*!< than a standard command. */
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card */
+ /*!< for general purpose/application specific commands. */
#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
- widths are given in SCR register. */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus */
+ /*!< widths are given in SCR register. */
#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
- 32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
- send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with */
+ /*!< 32bit+CRC data block. */
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to */
+ /*!< send its operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
@@ -370,11 +370,11 @@
#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
#define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U)
-#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
- ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
- ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
- ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
- ((MODE) == SDMMC_SPEED_MODE_DDR))
+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
+ ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
+ ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
+ ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
+ ((MODE) == SDMMC_SPEED_MODE_DDR))
/**
* @}
@@ -401,7 +401,7 @@
* @}
*/
-/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Tranceiver Present
+/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present
* @{
*/
#define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U)
@@ -485,7 +485,7 @@
* @}
*/
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
+/** @defgroup SDMMC_LL_Data_Length Data Length
* @{
*/
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
@@ -503,14 +503,18 @@
#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \
+ SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
@@ -642,21 +646,21 @@
#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
-#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
- SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
- SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
- SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
- SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
- SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
- SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
+#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
+ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
+ SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
+ SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
+ SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
-#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
- SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
+#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
+ SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
-#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
- SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
- SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
- SDMMC_FLAG_IDMABTC))
+#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
+ SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
+ SDMMC_FLAG_IDMABTC))
/**
* @}
*/
@@ -707,9 +711,9 @@
*/
/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/**
* @brief Enable the SDMMC device interrupt.
@@ -1034,14 +1038,20 @@
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
/* SDMMC Cards mode management functions */
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+/**
+ * @}
+ */
-/* SDMMC Commands management functions */
+/* SDMMC Commands management functions ******************************************/
+/** @addtogroup HAL_SDMMC_LL_Group4
+ * @{
+ */
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
@@ -1053,7 +1063,7 @@
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
@@ -1063,13 +1073,26 @@
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
+/**
+ * @}
+ */
+/* SDMMC Responses management functions *****************************************/
+/** @addtogroup HAL_SDMMC_LL_Group5
+ * @{
+ */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
/**
* @}
*/
@@ -1087,7 +1110,7 @@
* @}
*/
- /**
+/**
* @}
*/
diff --git a/Inc/stm32h7xx_ll_spi.h b/Inc/stm32h7xx_ll_spi.h
index e611b58..4dd1c2d 100644
--- a/Inc/stm32h7xx_ll_spi.h
+++ b/Inc/stm32h7xx_ll_spi.h
@@ -964,7 +964,7 @@
/**
* @brief Check if there is an unfinished master transfer
- * @rmtoll CR1 CSTART LL_SPI_IsMasterTransferActive
+ * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
@@ -1685,7 +1685,7 @@
}
/**
- * @brief Check that end of transfer event occured
+ * @brief Check that end of transfer event occurred
* @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
@@ -2818,7 +2818,7 @@
/**
* @brief Set I2S Channel Length Type
- * @note This feature is usefull with SLAVE only
+ * @note This feature is useful with SLAVE only
* @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType
* @param SPIx SPI Handle
* @param ChannelLengthType This parameter can be one of the following values:
@@ -2833,7 +2833,7 @@
/**
* @brief Get I2S Channel Length Type
- * @note This feature is usefull with SLAVE only
+ * @note This feature is useful with SLAVE only
* @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType
* @param SPIx SPI Handle
* @retval Return value can be one of the following values:
@@ -3247,7 +3247,7 @@
}
/**
- * @brief Disable the Master Clock Ouput (Pin MCK)
+ * @brief Disable the Master Clock Output (Pin MCK)
* @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock
* @param SPIx SPI Handle
* @retval None
diff --git a/Inc/stm32h7xx_ll_system.h b/Inc/stm32h7xx_ll_system.h
index df3fe3b..b4326b5 100644
--- a/Inc/stm32h7xx_ll_system.h
+++ b/Inc/stm32h7xx_ll_system.h
@@ -135,7 +135,7 @@
* @{
*/
#define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */
-#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL /*!< ETH Media RMII interface */
+#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */
/**
* @}
*/
@@ -770,7 +770,7 @@
* @brief Enable the Compensation Cell
* @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell
* @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V
+ * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
@@ -782,7 +782,7 @@
* @brief Disable the Compensation Cell
* @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell
* @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V
+ * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
@@ -1917,6 +1917,7 @@
#endif /* DUAL_CORE */
+#if defined(DBGMCU_CR_DBG_STOPD3)
/**
* @brief Enable D3 Domain/SRDomain debug during STOP mode
* @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode
@@ -1936,7 +1937,9 @@
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
}
+#endif /*DBGMCU_CR_DBG_STOPD3*/
+#if defined(DBGMCU_CR_DBG_STANDBYD3)
/**
* @brief Enable D3 Domain/SRDomain debug during STANDBY mode
* @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode
@@ -1956,6 +1959,7 @@
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
}
+#endif /*DBGMCU_CR_DBG_STANDBYD3*/
/**
* @brief Enable the trace port clock
diff --git a/Inc/stm32h7xx_ll_tim.h b/Inc/stm32h7xx_ll_tim.h
index 3bbdaa1..4ec1297 100644
--- a/Inc/stm32h7xx_ll_tim.h
+++ b/Inc/stm32h7xx_ll_tim.h
@@ -565,8 +565,8 @@
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
* @{
*/
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
@@ -1241,9 +1241,6 @@
#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */
#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */
#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
-/**
- * @}
- */
#if defined(TIM_BREAK_INPUT_SUPPORT)
/** Legacy definitions for compatibility purpose
@@ -1564,7 +1561,16 @@
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+ uint32_t counter_mode;
+
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+ if (counter_mode == 0U)
+ {
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+ }
+
+ return counter_mode;
}
/**
@@ -2019,8 +2025,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -2064,8 +2070,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -2103,8 +2109,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -2137,7 +2143,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2169,7 +2175,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@@ -2206,7 +2212,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@@ -2238,7 +2244,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@@ -2263,8 +2269,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2289,8 +2295,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2315,9 +2321,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2341,8 +2347,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2366,8 +2372,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2391,9 +2397,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2420,8 +2426,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2447,8 +2453,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2476,9 +2482,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2747,8 +2753,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2775,8 +2781,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2799,8 +2805,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2825,8 +2831,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2850,8 +2856,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2888,8 +2894,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2925,8 +2931,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2954,7 +2960,7 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2982,7 +2988,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
@@ -3435,7 +3441,6 @@
*/
__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
{
-
MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
}
@@ -3695,7 +3700,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
SET_BIT(*pReg, Source);
}
@@ -3724,7 +3729,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@@ -3754,7 +3759,7 @@
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
#endif /* TIM_BREAK_INPUT_SUPPORT */
diff --git a/Inc/stm32h7xx_ll_usart.h b/Inc/stm32h7xx_ll_usart.h
index 7b4121e..4a164ba 100644
--- a/Inc/stm32h7xx_ll_usart.h
+++ b/Inc/stm32h7xx_ll_usart.h
@@ -88,41 +88,49 @@
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref USART_LL_EC_PRESCALER.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_LL_EC_PARITY.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetHWFlowCtrl().*/
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetOverSampling().*/
} LL_USART_InitTypeDef;
@@ -141,20 +149,23 @@
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_LL_EC_POLARITY.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPolarity().
For more details, refer to description of this function. */
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_LL_EC_PHASE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPhase().
For more details, refer to description of this function. */
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetLastClkPulseOutput().
For more details, refer to description of this function. */
} LL_USART_ClockInitTypeDef;
@@ -173,21 +184,21 @@
* @brief Flags defines which can be used with LL_USART_WriteReg function
* @{
*/
-#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
-#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */
-#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
-#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
-#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
-#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
-#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */
-#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
-#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
-#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
-#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
-#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */
-#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
@@ -357,18 +368,18 @@
/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
-#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
-#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
-#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
-#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
-#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
-#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
-#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
-#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
-#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
-#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
-#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -563,8 +574,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
- + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@@ -586,8 +598,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
- + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
@@ -785,7 +798,8 @@
*/
__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
@@ -1870,6 +1884,10 @@
{
/* Do not overstep the size of USART_PRESCALER_TAB */
}
+ else if (BaudRate == 0U)
+ {
+ /* Can Not divide per 0 */
+ }
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
diff --git a/Inc/stm32h7xx_ll_usb.h b/Inc/stm32h7xx_ll_usb.h
index 8970cfb..5ee7cf7 100644
--- a/Inc/stm32h7xx_ll_usb.h
+++ b/Inc/stm32h7xx_ll_usb.h
@@ -81,7 +81,7 @@
} USB_OTG_HCStateTypeDef;
/**
- * @brief USB OTG Initialization Structure definition
+ * @brief USB Instance Initialization Structure definition
*/
typedef struct
{
@@ -94,14 +94,14 @@
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ This parameter can be any value of @ref USB_Core_Speed */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY_ */
+ This parameter can be any value of @ref USB_Core_PHY */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@@ -116,6 +116,7 @@
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+
} USB_OTG_CfgTypeDef;
typedef struct
@@ -185,6 +186,8 @@
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+ uint32_t XferSize; /*!< OTG Channel transfer size. */
+
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
@@ -197,13 +200,13 @@
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
- uint32_t ErrCnt; /*!< Host channel error count.*/
+ uint32_t ErrCnt; /*!< Host channel error count. */
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
- This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@@ -313,10 +316,10 @@
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
-#define DEP0CTL_MPS_64 0U
-#define DEP0CTL_MPS_32 1U
-#define DEP0CTL_MPS_16 2U
-#define DEP0CTL_MPS_8 3U
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
/**
* @}
*/
@@ -402,7 +405,7 @@
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-#define EP_ADDR_MSK 0xFU
+#define EP_ADDR_MSK 0xFU
/**
* @}
*/
@@ -442,7 +445,9 @@
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+ uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
@@ -470,7 +475,9 @@
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
+ USB_OTG_HCTypeDef *hc, uint8_t dma);
+
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
diff --git a/README.md b/README.md
index 3e4253b..6d10da2 100644
--- a/README.md
+++ b/README.md
@@ -1,19 +1,21 @@
# STM32CubeH7 HAL Driver MCU Component
+
+
## Overview
-**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+**STM32Cube** is an STMicroelectronics original initiative to ease developers' life by reducing efforts, time and cost.
-**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
- * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
- * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
- * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
- * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
- * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+ * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+ * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+ * A consistent set of middleware components such as RTOS, USB, FatFS, graphics, touch sensing library...
+ * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
Two models of publication are proposed for the STM32Cube embedded software:
- * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
- * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
+ * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+ * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
## Description
@@ -42,6 +44,7 @@
Tag v1.7.0 | Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next HAL tag)
Tag v1.8.0 | Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next HAL tag)
Tag v1.9.0 | Tag v1.9.0 | Tag v5.4.0 | Tag v1.8.0 (and following, if any, till next HAL tag)
+Tag v1.10.0 | Tag v1.10.0 | Tag v5.6.0 | Tag v1.9.0 (and following, if any, till next HAL tag)
The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7).
diff --git a/Release_Notes.html b/Release_Notes.html
index f4ede52..28e3c2a 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -38,10 +38,312 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
+<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li><p>General updates to fix known defects and implementation enhancements</p></li>
+<li><p>Fix minor issues related to English typo in comments</p></li>
+<li>Update stm32h7xx_hal_def.h implementation to support MDK-ARM AC6 compiler
+<ul>
+<li>Notes:
+<ul>
+<li>Only HAL and LL driver are compliant with MDK-ARM AC6 compiler. No warning on these drivers when using “AC5-like warning” in MDK-ARM project settings<br />
+</li>
+<li>Template projects updated with “Use default compiler version 6” setting and “AC5-like warning” setting</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL</strong>:
+<ul>
+<li>stm32h7xx_hal.h and stm32h7xx_hal.c:
+<ul>
+<li>Fix implementation values of SYSCFG_VREFBUF_VOLTAGE_SCALE0 to SYSCFG_VREFBUF_VOLTAGE_SCALE3 defines</li>
+<li>Delimit “HAL_EnableDomain3DBGStopMode” and “HAL_DisableDomain3DBGStopMode” APIs with the presence of the “DBGMCU_CR_DBG_STOPD3” field definition (from the CMSIS device header file)<br />
+</li>
+<li>Delimit “HAL_EnableDomain3DBGStandbyMode” and “HAL_DisableDomain3DBGStandbyMode” APIs with the presence of the “DBGMCU_CR_DBG_STANDBYD3” field definition (from the CMSIS device header file)</li>
+<li>Update comments of HAL_EnableCompensationCell and HAL_DisableCompensationCell according to the STM32H7 product data-sheet</li>
+</ul></li>
+<li>stm32h7xx_hal_conf_template.h:
+<ul>
+<li>Update HSE_STARTUP_TIMEOUT define value to 100 ms instead of 5000 ms</li>
+<li>Update USE_SD_TRANSCEIVER define default value to zero Notes: This define shall be set in the target project according to the given board: set to 1 in case of an SD transceiver is present or zero if not</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL ADC</strong>:
+<ul>
+<li>stm32h7xx_hal_adc.h:
+<ul>
+<li>stm32h7xx_hal_adc_ex.h: Update IS_ADC_RIGHT_BIT_SHIFT macro implementation to add support for ADC_RIGHTBITSHIFT_9, ADC_RIGHTBITSHIFT_10 and ADC_RIGHTBITSHIFT_11 values</li>
+</ul></li>
+<li>stm32h7xx_hal_adc.c/stm32h7xx_hal_adc_ex.c:
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL CEC</strong>:
+<ul>
+<li>stm32h7xx_hal_cec.c:
+<ul>
+<li>Update “HAL_CEC_IRQHandler” implementation to avoid extra byte sent with CEC command</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL CRYP</strong>:
+<ul>
+<li>stm32h7xx_hal_cryp.h:
+<ul>
+<li>Update CRYP_ConfigTypeDef structure to add “DataWidthUnit” field allowing to set the header width unit</li>
+</ul></li>
+<li>stm32h7xx_hal_cryp.c:
+<ul>
+<li>Update the implementation of the “CRYP_GCMCCM_SetHeaderPhase” function to support the header width unit setting</li>
+</ul></li>
+<li>stm32h7xx_hal_cryp_ex.c:
+<ul>
+<li>Update the implementation of the “HAL_CRYPEx_AESGCM_GenerateAuthTAG” function to support the header width unit setting</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL EXTI</strong>:
+<ul>
+<li>stm32h7xx_hal_exti.h:
+<ul>
+<li>Update IS_EXTI_PROPERTY to IS_EXTI_CONFIG_LINE macros implementation using “<strong>EXTI_LINE</strong>” instead of “<strong>LINE</strong>” o avoid clash with compiler key word “<strong>LINE</strong>”</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL ETH</strong>:
+<ul>
+<li>stm32h7xx_hal_eth.h:
+<ul>
+<li>New private fields “PacketAddress”, “CurrentPacketAddress” and “BuffersInUse” added to the “ETH_TxDescListTypeDef” structure</li>
+</ul></li>
+<li>stm32h7xx_hal_eth.c:
+<ul>
+<li>Update implementation of “ETH_Prepare_Tx_Descriptors” function to improve TX performance using the above “ETH_TxDescListTypeDef” structure new fields</li>
+</ul></li>
+<li>Notes:
+<ul>
+<li>This implementation allows to improve packet transmission performance using NetX Duo TCPIP stack, however a more elaborated implementation will be provided in next release</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL FLASH</strong>:
+<ul>
+<li>stm32h7xx_hal_flash_ex.h:
+<ul>
+<li>Remove unused defines “OB_WWDG_SW” and “OB_WWDG_HW” and corresponding “IS_OB_WWDG_SOURCE” macro</li>
+<li>Delimit “OB_SWAP_BANK_DISABLE” and “OB_SWAP_BANK_ENABLE” defines with “#if defines (DUAL_BANK)” as swap bank is available for dual bank devices only. same for macro “IS_OB_USER_SWAP_BANK”</li>
+<li>Update “OB_USER_ALL” macro implementation with variants for dual bank, single bank, dual core and single core devices</li>
+</ul></li>
+<li>stm32h7xx_hal_flash.c:
+<ul>
+<li>Update “HAL_FLASH_Program” description with details for “FlashAddress” and “DataAddress” alignment requirements</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL GPIO</strong>:
+<ul>
+<li>stm32h7xx_hal_gpio.c:
+<ul>
+<li>Update and fix HAL_GPIO_TogglePin implementation to allow toggle of multiple pin</li>
+</ul></li>
+<li>stm32h7xx_ll_gpio.h:
+<ul>
+<li>Update and fix LL_GPIO_TogglePin implementation to allow toggle of multiple pin</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL HRTIM</strong>:
+<ul>
+<li>stm32h7xx_hal_hrtim.c:
+<ul>
+<li>Update HRTIM_HRTIM_ISR implementation to optimize the read flags</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL IWDG</strong>:
+<ul>
+<li>stm32h7xx_hal_iwdg.c:
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemptio</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL LPTIM</strong>
+<ul>
+<li>stm32h7xx_hal_lptim.c:
+<ul>
+<li>Update “HAL_LPTIM_Init” implementation to improve behavior for external clock configuration</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL NAND</strong>:
+<ul>
+<li>stm32h7xx_hal_nand.c:
+<ul>
+<li>Update implementation of “HAL_NAND_Read_SpareArea_16b” and “HAL_NAND_Write_SpareArea_16b” to fix an issue with the spare area Column address calculation</li>
+<li>Update implementation of “HAL_NAND_Write_Page_16b” and “HAL_NAND_Read_Page_16b” APIs implementation to fix an issue with the page calculation of 8 bits memories</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL NOR</strong>:
+<ul>
+<li>stm32h7xx_hal_nor.c:
+<ul>
+<li>Fix “HAL_NOR_ProgramBuffer” API implementation regarding the current and end address calculation</li>
+<li>Update NOR APIs implementation to support some specific memories</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL RCC</strong>:
+<ul>
+<li>stm32h7xx_hal_rcc.c:
+<ul>
+<li>Update “HAL_RCC_DeInit” implementation to reset “HSEEXT” field</li>
+</ul></li>
+<li>stm32h7xx_hal_rcc_ex.c:
+<ul>
+<li>Update “HAL_RCCEx_PeriphCLKConfig” implementation with CEC Configuration</li>
+<li>Update “HAL_RCCEx_GetPeriphCLKFreq” implementation to:
+<ul>
+<li>Check oscillator ready flag</li>
+<li>Get FDCAN clock source</li>
+</ul></li>
+<li>Update implementation of “HAL_RCCEx_GetPLL1ClockFreq” to use HSI in default case as per the specification</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL RNG</strong>:
+<ul>
+<li>stm32h7xx_hal_rng.h:
+<ul>
+<li>Add “RNG_RecoverSeedError” function prototype</li>
+</ul></li>
+<li>stm32h7xx_hal_rng.c:
+<ul>
+<li>Update “HAL_RNG_GenerateRandomNumber” function implementation to check seed error if any</li>
+<li>Update “HAL_RNG_IRQHandler” function implementation to check seed error if any</li>
+<li>Add “RNG_RecoverSeedError” function</li>
+</ul></li>
+<li>stm32h7xx_hal_rng_ex.h:
+<ul>
+<li>Add “HAL_RNGEx_RecoverSeedError” API prototype</li>
+</ul></li>
+<li>stm32h7xx_hal_rng_ex.c:
+<ul>
+<li>Add “HAL_RNGEx_RecoverSeedError” function</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL SDMMC</strong>:
+<ul>
+<li>stm32h7xx_hal_mmc.c:
+<ul>
+<li>Update implementation of “HAL_MMC_Init” function to support SDMMC power class</li>
+<li>Add “HAL_MMC_GetCardExtCSD” function to get card extended information<br />
+</li>
+<li>Update “HAL_MMC_ConfigWideBusOperation” function implementation to support SDMMC power class</li>
+<li>Update “HAL_MMC_ConfigSpeedBusOperation” function implementation to adapt the speed to the card type</li>
+<li>Update “HAL_MMC_GetSupportedSecRemovalType” function implementation to support Secure Removal type</li>
+<li>Update “HAL_MMC_InitCard” implementation to avoid potential division by zero</li>
+<li>Update to support native 4KB sector size<br />
+</li>
+</ul></li>
+<li>stm32h7xx_hal_mmc_ex.c
+<ul>
+<li>Update to support native 4KB sector size</li>
+</ul></li>
+<li>stm32h7xx_hal_mmc.h:
+<ul>
+<li>Add eMMC_DUAL_VOLTAGE_RANGE and eMMC_LOW_VOLTAGE_RANGE voltage mode</li>
+<li>Add prototype for HAL_MMC_GetCardExtCSD API</li>
+</ul></li>
+<li>stm32h7xx_hal_sd.c:
+<ul>
+<li>Update “HAL_SD_InitCard” implementation to avoid potential division by zero</li>
+</ul></li>
+<li>stm32h7xx_ll_sdmmc.c
+<ul>
+<li>Add “SDMMC_CmdSetRelAddMmc” function to set relative address</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL SPI</strong>
+<ul>
+<li>Update “HAL_SPI_TransmitReceive_IT” implementation to disable RXP and TXP interrupt when DXP is enabled</li>
+<li>Update “HAL_SPI_Init” implementation with NSS Software Management</li>
+<li>stm32h7xx_ll_spi.c:
+<ul>
+<li>Update “LL_SPI_Init” implementation to set the internal SS level</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL TIM</strong>:
+<ul>
+<li>stm32h7xx_ll_tim.h:
+<ul>
+<li>Fix “LL_TIM_GetCounterMode” implementation to handle all possible return combinations</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL UART</strong>:
+<ul>
+<li>stm32h7xx_hal_uart.h:
+<ul>
+<li>Add “HAL_UART_RxTypeTypeDef” type with possible values HAL_UART_RECEPTION_STANDARD, HAL_UART_RECEPTION_TOIDLE, HAL_UART_RECEPTION_TORTO or HAL_UART_RECEPTION_TOCHARMATCH</li>
+<li>Update “UART_HandleTypeDef” structure to add “RxEventCallback”</li>
+<li>Add “pUART_RxEventCallbackTypeDef” type</li>
+</ul></li>
+<li>stm32h7xx_hal_uart_ex.h:
+<ul>
+<li>Add APIs prototypes: HAL_UARTEx_ReceiveToIdle, HAL_UARTEx_ReceiveToIdle_IT and HAL_UARTEx_ReceiveToIdle_DMA</li>
+</ul></li>
+<li>stm32h7xx_hal_uart.c:
+<ul>
+<li>Update “HAL_UART_DeInit” implementation to set the “ReceptionType” to HAL_UART_RECEPTION_STANDARD<br />
+</li>
+<li>Add “HAL_UART_RegisterRxEventCallback” and “HAL_UART_UnRegisterRxEventCallback” APIs implementation</li>
+<li>Update “HAL_UART_Receive”, “HAL_UART_Receive_IT” and “HAL_UART_Receive_DMA” to set the “ReceptionType” to HAL_UART_RECEPTION_STANDARD</li>
+<li>Update “HAL_UART_Abort”, “HAL_UART_AbortReceive”, “HAL_UART_Abort_IT” and “HAL_UART_AbortReceive_IT” to disable IDLEIE interrupt in case of reception till IDLE</li>
+<li>Update “HAL_UART_IRQHandler” to handle reception till IDLE</li>
+<li>Add “HAL_UARTEx_RxEventCallback” weak callback</li>
+</ul></li>
+<li>stm32h7xx_hal_uart_ex.c:
+<ul>
+<li>Add “HAL_UARTEx_ReceiveToIdle”, “HAL_UARTEx_ReceiveToIdle_IT” and “HAL_UARTEx_ReceiveToIdle_DMA” APIs implementation</li>
+</ul></li>
+<li>stm32h7xx_ll_lpuart.h
+<ul>
+<li>Update “LL_LPUART_SetBaudRate” implementation to avoid potential division by zero</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL USART</strong>:
+<ul>
+<li>stm32h7xx_ll_usart.h:
+<ul>
+<li>Update “LL_USART_SetBaudRate” implementation to avoid potential division by zero</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL USB</strong>:
+<ul>
+<li>Update to ensure to have coherency between USB APIs start and stop which should mainly control device connect and disconnect of the USB RPU</li>
+<li>Fix ping with DMA OFF, fix Data toggle issue with DMA multi max packet size transfers and clean up device and core speeds</li>
+<li>Enhance Host CH ERR and halt management</li>
+<li>Update to notify MW upper layers when transaction completes with an error</li>
+<li>Update to fix USB OTG read FIFO packet in stm32h7xx_ll_usb.c file</li>
+<li>Update to support USB OTG FIFO with scatter gather</li>
+</ul></li>
+<li><strong>LL SYSTEM</strong>:
+<ul>
+<li>stm32h7xx_ll_system.h:
+<ul>
+<li>Update LL_SYSCFG_EnableCompensationCell and LL_SYSCFG_DisableCompensationCell according to the STM32H7 product data-sheet</li>
+</ul></li>
+</ul></li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li><strong>HAL/ETH</strong>
+<ul>
+<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
+</ul></li>
+</ul>
+<h2 id="backward-compatibility">Backward compatibility</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li>First official release of the STM32CubeH7 Firmware Package supporting <strong>STM32H72x/3x</strong> new devices</li>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic, Update to support <strong>STM32H72x/3x</strong> new devices
@@ -379,10 +681,10 @@
</ul></li>
<li>stm32h7xx_hal_pwr_ex.c:
<ul>
-<li>Update HAL_PWREx_ControlVoltageScaling implemenation for <strong>STM32H72x/3x</strong> devices<br />
+<li>Update HAL_PWREx_ControlVoltageScaling implementation for <strong>STM32H72x/3x</strong> devices<br />
</li>
<li>Update HAL_PWREx_EnterSTOPMode implementation to domain Deep sleep entry foe each Core (CM7/CM4)</li>
-<li>Update HAL_PWREx_WAKEUP_PIN_IRQHandler implemenation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
+<li>Update HAL_PWREx_WAKEUP_PIN_IRQHandler implementation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
</ul></li>
<li>stm32h7xx_ll_pwr.h
<ul>
@@ -392,7 +694,7 @@
</ul></li>
<li>stm32h7xx_ll_pwr.c
<ul>
-<li>Update LL_PWR_DeInit implemenation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
+<li>Update LL_PWR_DeInit implementation to delimit wakeup pins 3 and 5 usage according to their availability (not available on <strong>STM32H72x/3x</strong> devices)</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL RCC</strong>:
@@ -634,20 +936,20 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility">Backward compatibility</h2>
+<h2 id="backward-compatibility-1">Backward compatibility</h2>
<ul>
-<li>Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 familes)</li>
+<li>Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 families)</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -662,7 +964,7 @@
<ul>
<li>stm32h7xx_hal_dac.c:
<ul>
-<li>Update HAL_DAC_ConfigChannel function implemenation to fix the “DAC_ConnectOnChipPeripheral” check and settings</li>
+<li>Update HAL_DAC_ConfigChannel function implementation to fix the “DAC_ConnectOnChipPeripheral” check and settings</li>
</ul></li>
</ul></li>
<li><strong>HAL/LL GPIO</strong>:
@@ -860,7 +1162,7 @@
<li>stm32h7xx_ll_fmc.h: Minor update to remove useless U suffix following uint32_t cast</li>
<li>stm32h7xx_ll_fmc.c:
<ul>
-<li>Update FMC_NORSRAM_Init implemenation to fix compilation issue with MS Visual 2017</li>
+<li>Update FMC_NORSRAM_Init implementation to fix compilation issue with MS Visual 2017</li>
<li>Update FMC_NAND_CommonSpace_Timing_Init, FMC_NAND_AttributeSpace_Timing_Init, FMC_NAND_ECC_Enable, FMC_NAND_ECC_Disable and FMC_NAND_GetECC to fix GCC compiler warning due to unused parameter</li>
</ul></li>
</ul></li>
@@ -881,7 +1183,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -891,7 +1193,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -900,7 +1202,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
</li>
@@ -937,7 +1239,7 @@
<li>stm32h7xx_hal_adc_ex.h:
<ul>
<li>ADC_IS_INDEPENDENT macro available only when device supports ADC3</li>
-<li>Update ADC_OFFSET_SHIFT_RESOLUTION , ADC_AWD1THRESHOLD_SHIFT_RESOLUTION and ADC_AWD23THRESHOLD_SHIFT_RESOLUTION macros implemenation to support STM32H7A3/B3xx/B0xx new devices<br />
+<li>Update ADC_OFFSET_SHIFT_RESOLUTION , ADC_AWD1THRESHOLD_SHIFT_RESOLUTION and ADC_AWD23THRESHOLD_SHIFT_RESOLUTION macros implementation to support STM32H7A3/B3xx/B0xx new devices<br />
</li>
<li>ADC3_COMMON_REGISTER macro available only when device supports ADC3</li>
<li>Update ADC_MASTER_REGISTER macro to consider ADC3 when it is available only</li>
@@ -955,12 +1257,12 @@
<ul>
<li>Update HAL_ADC_Init implementation to consider STM32H7A3/B3xx/B0xx devices (ADC_VER_V5_3)</li>
<li>Update HAL_ADC_Start_DMA to add configuration of Data transfer mode</li>
-<li>Update HAL_ADC_ConfigChannel implemenation to consider ADC3 when it is available only</li>
-<li>Update ADC_ConfigureBoostMode implemenation to consider frequency ranges for STM32H7A3/B3xx/B0xx devices (ADC_VER_V5_3)</li>
+<li>Update HAL_ADC_ConfigChannel implementation to consider ADC3 when it is available only</li>
+<li>Update ADC_ConfigureBoostMode implementation to consider frequency ranges for STM32H7A3/B3xx/B0xx devices (ADC_VER_V5_3)</li>
</ul></li>
<li>stm32h7xx_hal_adc_ex.c:
<ul>
-<li>Update HAL_ADCEx_LinearCalibration_GetValue and HAL_ADCEx_LinearCalibration_SetValue APIs implementation to stop the Ongoing conversion, if any, before the calibration. In this case the convertion is retsored after the calibration</li>
+<li>Update HAL_ADCEx_LinearCalibration_GetValue and HAL_ADCEx_LinearCalibration_SetValue APIs implementation to stop the Ongoing conversion, if any, before the calibration. In this case the conversion is retsored after the calibration</li>
<li>Update HAL_ADCEx_LinearCalibration_FactorLoad API implementation to consider ADC2 and ADC3 in addition to ADC1</li>
</ul></li>
</ul></li>
@@ -1013,7 +1315,7 @@
<ul>
<li>Backward compatibility ensured by the stm32_hal_legacy header file</li>
</ul></li>
-<li>HRTIM tiggers definitions (DAC_TRIGGER_HR1_TRGO1 and DAC_TRIGGER_HR1_TRGO2) are available only for devices where the HRTIM peripheral is present
+<li>HRTIM triggers definitions (DAC_TRIGGER_HR1_TRGO1 and DAC_TRIGGER_HR1_TRGO2) are available only for devices where the HRTIM peripheral is present
<ul>
<li>HRTIM peripheral not present on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
@@ -1040,7 +1342,7 @@
</ul></li>
<li>stm32h7xx_hal_dac_ex.c:
<ul>
-<li>Add implemenation of HAL_DACEx_DualStart, HAL_DACEx_DualStop, HAL_DACEx_DualStart_DMA, HAL_DACEx_DualStop_DMA, HAL_DACEx_DualSetValue and HAL_DACEx_DualGetValue APIs</li>
+<li>Add implementation of HAL_DACEx_DualStart, HAL_DACEx_DualStop, HAL_DACEx_DualStart_DMA, HAL_DACEx_DualStop_DMA, HAL_DACEx_DualSetValue and HAL_DACEx_DualGetValue APIs</li>
</ul></li>
<li>stm32h7xx_ll_dac.h: Update to support STM32H7A3/B3xx/B0xx devices New DAC triggers</li>
</ul></li>
@@ -1053,7 +1355,7 @@
</ul></li>
<li>stm32h7xx_hal_dcmi.c:
<ul>
-<li>Add implemenation HAL_DCMI_ConfigSyncUnmask API</li>
+<li>Add implementation HAL_DCMI_ConfigSyncUnmask API</li>
</ul></li>
</ul></li>
<li><strong>HAL DFSDM</strong>:
@@ -1450,12 +1752,12 @@
</ul></li>
<li>stm32h7xx_ll_delayblock.c:
<ul>
-<li>Add implemenation of DelayBlock_Configure function allowing to configure the delay block</li>
+<li>Add implementation of DelayBlock_Configure function allowing to configure the delay block</li>
<li>Rework DelayBlock_Enable function (delay block calibration procedure)</li>
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1469,7 +1771,7 @@
<li>New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-2">Backward compatibility</h2>
+<h2 id="backward-compatibility-3">Backward compatibility</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1493,7 +1795,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -1768,11 +2070,11 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-3">Backward compatibility</h2>
+<h2 id="backward-compatibility-4">Backward compatibility</h2>
<ul>
<li><strong>HAL TIM</strong>:
<ul>
@@ -1790,7 +2092,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add support for VOS0 power regulator voltage scaling with 480MHz over clock</li>
@@ -1880,7 +2182,7 @@
<ul>
<li>HAL_ETH_IRQHandler : Remove call to HAL_ETH_IsRxDataAvailable when RX Interrupt occurs as it may update the RX DMA descriptors while the last received data is being proceeded by TCPIP stack/Application: in this case data will be lost or corrupted</li>
</ul></li>
-<li>HAL_ETH_GetRxDataLength: Update descriptor informations (descidx and dmarxdesc) with the last values returned by HAL_ETH_IsRxDataAvailable() when new data is available</li>
+<li>HAL_ETH_GetRxDataLength: Update descriptor information (descidx and dmarxdesc) with the last values returned by HAL_ETH_IsRxDataAvailable() when new data is available</li>
</ul></li>
<li>Update to support <strong>DUAL CORE</strong> lines:
<ul>
@@ -2260,7 +2562,7 @@
<li>Update LL_Init1msTick and LL_SetSystemCoreClock description for <strong>DUAL CORE</strong> lines</li>
</ul></li>
</ul>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
<ul>
<li><strong>HAL SD</strong>:
<ul>
@@ -2274,7 +2576,7 @@
<li>Full duplex Transmit/receive feature not available</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-4">Backward compatibility</h2>
+<h2 id="backward-compatibility-5">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -2326,7 +2628,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</li>
@@ -2595,7 +2897,7 @@
<li>Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled</li>
</ul></li>
</ul>
-<h2 id="known-limitations-5">Known Limitations</h2>
+<h2 id="known-limitations-6">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -2603,7 +2905,7 @@
<li>A new version of this driver will be available in next release with full features tested</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-5">Backward compatibility</h2>
+<h2 id="backward-compatibility-6">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -2643,7 +2945,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers</li>
<li><strong>HAL Cortex</strong>: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15</li>
@@ -2655,7 +2957,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL SPI</strong>: Driver reworked to fix critical issues</li>
@@ -2666,7 +2968,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL FLASH</strong>: Add Mass Erase for both banks</li>
@@ -2681,7 +2983,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>First official release for STM32H743xx/753xx devices</li>
</ul>
diff --git a/Src/stm32h7xx_hal.c b/Src/stm32h7xx_hal.c
index c128145..099fb4b 100644
--- a/Src/stm32h7xx_hal.c
+++ b/Src/stm32h7xx_hal.c
@@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32H7xx HAL Driver version number V1.9.0
+ * @brief STM32H7xx HAL Driver version number V1.10.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
-#define __STM32H7xx_HAL_VERSION_SUB1 (0x09UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB1 (0x0AUL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@@ -507,14 +507,14 @@
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling specifies the output voltage to achieve
* This parameter can be one of the following values:
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
- * This requires VDDA equal to or higher than 2.4 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
- * This requires VDDA equal to or higher than 1.8 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V.
+ * This requires VDDA equal to or higher than 2.4 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V.
* This requires VDDA equal to or higher than 2.1 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V.
+ * This requires VDDA equal to or higher than 1.8 V.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
@@ -769,7 +769,7 @@
/**
* @brief Enables the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
+ * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
* @retval None
*/
void HAL_EnableCompensationCell(void)
@@ -780,7 +780,7 @@
/**
* @brief Power-down the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V.
+ * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
* @retval None
*/
void HAL_DisableCompensationCell(void)
@@ -1021,6 +1021,7 @@
}
#endif /*DUAL_CORE*/
+#if defined(DBGMCU_CR_DBG_STOPD3)
/**
* @brief Enable the Debug Module during Domain3/SRDomain STOP mode
* @retval None
@@ -1029,6 +1030,7 @@
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
}
+
/**
* @brief Disable the Debug Module during Domain3/SRDomain STOP mode
* @retval None
@@ -1037,7 +1039,9 @@
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
}
+#endif /*DBGMCU_CR_DBG_STOPD3*/
+#if defined(DBGMCU_CR_DBG_STANDBYD3)
/**
* @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode
* @retval None
@@ -1055,6 +1059,7 @@
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
}
+#endif /*DBGMCU_CR_DBG_STANDBYD3*/
/**
* @brief Set the FMC Memory Mapping Swapping config.
diff --git a/Src/stm32h7xx_hal_adc.c b/Src/stm32h7xx_hal_adc.c
index 9c1b530..7803f92 100644
--- a/Src/stm32h7xx_hal_adc.c
+++ b/Src/stm32h7xx_hal_adc.c
@@ -3,7 +3,7 @@
* @file stm32h7xx_hal_adc.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Initialization and de-initialization functions
* ++ Initialization and Configuration of ADC
@@ -26,7 +26,7 @@
[..]
(+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
Note: On devices STM32H72xx and STM32H73xx, these resolution are applicable to instances ADC1 and ADC2.
- ADC3 is featuring resolutions 12-bit, 10-bit, 8-bit, 6-bit.
+ ADC3 is featuring resolutions 12-bit, 10-bit, 8-bit, 6-bit.
(+) Interrupt generation at the end of regular conversion and in case of
analog watchdog or overrun events.
@@ -510,7 +510,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -1054,32 +1054,31 @@
HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
*/
ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
- }
- /* DeInit the low level hardware.
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripherals instances */
+ /* sharing the same common ADC instance: ADC state is forced to */
+ /* a similar state as after device power-on. */
+ /* Note: A possible implementation is to add RCC bus reset of ADC */
+ /* (for example, using macro */
+ /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+ /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
- For example:
- __HAL_RCC_ADC_FORCE_RESET();
- __HAL_RCC_ADC_RELEASE_RESET();
- __HAL_RCC_ADC_CLK_DISABLE();
-
- Keep in mind that all ADCs use the same clock: disabling
- the clock will reset all ADCs.
-
- */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- if (hadc->MspDeInitCallback == NULL)
- {
- hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
- }
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
- /* DeInit the low level hardware: RCC clock, NVIC */
- hadc->MspDeInitCallback(hadc);
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ hadc->MspDeInitCallback(hadc);
#else
- /* DeInit the low level hardware: RCC clock, NVIC */
- HAL_ADC_MspDeInit(hadc);
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
@@ -1646,13 +1645,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -1757,13 +1760,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if(__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -2274,7 +2281,7 @@
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
- /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1, 0UL);
/* Disable the DMA channel (in case of DMA in circular mode or stop */
@@ -3056,7 +3063,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -3124,7 +3131,7 @@
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef".
- * @note On this STM32 serie, analog watchdog thresholds cannot be modified
+ * @note On this STM32 series, analog watchdog thresholds cannot be modified
* while ADC conversion is on going.
* @param hadc ADC handle
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
@@ -3641,13 +3648,17 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
@@ -3718,13 +3729,17 @@
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
}
@@ -3779,13 +3794,17 @@
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
}
diff --git a/Src/stm32h7xx_hal_adc_ex.c b/Src/stm32h7xx_hal_adc_ex.c
index a325f76..8e44bf1 100644
--- a/Src/stm32h7xx_hal_adc_ex.c
+++ b/Src/stm32h7xx_hal_adc_ex.c
@@ -3,7 +3,7 @@
* @file stm32h7xx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Operation functions
* ++ Start, stop, get result of conversions of ADC group injected,
@@ -349,7 +349,7 @@
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
+ wait_loop_index = ((ADC_STAB_DELAY_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -682,13 +682,16 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ if((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -1026,6 +1029,8 @@
/* Process locked */
__HAL_LOCK(hadc);
+ tmphadcSlave.State = HAL_ADC_STATE_RESET;
+ tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1141,6 +1146,9 @@
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
+ tmphadcSlave.State = HAL_ADC_STATE_RESET;
+ tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1168,13 +1176,21 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- return HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
@@ -1623,6 +1639,9 @@
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ tmphadcSlave.State = HAL_ADC_STATE_RESET;
+ tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1650,13 +1669,21 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- return HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
@@ -2234,7 +2261,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -2316,6 +2343,9 @@
/* Process locked */
__HAL_LOCK(hadc);
+ tmphadcSlave.State = HAL_ADC_STATE_RESET;
+ tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
+
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
if (tmphadcSlave.Instance == NULL)
diff --git a/Src/stm32h7xx_hal_cec.c b/Src/stm32h7xx_hal_cec.c
index 72ad84e..d732a36 100644
--- a/Src/stm32h7xx_hal_cec.c
+++ b/Src/stm32h7xx_hal_cec.c
@@ -822,19 +822,15 @@
/* CEC TX byte request interrupt ------------------------------------------------*/
if ((reg & CEC_FLAG_TXBR) != 0U)
{
+ --hcec->TxXferCount;
if (hcec->TxXferCount == 0U)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr;
- hcec->pTxBuffPtr++;
}
- else
- {
- hcec->Instance->TXDR = *hcec->pTxBuffPtr;
- hcec->pTxBuffPtr++;
- hcec->TxXferCount--;
- }
+ /* In all cases transmit the byte */
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+ hcec->pTxBuffPtr++;
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
}
diff --git a/Src/stm32h7xx_hal_comp.c b/Src/stm32h7xx_hal_comp.c
index aae1146..59a2590 100644
--- a/Src/stm32h7xx_hal_comp.c
+++ b/Src/stm32h7xx_hal_comp.c
@@ -372,7 +372,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles.*/
- wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000UL * 2UL)));
+ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
@@ -782,7 +782,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
- wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
+ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -879,7 +879,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
- wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
+ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
diff --git a/Src/stm32h7xx_hal_cordic.c b/Src/stm32h7xx_hal_cordic.c
index 85c19c1..37f70e7 100644
--- a/Src/stm32h7xx_hal_cordic.c
+++ b/Src/stm32h7xx_hal_cordic.c
@@ -363,7 +363,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
{
HAL_StatusTypeDef status = HAL_OK;
@@ -525,8 +526,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions
- * @brief Control functions.
- *
+ * @brief Control functions.
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -602,7 +603,8 @@
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
@@ -659,8 +661,7 @@
return HAL_ERROR;
}
}
- }
- while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
+ } while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
/* Read output data from Read Data register, and increment output buffer pointer */
CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
@@ -696,7 +697,8 @@
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
@@ -788,7 +790,8 @@
* @param NbCalc Number of CORDIC calculation to process.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc)
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc)
{
int32_t *tmp_pInBuff = pInBuff;
@@ -879,7 +882,8 @@
* DMA transfer to and from the Peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection)
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t DMADirection)
{
uint32_t sizeinbuff;
uint32_t sizeoutbuff;
@@ -1026,8 +1030,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group3 Callback functions
- * @brief Callback functions.
- *
+ * @brief Callback functions.
+ *
@verbatim
==============================================================================
##### Callback functions #####
@@ -1077,8 +1081,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management
- * @brief IRQ handler.
- *
+ * @brief IRQ handler.
+ *
@verbatim
==============================================================================
##### IRQ handler management #####
@@ -1147,8 +1151,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
diff --git a/Src/stm32h7xx_hal_crc_ex.c b/Src/stm32h7xx_hal_crc_ex.c
index 6e5861b..97e70c1 100644
--- a/Src/stm32h7xx_hal_crc_ex.c
+++ b/Src/stm32h7xx_hal_crc_ex.c
@@ -11,7 +11,7 @@
##### How to use this driver #####
================================================================================
[..]
- (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+ (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
diff --git a/Src/stm32h7xx_hal_cryp.c b/Src/stm32h7xx_hal_cryp.c
index 0407c65..c1febda 100644
--- a/Src/stm32h7xx_hal_cryp.c
+++ b/Src/stm32h7xx_hal_cryp.c
@@ -4357,10 +4357,23 @@
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t loopcounter;
+ uint32_t size_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
/***************************** Header phase for GCM/GMAC or CCM *********************************/
- if ((hcryp->Init.HeaderSize != 0U))
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ size_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ size_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if ((size_in_bytes != 0U))
{
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
@@ -4368,10 +4381,12 @@
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
+ if ((size_in_bytes % 16U) == 0U)
{
- /* HeaderSize %4, no padding */
- for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ /* No padding */
+ for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
+
{
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
@@ -4400,8 +4415,8 @@
}
else
{
- /*Write header block in the IN FIFO without last block */
- for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ /* Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
{
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
@@ -4428,16 +4443,34 @@
}
}
/* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while (loopcounter < 4U)
+ /* If the header size is a multiple of words */
+ if ((size_in_bytes % 4U) == 0U)
{
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DIN = 0x0U;
- loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeroes */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[size_in_bytes % 4U];
+ hcryp->Instance->DIN = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
}
/* Wait for CCF IFEM to be raised */
if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
diff --git a/Src/stm32h7xx_hal_cryp_ex.c b/Src/stm32h7xx_hal_cryp_ex.c
index a8a94aa..ae24733 100644
--- a/Src/stm32h7xx_hal_cryp_ex.c
+++ b/Src/stm32h7xx_hal_cryp_ex.c
@@ -113,9 +113,15 @@
{
uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
- uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
+ uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
+ /* Correct header length if Init.HeaderSize is actually in bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
+ {
+ headerlength /= 4U;
+ }
+
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
diff --git a/Src/stm32h7xx_hal_dac.c b/Src/stm32h7xx_hal_dac.c
index 89fbd80..db5ab8c 100644
--- a/Src/stm32h7xx_hal_dac.c
+++ b/Src/stm32h7xx_hal_dac.c
@@ -693,7 +693,7 @@
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
- /* Enable the DMA Stream */
+ /* Enable the DMA Stream */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
else
@@ -734,8 +734,6 @@
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
- HAL_StatusTypeDef status;
-
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -751,7 +749,7 @@
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA Stream */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ (void)HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
@@ -759,26 +757,17 @@
else /* Channel2 is used for */
{
/* Disable the DMA Stream */
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ (void)HAL_DMA_Abort(hdac->DMA_Handle2);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
- /* Check if DMA Stream effectively disabled */
- if (status != HAL_OK)
- {
- /* Update DAC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -1085,9 +1074,11 @@
}
/* HoldTime */
- MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
/* RefreshTime */
- MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
}
if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
@@ -1339,7 +1330,7 @@
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
diff --git a/Src/stm32h7xx_hal_dac_ex.c b/Src/stm32h7xx_hal_dac_ex.c
index 15dc83e..50dd895 100644
--- a/Src/stm32h7xx_hal_dac_ex.c
+++ b/Src/stm32h7xx_hal_dac_ex.c
@@ -128,11 +128,11 @@
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Check if software trigger enabled */
- if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
+ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
}
- if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
+ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
}
@@ -380,7 +380,8 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the triangle wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -429,7 +430,8 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the noise wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
diff --git a/Src/stm32h7xx_hal_dcmi.c b/Src/stm32h7xx_hal_dcmi.c
index 46906e0..f9079cf 100644
--- a/Src/stm32h7xx_hal_dcmi.c
+++ b/Src/stm32h7xx_hal_dcmi.c
@@ -571,7 +571,7 @@
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
- /* Disable Capture */
+ /* Enable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
}
/* Process Unlocked */
diff --git a/Src/stm32h7xx_hal_dma.c b/Src/stm32h7xx_hal_dma.c
index 6a8bce5..934400c 100644
--- a/Src/stm32h7xx_hal_dma.c
+++ b/Src/stm32h7xx_hal_dma.c
@@ -292,7 +292,7 @@
}
/* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
- lock when transfering data to/from USART/UART */
+ lock when transferring data to/from USART/UART */
#if (STM32H7_DEV_ID == 0x450UL)
if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
{
@@ -967,7 +967,7 @@
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param CompleteLevel: Specifies the DMA level complete.
- * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+ * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead.
* This model could be used for debug purpose.
* @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
* @param Timeout: Timeout duration.
diff --git a/Src/stm32h7xx_hal_dma2d.c b/Src/stm32h7xx_hal_dma2d.c
index 1703055..dcc1883 100644
--- a/Src/stm32h7xx_hal_dma2d.c
+++ b/Src/stm32h7xx_hal_dma2d.c
@@ -201,7 +201,8 @@
/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height);
/**
* @}
*/
@@ -213,8 +214,8 @@
*/
/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -237,9 +238,9 @@
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
/* Check the DMA2D peripheral state */
- if(hdma2d == NULL)
+ if (hdma2d == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
@@ -258,7 +259,7 @@
/* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
- if(hdma2d->MspInitCallback == NULL)
+ if (hdma2d->MspInitCallback == NULL)
{
hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
}
@@ -267,7 +268,7 @@
hdma2d->MspInitCallback(hdma2d);
}
#else
- if(hdma2d->State == HAL_DMA2D_STATE_RESET)
+ if (hdma2d->State == HAL_DMA2D_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
@@ -283,12 +284,15 @@
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
/* DMA2D OPFCCR register configuration ---------------------------------------*/
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB,
+ hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
/* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
- MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
+ MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS),
+ ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \
+ (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
/* Update error code */
@@ -312,9 +316,9 @@
{
/* Check the DMA2D peripheral state */
- if(hdma2d == NULL)
+ if (hdma2d == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Before aborting any DMA2D transfer or CLUT loading, check
@@ -367,13 +371,13 @@
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
- if(hdma2d->MspDeInitCallback == NULL)
- {
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
- }
+ if (hdma2d->MspDeInitCallback == NULL)
+ {
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
+ }
- /* DeInit the low level hardware */
- hdma2d->MspDeInitCallback(hdma2d);
+ /* DeInit the low level hardware */
+ hdma2d->MspDeInitCallback(hdma2d);
#else
/* Carry on with de-initialization of low level hardware */
@@ -398,7 +402,7 @@
* the configuration information for the DMA2D.
* @retval None
*/
-__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
+__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
@@ -414,7 +418,7 @@
* the configuration information for the DMA2D.
* @retval None
*/
-__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
+__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
@@ -441,11 +445,12 @@
* @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
* @retval status
*/
-HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
+ pDMA2D_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
@@ -454,68 +459,68 @@
/* Process locked */
__HAL_LOCK(hdma2d);
- if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ if (HAL_DMA2D_STATE_READY == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
- hdma2d->XferCpltCallback = pCallback;
- break;
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = pCallback;
+ break;
- case HAL_DMA2D_TRANSFERERROR_CB_ID :
- hdma2d->XferErrorCallback = pCallback;
- break;
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = pCallback;
+ break;
- case HAL_DMA2D_LINEEVENT_CB_ID :
- hdma2d->LineEventCallback = pCallback;
- break;
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = pCallback;
+ break;
- case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
- hdma2d->CLUTLoadingCpltCallback = pCallback;
- break;
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = pCallback;
+ break;
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = pCallback;
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
/* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -540,73 +545,73 @@
*/
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
{
-HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma2d);
- if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ if (HAL_DMA2D_STATE_READY == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
- hdma2d->XferCpltCallback = NULL;
- break;
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = NULL;
+ break;
- case HAL_DMA2D_TRANSFERERROR_CB_ID :
- hdma2d->XferErrorCallback = NULL;
- break;
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = NULL;
+ break;
- case HAL_DMA2D_LINEEVENT_CB_ID :
- hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
- break;
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ break;
- case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
- hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
- break;
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ break;
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
{
switch (CallbackID)
{
- case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
- /* Update the error code */
- hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -621,8 +626,8 @@
/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -664,11 +669,13 @@
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -698,11 +705,13 @@
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -718,7 +727,7 @@
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
/* Enable the transfer complete, transfer error and configuration error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
@@ -733,11 +742,13 @@
* @param SrcAddress1 The source memory Buffer address for the foreground layer.
* @param SrcAddress2 The source memory Buffer address for the background layer.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -749,7 +760,7 @@
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+ if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
@@ -765,11 +776,11 @@
}
else
{
- /* Configure DMA2D Stream source2 address */
- WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
+ /* Configure DMA2D Stream source2 address */
+ WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
- /* Configure the source, destination address and the data size */
- DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
+ /* Configure the source, destination address and the data size */
+ DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
/* Enable the Peripheral */
@@ -785,11 +796,13 @@
* @param SrcAddress1 The source memory Buffer address for the foreground layer.
* @param SrcAddress2 The source memory Buffer address for the background layer.
* @param DstAddress The destination memory Buffer address.
- * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Width The width of data to be transferred from source
+ * to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
+ uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
@@ -801,7 +814,7 @@
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
+ if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
@@ -824,7 +837,7 @@
}
/* Enable the transfer complete, transfer error and configuration error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
@@ -846,15 +859,15 @@
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue) */
- MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively disabled */
- while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+ while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -870,7 +883,7 @@
}
/* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Change the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -895,7 +908,7 @@
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
- MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
+ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
/* Get tick */
tickstart = HAL_GetTick();
@@ -903,7 +916,7 @@
/* Check if the DMA2D is effectively suspended */
while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -915,7 +928,7 @@
}
}
- /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
@@ -923,7 +936,7 @@
else
{
/* Make sure SUSP bit is cleared since it is meaningless
- when no tranfer is on-going */
+ when no transfer is on-going */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
}
@@ -939,7 +952,7 @@
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
{
/* Check the SUSP and START bits */
- if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
+ if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
{
/* Ongoing transfer is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
@@ -949,7 +962,7 @@
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
- CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
+ CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
return HAL_OK;
}
@@ -975,7 +988,7 @@
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Enable the background CLUT loading */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1014,14 +1027,14 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1034,9 +1047,9 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
- /* Enable the CLUT loading for the foreground */
+ /* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
@@ -1054,7 +1067,8 @@
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
+ uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
@@ -1068,17 +1082,17 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1091,10 +1105,10 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
@@ -1131,14 +1145,14 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1151,9 +1165,9 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
- /* Enable the CLUT loading for the foreground */
+ /* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
@@ -1188,17 +1202,17 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -1211,10 +1225,10 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
@@ -1235,13 +1249,13 @@
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
uint32_t tickstart;
- const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Abort the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == DMA2D_FOREGROUND_LAYER)
+ if (LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
@@ -1251,9 +1265,9 @@
tickstart = HAL_GetTick();
/* Check if the CLUT loading is aborted */
- while((*reg & DMA2D_BGPFCCR_START) != 0U)
+ while ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1269,7 +1283,7 @@
}
/* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
- __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
+ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Change the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -1293,13 +1307,13 @@
{
uint32_t tickstart;
uint32_t loadsuspended;
- const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Suspend the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == DMA2D_FOREGROUND_LAYER)
+ if (LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
@@ -1308,11 +1322,13 @@
tickstart = HAL_GetTick();
/* Check if the CLUT loading is suspended */
- loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
- loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
+ /* 1st condition: Suspend Check */
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+ /* 2nd condition: Not Start Check */
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
while (loadsuspended == 0UL)
{
- if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
+ if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1322,11 +1338,13 @@
return HAL_TIMEOUT;
}
- loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
- loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
+ /* 1st condition: Suspend Check */
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
+ /* 2nd condition: Not Start Check */
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
}
- /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
+ /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
if ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
@@ -1334,7 +1352,7 @@
else
{
/* Make sure SUSP bit is cleared since it is meaningless
- when no tranfer is on-going */
+ when no transfer is on-going */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
}
@@ -1353,18 +1371,18 @@
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
/* Check the SUSP and START bits for background or foreground CLUT loading */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Background CLUT loading suspension check */
if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
- if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+ if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
{
- /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
}
}
- }
else
{
/* Foreground CLUT loading suspension check */
@@ -1372,11 +1390,11 @@
{
if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
{
- /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
- hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
+ hdma2d->State = HAL_DMA2D_STATE_BUSY;
+ }
}
}
- }
/* Resume the CLUT loading */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
@@ -1400,15 +1418,15 @@
__IO uint32_t isrflags = 0x0U;
/* Polling for DMA2D transfer */
- if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Get tick */
+ tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
+ while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
+ if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
{
if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
@@ -1430,9 +1448,9 @@
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1456,10 +1474,10 @@
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
+ while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
+ if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
{
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
@@ -1477,7 +1495,7 @@
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
/* Change DMA2D state */
- hdma2d->State= HAL_DMA2D_STATE_ERROR;
+ hdma2d->State = HAL_DMA2D_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
@@ -1485,15 +1503,15 @@
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
- hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
+ hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
@@ -1505,7 +1523,7 @@
}
/* Clear the transfer complete and CLUT loading flags */
- __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
+ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -1546,7 +1564,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferErrorCallback != NULL)
+ if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
@@ -1573,7 +1591,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferErrorCallback != NULL)
+ if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
@@ -1600,7 +1618,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferErrorCallback != NULL)
+ if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
@@ -1647,7 +1665,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
- if(hdma2d->XferCpltCallback != NULL)
+ if (hdma2d->XferCpltCallback != NULL)
{
/* Transfer complete Callback */
hdma2d->XferCpltCallback(hdma2d);
@@ -1722,8 +1740,8 @@
*/
/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -1753,15 +1771,16 @@
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
DMA2D_LayerCfgTypeDef *pLayerCfg;
- uint32_t regMask, regValue;
+ uint32_t regMask;
+ uint32_t regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
- if(hdma2d->Init.Mode != DMA2D_R2M)
+ if (hdma2d->Init.Mode != DMA2D_R2M)
{
assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
- if(hdma2d->Init.Mode != DMA2D_M2M)
+ if (hdma2d->Init.Mode != DMA2D_M2M)
{
assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
}
@@ -1769,7 +1788,7 @@
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
- if((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR))
+ if ((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR))
{
assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling));
}
@@ -1783,7 +1802,7 @@
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
/* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
- regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
@@ -1794,11 +1813,11 @@
}
else
{
- regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
+ regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
}
/* Configure the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
@@ -1809,20 +1828,21 @@
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
- WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
+ WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
+ DMA2D_BGCOLR_RED));
}
}
/* Configure the foreground DMA2D layer */
else
{
- if(pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
+ if (pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR)
{
regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos);
regMask |= DMA2D_FGPFCCR_CSS;
}
- /* Write DMA2D FGPFCCR register */
+ /* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
/* DMA2D FGOR register configuration -------------------------------------*/
@@ -1831,7 +1851,8 @@
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
- WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
+ WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
+ DMA2D_FGCOLR_RED));
}
}
/* Initialize the DMA2D state*/
@@ -1871,24 +1892,24 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == DMA2D_BACKGROUND_LAYER)
+ if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
- }
- /* Configure the CLUT of the foreground DMA2D layer */
- else
- {
- /* Write foreground CLUT memory address */
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
+ }
+ /* Configure the CLUT of the foreground DMA2D layer */
+ else
+ {
+ /* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
}
/* Set the DMA2D state to Ready*/
@@ -1914,8 +1935,6 @@
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
{
/* Check the parameters */
- assert_param(IS_DMA2D_LINEWATERMARK(Line));
-
if (Line > DMA2D_LWR_LW)
{
return HAL_ERROR;
@@ -2022,8 +2041,8 @@
/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -2082,7 +2101,8 @@
* @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
-static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
+static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
+ uint32_t Height)
{
uint32_t tmp;
uint32_t tmp1;
@@ -2091,7 +2111,7 @@
uint32_t tmp4;
/* Configure DMA2D data size */
- MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
+ MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
@@ -2107,7 +2127,7 @@
/* Prepare the value to be written to the OCOLR register according to the color mode */
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
{
- tmp = (tmp3 | tmp2 | tmp1| tmp4);
+ tmp = (tmp3 | tmp2 | tmp1 | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
{
@@ -2117,7 +2137,7 @@
{
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 10U);
- tmp4 = (tmp4 >> 3U );
+ tmp4 = (tmp4 >> 3U);
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
@@ -2125,7 +2145,7 @@
tmp1 = (tmp1 >> 31U);
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 11U);
- tmp4 = (tmp4 >> 3U );
+ tmp4 = (tmp4 >> 3U);
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
@@ -2133,15 +2153,15 @@
tmp1 = (tmp1 >> 28U);
tmp2 = (tmp2 >> 20U);
tmp3 = (tmp3 >> 12U);
- tmp4 = (tmp4 >> 4U );
+ tmp4 = (tmp4 >> 4U);
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
}
- else if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
+ else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
{
- WRITE_REG(hdma2d->Instance->BGMAR , pdata);
+ WRITE_REG(hdma2d->Instance->BGMAR, pdata);
}
else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
{
diff --git a/Src/stm32h7xx_hal_dsi.c b/Src/stm32h7xx_hal_dsi.c
index 6b93e38..073c2a6 100644
--- a/Src/stm32h7xx_hal_dsi.c
+++ b/Src/stm32h7xx_hal_dsi.c
@@ -13,36 +13,57 @@
==============================================================================
##### How to use this driver #####
==============================================================================
+ [..]
+ The DSI HAL driver can be used as follows:
+
+ (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi;
+
+ (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API:
+ (##) Enable the DSI interface clock
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the DSI interrupt priority
+ (+++) Enable the NVIC DSI IRQ Channel
+
+ (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and
+ TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit().
+
+ *** Configuration ***
+ =========================
[..]
- (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
- PLL parameters, number of lanes and TX Escape clock divider.
- (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
+ (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
command mode.
- (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
- (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
- (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
- (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
- Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
+
+ (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host.
+
+ (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
+
+ (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer().
+
+ (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop().
+ Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively
to write DSI short packets, long packets and to read DSI packets.
(#) The DSI Host Offers two Low power modes :
- (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
- It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
- and @ref HAL_DSI_ExitULPMData()
+ (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
+ It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData()
+ and HAL_DSI_ExitULPMData()
- (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
- It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
- and @ref HAL_DSI_ExitULPM()
-
- (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
- When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
- the error code by calling function @ref HAL_DSI_GetError()
+ (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
+ It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM()
+ and HAL_DSI_ExitULPM()
(#) To control DSI state you can use the following function: HAL_DSI_GetState()
- *** DSI HAL driver macros list ***
- =============================================
- [..]
+ *** Error management ***
+ ========================
+ [..]
+ (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor()
+ When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve
+ the error code by calling function HAL_DSI_GetError()
+
+ *** DSI HAL driver macros list ***
+ =============================================
+ [..]
Below the list of most used macros in DSI HAL driver.
(+) __HAL_DSI_ENABLE: Enable the DSI Host.
@@ -59,58 +80,63 @@
(+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
(+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
+ [..]
+ (@) You can refer to the DSI HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function HAL_DSI_RegisterCallback() to register a callback.
- *** Callback registration ***
- =============================================
+ [..]
+ Function HAL_DSI_RegisterCallback() allows to register following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
- The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_DSI_RegisterCallback() to register a callback.
+ [..]
+ Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ [..]
+ This function allows to reset following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
- Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
- (+) TearingEffectCallback : DSI Tearing Effect Callback.
- (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
- (+) ErrorCallback : DSI Error Callback
- (+) MspInitCallback : DSI MspInit.
- (+) MspDeInitCallback : DSI MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
+ [..]
+ By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
+ and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
- Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
- weak function.
- @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
- and the Callback ID.
- This function allows to reset following callbacks:
- (+) TearingEffectCallback : DSI Tearing Effect Callback.
- (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
- (+) ErrorCallback : DSI Error Callback
- (+) MspInitCallback : DSI MspInit.
- (+) MspDeInitCallback : DSI MspDeInit.
+ [..]
+ Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit()
+ or HAL_DSI_Init() function.
- By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
- all callbacks are set to the corresponding weak functions:
- examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
- Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
- these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
- Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
- or HAL_DSI_Init function.
-
- When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
-
- [..]
- (@) You can refer to the DSI HAL driver header file for more useful macros
+ [..]
+ When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
@@ -2263,7 +2289,7 @@
* @brief Custom lane pins configuration
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CustomLane Function to be applyed on selected lane.
+ * @param CustomLane Function to be applied on selected lane.
* This parameter can be any value of @arg DSI_CustomLane
* @param Lane select between clock or data lane 0 or data lane 1.
* This parameter can be any value of @arg DSI_Lane_Select
diff --git a/Src/stm32h7xx_hal_eth.c b/Src/stm32h7xx_hal_eth.c
index 033739e..decff79 100644
--- a/Src/stm32h7xx_hal_eth.c
+++ b/Src/stm32h7xx_hal_eth.c
@@ -902,7 +902,7 @@
/* Set the ETH peripheral state to BUSY */
heth->gState = HAL_ETH_STATE_BUSY;
- /* Disable intrrupts:
+ /* Disable interrupts:
- Tx complete interrupt
- Rx complete interrupt
- Fatal bus interrupt
@@ -986,7 +986,7 @@
tickstart = HAL_GetTick();
- /* Wait for data to be transmitted or timeout occured */
+ /* Wait for data to be transmitted or timeout occurred */
while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
{
if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
@@ -1232,7 +1232,7 @@
}
}
- /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */
+ /* Get intermediate descriptors buffers: in case of the Packet is split into multi descriptors */
for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
{
/* Get Address and length of the first buffer address */
@@ -1519,7 +1519,7 @@
{
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
- /* if fatal bus error occured */
+ /* if fatal bus error occurred */
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
{
/* Get DMA error code */
@@ -2242,7 +2242,7 @@
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
- * that contains the Power Down configration
+ * that contains the Power Down configuration
* @retval None.
*/
void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
@@ -2702,7 +2702,7 @@
WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
- /* Set Rx descritors adresses */
+ /* Set Rx descritors addresses */
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
}
@@ -2740,9 +2740,10 @@
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
+ uint32_t bd_count = 0;
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+ if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
{
return HAL_ETH_ERROR_BUSY;
}
@@ -2778,7 +2779,7 @@
}
}
- /* if tcp segementation is enabled for this packet */
+ /* if tcp segmentation is enabled for this packet */
if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
{
/* Set MSS value */
@@ -2880,7 +2881,7 @@
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
}
- /* only if the packet is splitted into more than one descriptors > 1 */
+ /* only if the packet is split into more than one descriptors > 1 */
while (txbuffer->next != NULL)
{
/* Clear the LD bit of previous descriptor */
@@ -2894,7 +2895,7 @@
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
+ if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
{
descidx = firstdescidx;
dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
@@ -2958,6 +2959,7 @@
}
}
+ bd_count += 1U;
/* Set Own bit */
SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
/* Mark it as NORMAL descriptor */
@@ -2966,20 +2968,31 @@
if(ItMode != ((uint32_t)RESET))
{
- /* Set Interrupt on completition bit */
+ /* Set Interrupt on completion bit */
SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
}
else
{
- /* Clear Interrupt on completition bit */
+ /* Clear Interrupt on completion bit */
CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
}
/* Mark it as LAST descriptor */
SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+ /* Save the current packet address to expose it to the application */
+ dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
dmatxdesclist->CurTxDesc = descidx;
+ /* disable the interrupt */
+ __disable_irq();
+
+ dmatxdesclist->BuffersInUse += bd_count + 1U;
+
+ /* Enable interrupts back */
+ __enable_irq();
+
+
/* Return function status */
return HAL_ETH_ERROR_NONE;
}
diff --git a/Src/stm32h7xx_hal_eth_ex.c b/Src/stm32h7xx_hal_eth_ex.c
index 8504f75..5672dfe 100644
--- a/Src/stm32h7xx_hal_eth_ex.c
+++ b/Src/stm32h7xx_hal_eth_ex.c
@@ -494,8 +494,8 @@
* @brief Enters the Low Power Idle (LPI) mode
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param TxAutomate: Enable/Disbale automate enter/exit LPI mode.
- * @param TxClockStop: Enable/Disbale Tx clock stop in LPI mode.
+ * @param TxAutomate: Enable/Disable automate enter/exit LPI mode.
+ * @param TxClockStop: Enable/Disable Tx clock stop in LPI mode.
* @retval None
*/
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
diff --git a/Src/stm32h7xx_hal_exti.c b/Src/stm32h7xx_hal_exti.c
index 4b2c662..e49dc3a 100644
--- a/Src/stm32h7xx_hal_exti.c
+++ b/Src/stm32h7xx_hal_exti.c
@@ -32,34 +32,34 @@
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
- be selected throught multiplexer.
+ be selected through multiplexer.
- (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
+ (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear source.
It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
Value can be one of the following:
- (++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
+ (++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 0
(+++) On a configurable Line : the D3 domain wakeup signal is
automatically cleared after after the Delay + Rising Edge detect
(+++) On a direct Line : the D3 domain wakeup signal is
cleared after the direct event input signal is cleared
- (++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
+ (++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b00 :
DMA ch6 event selected as D3 domain pendclear source
- (++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
+ (++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b01 :
DMA ch7 event selected as D3 domain pendclear source
- (++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
+ (++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b10 :
LPTIM4 out selected as D3 domain pendclear source
- (++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
+ (++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selected :
In this case corresponding bit of D2PMRx register is set to 1
and corresponding bits(2) of D3PCRxL/H is set to b11 :
LPTIM5 out selected as D3 domain pendclear source
diff --git a/Src/stm32h7xx_hal_fdcan.c b/Src/stm32h7xx_hal_fdcan.c
index 35b51b6..0549620 100644
--- a/Src/stm32h7xx_hal_fdcan.c
+++ b/Src/stm32h7xx_hal_fdcan.c
@@ -67,7 +67,7 @@
registers through the configuration functions listed here above.
(#) All other control functions can be called any time after initialization
- phase, no matter if the FDCAN module is started or stoped.
+ phase, no matter if the FDCAN module is started or stopped.
*** Polling mode operation ***
==============================
@@ -2802,7 +2802,7 @@
return HAL_ERROR;
}
- /* Check that there is no transmittion request pending for the selected buffer */
+ /* Check that there is no transmission request pending for the selected buffer */
if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
{
/* Update error code */
@@ -3311,7 +3311,7 @@
*/
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
{
- /* Check pending transmittion request on the selected buffer */
+ /* Check pending transmission request on the selected buffer */
if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
{
return 0;
@@ -5059,14 +5059,14 @@
if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
{
/* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
- but interrupt will only occure if TC is enabled in IE register */
+ but interrupt will only occur if TC is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
}
if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
{
/* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
- but interrupt will only occure if TCF is enabled in IE register */
+ but interrupt will only occur if TCF is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
}
diff --git a/Src/stm32h7xx_hal_flash.c b/Src/stm32h7xx_hal_flash.c
index 6383da5..a73e8ed 100644
--- a/Src/stm32h7xx_hal_flash.c
+++ b/Src/stm32h7xx_hal_flash.c
@@ -134,11 +134,16 @@
*/
/**
- * @brief Program flash word at a specified address
+ * @brief Program a flash word at a specified address
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param FlashAddress specifies the address to be programmed.
- * @param DataAddress specifies the address of data to be programmed
+ * This parameter shall be aligned to the Flash word:
+ * - 256 bits for STM32H74x/5X devices (8x 32bits words)
+ * - 128 bits for STM32H7Ax/BX devices (4x 32bits words)
+ * - 256 bits for STM32H72x/3X devices (8x 32bits words)
+ * @param DataAddress specifies the address of data to be programmed.
+ * This parameter shall be 32-bit aligned
*
* @retval HAL_StatusTypeDef HAL Status
*/
@@ -292,11 +297,16 @@
}
/**
- * @brief Program flash words of 256 bits at a specified address with interrupt enabled.
+ * @brief Program a flash word at a specified address with interrupt enabled.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param FlashAddress specifies the address to be programmed.
- * @param DataAddress specifies the address of data (256 bits) to be programmed
+ * This parameter shall be aligned to the Flash word:
+ * - 256 bits for STM32H74x/5X devices (8x 32bits words)
+ * - 128 bits for STM32H7Ax/BX devices (4x 32bits words)
+ * - 256 bits for STM32H72x/3X devices (8x 32bits words)
+ * @param DataAddress specifies the address of data to be programmed.
+ * This parameter shall be 32-bit aligned
*
* @retval HAL Status
*/
diff --git a/Src/stm32h7xx_hal_flash_ex.c b/Src/stm32h7xx_hal_flash_ex.c
index dc45d4a..d021924 100644
--- a/Src/stm32h7xx_hal_flash_ex.c
+++ b/Src/stm32h7xx_hal_flash_ex.c
@@ -22,7 +22,7 @@
(+) Global readout protection (RDP)
(+) Write protection
(+) Secure access only protection
- (+) Bank / register swapping
+ (+) Bank / register swapping (when Dual-Bank)
(+) Cyclic Redundancy Check (CRC)
##### How to use this driver #####
@@ -1813,7 +1813,7 @@
}
/**
- * @brief Get the TCM / AXI Shared RAM configurtion.
+ * @brief Get the TCM / AXI Shared RAM configuration.
* @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration.
* This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED
*/
diff --git a/Src/stm32h7xx_hal_gfxmmu.c b/Src/stm32h7xx_hal_gfxmmu.c
index d1bdcbd..bed9b62 100644
--- a/Src/stm32h7xx_hal_gfxmmu.c
+++ b/Src/stm32h7xx_hal_gfxmmu.c
@@ -7,7 +7,7 @@
* + Initialization and De-initialization.
* + LUT configuration.
* + Force flush and/or invalidate of cache.
- * + Modify physical buffer adresses.
+ * + Modify physical buffer addresses.
* + Modify cache and pre-fetch parameters.
* + Error management.
*
@@ -40,7 +40,7 @@
[..]
(#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache.
- *** Modify physical buffer adresses ***
+ *** Modify physical buffer addresses ***
=======================================
[..]
(#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
@@ -250,7 +250,7 @@
/* Configure default value on GFXMMU_DVR register */
hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
- /* Configure physical buffer adresses on GFXMMU_BxCR registers */
+ /* Configure physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
@@ -501,7 +501,7 @@
[..] This section provides functions allowing to:
(+) Configure LUT.
(+) Force flush and/or invalidate of cache.
- (+) Modify physical buffer adresses.
+ (+) Modify physical buffer addresses.
(+) Modify cache and pre-fetch parameters.
(+) Manage error.
@endverbatim
@@ -713,7 +713,7 @@
}
else
{
- /* Modify physical buffer adresses on GFXMMU_BxCR registers */
+ /* Modify physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
diff --git a/Src/stm32h7xx_hal_gpio.c b/Src/stm32h7xx_hal_gpio.c
index 25a19de..8d0a5f6 100644
--- a/Src/stm32h7xx_hal_gpio.c
+++ b/Src/stm32h7xx_hal_gpio.c
@@ -447,17 +447,16 @@
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
+ uint32_t odr;
+
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
- }
- else
- {
- GPIOx->BSRR = GPIO_Pin;
- }
+ /* get current Output Data Register value */
+ odr = GPIOx->ODR;
+
+ /* Set selected pins that were at low level, and reset ones that were high */
+ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
diff --git a/Src/stm32h7xx_hal_hash.c b/Src/stm32h7xx_hal_hash.c
index e900166..bdfea69 100644
--- a/Src/stm32h7xx_hal_hash.c
+++ b/Src/stm32h7xx_hal_hash.c
@@ -34,7 +34,7 @@
(+++) Associate the initialized DMA handle to the HASH DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream: use
+ interrupt on the DMA stream: use
HAL_NVIC_SetPriority() and
HAL_NVIC_EnableIRQ()
@@ -71,10 +71,10 @@
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASH_xxx_Finish().
(+++) HMAC processing (requires to resort to extended functions):
@@ -483,7 +483,7 @@
* @brief Input data transfer complete call back.
* @note HAL_HASH_InCpltCallback() is called when the complete input message
* has been fed to the Peripheral. This API is invoked only when input data are
- * entered under interruption or thru DMA.
+ * entered under interruption or through DMA.
* @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
* HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
* to the Peripheral.
@@ -1729,10 +1729,10 @@
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(buffersize);
- /* Set the HASH DMA transfert completion call back */
+ /* Set the HASH DMA transfer completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Enable the DMA In DMA Stream */
+ /* Enable the DMA In DMA stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
/* Enable DMA requests */
@@ -2074,7 +2074,7 @@
return HAL_OK;
}
- /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and
+ /* Enter input data in the Peripheral through HASH_Write_Block_Data() call and
check whether the digest calculation has been triggered */
if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
{
@@ -3006,7 +3006,7 @@
}
- /* Set the HASH DMA transfert complete callback */
+ /* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
@@ -3014,7 +3014,7 @@
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Enable the DMA In DMA Stream */
+ /* Enable the DMA In DMA stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
/* Enable DMA requests */
@@ -3395,7 +3395,7 @@
}
- /* Set the HASH DMA transfert complete callback */
+ /* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
@@ -3403,7 +3403,7 @@
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Enable the DMA In DMA Stream */
+ /* Enable the DMA In DMA stream */
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
diff --git a/Src/stm32h7xx_hal_hash_ex.c b/Src/stm32h7xx_hal_hash_ex.c
index 1cf8a5c..2ddac61 100644
--- a/Src/stm32h7xx_hal_hash_ex.c
+++ b/Src/stm32h7xx_hal_hash_ex.c
@@ -5,7 +5,7 @@
* @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral for SHA-224 and SHA-256
- * alogrithms:
+ * algorithms:
* + HASH or HMAC processing in polling mode
* + HASH or HMAC processing in interrupt mode
* + HASH or HMAC processing in DMA mode
@@ -46,10 +46,10 @@
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASHEx_xxx_Finish().
@@ -388,7 +388,7 @@
*
@verbatim
===============================================================================
- ##### DMA mode HASH extended processing functionss #####
+ ##### DMA mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the hash value using one of the following algorithms:
diff --git a/Src/stm32h7xx_hal_hcd.c b/Src/stm32h7xx_hal_hcd.c
index 45d8061..1e5a89a 100644
--- a/Src/stm32h7xx_hal_hcd.c
+++ b/Src/stm32h7xx_hal_hcd.c
@@ -91,8 +91,8 @@
*/
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -185,9 +185,9 @@
* This parameter can be a value from 0 to 255
* @param speed Current device speed.
* This parameter can be one of these values:
- * HCD_SPEED_HIGH: High speed mode,
- * HCD_SPEED_FULL: Full speed mode,
- * HCD_SPEED_LOW: Low speed mode
+ * HCD_DEVICE_SPEED_HIGH: High speed mode,
+ * HCD_DEVICE_SPEED_FULL: Full speed mode,
+ * HCD_DEVICE_SPEED_LOW: Low speed mode
* @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type,
@@ -566,6 +566,16 @@
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
+ /* Handle Rx Queue Level Interrupts */
+ if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
+ {
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ HCD_RXQLVL_IRQHandler(hhcd);
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
+
/* Handle Host channel Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
@@ -586,19 +596,10 @@
}
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
}
-
- /* Handle Rx Queue Level Interrupts */
- if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
- {
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
- HCD_RXQLVL_IRQHandler(hhcd);
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
}
}
+
/**
* @brief SOF callback.
* @param hhcd HCD handle
@@ -718,7 +719,9 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
+ HAL_HCD_CallbackIDTypeDef CallbackID,
+ pHCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -806,7 +809,7 @@
/**
* @brief Unregister an USB HCD Callback
- * USB HCD callabck is redirected to the weak predefined callback
+ * USB HCD callback is redirected to the weak predefined callback
* @param hhcd USB HCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -910,7 +913,8 @@
* @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
+ pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -945,7 +949,7 @@
}
/**
- * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback
+ * @brief Unregister the USB HCD Host Channel Notify URB Change Callback
* USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
* @param hhcd HCD handle
* @retval HAL status
@@ -982,8 +986,8 @@
*/
/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief Management functions
- *
+ * @brief Management functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -1041,8 +1045,8 @@
*/
/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -1192,10 +1196,17 @@
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
hhcd->hc[ch_num].state = HC_DATATGLERR;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else
{
@@ -1212,7 +1223,7 @@
{
if (hhcd->Init.dma_enable != 0U)
{
- hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
+ hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
(USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
@@ -1253,8 +1264,18 @@
{
/* ... */
}
- hhcd->hc[ch_num].toggle_in ^= 1U;
+ if (hhcd->Init.dma_enable == 1U)
+ {
+ if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
+ {
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
+ }
+ else
+ {
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
@@ -1262,17 +1283,17 @@
if (hhcd->hc[ch_num].state == HC_XFRC)
{
- hhcd->hc[ch_num].urb_state = URB_DONE;
+ hhcd->hc[ch_num].urb_state = URB_DONE;
}
else if (hhcd->hc[ch_num].state == HC_STALL)
{
- hhcd->hc[ch_num].urb_state = URB_STALL;
+ hhcd->hc[ch_num].urb_state = URB_STALL;
}
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
- if (hhcd->hc[ch_num].ErrCnt > 3U)
+ if (hhcd->hc[ch_num].ErrCnt > 2U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
@@ -1280,18 +1301,19 @@
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
- }
- /* re-activate the channel */
- tmpreg = USBx_HC(ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(ch_num)->HCCHAR = tmpreg;
+ /* re-activate the channel */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ }
}
else if (hhcd->hc[ch_num].state == HC_NAK)
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
- /* re-activate the channel */
+
+ /* re-activate the channel */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
@@ -1309,14 +1331,6 @@
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
}
- else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- hhcd->hc[ch_num].ErrCnt++;
- hhcd->hc[ch_num].state = HC_XACTERR;
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
- }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
@@ -1362,6 +1376,7 @@
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)chnum;
uint32_t tmpreg;
+ uint32_t num_packets;
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
@@ -1380,15 +1395,6 @@
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
- else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
- {
- hhcd->hc[ch_num].state = HC_NYET;
- hhcd->hc[ch_num].do_ping = 1U;
- hhcd->hc[ch_num].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
- }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
@@ -1398,11 +1404,27 @@
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
hhcd->hc[ch_num].ErrCnt = 0U;
+
+ /* transaction completed with NYET state, update do ping state */
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
+ {
+ hhcd->hc[ch_num].do_ping = 1U;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+ }
__HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
hhcd->hc[ch_num].state = HC_XFRC;
}
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
+ {
+ hhcd->hc[ch_num].state = HC_NYET;
+ hhcd->hc[ch_num].do_ping = 1U;
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+ }
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
@@ -1417,7 +1439,7 @@
if (hhcd->hc[ch_num].do_ping == 0U)
{
- if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)
+ if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
{
hhcd->hc[ch_num].do_ping = 1U;
}
@@ -1429,9 +1451,26 @@
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- hhcd->hc[ch_num].state = HC_XACTERR;
+ if (hhcd->Init.dma_enable == 0U)
+ {
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ else
+ {
+ hhcd->hc[ch_num].ErrCnt++;
+ if (hhcd->hc[ch_num].ErrCnt > 2U)
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+ }
+ else
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+ }
+ }
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
@@ -1452,7 +1491,22 @@
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
{
- hhcd->hc[ch_num].toggle_out ^= 1U;
+ if (hhcd->Init.dma_enable == 1U)
+ {
+ if (hhcd->hc[ch_num].xfer_len > 0U)
+ {
+ num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
+
+ if ((num_packets & 1U) != 0U)
+ {
+ hhcd->hc[ch_num].toggle_out ^= 1U;
+ }
+ }
+ }
+ else
+ {
+ hhcd->hc[ch_num].toggle_out ^= 1U;
+ }
}
}
else if (hhcd->hc[ch_num].state == HC_NAK)
@@ -1471,7 +1525,7 @@
(hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
- if (hhcd->hc[ch_num].ErrCnt > 3U)
+ if (hhcd->hc[ch_num].ErrCnt > 2U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
@@ -1479,13 +1533,13 @@
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
- }
- /* re-activate the channel */
- tmpreg = USBx_HC(ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(ch_num)->HCCHAR = tmpreg;
+ /* re-activate the channel */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ }
}
else
{
@@ -1512,14 +1566,15 @@
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
- uint32_t temp;
+ uint32_t GrxstspReg;
+ uint32_t xferSizePktCnt;
uint32_t tmpreg;
uint32_t ch_num;
- temp = hhcd->Instance->GRXSTSP;
- ch_num = temp & USB_OTG_GRXSTSP_EPNUM;
- pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
- pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ GrxstspReg = hhcd->Instance->GRXSTSP;
+ ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
+ pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
+ pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
switch (pktsts)
{
@@ -1527,20 +1582,31 @@
/* Read the data into the host buffer. */
if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
{
- (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
-
- /*manage multiple Xfer */
- hhcd->hc[ch_num].xfer_buff += pktcnt;
- hhcd->hc[ch_num].xfer_count += pktcnt;
-
- if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
+ if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
{
- /* re-activate the channel when more packets are expected */
- tmpreg = USBx_HC(ch_num)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(ch_num)->HCCHAR = tmpreg;
- hhcd->hc[ch_num].toggle_in ^= 1U;
+ (void)USB_ReadPacket(hhcd->Instance,
+ hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
+
+ /* manage multiple Xfer */
+ hhcd->hc[ch_num].xfer_buff += pktcnt;
+ hhcd->hc[ch_num].xfer_count += pktcnt;
+
+ /* get transfer size packet count */
+ xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
+
+ if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
+ {
+ /* re-activate the channel when more packets are expected */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
+ }
+ else
+ {
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
}
}
break;
diff --git a/Src/stm32h7xx_hal_hrtim.c b/Src/stm32h7xx_hal_hrtim.c
index 914930c..1d7efa1 100644
--- a/Src/stm32h7xx_hal_hrtim.c
+++ b/Src/stm32h7xx_hal_hrtim.c
@@ -1220,6 +1220,9 @@
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_BUSY;
@@ -1341,6 +1344,9 @@
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
return HAL_OK;
}
@@ -2474,7 +2480,7 @@
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
* @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
- * @note When the timer operates in simple capture mode the capture is trigerred
+ * @note When the timer operates in simple capture mode the capture is triggered
* by the designated external event and GPIO input is implicitly used as event source.
* The cature can be triggered by a rising edge, a falling edge or both
* edges on event channel.
@@ -5308,7 +5314,7 @@
* @arg HRTIM_TIMERID_TIMER_D
* @arg HRTIM_TIMERID_TIMER_E
* @retval HAL status
- * @note This function enables the dma request(s) mentionned in the timer
+ * @note This function enables the dma request(s) mentioned in the timer
* configuration data structure for every timers to start.
* @note The source memory address, the destination memory address and the
* size of each DMA transfer are specified at timer configuration time
@@ -5652,7 +5658,7 @@
* @arg HRTIM_TIMERUPDATE_D
* @arg HRTIM_TIMERUPDATE_E
* @retval HAL status
- * @note The 'software update' bits in the HRTIM conrol register 2 register are
+ * @note The 'software update' bits in the HRTIM control register 2 register are
* automatically reset by hardware
*/
HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
@@ -5694,7 +5700,7 @@
* @arg HRTIM_TIMERRESET_TIMER_D
* @arg HRTIM_TIMERRESET_TIMER_E
* @retval HAL status
- * @note The 'software reset' bits in the HRTIM conrol register 2 are
+ * @note The 'software reset' bits in the HRTIM control register 2 are
* automatically reset by hardware
*/
HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
@@ -6190,7 +6196,7 @@
if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
{
- /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
+ /* Output is enabled: output in RUN state (whatever output disable status is)*/
output_state = HRTIM_OUTPUTSTATE_RUN;
}
else
@@ -7573,7 +7579,7 @@
hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
hrtim_mcr |= pTimerCfg->DACSynchro;
- /* Enable/Disable preload meachanism for timer registers */
+ /* Enable/Disable preload mechanism for timer registers */
hrtim_mcr &= ~(HRTIM_MCR_PREEN);
hrtim_mcr |= pTimerCfg->PreloadEnable;
@@ -7636,7 +7642,7 @@
hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
hrtim_timcr |= pTimerCfg->DACSynchro;
- /* Enable/Disable preload meachanism for timer registers */
+ /* Enable/Disable preload mechanism for timer registers */
hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
hrtim_timcr |= pTimerCfg->PreloadEnable;
@@ -8549,10 +8555,13 @@
*/
static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
{
+ uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
+ uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
+
/* Fault 1 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
@@ -8566,9 +8575,9 @@
}
/* Fault 2 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
@@ -8582,9 +8591,9 @@
}
/* Fault 3 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
@@ -8598,9 +8607,9 @@
}
/* Fault 4 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
@@ -8614,9 +8623,9 @@
}
/* Fault 5 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
@@ -8630,9 +8639,9 @@
}
/* System fault event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
@@ -8653,10 +8662,15 @@
*/
static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
{
+ uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
+ uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
+ uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
+ uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
+
/* Burst mode period event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
@@ -8670,9 +8684,9 @@
}
/* Master timer compare 1 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
@@ -8686,9 +8700,9 @@
}
/* Master timer compare 2 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
@@ -8702,9 +8716,9 @@
}
/* Master timer compare 3 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
@@ -8718,9 +8732,9 @@
}
/* Master timer compare 4 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
@@ -8734,9 +8748,9 @@
}
/* Master timer repetition event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
@@ -8750,9 +8764,9 @@
}
/* Synchronization input event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
@@ -8766,9 +8780,9 @@
}
/* Master timer registers update event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
@@ -8797,10 +8811,13 @@
static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx)
{
+ uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
+ uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
+
/* Timer compare 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
@@ -8814,9 +8831,9 @@
}
/* Timer compare 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
@@ -8830,9 +8847,9 @@
}
/* Timer compare 3 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
@@ -8846,9 +8863,9 @@
}
/* Timer compare 4 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
@@ -8862,9 +8879,9 @@
}
/* Timer repetition event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
@@ -8878,9 +8895,9 @@
}
/* Timer registers update event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
@@ -8894,9 +8911,9 @@
}
/* Timer capture 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
@@ -8910,9 +8927,9 @@
}
/* Timer capture 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
@@ -8926,9 +8943,9 @@
}
/* Timer output 1 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
@@ -8942,9 +8959,9 @@
}
/* Timer output 1 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
@@ -8958,9 +8975,9 @@
}
/* Timer output 2 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
@@ -8974,9 +8991,9 @@
}
/* Timer output 2 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
@@ -8990,9 +9007,9 @@
}
/* Timer reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
@@ -9006,9 +9023,9 @@
}
/* Delayed protection event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
diff --git a/Src/stm32h7xx_hal_i2c.c b/Src/stm32h7xx_hal_i2c.c
index cecdbb4..09b3e2a 100644
--- a/Src/stm32h7xx_hal_i2c.c
+++ b/Src/stm32h7xx_hal_i2c.c
@@ -93,7 +93,7 @@
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
@@ -112,7 +112,7 @@
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
interface.
@@ -122,7 +122,7 @@
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
- (+) Differents sequential I2C interfaces are listed below:
+ (+) Different sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
@@ -390,8 +390,10 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
@@ -400,7 +402,8 @@
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
@@ -417,7 +420,8 @@
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
/* Private function to handle start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request);
/* Private function to Convert Specific options */
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
@@ -432,8 +436,8 @@
*/
/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -672,7 +676,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+ pI2C_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -977,8 +982,8 @@
*/
/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -1060,7 +1065,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1174,7 +1180,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1550,7 +1557,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
@@ -1786,7 +1794,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
@@ -1929,7 +1938,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
@@ -2280,7 +2290,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -2372,8 +2383,7 @@
}
}
- }
- while (hi2c->XferCount > 0U);
+ } while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
@@ -2415,7 +2425,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -2507,8 +2518,7 @@
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
- }
- while (hi2c->XferCount > 0U);
+ } while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
@@ -2548,7 +2558,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -2639,7 +2650,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -2729,7 +2741,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -2873,7 +2886,8 @@
* @param Size Amount of data to be read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -3124,8 +3138,7 @@
/* Increment Trials */
I2C_Trials++;
- }
- while (I2C_Trials < Trials);
+ } while (I2C_Trials < Trials);
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
@@ -3156,7 +3169,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
@@ -3240,7 +3254,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
@@ -3402,7 +3417,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_READ;
@@ -3486,7 +3502,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_READ;
@@ -3646,7 +3663,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3741,7 +3759,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
HAL_StatusTypeDef dmaxferstatus;
@@ -3920,7 +3939,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -4015,7 +4035,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
HAL_StatusTypeDef dmaxferstatus;
@@ -4300,8 +4321,8 @@
*/
/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/**
* @brief This function handles I2C event interrupt request.
@@ -4539,8 +4560,8 @@
*/
/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @brief Peripheral State, Mode and Error functions
- *
+ * @brief Peripheral State, Mode and Error functions
+ *
@verbatim
===============================================================================
##### Peripheral State, Mode and Error functions #####
@@ -4577,11 +4598,11 @@
}
/**
-* @brief Return the I2C error code.
+ * @brief Return the I2C error code.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
+ * @retval I2C Error Code
+ */
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
@@ -4767,7 +4788,8 @@
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
@@ -4827,7 +4849,8 @@
I2C_ITSlaveSeqCplt(hi2c);
}
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, tmpITFlags);
}
@@ -4835,7 +4858,7 @@
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
+ /* Check if all data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
@@ -5063,7 +5086,8 @@
if (treatdmanack == 1U)
{
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
@@ -5151,7 +5175,8 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
@@ -5204,7 +5229,8 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
@@ -5719,7 +5745,7 @@
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
I2C_ITSlaveSeqCplt(hi2c);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -5856,7 +5882,7 @@
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
- /* If state is an abort treatment on goind, don't change state */
+ /* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
@@ -5868,7 +5894,8 @@
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
- if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
@@ -5897,7 +5924,8 @@
}
}
/* Abort DMA RX transfer if any */
- else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
@@ -6210,7 +6238,8 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
@@ -6442,7 +6471,8 @@
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@@ -6450,8 +6480,11 @@
assert_param(IS_TRANSFER_REQUEST(Request));
/* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ MODIFY_REG(hi2c->Instance->CR2,
+ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -6591,7 +6624,7 @@
}
/**
- * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
* @param hi2c I2C handle.
* @retval None
*/
diff --git a/Src/stm32h7xx_hal_i2c_ex.c b/Src/stm32h7xx_hal_i2c_ex.c
index f568c3e..26a046b 100644
--- a/Src/stm32h7xx_hal_i2c_ex.c
+++ b/Src/stm32h7xx_hal_i2c_ex.c
@@ -73,7 +73,7 @@
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
- *
+ *
@verbatim
===============================================================================
##### Extended features functions #####
diff --git a/Src/stm32h7xx_hal_irda.c b/Src/stm32h7xx_hal_irda.c
index eec986d..865e9c8 100644
--- a/Src/stm32h7xx_hal_irda.c
+++ b/Src/stm32h7xx_hal_irda.c
@@ -40,7 +40,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
the normal or low power mode and the clock prescaler in the hirda handle Init structure.
@@ -612,43 +613,45 @@
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
- hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
- hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
- hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
- hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_IRDA_ERROR_CB_ID :
- hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
- hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
- hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
- hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
case HAL_IRDA_MSPINIT_CB_ID :
- hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
- hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -771,13 +774,16 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ Error code is set to allow user to identify error type, and
+ HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -815,7 +821,7 @@
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
@@ -905,7 +911,7 @@
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->RxXferSize = Size;
@@ -1280,7 +1286,7 @@
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1380,7 +1386,8 @@
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Tx request if enabled */
@@ -1578,7 +1585,8 @@
uint32_t abortcplt = 1U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
@@ -2236,7 +2244,7 @@
uint32_t tmpreg;
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
@@ -2331,7 +2339,7 @@
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -2386,7 +2394,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
diff --git a/Src/stm32h7xx_hal_iwdg.c b/Src/stm32h7xx_hal_iwdg.c
index d90bfb1..85548ac 100644
--- a/Src/stm32h7xx_hal_iwdg.c
+++ b/Src/stm32h7xx_hal_iwdg.c
@@ -48,7 +48,7 @@
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
- This frequency being subject to variations as mentioned above, the
+ This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining
@@ -66,13 +66,13 @@
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
+ (++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@@ -126,7 +126,8 @@
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
*/
@@ -197,11 +198,14 @@
tickstart = HAL_GetTick();
/* Wait for register to be updated */
- while (hiwdg->Instance->SR != 0x00u)
+ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
- return HAL_TIMEOUT;
+ if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -224,6 +228,7 @@
return HAL_OK;
}
+
/**
* @}
*/
@@ -243,7 +248,6 @@
* @{
*/
-
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
@@ -259,6 +263,7 @@
return HAL_OK;
}
+
/**
* @}
*/
diff --git a/Src/stm32h7xx_hal_jpeg.c b/Src/stm32h7xx_hal_jpeg.c
index 160b0f4..ce873e2 100644
--- a/Src/stm32h7xx_hal_jpeg.c
+++ b/Src/stm32h7xx_hal_jpeg.c
@@ -1284,7 +1284,7 @@
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
* the configuration information for JPEG module
* @param pInfo pointer to a JPEG_ConfTypeDef structure that contains
- * The JPEG decoded header informations
+ * The JPEG decoded header information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
@@ -2313,7 +2313,7 @@
* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains
* the configuration information for JPEG module
* @param pInfo pointer to a JPEG_ConfTypeDef structure that contains
- * The JPEG decoded header informations
+ * The JPEG decoded header information
* @retval None
*/
__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
@@ -2524,7 +2524,7 @@
* @param Bits pointer to bits table
* @param Huffsize pointer to sizes table
* @param Huffcode pointer to codes table
- * @param LastK pointer to last Coeff (table dimmension)
+ * @param LastK pointer to last Coeff (table dimension)
* @retval HAL status
*/
static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
@@ -3328,12 +3328,12 @@
{
uint32_t tmpContext;
- /*End of header processing flag rised*/
+ /*End of header processing flag */
if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
{
if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL)
{
- /*Call Header parsing complet callback */
+ /*Call Header parsing complete callback */
(void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);
/* Reset the ImageQuality */
hjpeg->Conf.ImageQuality = 0;
@@ -3359,13 +3359,13 @@
{
if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL)
{
- /*Input FIFO threshold flag rised*/
+ /*Input FIFO threshold flag */
/*JPEG_FIFO_TH_SIZE words can be written in */
JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE);
}
else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL)
{
- /*Input FIFO Not Full flag rised*/
+ /*Input FIFO Not Full flag */
/*32-bit value can be written in */
JPEG_ReadInputData(hjpeg, 1);
}
@@ -3381,13 +3381,13 @@
{
if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL)
{
- /*Output FIFO threshold flag rised*/
+ /*Output FIFO threshold flag */
/*JPEG_FIFO_TH_SIZE words can be read out */
JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE);
}
else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL)
{
- /*Output FIFO Not Empty flag rised*/
+ /*Output FIFO Not Empty flag */
/*32-bit value can be read out */
JPEG_StoreOutputData(hjpeg, 1);
}
@@ -3828,7 +3828,7 @@
hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
tmpContext = hjpeg->Context;
- /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
+ /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
/* Process Unlocked */
@@ -3927,7 +3927,7 @@
}
tmpContext = hjpeg->Context;
- /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
+ /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
/* Process Unlocked */
diff --git a/Src/stm32h7xx_hal_lptim.c b/Src/stm32h7xx_hal_lptim.c
index 0a579dc..5c39666 100644
--- a/Src/stm32h7xx_hal_lptim.c
+++ b/Src/stm32h7xx_hal_lptim.c
@@ -197,8 +197,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -235,19 +235,17 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
- }
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
- {
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@@ -281,21 +279,18 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
- }
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
- {
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
}
- /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
/* Set initialization parameters */
@@ -314,19 +309,21 @@
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- /* Configure the active edge or edges used by the counter only if LPTIM is
- * clocked by an external clock source
- */
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ /* Configure LPTIM external clock polarity and digital filter */
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ hlptim->Init.UltraLowPowerClock.SampleTime);
}
+ /* Configure LPTIM external trigger */
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge |
+ hlptim->Init.Trigger.SampleTime);
}
/* Write to LPTIMx CFGR */
@@ -443,8 +440,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
- * @brief Start-Stop operation functions.
- *
+ * @brief Start-Stop operation functions.
+ *
@verbatim
==============================================================================
##### LPTIM Start Stop operation functions #####
@@ -1563,7 +1560,8 @@
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1641,7 +1639,8 @@
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1729,8 +1728,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
- * @brief Read operation functions.
- *
+ * @brief Read operation functions.
+ *
@verbatim
==============================================================================
##### LPTIM Read operation functions #####
@@ -1787,8 +1786,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
- * @brief LPTIM IRQ handler.
- *
+ * @brief LPTIM IRQ handler.
+ *
@verbatim
==============================================================================
##### LPTIM IRQ handler and callbacks #####
@@ -2255,8 +2254,8 @@
*/
/** @defgroup LPTIM_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
@@ -2331,8 +2330,7 @@
{
result = HAL_TIMEOUT;
}
- }
- while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+ } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
}
diff --git a/Src/stm32h7xx_hal_mdios.c b/Src/stm32h7xx_hal_mdios.c
index 5ad0ff7..834ffeb 100644
--- a/Src/stm32h7xx_hal_mdios.c
+++ b/Src/stm32h7xx_hal_mdios.c
@@ -55,8 +55,8 @@
(@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
and execute the previous callbacks
- (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
- (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
+ (#) Reset the MDIOS peripheral and all related resources by calling the HAL_MDIOS_DeInit() API.
+ (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level resources
(GPIO, Clocks, NVIC configuration ...)
*** Callback registration ***
diff --git a/Src/stm32h7xx_hal_mdma.c b/Src/stm32h7xx_hal_mdma.c
index 4e60600..1ce7664 100644
--- a/Src/stm32h7xx_hal_mdma.c
+++ b/Src/stm32h7xx_hal_mdma.c
@@ -1475,14 +1475,14 @@
if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U)
{
- /* if no Transfer on going (MDMA enable bit not set) retrun error */
+ /* if no Transfer on going (MDMA enable bit not set) return error */
hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
return HAL_ERROR;
}
else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
{
- /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */
+ /* if an MDMA ongoing request has not yet end or if request mode is not SW request return error */
hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
return HAL_ERROR;
@@ -1755,7 +1755,7 @@
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param BlockDataLength : The length of a block transfer in bytes
- * @param BlockCount: The number of blocks to be transfered
+ * @param BlockCount: The number of blocks to be transferred
* @retval HAL status
*/
static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
diff --git a/Src/stm32h7xx_hal_mmc.c b/Src/stm32h7xx_hal_mmc.c
index ad69334..07ec0b2 100644
--- a/Src/stm32h7xx_hal_mmc.c
+++ b/Src/stm32h7xx_hal_mmc.c
@@ -105,7 +105,7 @@
(+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
@@ -129,18 +129,18 @@
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
- You could also check the DMA transfer process through the MMC Tx interrupt event.
+ You could also check the DMA transfer process through the MMC Tx interrupt event.
(+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Tx interrupt event.
*** MMC card information ***
- ===========================
+ ===========================
[..]
(+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
It returns useful information about the MMC card such as block size, card type,
@@ -260,7 +260,31 @@
/** @addtogroup MMC_Private_Defines
* @{
*/
+#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
+#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE
+#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
+#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238
+
+#define MMC_EXT_CSD_PWR_CL_26_POS 8
+#define MMC_EXT_CSD_PWR_CL_52_POS 0
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
+#else
+#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE
+
+#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
+#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239
+
+#define MMC_EXT_CSD_PWR_CL_26_POS 24
+#define MMC_EXT_CSD_PWR_CL_52_POS 16
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
+#endif
+
+/* Frequencies used in the driver for clock divider calculation */
+#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
/**
* @}
*/
@@ -280,8 +304,9 @@
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
-HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
-
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex,
+ uint32_t Timeout);
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed);
/**
* @}
@@ -292,8 +317,8 @@
*/
/** @addtogroup MMC_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
+ * @brief Initialization and de-initialization functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -315,7 +340,7 @@
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
- if(hmmc == NULL)
+ if (hmmc == NULL)
{
return HAL_ERROR;
}
@@ -328,7 +353,7 @@
assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
- if(hmmc->State == HAL_MMC_STATE_RESET)
+ if (hmmc->State == HAL_MMC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
@@ -343,7 +368,7 @@
hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback;
hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback;
- if(hmmc->MspInitCallback == NULL)
+ if (hmmc->MspInitCallback == NULL)
{
hmmc->MspInitCallback = HAL_MMC_MspInit;
}
@@ -359,7 +384,7 @@
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize the Card parameters */
- if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
+ if (HAL_MMC_InitCard(hmmc) == HAL_ERROR)
{
return HAL_ERROR;
}
@@ -373,6 +398,15 @@
/* Initialize the MMC state */
hmmc->State = HAL_MMC_STATE_READY;
+ /* Configure bus width */
+ if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B)
+ {
+ if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
return HAL_OK;
}
@@ -397,7 +431,17 @@
/* Init Clock should be less or equal to 400Khz*/
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
- Init.ClockDiv = sdmmc_clk/(2U*400000U);
+ if (sdmmc_clk == 0U)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
+ }
+ Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
+#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
(void)SDMMC_Init(hmmc->Instance, Init);
@@ -407,20 +451,12 @@
/* wait 74 Cycles: required power up waiting time before starting
the MMC initialization sequence */
- sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
-
- if(sdmmc_clk != 0U)
- {
- HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
- }
- else
- {
- HAL_Delay(2U);
- }
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
@@ -429,7 +465,7 @@
/* Card initialization */
errorstate = MMC_InitCard(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
@@ -438,7 +474,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -458,7 +494,7 @@
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
- if(hmmc == NULL)
+ if (hmmc == NULL)
{
return HAL_ERROR;
}
@@ -472,7 +508,7 @@
MMC_PowerOFF(hmmc);
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- if(hmmc->MspDeInitCallback == NULL)
+ if (hmmc->MspDeInitCallback == NULL)
{
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
}
@@ -526,8 +562,8 @@
*/
/** @addtogroup MMC_Exported_Functions_Group2
- * @brief Data transfer functions
- *
+ * @brief Data transfer functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -552,7 +588,8 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -561,22 +598,40 @@
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -595,10 +650,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
@@ -612,7 +667,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -623,12 +678,13 @@
/* Poll on SDMMC flags */
dataremaining = config.DataLength;
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
@@ -643,23 +699,23 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
+ hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Send stop transmission command in case of multiblock read */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -670,7 +726,7 @@
}
/* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -678,7 +734,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -686,7 +742,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -725,7 +781,8 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -734,22 +791,40 @@
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -768,10 +843,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
@@ -785,7 +860,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -796,12 +871,13 @@
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
@@ -816,7 +892,7 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -825,14 +901,14 @@
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Send stop transmission command in case of multiblock write */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -843,7 +919,7 @@
}
/* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -851,7 +927,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -859,7 +935,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -899,28 +975,47 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -942,10 +1037,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
@@ -960,7 +1055,7 @@
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -969,7 +1064,8 @@
return HAL_ERROR;
}
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_RXFIFOHF));
return HAL_OK;
}
@@ -992,28 +1088,47 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -1036,12 +1151,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
- hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
@@ -1053,7 +1168,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1063,7 +1178,8 @@
}
/* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_TXFIFOHE));
return HAL_OK;
}
@@ -1086,28 +1202,47 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -1130,12 +1265,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
@@ -1149,7 +1284,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1182,28 +1317,47 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -1226,13 +1380,13 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
@@ -1246,7 +1400,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1281,26 +1435,37 @@
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if(end_add < start_add)
+ if (end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(end_add > (hmmc->MmcCard.LogBlockNbr))
+ if (end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check if the card command class supports erase command */
- if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1309,7 +1474,7 @@
return HAL_ERROR;
}
- if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1326,7 +1491,7 @@
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1337,7 +1502,7 @@
/* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1348,7 +1513,7 @@
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1378,33 +1543,33 @@
uint32_t context = hmmc->Context;
/* Check for SDMMC interrupt flags */
- if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+ if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Read_IT(hmmc);
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
- SDMMC_IT_RXFIFOHF);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \
+ SDMMC_IT_RXFIFOHF);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
- if((context & MMC_CONTEXT_DMA) != 0U)
+ if ((context & MMC_CONTEXT_DMA) != 0U)
{
hmmc->Instance->DLEN = 0;
hmmc->Instance->DCTRL = 0;
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
- if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
@@ -1419,7 +1584,7 @@
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
- if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
@@ -1427,7 +1592,7 @@
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
- if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
@@ -1436,13 +1601,13 @@
#endif
}
}
- else if((context & MMC_CONTEXT_IT) != 0U)
+ else if ((context & MMC_CONTEXT_IT) != 0U)
{
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
- if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
@@ -1457,7 +1622,7 @@
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
- if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
@@ -1480,27 +1645,28 @@
}
}
- else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+ else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Write_IT(hmmc);
}
- else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL |
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
}
@@ -1509,17 +1675,17 @@
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* Disable all interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP;
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT);
- if((context & MMC_CONTEXT_IT) != 0U)
+ if ((context & MMC_CONTEXT_IT) != 0U)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
@@ -1529,9 +1695,9 @@
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
- else if((context & MMC_CONTEXT_DMA) != 0U)
+ else if ((context & MMC_CONTEXT_DMA) != 0U)
{
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
/* Disable Internal DMA */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
@@ -1552,13 +1718,13 @@
}
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
- if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
+ if (READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
{
/* Current buffer is buffer0, Transfer complete for buffer1 */
- if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->Write_DMADblBuf1CpltCallback(hmmc);
@@ -1578,7 +1744,7 @@
else /* MMC_DMA_BUFFER1 */
{
/* Current buffer is buffer1, Transfer complete for buffer0 */
- if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->Write_DMADblBuf0CpltCallback(hmmc);
@@ -1614,11 +1780,11 @@
}
/**
-* @brief Return the MMC error code
-* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
+ * @brief Return the MMC error code
+ * @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
-* @retval MMC Error Code
-*/
+ * @retval MMC Error Code
+ */
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
{
return hmmc->ErrorCode;
@@ -1704,11 +1870,12 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+ pMMC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
@@ -1718,64 +1885,64 @@
/* Process locked */
__HAL_LOCK(hmmc);
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
- case HAL_MMC_TX_CPLT_CB_ID :
- hmmc->TxCpltCallback = pCallback;
- break;
- case HAL_MMC_RX_CPLT_CB_ID :
- hmmc->RxCpltCallback = pCallback;
- break;
- case HAL_MMC_ERROR_CB_ID :
- hmmc->ErrorCallback = pCallback;
- break;
- case HAL_MMC_ABORT_CB_ID :
- hmmc->AbortCpltCallback = pCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Read_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Read_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Write_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Write_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = pCallback;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = pCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = pCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = pCallback;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1816,64 +1983,64 @@
/* Process locked */
__HAL_LOCK(hmmc);
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
- case HAL_MMC_TX_CPLT_CB_ID :
- hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
- break;
- case HAL_MMC_RX_CPLT_CB_ID :
- hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
- break;
- case HAL_MMC_ERROR_CB_ID :
- hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
- break;
- case HAL_MMC_ABORT_CB_ID :
- hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback;
- break;
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = HAL_MMC_MspInit;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = HAL_MMC_MspInit;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1895,8 +2062,8 @@
*/
/** @addtogroup MMC_Exported_Functions_Group3
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -1980,12 +2147,12 @@
pCSD->Reserved2 = 0U; /*!< Reserved */
- if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
+ if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
{
return HAL_ERROR;
}
- if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
+ if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
{
pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
@@ -2003,10 +2170,10 @@
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
- hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
hmmc->MmcCard.LogBlockSize = 512U;
}
- else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
+ else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
{
hmmc->MmcCard.BlockNbr = block_nbr;
hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
@@ -2034,7 +2201,7 @@
pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
- pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
+ pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
@@ -2052,7 +2219,7 @@
pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
- pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
+ pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
@@ -2082,6 +2249,126 @@
}
/**
+ * @brief Returns information the information of the card which are stored on
+ * the Extended CSD register.
+ * @param hmmc Pointer to MMC handle
+ * @param pExtCSD Pointer to a memory area (512 bytes) that contains all
+ * Extended CSD register parameters
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t *tmp_buf;
+
+ if (NULL == pExtCSD)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0;
+
+ /* Initiaize the destination pointer */
+ tmp_buf = pExtCSD;
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 512;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
+
+ /* Send ExtCSD Read command to Card */
+ errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR |
+ SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for (count = 0U; count < 8U; count++)
+ {
+ *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance);
+ tmp_buf++;
+ }
+ }
+
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ hmmc->State = HAL_MMC_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
* @param hmmc: Pointer to MMC handle
@@ -2102,78 +2389,95 @@
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
- /* Chnage Satte */
+ /* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
- if(WideMode == SDMMC_BUS_WIDE_8B)
+ /* Check and update the power class if needed */
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
{
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
- }
- else if(WideMode == SDMMC_BUS_WIDE_4B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
- }
- else if(WideMode == SDMMC_BUS_WIDE_1B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
- }
- else
- {
- /* WideMode is not a valid argument*/
- errorstate = HAL_MMC_ERROR_PARAM;
- }
-
- /* Check for switch error and violation of the trial number of sending CMD 13 */
- if(errorstate == HAL_MMC_ERROR_NONE)
- {
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- count = SDMMC_MAX_TRIAL;
- do
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
{
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- break;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
-
- /* Check the status after the switch command execution */
- if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
- {
- /* Check the bit SWITCH_ERROR of the device status */
- if ((response & 0x80U) != 0U)
- {
- errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
- else
- {
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
- (void)SDMMC_Init(hmmc->Instance, Init);
- }
- }
- else if (count == 0U)
- {
- errorstate = SDMMC_ERROR_TIMEOUT;
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DDR);
}
else
{
- /* Nothing to do */
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_HIGH);
+ }
+ }
+ else
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT);
+ }
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (WideMode == SDMMC_BUS_WIDE_8B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ }
+ else if (WideMode == SDMMC_BUS_WIDE_4B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ }
+ else if (WideMode == SDMMC_BUS_WIDE_1B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ errorstate = HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Check for switch error and violation of the trial number of sending CMD 13 */
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ else
+ {
+ /* Configure the SDMMC peripheral */
+ Init = hmmc->Init;
+ Init.BusWide = WideMode;
+ (void)SDMMC_Init(hmmc->Instance, Init);
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2205,14 +2509,13 @@
/* Check the parameters */
assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
+
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
- if(MMC_ReadExtCSD(hmmc, &device_type, 196, 0x0FFFFFFFU) != HAL_OK) /* Field DEVICE_TYPE [196] */
- {
- return HAL_ERROR;
- }
-
+ /* Field DEVICE_TYPE [196 = 49*4] of Extended CSD register */
+ device_type = (hmmc->Ext_CSD[49] & 0x000000FFU);
+
switch (SpeedMode)
{
case SDMMC_SPEED_MODE_AUTO:
@@ -2221,16 +2524,20 @@
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
- errorstate = MMC_DDR_Mode(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
{
- hmmc->ErrorCode |= errorstate;
+ /* DDR mode not supported with CLKDIV = 0 */
+ errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
}
}
}
@@ -2238,7 +2545,7 @@
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2255,16 +2562,20 @@
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
- errorstate = MMC_DDR_Mode(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
{
- hmmc->ErrorCode |= errorstate;
+ /* DDR mode not supported with CLKDIV = 0 */
+ errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
}
}
}
@@ -2272,7 +2583,7 @@
{
/* High Speed DDR mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
break;
}
@@ -2282,7 +2593,7 @@
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2291,7 +2602,7 @@
{
/* High Speed mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
break;
}
@@ -2301,7 +2612,7 @@
{
/* High Speed DDR mode activated */
errorstate = MMC_DDR_Mode(hmmc, DISABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2310,7 +2621,7 @@
{
/* High Speed mode activated */
errorstate = MMC_HighSpeed(hmmc, DISABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2352,7 +2663,7 @@
uint32_t resp1 = 0U;
errorstate = MMC_SendStatus(hmmc, &resp1);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2373,8 +2684,8 @@
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
@@ -2388,11 +2699,11 @@
hmmc->Context = MMC_CONTEXT_NONE;
CardState = HAL_MMC_GetCardState(hmmc);
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2410,8 +2721,8 @@
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
@@ -2422,11 +2733,11 @@
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2449,17 +2760,20 @@
* @param hmmc Pointer to MMC handle
* @param EraseType Specifies the type of erase to be performed
* This parameter can be one of the following values:
- * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
- * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
- * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
- * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified by CMD35 & 36
- * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
- * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks previously identified
+ * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
+ * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified
+ * by CMD35 & 36
+ * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
+ * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks
+ * previously identified
* @param BlockStartAdd Start Block address
* @param BlockEndAdd End Block address
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType,
+ uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
uint32_t errorstate;
uint32_t start_add = BlockStartAdd;
@@ -2470,34 +2784,45 @@
assert_param(IS_MMC_ERASE_TYPE(EraseType));
/* Check the coherence between start and end address */
- if(end_add < start_add)
+ if (end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
/* Check that the end address is not out of range of device memory */
- if(end_add > (hmmc->MmcCard.LogBlockNbr))
+ if (end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
/* Check if the card command class supports erase command */
- if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
return HAL_ERROR;
}
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check that the card is not locked */
- if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
hmmc->State = HAL_MMC_STATE_READY;
@@ -2513,22 +2838,22 @@
/* Send CMD35 MMC_ERASE_GRP_START with start address as argument */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Send CMD36 MMC_ERASE_GRP_END with end address as argument */
errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Send CMD38 ERASE with erase type as argument */
errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2))
{
/* Wait that the device is ready by checking the D0 line */
- while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
- if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
{
errorstate = HAL_MMC_ERROR_TIMEOUT;
}
@@ -2545,13 +2870,13 @@
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
- if(errorstate != HAL_MMC_ERROR_TIMEOUT)
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
@@ -2584,19 +2909,19 @@
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Index : 165 - Value : 0x01 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Wait that the device is ready by checking the D0 line */
- while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
- if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
{
errorstate = HAL_MMC_ERROR_TIMEOUT;
}
@@ -2605,14 +2930,14 @@
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -2620,7 +2945,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -2646,13 +2971,13 @@
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
- if(errorstate != HAL_MMC_ERROR_TIMEOUT)
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
@@ -2680,8 +3005,10 @@
* @param SRTMode Specifies the type of erase to be performed
* This parameter can be one of the following values:
* @arg HAL_MMC_SRT_ERASE Information removed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character
+ * followed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+ * its complement then a random character
* @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
* @retval HAL status
*/
@@ -2693,28 +3020,28 @@
assert_param(IS_MMC_SRT_TYPE(SRTMode));
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Get the supported values by the device */
- if(HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
+ if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check the value passed as parameter is supported by the device */
- if((SRTMode & srt) != 0U)
+ if ((SRTMode & srt) != 0U)
{
/* Index : 16 - Value : SRTMode */
srt |= ((POSITION_VAL(SRTMode)) << 4U);
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U)));
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -2722,7 +3049,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -2757,7 +3084,7 @@
}
/* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2781,47 +3108,28 @@
* @param SupportedSRT pointer for supported SRT value
* This parameter is a bit field of the following values:
* @arg HAL_MMC_SRT_ERASE Information removed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed
+ * by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+ * its complement then a random character
* @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT)
{
- uint32_t srt = 0U;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
- /* Read the Extended CSD register and get expected value */
- if(MMC_ReadExtCSD(hmmc, &srt, 16, 0x0FFFFFFFU) == HAL_OK) /* Field SECURE_REMOVAL_TYPE [16] */
- {
- *SupportedSRT = (srt & 0x0000000FU); /* Bits [3:0] of field 16 */
- }
- else
- {
- errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
+ /* Read field SECURE_REMOVAL_TYPE [16 = 4*4] of the Extended CSD register */
+ *SupportedSRT = (hmmc->Ext_CSD[4] & 0x0000000FU); /* Bits [3:0] of field 16 */
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
- /* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
- else
- {
- return HAL_OK;
- }
+ return HAL_OK;
}
else
{
@@ -2852,11 +3160,11 @@
{
HAL_MMC_CardCSDTypeDef CSD;
uint32_t errorstate;
- uint16_t mmc_rca = 1U;
+ uint16_t mmc_rca = 2U;
MMC_InitTypeDef Init;
/* Check the power State */
- if(SDMMC_GetPowerState(hmmc->Instance) == 0U)
+ if (SDMMC_GetPowerState(hmmc->Instance) == 0U)
{
/* Power off */
return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
@@ -2864,7 +3172,7 @@
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -2877,10 +3185,10 @@
hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
}
- /* Send CMD3 SET_REL_ADDR with argument 0 */
+ /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */
/* MMC Card publishes its RCA. */
- errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca);
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -2890,7 +3198,7 @@
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -2906,9 +3214,9 @@
/* Get the Card Class */
hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
- /* Select the Card */
+ /* Select the Card */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -2921,17 +3229,28 @@
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+
+ /* Get Extended CSD parameters */
+ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
+ {
+ return hmmc->ErrorCode;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
/* Configure the SDMMC peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = SDMMC_BUS_WIDE_1B;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
+ Init = hmmc->Init;
+ Init.BusWide = SDMMC_BUS_WIDE_1B;
(void)SDMMC_Init(hmmc->Instance, Init);
/* All cards are initialized */
@@ -2953,21 +3272,21 @@
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
- while(validvoltage == 0U)
+ while (validvoltage == 0U)
{
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ if (count++ == SDMMC_MAX_VOLT_TRIAL)
{
return HAL_MMC_ERROR_INVALID_VOLTRANGE;
}
- /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
- errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ /* SEND CMD1 APP_CMD with voltage range as argument */
+ errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3014,14 +3333,14 @@
{
uint32_t errorstate;
- if(pCardStatus == NULL)
+ if (pCardStatus == NULL)
{
return HAL_MMC_ERROR_PARAM;
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -3040,7 +3359,8 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
+ uint16_t FieldIndex, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -3065,7 +3385,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -3075,17 +3395,17 @@
}
/* Poll on SDMMC flags */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
- /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
- /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
- if ((i + count) == ((uint32_t)FieldIndex/4U))
+ /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
+ /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
+ if ((i + count) == ((uint32_t)FieldIndex / 4U))
{
*pFieldData = tmp_data;
}
@@ -3093,19 +3413,49 @@
i += 8U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
+ hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
+ /* Get error state */
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -3127,14 +3477,14 @@
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count, data;
- uint8_t* tmp;
+ uint8_t *tmp;
tmp = hmmc->pRxBuffPtr;
if (hmmc->RxXferSize >= 32U)
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tmp = (uint8_t)(data & 0xFFU);
@@ -3161,14 +3511,14 @@
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count, data;
- uint8_t* tmp;
+ uint8_t *tmp;
tmp = hmmc->pTxBuffPtr;
if (hmmc->TxXferSize >= 32U)
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tmp);
tmp++;
@@ -3196,28 +3546,37 @@
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t response = 0U, count;
+ uint32_t sdmmc_clk;
SDMMC_InitTypeDef Init;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
{
- /* Index : 185 - Value : 0 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
- }
-
- if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
- {
- /* Index : 185 - Value : 1 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
+ errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 185 - Value : 0 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
+ }
}
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 185 - Value : 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
+ }
+ }
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -3225,7 +3584,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -3247,15 +3606,24 @@
{
Init.ClockDiv = hmmc->Init.ClockDiv;
(void)SDMMC_Init(hmmc->Instance, Init);
-
+
CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
}
else
{
- Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
- (void)SDMMC_Init(hmmc->Instance, Init);
-
- SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+ /* High Speed Clock should be less or equal to 52MHz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ if (sdmmc_clk == 0U)
+ {
+ errorstate = SDMMC_ERROR_INVALID_PARAMETER;
+ }
+ else
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ);
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
+ SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+ }
}
}
}
@@ -3287,38 +3655,54 @@
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
- /* Index : 183 - Value : 1 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ }
}
else
{
- /* Index : 183 - Value : 2 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 2 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ }
}
}
-
+
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
- /* Index : 183 - Value : 5 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 5 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
+ }
}
else
{
- /* Index : 183 - Value : 6 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR);
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 6 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
+ }
}
}
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -3326,7 +3710,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -3363,6 +3747,109 @@
}
/**
+ * @brief Update the power class of the device.
+ * @param hmmc MMC handle
+ * @param Wide Wide of MMC bus
+ * @param Speed Speed of the MMC bus
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed)
+{
+ uint32_t count;
+ uint32_t response = 0U;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t power_class, supported_pwr_class;
+
+ if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
+ {
+ power_class = 0U; /* Default value after power-on or software reset */
+
+ /* Read the PowerClass field of the Extended CSD register */
+ if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ else
+ {
+ power_class = ((power_class >> 24U) & 0x000000FFU);
+ }
+
+ /* Get the supported PowerClass field of the Extended CSD register */
+ if (Speed == SDMMC_SPEED_MODE_DDR)
+ {
+ /* Field PWR_CL_DDR_52_xxx [238 or 239] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) &
+ 0x000000FFU);
+ }
+ else if (Speed == SDMMC_SPEED_MODE_HIGH)
+ {
+ /* Field PWR_CL_52_xxx [200 or 202] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) &
+ 0x000000FFU);
+ }
+ else
+ {
+ /* Field PWR_CL_26_xxx [201 or 203] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) &
+ 0x000000FFU);
+ }
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (Wide == SDMMC_BUS_WIDE_8B)
+ {
+ /* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */
+ supported_pwr_class = (supported_pwr_class >> 4U);
+ }
+
+ if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU))
+ {
+ /* Need to change current power class */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U)));
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ }
+ }
+
+ return errorstate;
+}
+
+/**
* @brief Read DMA Buffer 0 Transfer completed callbacks
* @param hmmc: MMC handle
* @retval None
diff --git a/Src/stm32h7xx_hal_mmc_ex.c b/Src/stm32h7xx_hal_mmc_ex.c
index 6c404ca..f392a54 100644
--- a/Src/stm32h7xx_hal_mmc_ex.c
+++ b/Src/stm32h7xx_hal_mmc_ex.c
@@ -15,7 +15,8 @@
The MMC Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
- (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
+ (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and
+ HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
@@ -60,8 +61,8 @@
/** @addtogroup MMCEx_Exported_Functions_Group1
- * @brief Multibuffer functions
- *
+ * @brief Multibuffer functions
+ *
@verbatim
==============================================================================
##### Multibuffer functions #####
@@ -77,18 +78,19 @@
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hmmc: MMC handle
- * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
+ * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data
+ * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0,
+ uint32_t *pDataBuffer1, uint32_t BufferSize)
{
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
- hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
- hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize);
+ hmmc->Instance->IDMABASE0 = (uint32_t) pDataBuffer0 ;
+ hmmc->Instance->IDMABASE1 = (uint32_t) pDataBuffer1 ;
+ hmmc->Instance->IDMABSIZE = (uint32_t)(MMC_BLOCKSIZE * BufferSize);
return HAL_OK;
}
@@ -100,27 +102,48 @@
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
@@ -152,7 +175,7 @@
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -161,14 +184,15 @@
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
@@ -180,28 +204,49 @@
}
/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+ */
+HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t add = BlockAdd;
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
@@ -232,7 +277,7 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -241,14 +286,15 @@
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
@@ -270,9 +316,10 @@
* transfer use BUFFER0.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
+HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer)
{
- if(Buffer == MMC_DMA_BUFFER0)
+ if (Buffer == MMC_DMA_BUFFER0)
{
/* change the buffer0 address */
hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
diff --git a/Src/stm32h7xx_hal_nand.c b/Src/stm32h7xx_hal_nand.c
index 955556b..1b59059 100644
--- a/Src/stm32h7xx_hal_nand.c
+++ b/Src/stm32h7xx_hal_nand.c
@@ -155,7 +155,8 @@
* @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
{
/* Check the NAND handle state */
if (hnand == NULL)
@@ -169,7 +170,7 @@
hnand->Lock = HAL_UNLOCKED;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- if(hnand->MspInitCallback == NULL)
+ if (hnand->MspInitCallback == NULL)
{
hnand->MspInitCallback = HAL_NAND_MspInit;
}
@@ -180,7 +181,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
}
/* Initialize NAND control Interface */
@@ -194,7 +195,7 @@
/* Enable the NAND device */
__FMC_NAND_ENABLE(hnand->Instance);
-
+
/* Enable FMC Peripheral */
__FMC_ENABLE();
/* Update the NAND controller state */
@@ -212,7 +213,7 @@
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
{
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- if(hnand->MspDeInitCallback == NULL)
+ if (hnand->MspDeInitCallback == NULL)
{
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
}
@@ -222,7 +223,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspDeInit(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Configure the NAND registers with their reset values */
(void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
@@ -274,7 +275,7 @@
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
-*/
+ */
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
{
/* Check NAND interrupt Rising edge flag */
@@ -285,7 +286,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Rising edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
@@ -299,7 +300,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Level pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
@@ -313,7 +314,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Falling edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
@@ -327,7 +328,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt FIFO empty pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
@@ -381,7 +382,7 @@
{
__IO uint32_t data = 0;
__IO uint32_t data1 = 0;
- uint32_t deviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -397,18 +398,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
__DSB();
/* Read the electronic signature from NAND flash */
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
- data = *(__IO uint32_t *)deviceAddress;
+ data = *(__IO uint32_t *)deviceaddress;
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
@@ -418,8 +419,8 @@
}
else
{
- data = *(__IO uint32_t *)deviceAddress;
- data1 = *((__IO uint32_t *)deviceAddress + 4);
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4);
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
@@ -450,7 +451,7 @@
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
- uint32_t deviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -466,10 +467,10 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -515,12 +516,16 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -536,16 +541,16 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -553,22 +558,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -576,31 +581,31 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
@@ -625,25 +630,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *buff = *(uint8_t *)deviceAddress;
+ *buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -669,12 +674,16 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -690,16 +699,16 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -707,22 +716,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -730,31 +739,31 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -778,25 +787,36 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
+ /* Calculate PageSize */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+ {
+ hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+ }
+ else
+ {
+ /* Do nothing */
+ /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+ }
+
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *buff = *(uint16_t *)deviceAddress;
+ *buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -822,12 +842,16 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -843,18 +867,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -862,22 +886,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -885,26 +909,26 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -912,12 +936,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *(__IO uint8_t *)deviceAddress = *buff;
+ *(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -939,13 +963,13 @@
}
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -971,12 +995,16 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -992,18 +1020,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -1011,22 +1039,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1034,39 +1062,50 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
+ /* Calculate PageSize */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+ {
+ hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+ }
+ else
+ {
+ /* Do nothing */
+ /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+ }
+
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *(__IO uint16_t *)deviceAddress = *buff;
+ *(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1088,13 +1127,13 @@
}
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1119,13 +1158,18 @@
* @param pBuffer pointer to source buffer to write
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1141,78 +1185,78 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) read loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -1236,25 +1280,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *buff = *(uint8_t *)deviceAddress;
+ *buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1279,13 +1323,18 @@
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1301,78 +1350,78 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) read loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -1396,25 +1445,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *buff = *(uint16_t *)deviceAddress;
+ *buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1440,12 +1489,17 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1461,77 +1515,77 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Page address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) write loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1539,12 +1593,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *(__IO uint8_t *)deviceAddress = *buff;
+ *(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1566,13 +1620,13 @@
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1598,12 +1652,17 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1619,77 +1678,77 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) write loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1697,12 +1756,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *(__IO uint16_t *)deviceAddress = *buff;
+ *(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1724,13 +1783,13 @@
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1756,7 +1815,7 @@
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
- uint32_t DeviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1772,19 +1831,19 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- DeviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
__DSB();
/* Update the NAND controller state */
@@ -1851,11 +1910,12 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -1863,39 +1923,39 @@
/* Process locked */
__HAL_LOCK(hnand);
- if(hnand->State == HAL_NAND_STATE_READY)
+ if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = pCallback;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = pCallback;
- break;
- case HAL_NAND_IT_CB_ID :
- hnand->ItCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hnand->State == HAL_NAND_STATE_RESET)
+ else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = pCallback;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1920,46 +1980,46 @@
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hnand);
- if(hnand->State == HAL_NAND_STATE_READY)
+ if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = HAL_NAND_MspInit;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- break;
- case HAL_NAND_IT_CB_ID :
- hnand->ItCallback = HAL_NAND_ITCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = HAL_NAND_ITCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hnand->State == HAL_NAND_STATE_RESET)
+ else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = HAL_NAND_MspInit;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1972,15 +2032,15 @@
__HAL_UNLOCK(hnand);
return status;
}
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### NAND Control functions #####
@@ -2100,8 +2160,8 @@
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### NAND State functions #####
@@ -2134,17 +2194,17 @@
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
uint32_t data;
- uint32_t DeviceAddress;
+ uint32_t deviceaddress;
UNUSED(hnand);
/* Identify the device address */
- DeviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
- data = *(__IO uint8_t *)DeviceAddress;
+ data = *(__IO uint8_t *)deviceaddress;
/* Return the status */
if ((data & NAND_ERROR) == NAND_ERROR)
diff --git a/Src/stm32h7xx_hal_nor.c b/Src/stm32h7xx_hal_nor.c
index 4a354ae..1fab108 100644
--- a/Src/stm32h7xx_hal_nor.c
+++ b/Src/stm32h7xx_hal_nor.c
@@ -150,9 +150,35 @@
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
+#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
+#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
+#define NOR_CMD_CONFIRM (uint16_t)0x00D0
+#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
+#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
+#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
+#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
+
/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
+
+/* Address of the primary command set */
+#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
+
+/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
+#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
+#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
+#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
+#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
+#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
+#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
+#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
+#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
/**
* @}
@@ -199,8 +225,11 @@
* @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
+ uint32_t deviceaddress;
+
/* Check the NOR handle parameter */
if (hnor == NULL)
{
@@ -213,7 +242,7 @@
hnor->Lock = HAL_UNLOCKED;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- if(hnor->MspInitCallback == NULL)
+ if (hnor->MspInitCallback == NULL)
{
hnor->MspInitCallback = HAL_NOR_MspInit;
}
@@ -254,7 +283,29 @@
/* Initialize the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
- return HAL_OK;
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Get the value of the command set */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ return HAL_NOR_ReturnToReadMode(hnor);
}
/**
@@ -266,7 +317,7 @@
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- if(hnor->MspDeInitCallback == NULL)
+ if (hnor->MspDeInitCallback == NULL)
{
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
}
@@ -369,6 +420,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -403,15 +455,33 @@
}
/* Send read ID command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+ if (status != HAL_ERROR)
+ {
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE3_ADDR);
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -424,7 +494,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -437,6 +507,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -470,7 +541,19 @@
deviceaddress = NOR_MEMORY_ADRESS4;
}
- NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -483,7 +566,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -498,6 +581,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -532,12 +616,27 @@
}
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Read the data */
- *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+ if (status != HAL_ERROR)
+ {
+ /* Read the data */
+ *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -550,7 +649,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -564,6 +663,7 @@
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -597,12 +697,27 @@
}
/* Send program data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Write the data */
- NOR_WRITE(pAddress, *pData);
+ if (status != HAL_ERROR)
+ {
+ /* Write the data */
+ NOR_WRITE(pAddress, *pData);
+ }
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -615,7 +730,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -627,11 +742,15 @@
* @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
{
- uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
+ uint32_t deviceaddress;
+ uint32_t size = uwBufferSize;
+ uint32_t address = uwAddress;
uint16_t *data = pData;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -666,17 +785,32 @@
}
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
-
- /* Read buffer */
- while (size > 0U)
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- *data = *(__IO uint16_t *)address;
- data++;
- address += 2U;
- size--;
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Read buffer */
+ while (size > 0U)
+ {
+ *data = *(__IO uint16_t *)address;
+ data++;
+ address += 2U;
+ size--;
+ }
}
/* Check the NOR controller state */
@@ -690,7 +824,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -702,12 +836,14 @@
* @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
{
uint16_t *p_currentaddress;
const uint16_t *p_endaddress;
uint16_t *data = pData;
- uint32_t lastloadedaddress, deviceaddress;
+ uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -741,31 +877,51 @@
}
/* Initialize variables */
- p_currentaddress = (uint16_t *)(uwAddress);
- p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
- lastloadedaddress = uwAddress;
+ p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
+ p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
- /* Write Buffer Load Command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
-
- /* Load Data into NOR Buffer */
- while (p_currentaddress <= p_endaddress)
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Store last loaded address & data value (for polling) */
- lastloadedaddress = (uint32_t)p_currentaddress;
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(p_currentaddress, *data);
-
- data++;
- p_currentaddress ++;
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
}
- NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+ if (status != HAL_ERROR)
+ {
+ /* Load Data into NOR Buffer */
+ while (p_currentaddress <= p_endaddress)
+ {
+ NOR_WRITE(p_currentaddress, *data);
+
+ data++;
+ p_currentaddress ++;
+ }
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+ }
+ else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
+ }
+ }
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -778,7 +934,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
@@ -793,6 +949,7 @@
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -826,12 +983,30 @@
}
/* Send block erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -844,7 +1019,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
@@ -858,6 +1033,7 @@
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
UNUSED(Address);
/* Check the NOR controller state */
@@ -892,12 +1068,23 @@
}
/* Send NOR chip erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -910,7 +1097,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -992,12 +1179,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -1006,20 +1194,20 @@
__HAL_LOCK(hnor);
state = hnor->State;
- if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_NOR_MSP_INIT_CB_ID :
- hnor->MspInitCallback = pCallback;
- break;
- case HAL_NOR_MSP_DEINIT_CB_ID :
- hnor->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = pCallback;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1043,7 +1231,7 @@
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
@@ -1052,20 +1240,20 @@
__HAL_LOCK(hnor);
state = hnor->State;
- if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_NOR_MSP_INIT_CB_ID :
- hnor->MspInitCallback = HAL_NOR_MspInit;
- break;
- case HAL_NOR_MSP_DEINIT_CB_ID :
- hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1085,8 +1273,8 @@
*/
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### NOR Control functions #####
@@ -1108,7 +1296,7 @@
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_PROTECTED)
+ if (hnor->State == HAL_NOR_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1142,7 +1330,7 @@
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_READY)
+ if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1172,8 +1360,8 @@
*/
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### NOR State functions #####
@@ -1209,7 +1397,8 @@
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
- uint16_t tmpSR1, tmpSR2;
+ uint16_t tmpsr1;
+ uint16_t tmpsr2;
uint32_t tickstart;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
@@ -1219,45 +1408,84 @@
/* Get tick */
tickstart = HAL_GetTick();
- while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
+ while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
{
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- status = HAL_NOR_STATUS_TIMEOUT;
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS ;
+ }
+
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
}
}
-
- /* Read NOR status register (DQ6 and DQ5) */
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ do
{
- return HAL_NOR_STATUS_SUCCESS ;
- }
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpsr2 = *(__IO uint16_t *)(Address);
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
- {
- status = HAL_NOR_STATUS_ONGOING;
- }
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ return HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+ } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpsr1 = *(__IO uint16_t *)(Address);
+ if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
{
- return HAL_NOR_STATUS_SUCCESS;
+ /* Clear the Status Register */
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ status = HAL_NOR_STATUS_ERROR;
}
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ else
{
- return HAL_NOR_STATUS_ERROR;
+ status = HAL_NOR_STATUS_SUCCESS;
}
}
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_NOR_STATUS_ERROR;
+ }
/* Return the operation status */
return status;
diff --git a/Src/stm32h7xx_hal_ospi.c b/Src/stm32h7xx_hal_ospi.c
index b76f805..69cb96e 100644
--- a/Src/stm32h7xx_hal_ospi.c
+++ b/Src/stm32h7xx_hal_ospi.c
@@ -23,201 +23,224 @@
*** Initialization ***
======================
[..]
- (#) As prerequisite, fill in the HAL_OSPI_MspInit() :
- (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE().
- (++) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
- (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
- (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
- (++) If interrupt or DMA mode is used, enable and configure OctoSPI global
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
- with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
- link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
- DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (#) Configure the fifo threshold, the dual-quad mode, the memory type, the
- device size, the CS high time, the free running clock, the clock mode,
- the wrap size, the clock prescaler, the sample shifting, the hold delay
- and the CS boundary using the HAL_OSPI_Init() function.
- (#) When using Hyperbus, configure the RW recovery time, the access time,
- the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
- function.
+ As prerequisite, fill in the HAL_OSPI_MspInit() :
+ (+) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE().
+ (+) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
+ (+) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (+) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
+ (+) If interrupt or DMA mode is used, enable and configure OctoSPI global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (+) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ [..]
+ Configure the fifo threshold, the dual-quad mode, the memory type, the
+ device size, the CS high time, the free running clock, the clock mode,
+ the wrap size, the clock prescaler, the sample shifting, the hold delay
+ and the CS boundary using the HAL_OSPI_Init() function.
+ [..]
+ When using Hyperbus, configure the RW recovery time, the access time,
+ the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
+ function.
*** Indirect functional mode ***
================================
[..]
- (#) In regular mode, configure the command sequence using the HAL_OSPI_Command()
- or HAL_OSPI_Command_IT() functions :
- (++) Instruction phase : the mode used and if present the size, the instruction
- opcode and the DTR mode.
- (++) Address phase : the mode used and if present the size, the address
- value and the DTR mode.
- (++) Alternate-bytes phase : the mode used and if present the size, the
- alternate bytes values and the DTR mode.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used and if present the number of bytes and the DTR mode.
- (++) Data strobe (DQS) mode : the activation (or not) of this mode
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (++) Flash identifier : in dual-quad mode, indicates which flash is concerned
- (++) Operation type : always common configuration
- (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
- function :
- (++) Address space : indicate if the access will be done in register or memory
- (++) Address size
- (++) Number of data
- (++) Data strobe (DQS) mode : the activation (or not) of this mode
- (#) If no data is required for the command (only for regular mode, not for
- Hyperbus mode), it is sent directly to the memory :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
- (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
- HAL_OSPI_Transmit_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
- HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
- (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
- HAL_OSPI_Receive_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
- HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
+ In regular mode, configure the command sequence using the HAL_OSPI_Command()
+ or HAL_OSPI_Command_IT() functions :
+ (+) Instruction phase : the mode used and if present the size, the instruction
+ opcode and the DTR mode.
+ (+) Address phase : the mode used and if present the size, the address
+ value and the DTR mode.
+ (+) Alternate-bytes phase : the mode used and if present the size, the
+ alternate bytes values and the DTR mode.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used and if present the number of bytes and the DTR mode.
+ (+) Data strobe (DQS) mode : the activation (or not) of this mode
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (+) Flash identifier : in dual-quad mode, indicates which flash is concerned
+ (+) Operation type : always common configuration
+ [..]
+ In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
+ function :
+ (+) Address space : indicate if the access will be done in register or memory
+ (+) Address size
+ (+) Number of data
+ (+) Data strobe (DQS) mode : the activation (or not) of this mode
+ [..]
+ If no data is required for the command (only for regular mode, not for
+ Hyperbus mode), it is sent directly to the memory :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
+ [..]
+ For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
+ HAL_OSPI_Transmit_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
+ HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
+ [..]
+ For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
+ HAL_OSPI_Receive_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
+ HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
[..]
- (#) Configure the command sequence by the same way than the indirect mode
- (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
- or HAL_OSPI_AutoPolling_IT() functions :
- (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
- the polling interval and the automatic stop activation.
- (#) After the configuration :
- (++) In polling mode, the output of the function is done when the status match is reached. The
- automatic stop is activated to avoid an infinite loop.
- (++) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
+ Configure the command sequence by the same way than the indirect mode
+ [..]
+ Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
+ or HAL_OSPI_AutoPolling_IT() functions :
+ (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+ the polling interval and the automatic stop activation.
+ [..]
+ After the configuration :
+ (+) In polling mode, the output of the function is done when the status match is reached. The
+ automatic stop is activated to avoid an infinite loop.
+ (+) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
+
*** MDMA functional mode ***
====================================
[..]
- (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_OSPI_MspInit() function :
- (++) MDMA settings for write operation :
- (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
- (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
- (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
+ Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_OSPI_MspInit() function :
+ (+) MDMA settings for write operation :
+ (++) The DestinationInc should be MDMA_DEST_INC_DISABLE
+ (++) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
+ (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Source_increment_mode .
- (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
- (++) MDMA settings for read operation :
- (+) The SourceInc should be MDMA_SRC_INC_DISABLE
- (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
- (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
- (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ (+) MDMA settings for read operation :
+ (++) The SourceInc should be MDMA_SRC_INC_DISABLE
+ (++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
+ (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
+ (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Destination_increment_mode.
- (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi.
- (#)In case of wrong MDMA setting
- (++) For write operation :
- (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA().
- (++) For read operation :
- (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA().
+ (+) The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi.
+ [..]
+ In case of wrong MDMA setting
+ (+) For write operation :
+ (++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA().
+ (+) For read operation :
+ (++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA().
*** Memory-mapped functional mode ***
=====================================
[..]
- (#) Configure the command sequence by the same way than the indirect mode except
- for the operation type in regular mode :
- (++) Operation type equals to read configuration : the command configuration
- applies to read access in memory-mapped mode
- (++) Operation type equals to write configuration : the command configuration
- applies to write access in memory-mapped mode
- (++) Both read and write configuration should be performed before activating
- memory-mapped mode
- (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
- functions :
- (++) The timeout activation and the timeout period.
- (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
- the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.
+ Configure the command sequence by the same way than the indirect mode except
+ for the operation type in regular mode :
+ (+) Operation type equals to read configuration : the command configuration
+ applies to read access in memory-mapped mode
+ (+) Operation type equals to write configuration : the command configuration
+ applies to write access in memory-mapped mode
+ (+) Both read and write configuration should be performed before activating
+ memory-mapped mode
+ [..]
+ Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
+ functions :
+ (+) The timeout activation and the timeout period.
+ [..]
+ After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
+ the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.
*** Errors management and abort functionality ***
=================================================
[..]
- (#) HAL_OSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
- flushes the fifo :
- (++) In polling mode, the output of the function is done when the transfer
- complete bit is set and the busy bit cleared.
- (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
- the transfer complete bit is set.
+ HAL_OSPI_GetError() function gives the error raised during the last operation.
+ [..]
+ HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
+ flushes the fifo :
+ (+) In polling mode, the output of the function is done when the transfer
+ complete bit is set and the busy bit cleared.
+ (+) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
+ the transfer complete bit is set.
*** Control functions ***
=========================
[..]
- (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
- (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
- (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
- (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+ HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
+ [..]
+ HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
+ [..]
+ HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
+ [..]
+ HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
*** IO manager configuration functions ***
==========================================
[..]
- (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance.
+ HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance.
*** Callback registration ***
=============================================
[..]
- The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
+ The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_OSPI_RegisterCallback() to register a user callback,
- it allows to register following callbacks:
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) FifoThresholdCallback : callback when the fifo threshold is reached.
- (+) CmdCpltCallback : callback when a command without data is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
- (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
- (+) StatusMatchCallback : callback when a status match occurs.
- (+) TimeOutCallback : callback when the timeout perioed expires.
- (+) MspInitCallback : OSPI MspInit.
- (+) MspDeInitCallback : OSPI MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
+ [..]
+ Use function HAL_OSPI_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : OSPI MspInit.
+ (+) MspDeInitCallback : OSPI MspDeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
- Use function @ref HAL_OSPI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) FifoThresholdCallback : callback when the fifo threshold is reached.
- (+) CmdCpltCallback : callback when a command without data is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
- (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
- (+) StatusMatchCallback : callback when a status match occurs.
- (+) TimeOutCallback : callback when the timeout perioed expires.
- (+) MspInitCallback : OSPI MspInit.
- (+) MspDeInitCallback : OSPI MspDeInit.
- This function) takes as parameters the HAL peripheral handle and the Callback ID.
+ [..]
+ Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : OSPI MspInit.
+ (+) MspDeInitCallback : OSPI MspDeInit.
+ [..]
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
- Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init
- and @ref HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
+ By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
+ and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
- Callbacks can be registered/unregistered in READY state only.
- Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
- in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
- during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit
- or @ref HAL_OSPI_Init function.
+ [..]
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_OSPI_RegisterCallback() before calling HAL_OSPI_DeInit()
+ or HAL_OSPI_Init() function.
- When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ [..]
+ When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
@@ -280,7 +303,8 @@
static void OSPI_DMACplt (MDMA_HandleTypeDef *hmdma);
static void OSPI_DMAError (MDMA_HandleTypeDef *hmdma);
static void OSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma);
-static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
+ uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
/**
@@ -374,7 +398,7 @@
#else
/* Initialization of the low level hardware */
HAL_OSPI_MspInit(hospi);
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/* Configure the default timeout for the OSPI memory access */
(void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
@@ -391,8 +415,9 @@
/* Configure wrap size */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);
- /* Configure chip select boundary and maximun transfer */
- hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
+ /* Configure chip select boundary and maximum transfer */
+ hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) |
+ (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
/* Configure refresh */
hospi->Instance->DCR4 = hospi->Init.Refresh;
@@ -406,13 +431,15 @@
if (status == HAL_OK)
{
/* Configure clock prescaler */
- MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
+ ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
/* Configure sample shifting and delay hold quarter cycle */
- MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
+ (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
/* Enable OctoSPI */
__HAL_OSPI_ENABLE(hospi);
@@ -489,7 +516,7 @@
#else
/* De-initialize the low-level hardware */
HAL_OSPI_MspDeInit(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/* Reset the driver state */
hospi->State = HAL_OSPI_STATE_RESET;
@@ -584,7 +611,7 @@
hospi->FifoThresholdCallback(hospi);
#else
HAL_OSPI_FifoThresholdCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
/* OctoSPI transfer complete interrupt occurred ----------------------------*/
else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
@@ -614,7 +641,7 @@
hospi->RxCpltCallback(hospi);
#else
HAL_OSPI_RxCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
@@ -639,7 +666,7 @@
hospi->TxCpltCallback(hospi);
#else
HAL_OSPI_TxCpltCallback(hospi);
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
{
@@ -648,7 +675,7 @@
hospi->CmdCpltCallback(hospi);
#else
HAL_OSPI_CmdCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else if (currentstate == HAL_OSPI_STATE_ABORT)
{
@@ -660,7 +687,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
else
{
@@ -670,7 +697,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
else
@@ -700,7 +727,7 @@
hospi->StatusMatchCallback(hospi);
#else
HAL_OSPI_StatusMatchCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
/* OctoSPI transfer error interrupt occurred -------------------------------*/
else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U))
@@ -732,7 +759,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
else
@@ -745,7 +772,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
/* OctoSPI timeout interrupt occurred --------------------------------------*/
@@ -759,7 +786,7 @@
hospi->TimeOutCallback(hospi);
#else
HAL_OSPI_TimeOutCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
@@ -826,8 +853,10 @@
/* Check the state of the driver */
state = hospi->State;
if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
- ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
- ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
+ ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
+ || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
+ ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
+ (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
@@ -1457,16 +1486,16 @@
/* Enable the transmit MDMA Channel */
if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
-
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+
+ /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
hospi->State = HAL_OSPI_STATE_READY;
}
}
@@ -1618,7 +1647,7 @@
uint32_t ir_reg = hospi->Instance->IR;
#ifdef USE_FULL_ASSERT
uint32_t dlr_reg = hospi->Instance->DLR;
-#endif
+#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
@@ -1696,7 +1725,7 @@
uint32_t ir_reg = hospi->Instance->IR;
#ifdef USE_FULL_ASSERT
uint32_t dlr_reg = hospi->Instance->DLR;
-#endif
+#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
@@ -1983,7 +2012,8 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
+ pOSPI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2171,7 +2201,7 @@
return status;
}
-#endif
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
@@ -2302,7 +2332,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
else
@@ -2328,7 +2358,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
}
@@ -2442,7 +2472,9 @@
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t instance;
- uint8_t index, ospi_enabled = 0U, other_instance;
+ uint8_t index;
+ uint8_t ospi_enabled = 0U;
+ uint8_t other_instance;
OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE];
/* Prevent unused argument(s) compilation warning */
@@ -2450,7 +2482,7 @@
/* Check the parameters of the OctoSPI IO Manager configuration structure */
assert_param(IS_OSPIM_PORT(cfg->ClkPort));
- assert_param(IS_OSPIM_PORT(cfg->DQSPort));
+ assert_param(IS_OSPIM_DQS_PORT(cfg->DQSPort));
assert_param(IS_OSPIM_PORT(cfg->NCSPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
@@ -2500,20 +2532,38 @@
if (other_instance == 1U)
{
- SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
- SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
- SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
- SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
+ if (IOM_cfg[other_instance].DQSPort != 0U)
+ {
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
+ }
+ if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
+ }
+ if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
+ }
}
}
else
{
if (IOM_cfg[instance].ClkPort != 0U)
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ if (IOM_cfg[instance].DQSPort != 0U)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ }
+ if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ }
+ if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ }
}
}
@@ -2522,24 +2572,38 @@
(cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
- if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
- (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) &&
+ (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
+ (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
+ (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
/* Multiplexing should be performed */
SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
}
else
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ if (IOM_cfg[other_instance].DQSPort != 0U)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ }
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+ if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOLEN);
+ }
+ if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ OCTOSPIM_PCR_IOHEN);
+ }
}
}
/******************** Activation of new configuration *********************/
- MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
+ (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
{
@@ -2549,51 +2613,83 @@
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
+ if (cfg->DQSPort != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
+ }
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+ }
+ else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
+ /* Nothing to do */
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+ }
+ else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
+ /* Nothing to do */
}
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
+ (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
+ if (cfg->DQSPort != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
+ (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+ }
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ }
+ else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ /* Nothing to do */
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ }
+ else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ /* Nothing to do */
}
}
@@ -2667,7 +2763,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
@@ -2706,7 +2802,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
else
@@ -2720,7 +2816,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
@@ -2763,7 +2859,10 @@
static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
{
HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg;
+ __IO uint32_t *ccr_reg;
+ __IO uint32_t *tcr_reg;
+ __IO uint32_t *ir_reg;
+ __IO uint32_t *abr_reg;
/* Re-initialize the value of the functional mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
@@ -2941,7 +3040,8 @@
static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t reg, value = 0U;
+ uint32_t reg;
+ uint32_t value = 0U;
uint32_t index;
if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL))
@@ -2962,7 +3062,8 @@
{
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
{
- value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
+ | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
}
else
{
diff --git a/Src/stm32h7xx_hal_otfdec.c b/Src/stm32h7xx_hal_otfdec.c
index a54882e..2b3fd1b 100644
--- a/Src/stm32h7xx_hal_otfdec.c
+++ b/Src/stm32h7xx_hal_otfdec.c
@@ -305,7 +305,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, pOTFDEC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
+ pOTFDEC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -644,10 +645,14 @@
* the configuration information for OTFDEC module
* @param RegionIndex index of region the mode of which is set
* @param mode This parameter can be only:
- * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY Only instruction accesses are decrypted
- * @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY Only data accesses are decrypted
- * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES All read accesses are decrypted (instruction or data)
- * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER Only instruction accesses are decrypted with proprietary cipher activated
+ * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY
+ Only instruction accesses are decrypted
+ * @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY
+ Only data accesses are decrypted
+ * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES
+ All read accesses are decrypted (instruction or data)
+ * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER
+ Only instruction accesses are decrypted with proprietary cipher activated
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
@@ -689,7 +694,8 @@
* @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC region configuration is locked
* @retval HAL state
*/
-HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
@@ -723,7 +729,8 @@
WRITE_REG( region->REG_END_ADDR, Config->EndAddress);
/* Write Version */
- MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos );
+ MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION,
+ (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos );
/* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */
SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
@@ -754,7 +761,9 @@
uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
uint8_t i;
uint8_t crc = 0;
- uint32_t j, keyval, k;
+ uint32_t j;
+ uint32_t keyval;
+ uint32_t k;
uint32_t * temp = pKey;
for (j = 0U; j < 4U; j++)
@@ -935,7 +944,8 @@
* @param Config pointer on structure that will be filled up with the region configuration parameters
* @retval HAL state
*/
-HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config)
+HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
+ OTFDEC_RegionConfigTypeDef *Config)
{
OTFDEC_Region_TypeDef * region;
uint32_t address;
@@ -965,7 +975,8 @@
Config->EndAddress = READ_REG(region->REG_END_ADDR);
/* Read Version */
- Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
+ Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) &
+ OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
/* Release Lock */
__HAL_UNLOCK(hotfdec);
diff --git a/Src/stm32h7xx_hal_pcd.c b/Src/stm32h7xx_hal_pcd.c
index 031f01f..e577f40 100644
--- a/Src/stm32h7xx_hal_pcd.c
+++ b/Src/stm32h7xx_hal_pcd.c
@@ -102,8 +102,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -230,7 +230,7 @@
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
-
+
(void)USB_DevDisconnect(hpcd->Instance);
return HAL_OK;
@@ -252,7 +252,10 @@
hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
- (void)HAL_PCD_Stop(hpcd);
+ if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
if (hpcd->MspDeInitCallback == NULL)
@@ -321,7 +324,9 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -531,7 +536,8 @@
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -566,7 +572,7 @@
}
/**
- * @brief UnRegister the USB PCD Data OUT Stage Callback
+ * @brief Unregister the USB PCD Data OUT Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -604,7 +610,8 @@
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -639,7 +646,7 @@
}
/**
- * @brief UnRegister the USB PCD Data IN Stage Callback
+ * @brief Unregister the USB PCD Data IN Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -677,7 +684,8 @@
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -712,7 +720,7 @@
}
/**
- * @brief UnRegister the USB PCD Iso OUT incomplete Callback
+ * @brief Unregister the USB PCD Iso OUT incomplete Callback
* USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -750,7 +758,8 @@
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -785,7 +794,7 @@
}
/**
- * @brief UnRegister the USB PCD Iso IN incomplete Callback
+ * @brief Unregister the USB PCD Iso IN incomplete Callback
* USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -858,7 +867,7 @@
}
/**
- * @brief UnRegister the USB PCD BCD Callback
+ * @brief Unregister the USB PCD BCD Callback
* USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -931,7 +940,7 @@
}
/**
- * @brief UnRegister the USB PCD LPM Callback
+ * @brief Unregister the USB PCD LPM Callback
* USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -968,8 +977,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -989,22 +998,21 @@
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
__HAL_LOCK(hpcd);
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
- (void)USB_DevConnect(hpcd->Instance);
+
__HAL_PCD_ENABLE(hpcd);
+ (void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -1015,20 +1023,26 @@
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
+ (void)USB_DevDisconnect(hpcd->Instance);
- if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+ (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+
+ if ((hpcd->Init.battery_charging_enable == 1U) &&
+ (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
{
- __HAL_UNLOCK(hpcd);
- return HAL_ERROR;
+ /* Disable USB Transceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
}
- (void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
+
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Handles PCD interrupt request.
@@ -1058,7 +1072,7 @@
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
- /* Handle RxQLevel Interrupt */
+ /* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
@@ -1243,7 +1257,7 @@
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
-
+
/* Handle LPM Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
@@ -1269,7 +1283,7 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
-
+
/* Handle Reset Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
@@ -1593,8 +1607,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -1614,21 +1628,19 @@
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
__HAL_LOCK(hpcd);
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -1639,9 +1651,20 @@
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
__HAL_LOCK(hpcd);
(void)USB_DevDisconnect(hpcd->Instance);
+
+ if ((hpcd->Init.battery_charging_enable == 1U) &&
+ (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+ {
+ /* Disable USB Transceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+ }
+
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -1657,6 +1680,7 @@
hpcd->USB_Address = address;
(void)USB_SetDevAddress(hpcd->Instance, address);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
/**
@@ -1667,7 +1691,8 @@
* @param ep_type endpoint type
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
@@ -1852,10 +1877,12 @@
__HAL_LOCK(hpcd);
(void)USB_EPSetStall(hpcd->Instance, ep);
+
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
+
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -1946,8 +1973,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
diff --git a/Src/stm32h7xx_hal_pcd_ex.c b/Src/stm32h7xx_hal_pcd_ex.c
index a2a30eb..5debbe0 100644
--- a/Src/stm32h7xx_hal_pcd_ex.c
+++ b/Src/stm32h7xx_hal_pcd_ex.c
@@ -49,7 +49,7 @@
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
- *
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -260,7 +260,7 @@
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
- /* Power Down USB tranceiver */
+ /* Power Down USB transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Enable Battery charging */
diff --git a/Src/stm32h7xx_hal_pwr.c b/Src/stm32h7xx_hal_pwr.c
index 88c8d1a..0de6bb2 100644
--- a/Src/stm32h7xx_hal_pwr.c
+++ b/Src/stm32h7xx_hal_pwr.c
@@ -36,7 +36,7 @@
memory and peripherals. The SmartRun domain contains the system
control, I/O logic and low-power peripherals.
- (#) Every entity have low power mode as decribed below :
+ (#) Every entity have low power mode as described below :
(#) The CPU low power modes are :
(+) CPU CRUN.
(+) CPU CSLEEP.
@@ -587,7 +587,7 @@
/**
* @brief Enter STOP mode.
* @note For single core devices, this API will enter the system in STOP mode
- * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
+ * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is
* cleared.
* For dual core devices, this API will enter the domain (containing
* Cortex-Mx that executing this function) in DSTOP mode. If all
@@ -672,7 +672,7 @@
* @brief Enter STANDBY mode.
* @note For single core devices, this API will enter the system in STANDBY
* mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
- * regiter is cleared.
+ * register is cleared.
* For dual core devices, this API will enter the domain (containing
* Cortex-Mx that executing this function) in DSTANDBY mode. If all
* Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
diff --git a/Src/stm32h7xx_hal_pwr_ex.c b/Src/stm32h7xx_hal_pwr_ex.c
index 77cd337..aaa5809 100644
--- a/Src/stm32h7xx_hal_pwr_ex.c
+++ b/Src/stm32h7xx_hal_pwr_ex.c
@@ -102,7 +102,7 @@
(#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
HAL_PWREx_EnableUSBVoltageDetector() and
HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
- regulation functionnalities.
+ regulation functionalities.
(#) Call HAL_PWREx_EnableBatteryCharging() and
HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
diff --git a/Src/stm32h7xx_hal_qspi.c b/Src/stm32h7xx_hal_qspi.c
index 0587b0b..1221496 100644
--- a/Src/stm32h7xx_hal_qspi.c
+++ b/Src/stm32h7xx_hal_qspi.c
@@ -90,7 +90,7 @@
*** MDMA functional mode ***
====================================
[..]
- (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function :
+ (#) Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_QSPI_MspInit() function :
(++) MDMA settings for write operation :
(+) The DestinationInc should be MDMA_DEST_INC_DISABLE
(+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
@@ -569,7 +569,8 @@
{
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Disable the MDMA channel */
@@ -591,7 +592,8 @@
{
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Disable the MDMA channel */
@@ -715,7 +717,8 @@
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Disable the MDMA channel */
@@ -1332,7 +1335,8 @@
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
- /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
+ /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
@@ -1446,7 +1450,8 @@
/* Enable the QSPI transfer error Interrupt */
__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
- /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
+ /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
}
else
@@ -2160,7 +2165,8 @@
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Abort MDMA */
@@ -2221,7 +2227,8 @@
if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
- /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Abort MDMA channel */
@@ -2396,7 +2403,8 @@
hqspi->TxXferCount = 0U;
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- /* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */
+ /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+ but no impact on H7 HW and it minimize the cost in the footprint */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
/* Abort the QSPI */
diff --git a/Src/stm32h7xx_hal_ramecc.c b/Src/stm32h7xx_hal_ramecc.c
index 0ee2e2a..54491f9 100644
--- a/Src/stm32h7xx_hal_ramecc.c
+++ b/Src/stm32h7xx_hal_ramecc.c
@@ -7,14 +7,14 @@
* functionalities of the RAM ECC monitoring (RAMECC) peripheral:
* + Initialization and de-initialization functions
* + Monitoring operation functions
- * + Error informations functions
+ * + Error information functions
* + State and error functions
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- (#) Enable and latch error informations through HAL_RAMECC_Init().
+ (#) Enable and latch error information through HAL_RAMECC_Init().
(#) For a given Monitor, enable and disable interrupt through
HAL_RAMECC_EnableNotifiaction().
@@ -39,7 +39,7 @@
HAL_NVIC_SetPriority().
(+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ().
- *** Failing informations ***
+ *** Failing information ***
======================
[..]
(#) Use HAL_RAMECC_GetFailingAddress() function to return the RAMECC
@@ -230,7 +230,7 @@
##### Monitoring operation functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Configure latching error informations.
+ (+) Configure latching error information.
(+) Configure RAMECC Global/Monitor interrupts.
(+) Register and Unregister RAMECC callbacks
(+) Handle RAMECC interrupt request
@@ -278,7 +278,7 @@
/**
- * @brief Stop the RAMECC latching error informations.
+ * @brief Stop the RAMECC latching error information.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
@@ -494,7 +494,7 @@
/* Clear active flags */
__HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & sr_reg) >> 1U));
- /* Check if a valid double error callback is registred */
+ /* Check if a valid double error callback is registered */
if (hramecc->DetectErrorCallback != NULL)
{
/* Error detection callback */
@@ -507,7 +507,7 @@
*
@verbatim
===============================================================================
- ##### Error informations functions #####
+ ##### Error information functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Get failing address.
@@ -589,7 +589,7 @@
}
/**
- * @brief Check if an ECC single error was occured.
+ * @brief Check if an ECC single error was occurred.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
@@ -605,7 +605,7 @@
}
/**
- * @brief Check if an ECC double error was occured.
+ * @brief Check if an ECC double error was occurred.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
diff --git a/Src/stm32h7xx_hal_rcc.c b/Src/stm32h7xx_hal_rcc.c
index 17c241b..b5e93c7 100644
--- a/Src/stm32h7xx_hal_rcc.c
+++ b/Src/stm32h7xx_hal_rcc.c
@@ -355,6 +355,11 @@
/* Reset PLL3FRACR register */
CLEAR_REG(RCC->PLL3FRACR);
+#if defined(RCC_CR_HSEEXT)
+ /* Reset HSEEXT */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
+#endif /* RCC_CR_HSEEXT */
+
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
@@ -746,6 +751,8 @@
{
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLRGE_VALUE(RCC_OscInitStruct->PLL.PLLRGE));
+ assert_param(IS_RCC_PLLVCO_VALUE(RCC_OscInitStruct->PLL.PLLVCOSEL));
assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
diff --git a/Src/stm32h7xx_hal_rcc_ex.c b/Src/stm32h7xx_hal_rcc_ex.c
index 508dd9d..afde46b 100644
--- a/Src/stm32h7xx_hal_rcc_ex.c
+++ b/Src/stm32h7xx_hal_rcc_ex.c
@@ -1566,6 +1566,16 @@
__HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
}
+ /*------------------------------ CEC Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC interface clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+
if (status == HAL_OK)
{
return HAL_OK;
@@ -1779,7 +1789,7 @@
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
- /* This variable is used to store the SAI clock frequency (value in Hz) */
+ /* This variable is used to store the clock frequency (value in Hz) */
uint32_t frequency;
/* This variable is used to store the SAI and CKP clock source */
uint32_t saiclocksource;
@@ -1795,21 +1805,42 @@
{
case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
{
- HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
- frequency = pll1_clocks.PLL1_Q_Frequency;
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
@@ -1818,19 +1849,19 @@
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -1866,23 +1897,44 @@
switch (saiclocksource)
{
- case 0: /* PLL1 is the clock source for SAI2/3 */
+ case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
@@ -1891,19 +1943,19 @@
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -1940,23 +1992,44 @@
switch (saiclocksource)
{
- case 0: /* PLL1 is the clock source for SAI2A */
+ case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
@@ -1965,19 +2038,19 @@
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -2016,23 +2089,44 @@
switch (saiclocksource)
{
- case 0: /* PLL1 is the clock source for SAI2B */
+ case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
@@ -2041,19 +2135,19 @@
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -2090,44 +2184,65 @@
switch (saiclocksource)
{
- case 0: /* PLL1 is the clock source for SAI4A */
+ case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
+ case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
+ case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
+ case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
{
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -2142,7 +2257,7 @@
break;
}
- case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
+ case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
{
frequency = EXTERNAL_CLOCK_VALUE;
break;
@@ -2163,44 +2278,65 @@
switch (saiclocksource)
{
- case 0: /* PLL1 is the clock source for SAI4B */
+ case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
+ case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
+ case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
+ case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
{
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -2215,7 +2351,7 @@
break;
}
- case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
+ case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
{
frequency = EXTERNAL_CLOCK_VALUE;
break;
@@ -2236,44 +2372,65 @@
switch (srcclk)
{
- case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */
+ case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */
+ case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */
+ case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
- case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */
+ case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
{
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -2309,14 +2466,28 @@
{
case RCC_ADCCLKSOURCE_PLL2:
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_P_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_ADCCLKSOURCE_PLL3:
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_R_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
@@ -2325,19 +2496,19 @@
ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
- if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+ if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
{
/* In Case the CKPER Source is HSI */
- frequency = HSI_VALUE;
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
}
- else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
{
/* In Case the CKPER Source is CSI */
frequency = CSI_VALUE;
}
- else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
{
/* In Case the CKPER Source is HSE */
frequency = HSE_VALUE;
@@ -2368,14 +2539,28 @@
{
case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_R_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
@@ -2400,29 +2585,64 @@
}
case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
frequency = pll2_clocks.PLL2_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ {
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
frequency = pll3_clocks.PLL3_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
{
- frequency = HSI_VALUE;
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ {
+ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
+ {
frequency = CSI_VALUE;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
{
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ {
frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = 0;
+ }
break;
}
#if defined(RCC_SPI6CLKSOURCE_PIN)
@@ -2439,6 +2659,58 @@
}
}
}
+ else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
+ {
+ /* Get FDCAN clock source */
+ srcclk= __HAL_RCC_GET_FDCAN_SOURCE();
+
+ switch (srcclk)
+ {
+ case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ {
+ frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ {
+ HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ frequency = pll1_clocks.PLL1_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
+ {
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ {
+ HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ }
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ default :
+ {
+ frequency = 0;
+ break;
+ }
+ }
+ }
else
{
frequency = 0;
@@ -2668,7 +2940,7 @@
break;
default:
- pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
break;
}
diff --git a/Src/stm32h7xx_hal_rng.c b/Src/stm32h7xx_hal_rng.c
index 09aa1e8..ff1cf10 100644
--- a/Src/stm32h7xx_hal_rng.c
+++ b/Src/stm32h7xx_hal_rng.c
@@ -114,12 +114,12 @@
* @{
*/
/* Health test control register information to use in CCM algorithm */
-#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */
+#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
-#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */
-#else /*RNG_VER_3_2*/
-#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */
-#endif
+#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */
+#else /* RNG_VER_3_2 */
+#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */
+#endif /* RNG_VER_3_1 || RNG_VER_3_0 */
/**
* @}
*/
@@ -134,7 +134,6 @@
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_Exported_Functions
@@ -142,8 +141,8 @@
*/
/** @addtogroup RNG_Exported_Functions_Group1
- * @brief Initialization and configuration functions
- *
+ * @brief Initialization and configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and configuration functions #####
@@ -220,9 +219,9 @@
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
/* for best latency and to be compliant with NIST */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
-#endif
+#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
- /* Writing bits CONDRST=0*/
+ /* Writing bit CONDRST=0 */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
@@ -241,7 +240,7 @@
#else
/* Clock Error Detection Configuration */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
-#endif /* end of RNG_CR_CONDRST */
+#endif /* RNG_CR_CONDRST */
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
@@ -297,7 +296,7 @@
/* Clear Clock Error Detection bit when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST);
- /* Writing bits CONDRST=0*/
+ /* Writing bit CONDRST=0 */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
@@ -395,7 +394,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+ pRNG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -614,8 +614,8 @@
*/
/** @addtogroup RNG_Exported_Functions_Group2
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -660,6 +660,20 @@
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
+#if defined(RNG_CR_CONDRST)
+ /* Check if there is a seed error */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ /* Reset from seed error */
+ status = RNG_RecoverSeedError(hrng);
+ if (status == HAL_ERROR)
+ {
+ return status;
+ }
+ }
+#endif /* RNG_CR_CONDRST */
/* Get tick */
tickstart = HAL_GetTick();
@@ -679,8 +693,24 @@
/* Get a 32bit Random number */
hrng->RandomNumber = hrng->Instance->DR;
+#if defined(RNG_CR_CONDRST)
+ /* In case of seed error, the value available in the RNG_DR register must not
+ be used as it may not have enough entropy */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ /* Clear bit DRDY */
+ CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
+ }
+ else /* No seed error */
+ {
+ *random32bit = hrng->RandomNumber;
+ }
+#else
*random32bit = hrng->RandomNumber;
+#endif /* RNG_CR_CONDRST */
hrng->State = HAL_RNG_STATE_READY;
}
else
@@ -763,9 +793,21 @@
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_SEED;
- rngclockerror = 1U;
+ /* Check if Seed Error Current Status (SECS) is set */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ {
+ /* RNG IP performed the reset automatically (auto-reset) */
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+ else
+ {
+ /* Seed Error has not been recovered : Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ rngclockerror = 1U;
+ /* Disable the IT */
+ __HAL_RNG_DISABLE_IT(hrng);
+ }
}
else
{
@@ -787,6 +829,8 @@
/* Clear the clock error flag */
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
+
+ return;
}
/* Check RNG data ready interrupt occurred */
@@ -869,8 +913,8 @@
/** @addtogroup RNG_Exported_Functions_Group3
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -898,7 +942,7 @@
* @brief Return the RNG handle error code.
* @param hrng: pointer to a RNG_HandleTypeDef structure.
* @retval RNG Error Code
-*/
+ */
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
{
/* Return RNG Error Code */
@@ -911,6 +955,96 @@
/**
* @}
*/
+#if defined(RNG_CR_CONDRST)
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief RNG sequence to recover from a seed error
+ * @param hrng pointer to a RNG_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+ __IO uint32_t count = 0U;
+
+ /*Check if seed error current status (SECS)is set */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ {
+ /* RNG performed the reset automatically (auto-reset) */
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+ else /* Sequence to fully recover from a seed error*/
+ {
+ /* Writing bit CONDRST=1*/
+ SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+ /* Writing bit CONDRST=0*/
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+ /* Wait for conditioning reset process to be completed */
+ count = RNG_TIMEOUT_VALUE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
+ HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
+
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+
+ /* Wait for SECS to be cleared */
+ count = RNG_TIMEOUT_VALUE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
+ HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
+ }
+ /* Update the error code */
+ hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED;
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* RNG_CR_CONDRST */
#endif /* HAL_RNG_MODULE_ENABLED */
diff --git a/Src/stm32h7xx_hal_rng_ex.c b/Src/stm32h7xx_hal_rng_ex.c
index dad4322..4377a04 100644
--- a/Src/stm32h7xx_hal_rng_ex.c
+++ b/Src/stm32h7xx_hal_rng_ex.c
@@ -29,7 +29,7 @@
* @{
*/
-#if defined (RNG)
+#if defined(RNG)
/** @addtogroup RNGEx
* @brief RNG Extended HAL module driver.
@@ -37,19 +37,19 @@
*/
#ifdef HAL_RNG_MODULE_ENABLED
-#if defined (RNG_CR_CONDRST)
+#if defined(RNG_CR_CONDRST)
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup RNGEx_Private_Defines RNGEx Private Defines
* @{
*/
/* Health test control register information to use in CCM algorithm */
-#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */
+#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
-#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */
-#else /*RNG_VER_3_2*/
-#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */
-#endif
+#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */
+#else /* RNG_VER_3_2 */
+#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */
+#endif /* RNG_VER_3_1 || RNG_VER_3_0 */
/**
* @}
*/
@@ -64,7 +64,7 @@
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNGEx_Exported_Functions
@@ -72,8 +72,8 @@
*/
/** @addtogroup RNGEx_Exported_Functions_Group1
- * @brief Configuration functions
- *
+ * @brief Configuration functions
+ *
@verbatim
===============================================================================
##### Configuration and lock functions #####
@@ -95,7 +95,7 @@
* the configuration information for RNG module
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
{
uint32_t tickstart;
@@ -144,9 +144,9 @@
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
/* for best latency and to be compliant with NIST */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
-#endif
+#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
- /* Writing bits CONDRST=0*/
+ /* Writing bit CONDRST=0*/
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
tickstart = HAL_GetTick();
@@ -190,7 +190,7 @@
* the configuration information for RNG module
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
{
@@ -234,12 +234,12 @@
/**
* @brief RNG current configuration lock.
* @note This function allows to lock RNG peripheral configuration.
- * Once locked, HW RNG reset has to be perfomed prior any further
+ * Once locked, HW RNG reset has to be performed prior any further
* configuration update.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
{
HAL_StatusTypeDef status;
@@ -280,11 +280,63 @@
* @}
*/
+/** @addtogroup RNGEx_Exported_Functions_Group2
+ * @brief Recover from seed error function
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration and lock functions #####
+ ===============================================================================
+ [..] This section provide function allowing to:
+ (+) Recover from a seed error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief RNG sequence to recover from a seed error
+ * @param hrng: pointer to a RNG_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the RNG handle allocation */
+ if (hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* sequence to fully recover from a seed error */
+ status = RNG_RecoverSeedError(hrng);
+ }
+ else
+ {
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ /* Return the function status */
+ return status;
+}
+
/**
* @}
*/
-#endif /* CONDRST */
+/**
+ * @}
+ */
+
+#endif /* RNG_CR_CONDRST */
#endif /* HAL_RNG_MODULE_ENABLED */
/**
* @}
diff --git a/Src/stm32h7xx_hal_sai.c b/Src/stm32h7xx_hal_sai.c
index bdbdb62..fefb011 100644
--- a/Src/stm32h7xx_hal_sai.c
+++ b/Src/stm32h7xx_hal_sai.c
@@ -1687,7 +1687,7 @@
/* Enable SAI Tx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
- /* Wait untill FIFO is not empty */
+ /* Wait until FIFO is not empty */
while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
{
/* Check for the Timeout */
@@ -1886,7 +1886,7 @@
uint32_t cr1config = hsai->Instance->CR1;
uint32_t tmperror;
- /* SAI Fifo request interrupt occured ------------------------------------*/
+ /* SAI Fifo request interrupt occurred ------------------------------------*/
if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
{
hsai->InterruptServiceRoutine(hsai);
diff --git a/Src/stm32h7xx_hal_sd.c b/Src/stm32h7xx_hal_sd.c
index b2467ca..6bf4dcc 100644
--- a/Src/stm32h7xx_hal_sd.c
+++ b/Src/stm32h7xx_hal_sd.c
@@ -268,38 +268,42 @@
/** @addtogroup SD_Private_Defines
* @{
*/
+/* Frequencies used in the driver for clock divider calculation */
+#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */
+#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */
+/* Private macro -------------------------------------------------------------*/
+#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \
+ DLYB_SDMMC1 : DLYB_SDMMC2 )
+#elif defined (DLYB_SDMMC1)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
+#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
-#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
-#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \
- DLYB_SDMMC1 : DLYB_SDMMC2 )
-#elif defined (DLYB_SDMMC1)
-#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
-#endif
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SD_Private_Functions SD Private Functions
* @{
*/
-static uint32_t SD_InitCard (SD_HandleTypeDef *hsd);
-static uint32_t SD_PowerON (SD_HandleTypeDef *hsd);
-static uint32_t SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd);
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static void SD_PowerOFF (SD_HandleTypeDef *hsd);
-static void SD_Write_IT (SD_HandleTypeDef *hsd);
-static void SD_Read_IT (SD_HandleTypeDef *hsd);
-static uint32_t SD_HighSpeed (SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
+static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
-static uint32_t SD_UltraHighSpeed (SD_HandleTypeDef *hsd);
-static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd);
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd);
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
#endif /* USE_SD_TRANSCEIVER */
/**
* @}
@@ -311,8 +315,8 @@
*/
/** @addtogroup SD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
+ * @brief Initialization and de-initialization functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -334,11 +338,12 @@
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStatusTypeDef CardStatus;
- uint32_t speedgrade, unitsize;
+ uint32_t speedgrade;
+ uint32_t unitsize;
uint32_t tickstart;
/* Check the SD handle allocation */
- if(hsd == NULL)
+ if (hsd == NULL)
{
return HAL_ERROR;
}
@@ -351,7 +356,7 @@
assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
- if(hsd->State == HAL_SD_STATE_RESET)
+ if (hsd->State == HAL_SD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
@@ -362,7 +367,7 @@
{
hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT;
}
-#endif
+#endif /*USE_SD_TRANSCEIVER */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_SD_STATE_RESET only */
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
@@ -380,7 +385,7 @@
}
#endif /* USE_SD_TRANSCEIVER */
- if(hsd->MspInitCallback == NULL)
+ if (hsd->MspInitCallback == NULL)
{
hsd->MspInitCallback = HAL_SD_MspInit;
}
@@ -401,7 +406,7 @@
return HAL_ERROR;
}
- if( HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
+ if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
{
return HAL_ERROR;
}
@@ -425,19 +430,19 @@
}
/* Configure the bus wide */
- if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
+ if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
{
return HAL_ERROR;
}
/* Verify that SD card is ready to use after Initialization */
tickstart = HAL_GetTick();
- while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+ while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
{
- if((HAL_GetTick()-tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -475,17 +480,25 @@
/* Init Clock should be less or equal to 400Khz*/
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
- Init.ClockDiv = sdmmc_clk/(2U*400000U);
+ if (sdmmc_clk == 0U)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
+ }
+ Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
/* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
}
#elif defined (USE_SD_DIRPOL)
- /* Set Transceiver polarity */
- hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+ /* Set Transceiver polarity */
+ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
@@ -496,20 +509,12 @@
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
- sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
-
- if(sdmmc_clk != 0U)
- {
- HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
- }
- else
- {
- HAL_Delay(2U);
- }
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
@@ -518,7 +523,7 @@
/* Card initialization */
errorstate = SD_InitCard(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
@@ -527,7 +532,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -547,7 +552,7 @@
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
{
/* Check the SD handle allocation */
- if(hsd == NULL)
+ if (hsd == NULL)
{
return HAL_ERROR;
}
@@ -558,11 +563,11 @@
hsd->State = HAL_SD_STATE_BUSY;
#if (USE_SD_TRANSCEIVER != 0U)
- /* Desactivate the 1.8V Mode */
+ /* Deactivate the 1.8V Mode */
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
- if(hsd->DriveTransceiver_1_8V_Callback == NULL)
+ if (hsd->DriveTransceiver_1_8V_Callback == NULL)
{
hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
}
@@ -577,7 +582,7 @@
SD_PowerOFF(hsd);
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
- if(hsd->MspDeInitCallback == NULL)
+ if (hsd->MspDeInitCallback == NULL)
{
hsd->MspDeInitCallback = HAL_SD_MspDeInit;
}
@@ -631,8 +636,8 @@
*/
/** @addtogroup SD_Exported_Functions_Group2
- * @brief Data transfer functions
- *
+ * @brief Data transfer functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -657,26 +662,29 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count, data, dataremaining;
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -687,7 +695,7 @@
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -700,10 +708,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
@@ -717,7 +725,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -729,12 +737,12 @@
/* Poll on SDMMC flags */
dataremaining = config.DataLength;
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hsd->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
@@ -749,26 +757,26 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
/* Send stop transmission command in case of multiblock read */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -781,7 +789,7 @@
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -790,7 +798,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -799,7 +807,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -839,26 +847,29 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count, data, dataremaining;
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -869,7 +880,7 @@
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -882,10 +893,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
@@ -899,7 +910,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -911,12 +922,13 @@
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+ SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
@@ -931,7 +943,7 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -941,16 +953,16 @@
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
/* Send stop transmission command in case of multiblock write */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -963,7 +975,7 @@
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -972,7 +984,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -981,7 +993,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1022,23 +1034,24 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1052,7 +1065,7 @@
hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1065,10 +1078,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
@@ -1082,7 +1095,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1092,7 +1105,8 @@
return HAL_ERROR;
}
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_RXFIFOHF));
return HAL_OK;
}
@@ -1115,23 +1129,24 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1145,7 +1160,7 @@
hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1159,12 +1174,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
- hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
@@ -1176,7 +1191,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1187,7 +1202,8 @@
}
/* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_TXFIFOHE));
return HAL_OK;
}
@@ -1210,23 +1226,24 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1240,7 +1257,7 @@
hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1254,12 +1271,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMABASE0 = (uint32_t) pData ;
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
@@ -1273,7 +1290,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1308,23 +1325,24 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1338,7 +1356,7 @@
hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1353,13 +1371,13 @@
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMABASE0 = (uint32_t) pData ;
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
@@ -1373,7 +1391,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1409,17 +1427,17 @@
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if(end_add < start_add)
+ if (end_add < start_add)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(end_add > (hsd->SdCard.LogBlockNbr))
+ if (end_add > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1428,7 +1446,7 @@
hsd->State = HAL_SD_STATE_BUSY;
/* Check if the card command class supports erase command */
- if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1437,7 +1455,7 @@
return HAL_ERROR;
}
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1447,18 +1465,18 @@
}
/* Get start and end block for high capacity cards */
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
start_add *= 512U;
end_add *= 512U;
}
/* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD32 SD_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1469,7 +1487,7 @@
/* Send CMD33 SD_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1481,7 +1499,7 @@
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hsd->Instance, 0UL);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1511,28 +1529,28 @@
uint32_t context = hsd->Context;
/* Check for SDMMC interrupt flags */
- if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Read_IT(hsd);
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
- SDMMC_IT_RXFIFOHF);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \
+ SDMMC_IT_RXFIFOHF);
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
- if((context & SD_CONTEXT_IT) != 0U)
+ if ((context & SD_CONTEXT_IT) != 0U)
{
- if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -1548,7 +1566,7 @@
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
- if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->RxCpltCallback(hsd);
@@ -1565,17 +1583,17 @@
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- else if((context & SD_CONTEXT_DMA) != 0U)
+ else if ((context & SD_CONTEXT_DMA) != 0U)
{
hsd->Instance->DLEN = 0;
hsd->Instance->DCTRL = 0;
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
- if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -1588,7 +1606,7 @@
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
- if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
@@ -1596,7 +1614,7 @@
HAL_SD_TxCpltCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
- if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->RxCpltCallback(hsd);
@@ -1611,27 +1629,28 @@
}
}
- else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Write_IT(hsd);
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR |
+ SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
}
@@ -1640,17 +1659,17 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Disable all interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
- if((context & SD_CONTEXT_IT) != 0U)
+ if ((context & SD_CONTEXT_IT) != 0U)
{
/* Set the SD state to ready to be able to start again the process */
hsd->State = HAL_SD_STATE_READY;
@@ -1661,9 +1680,9 @@
HAL_SD_ErrorCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
- else if((context & SD_CONTEXT_DMA) != 0U)
+ else if ((context & SD_CONTEXT_DMA) != 0U)
{
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Disable Internal DMA */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
@@ -1684,13 +1703,13 @@
}
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
- if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
+ if (READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
{
/* Current buffer is buffer0, Transfer complete for buffer1 */
- if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->Write_DMADblBuf1CpltCallback(hsd);
@@ -1710,7 +1729,7 @@
else /* SD_DMA_BUFFER1 */
{
/* Current buffer is buffer1, Transfer complete for buffer0 */
- if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->Write_DMADblBuf0CpltCallback(hsd);
@@ -1745,11 +1764,11 @@
}
/**
-* @brief Return the SD error code
-* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
+ * @brief Return the SD error code
+ * @param hsd : Pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
-* @retval SD Error Code
-*/
+ * @retval SD Error Code
+ */
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
{
return hsd->ErrorCode;
@@ -1851,11 +1870,12 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+ pSD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
@@ -1865,64 +1885,64 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SD_TX_CPLT_CB_ID :
- hsd->TxCpltCallback = pCallback;
- break;
- case HAL_SD_RX_CPLT_CB_ID :
- hsd->RxCpltCallback = pCallback;
- break;
- case HAL_SD_ERROR_CB_ID :
- hsd->ErrorCallback = pCallback;
- break;
- case HAL_SD_ABORT_CB_ID :
- hsd->AbortCpltCallback = pCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Read_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Read_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Write_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Write_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = pCallback;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = pCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = pCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = pCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = pCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Read_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Read_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Write_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Write_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = pCallback;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1963,64 +1983,64 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SD_TX_CPLT_CB_ID :
- hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
- break;
- case HAL_SD_RX_CPLT_CB_ID :
- hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
- break;
- case HAL_SD_ERROR_CB_ID :
- hsd->ErrorCallback = HAL_SD_ErrorCallback;
- break;
- case HAL_SD_ABORT_CB_ID :
- hsd->AbortCpltCallback = HAL_SD_AbortCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback;
- break;
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = HAL_SD_MspInit;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = HAL_SD_MspDeInit;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = HAL_SD_MspInit;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = HAL_SD_MspDeInit;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -2048,7 +2068,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
@@ -2058,7 +2078,7 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->DriveTransceiver_1_8V_Callback = pCallback;
}
@@ -2088,7 +2108,7 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
}
@@ -2112,8 +2132,8 @@
*/
/** @addtogroup SD_Exported_Functions_Group3
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -2195,7 +2215,7 @@
pCSD->Reserved2 = 0U; /*!< Reserved */
- if(hsd->SdCard.CardType == CARD_SDSC)
+ if (hsd->SdCard.CardType == CARD_SDSC)
{
pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
@@ -2213,10 +2233,10 @@
hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
hsd->SdCard.LogBlockSize = 512U;
}
- else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
+ else if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
{
/* Byte 7 */
pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
@@ -2247,7 +2267,7 @@
pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
- pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+ pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
@@ -2265,7 +2285,7 @@
pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
- pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+ pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
@@ -2288,7 +2308,7 @@
HAL_StatusTypeDef status = HAL_OK;
errorstate = SD_SendSDStatus(hsd, sd_status);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2326,7 +2346,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2374,6 +2394,7 @@
{
SDMMC_InitTypeDef Init;
uint32_t errorstate;
+ uint32_t sdmmc_clk;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@@ -2382,19 +2403,19 @@
/* Change State */
hsd->State = HAL_SD_STATE_BUSY;
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
- if(WideMode == SDMMC_BUS_WIDE_8B)
+ if (WideMode == SDMMC_BUS_WIDE_8B)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
- else if(WideMode == SDMMC_BUS_WIDE_4B)
+ else if (WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SD_WideBus_Enable(hsd);
hsd->ErrorCode |= errorstate;
}
- else if(WideMode == SDMMC_BUS_WIDE_1B)
+ else if (WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SD_WideBus_Disable(hsd);
@@ -2412,7 +2433,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2420,39 +2441,94 @@
}
else
{
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hsd->Init.ClockEdge;
- Init.ClockPowerSave = hsd->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+ if (sdmmc_clk != 0U)
+ {
+ /* Configure the SDMMC peripheral */
+ Init.ClockEdge = hsd->Init.ClockEdge;
+ Init.ClockPowerSave = hsd->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
- /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
- if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV)
- {
- Init.ClockDiv = hsd->Init.ClockDiv;
- }
- else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
- {
- /* UltraHigh speed SD card,user Clock div */
- Init.ClockDiv = hsd->Init.ClockDiv;
- }
- else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
- {
- /* High speed SD card, Max Frequency = 50Mhz */
- Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
+ /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
+ if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ {
+ /* UltraHigh speed SD card,user Clock div */
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ {
+ /* High speed SD card, Max Frequency = 50Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+ else
+ {
+ /* No High speed SD card, Max Frequency = 25Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+#endif /* USE_SD_TRANSCEIVER */
+
+ (void)SDMMC_Init(hsd->Instance, Init);
}
else
{
- /* No High speed SD card, Max Frequency = 25Mhz */
- Init.ClockDiv = SDMMC_NSpeed_CLK_DIV;
+ hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER;
+ status = HAL_ERROR;
}
-
- (void)SDMMC_Init(hsd->Instance, Init);
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2494,7 +2570,7 @@
{
switch (SpeedMode)
{
- case SDMMC_SPEED_MODE_AUTO:
+ case SDMMC_SPEED_MODE_AUTO:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
@@ -2525,7 +2601,7 @@
}
break;
}
- case SDMMC_SPEED_MODE_ULTRA:
+ case SDMMC_SPEED_MODE_ULTRA:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
@@ -2545,7 +2621,7 @@
}
break;
}
- case SDMMC_SPEED_MODE_DDR:
+ case SDMMC_SPEED_MODE_DDR:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
@@ -2565,11 +2641,11 @@
}
break;
}
- case SDMMC_SPEED_MODE_HIGH:
+ case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2585,23 +2661,23 @@
}
break;
}
- case SDMMC_SPEED_MODE_DEFAULT:
- break;
- default:
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- status = HAL_ERROR;
- break;
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
}
}
else
{
switch (SpeedMode)
{
- case SDMMC_SPEED_MODE_AUTO:
+ case SDMMC_SPEED_MODE_AUTO:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2616,11 +2692,11 @@
}
break;
}
- case SDMMC_SPEED_MODE_HIGH:
+ case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2636,23 +2712,23 @@
}
break;
}
- case SDMMC_SPEED_MODE_DEFAULT:
- break;
- case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
- default:
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- status = HAL_ERROR;
- break;
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
}
}
#else
switch (SpeedMode)
{
- case SDMMC_SPEED_MODE_AUTO:
+ case SDMMC_SPEED_MODE_AUTO:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2667,11 +2743,11 @@
}
break;
}
- case SDMMC_SPEED_MODE_HIGH:
+ case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2687,13 +2763,13 @@
}
break;
}
- case SDMMC_SPEED_MODE_DEFAULT:
- break;
- case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
- default:
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- status = HAL_ERROR;
- break;
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
}
#endif /* USE_SD_TRANSCEIVER */
@@ -2711,7 +2787,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2736,7 +2812,7 @@
uint32_t resp1 = 0;
errorstate = SD_SendStatus(hsd, &resp1);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
}
@@ -2757,8 +2833,8 @@
HAL_SD_CardStateTypeDef CardState;
/* DIsable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
@@ -2772,11 +2848,11 @@
hsd->Context = SD_CONTEXT_NONE;
CardState = HAL_SD_GetCardState(hsd);
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2794,8 +2870,8 @@
HAL_SD_CardStateTypeDef CardState;
/* Disable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* If IDMA Context, disable Internal DMA */
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
@@ -2806,12 +2882,12 @@
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2853,17 +2929,17 @@
uint16_t sd_rca = 1U;
/* Check the power State */
- if(SDMMC_GetPowerState(hsd->Instance) == 0U)
+ if (SDMMC_GetPowerState(hsd->Instance) == 0U)
{
/* Power off */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2877,24 +2953,24 @@
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Get the SD card RCA */
hsd->SdCard.RelCardAdd = sd_rca;
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2919,7 +2995,7 @@
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2938,7 +3014,8 @@
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
__IO uint32_t count = 0U;
- uint32_t response = 0U, validvoltage = 0U;
+ uint32_t response = 0U;
+ uint32_t validvoltage = 0U;
uint32_t errorstate;
#if (USE_SD_TRANSCEIVER != 0U)
uint32_t tickstart = HAL_GetTick();
@@ -2946,19 +3023,19 @@
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->SdCard.CardVersion = CARD_V1_X;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2969,29 +3046,30 @@
hsd->SdCard.CardVersion = CARD_V2_X;
}
- if( hsd->SdCard.CardVersion == CARD_V2_X)
+ if (hsd->SdCard.CardVersion == CARD_V2_X)
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
}
/* SD CARD */
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+ while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY |
+ SD_SWITCH_1_8V_CAPACITY);
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3005,18 +3083,18 @@
count++;
}
- if(count >= SDMMC_MAX_VOLT_TRIAL)
+ if (count >= SDMMC_MAX_VOLT_TRIAL)
{
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
- if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
- if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
+ if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
{
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
@@ -3025,15 +3103,15 @@
/* Send CMD11 to switch 1.8V mode */
errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Check to CKSTOP */
- while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
+ while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
{
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3043,7 +3121,7 @@
hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
/* Check to BusyD0 */
- if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
+ if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
{
/* Error when activate Voltage Switch in SDMMC Peripheral */
return SDMMC_ERROR_UNSUPPORTED_FEATURE;
@@ -3061,9 +3139,9 @@
hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
/* Check VSWEND Flag */
- while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
+ while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
{
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3073,7 +3151,7 @@
hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
/* Check BusyD0 status */
- if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
+ if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
{
/* Error when enabling 1.8V mode */
return HAL_SD_ERROR_INVALID_VOLTRANGE;
@@ -3121,14 +3199,14 @@
uint32_t *pData = pSDstatus;
/* Check SD response */
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Set block size for card if it is not equal to current block size for card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
@@ -3136,7 +3214,7 @@
/* Send CMD55 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
@@ -3153,39 +3231,39 @@
/* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
/* Get status data */
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
*pData = SDMMC_ReadFIFO(hsd->Instance);
pData++;
}
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
return HAL_SD_ERROR_RX_OVERRUN;
}
@@ -3199,7 +3277,7 @@
*pData = SDMMC_ReadFIFO(hsd->Instance);
pData++;
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3222,14 +3300,14 @@
{
uint32_t errorstate;
- if(pCardStatus == NULL)
+ if (pCardStatus == NULL)
{
return HAL_SD_ERROR_PARAM;
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3250,31 +3328,31 @@
uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* If requested card supports wide bus operation */
- if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3297,31 +3375,31 @@
uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* If requested card supports 1 bit mode operation */
- if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3352,14 +3430,14 @@
/* Set Block Size To 8 Bytes */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3374,14 +3452,15 @@
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
errorstate = SDMMC_CmdSendSCR(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
- if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
+ if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
{
tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
@@ -3389,25 +3468,25 @@
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
return HAL_SD_ERROR_DATA_TIMEOUT;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
@@ -3419,10 +3498,10 @@
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
- *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+ *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
scr++;
- *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+ *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
}
@@ -3438,15 +3517,16 @@
*/
static void SD_Read_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count, data;
- uint8_t* tmp;
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
tmp = hsd->pRxBuffPtr;
if (hsd->RxXferSize >= 32U)
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hsd->Instance);
*tmp = (uint8_t)(data & 0xFFU);
@@ -3472,15 +3552,16 @@
*/
static void SD_Write_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count, data;
- uint8_t* tmp;
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
tmp = hsd->pTxBuffPtr;
if (hsd->TxXferSize >= 32U)
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tmp);
tmp++;
@@ -3511,16 +3592,17 @@
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
+ uint32_t count;
+ uint32_t loop = 0 ;
uint32_t Timeout = HAL_GetTick();
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
@@ -3542,27 +3624,28 @@
(void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
- errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
+ errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN);
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
for (count = 0U; count < 8U; count++)
{
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
}
loop ++;
}
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_SD_ERROR_TIMEOUT;
}
}
@@ -3598,7 +3681,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode HS is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3622,16 +3705,17 @@
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
+ uint32_t count;
+ uint32_t loop = 0 ;
uint32_t Timeout = HAL_GetTick();
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
@@ -3650,32 +3734,33 @@
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+ if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
for (count = 0U; count < 8U; count++)
{
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
}
loop ++;
}
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_SD_ERROR_TIMEOUT;
}
}
@@ -3711,7 +3796,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode HS is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3725,7 +3810,7 @@
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
/* Enable DelayBlock Peripheral */
/* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
- MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1);
+ MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1);
if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
@@ -3750,16 +3835,17 @@
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
+ uint32_t count;
+ uint32_t loop = 0 ;
uint32_t Timeout = HAL_GetTick();
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
@@ -3778,32 +3864,33 @@
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+ if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
for (count = 0U; count < 8U; count++)
{
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
}
loop ++;
}
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_SD_ERROR_TIMEOUT;
}
}
@@ -3839,7 +3926,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3853,7 +3940,7 @@
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
/* Enable DelayBlock Peripheral */
/* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */
- MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_0);
+ MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0);
if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
diff --git a/Src/stm32h7xx_hal_sd_ex.c b/Src/stm32h7xx_hal_sd_ex.c
index d18122d..67124cb 100644
--- a/Src/stm32h7xx_hal_sd_ex.c
+++ b/Src/stm32h7xx_hal_sd_ex.c
@@ -14,7 +14,8 @@
[..]
The SD Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
- (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
+ (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer()
+ and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
@@ -57,8 +58,8 @@
*/
/** @addtogroup SDEx_Exported_Functions_Group1
- * @brief Multibuffer functions
- *
+ * @brief Multibuffer functions
+ *
@verbatim
==============================================================================
##### Multibuffer functions #####
@@ -74,18 +75,19 @@
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hsd: SD handle
- * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
+ * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data
+ * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1,
+ uint32_t BufferSize)
{
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
- hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0;
- hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1;
- hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize);
+ hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0;
+ hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1;
+ hsd->Instance->IDMABSIZE = (uint32_t)(BLOCKSIZE * BufferSize);
return HAL_OK;
}
@@ -97,7 +99,8 @@
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hsd: SD handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
@@ -107,12 +110,13 @@
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t add = BlockAdd;
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -135,7 +139,7 @@
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_BUSY;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -151,7 +155,7 @@
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -160,14 +164,15 @@
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_IT_IDMABTC));
return HAL_OK;
}
@@ -179,23 +184,25 @@
}
/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hsd: SD handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t add = BlockAdd;
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -216,7 +223,7 @@
hsd->State = HAL_SD_STATE_BUSY;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -230,7 +237,7 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -239,14 +246,15 @@
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_IT_IDMABTC));
return HAL_OK;
}
@@ -268,9 +276,10 @@
* transfer use BUFFER0.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
+HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer)
{
- if(Buffer == SD_DMA_BUFFER0)
+ if (Buffer == SD_DMA_BUFFER0)
{
/* change the buffer0 address */
hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
@@ -303,4 +312,8 @@
* @}
*/
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_sdram.c b/Src/stm32h7xx_hal_sdram.c
index 8d71bc2..47c34a5 100644
--- a/Src/stm32h7xx_hal_sdram.c
+++ b/Src/stm32h7xx_hal_sdram.c
@@ -126,20 +126,14 @@
* @{
*/
-/**
- @cond 0
- */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void SDRAM_DMACplt (MDMA_HandleTypeDef *hmdma);
+static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
-static void SDRAM_DMAError (MDMA_HandleTypeDef *hmdma);
-/**
- @endcond
- */
+static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma);
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
@@ -181,7 +175,7 @@
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
- if(hsdram->MspInitCallback == NULL)
+ if (hsdram->MspInitCallback == NULL)
{
hsdram->MspInitCallback = HAL_SDRAM_MspInit;
}
@@ -194,7 +188,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
/* Initialize the SDRAM controller state */
@@ -223,7 +217,7 @@
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
{
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
- if(hsdram->MspDeInitCallback == NULL)
+ if (hsdram->MspDeInitCallback == NULL)
{
hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
}
@@ -233,7 +227,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspDeInit(hsdram);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/* Configure the SDRAM registers with their reset values */
(void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
@@ -284,7 +278,7 @@
* @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
-*/
+ */
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
{
/* Check SDRAM interrupt Rising edge flag */
@@ -295,7 +289,7 @@
hsdram->RefreshErrorCallback(hsdram);
#else
HAL_SDRAM_RefreshErrorCallback(hsdram);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/* Clear SDRAM refresh error interrupt pending bit */
__FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
@@ -376,11 +370,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
- uint8_t * pdestbuff = pDstBuffer;
+ uint8_t *pdestbuff = pDstBuffer;
HAL_SDRAM_StateTypeDef state = hsdram->State;
/* Check the SDRAM controller state */
@@ -427,12 +422,13 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
- uint8_t * psrcbuff = pSrcBuffer;
-
+ uint8_t *psrcbuff = pSrcBuffer;
+
/* Check the SDRAM controller state */
if (hsdram->State == HAL_SDRAM_STATE_BUSY)
{
@@ -456,7 +452,7 @@
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
}
@@ -477,7 +473,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *pSdramAddress = pAddress;
@@ -498,7 +495,7 @@
hsdram->State = HAL_SDRAM_STATE_BUSY;
/* Read data from memory */
- for (size = BufferSize; size >= 2U ; size-=2U)
+ for (size = BufferSize; size >= 2U ; size -= 2U)
{
*pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
pdestbuff++;
@@ -508,7 +505,7 @@
}
/* Read last 16-bits if size is not 32-bits multiple */
- if ((BufferSize % 2U)!= 0U)
+ if ((BufferSize % 2U) != 0U)
{
*pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
}
@@ -536,12 +533,13 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psdramaddress = pAddress;
- uint16_t * psrcbuff = pSrcBuffer;
-
+ uint16_t *psrcbuff = pSrcBuffer;
+
/* Check the SDRAM controller state */
if (hsdram->State == HAL_SDRAM_STATE_BUSY)
{
@@ -554,9 +552,9 @@
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
-
+
/* Write data to memory */
- for (size = BufferSize; size >= 2U ; size-=2U)
+ for (size = BufferSize; size >= 2U ; size -= 2U)
{
*psdramaddress = (uint32_t)(*psrcbuff);
psrcbuff++;
@@ -566,14 +564,14 @@
}
/* Write last 16-bits if size is not 32-bits multiple */
- if ((BufferSize % 2U)!= 0U)
+ if ((BufferSize % 2U) != 0U)
{
*psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
}
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
}
@@ -594,11 +592,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
- uint32_t * pdestbuff = pDstBuffer;
+ uint32_t *pdestbuff = pDstBuffer;
HAL_SDRAM_StateTypeDef state = hsdram->State;
/* Check the SDRAM controller state */
@@ -645,11 +644,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *pSdramAddress = pAddress;
- uint32_t * psrcbuff = pSrcBuffer;
+ uint32_t *psrcbuff = pSrcBuffer;
/* Check the SDRAM controller state */
if (hsdram->State == HAL_SDRAM_STATE_BUSY)
@@ -674,7 +674,7 @@
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
}
@@ -695,7 +695,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
HAL_SDRAM_StateTypeDef state = hsdram->State;
@@ -703,7 +704,7 @@
/* Check the SDRAM controller state */
if (state == HAL_SDRAM_STATE_BUSY)
{
- return HAL_BUSY;
+ status = HAL_BUSY;
}
else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
@@ -724,15 +725,15 @@
}
hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
- /* Enable the DMA Stream */
- status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
+ /* Enable the DMA Stream */
+ status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -747,14 +748,15 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
/* Check the SDRAM controller state */
if (hsdram->State == HAL_SDRAM_STATE_BUSY)
{
- return HAL_BUSY;
+ status = HAL_BUSY;
}
else if (hsdram->State == HAL_SDRAM_STATE_READY)
{
@@ -768,15 +770,15 @@
hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
- /* Enable the DMA Stream */
- status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
+ /* Enable the DMA Stream */
+ status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -795,53 +797,54 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+ pSDRAM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SDRAM_StateTypeDef state;
-
- if(pCallback == NULL)
+
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hsdram);
-
+
state = hsdram->State;
- if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SDRAM_MSP_INIT_CB_ID :
- hsdram->MspInitCallback = pCallback;
- break;
- case HAL_SDRAM_MSP_DEINIT_CB_ID :
- hsdram->MspDeInitCallback = pCallback;
- break;
- case HAL_SDRAM_REFRESH_ERR_CB_ID :
- hsdram->RefreshErrorCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_REFRESH_ERR_CB_ID :
+ hsdram->RefreshErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hsdram->State == HAL_SDRAM_STATE_RESET)
+ else if (hsdram->State == HAL_SDRAM_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_SDRAM_MSP_INIT_CB_ID :
- hsdram->MspInitCallback = pCallback;
- break;
- case HAL_SDRAM_MSP_DEINIT_CB_ID :
- hsdram->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -868,54 +871,54 @@
* @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SDRAM_StateTypeDef state;
-
+
/* Process locked */
__HAL_LOCK(hsdram);
state = hsdram->State;
- if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SDRAM_MSP_INIT_CB_ID :
- hsdram->MspInitCallback = HAL_SDRAM_MspInit;
- break;
- case HAL_SDRAM_MSP_DEINIT_CB_ID :
- hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
- break;
- case HAL_SDRAM_REFRESH_ERR_CB_ID :
- hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
- break;
- case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
- hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
- break;
- case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
- hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ break;
+ case HAL_SDRAM_REFRESH_ERR_CB_ID :
+ hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+ hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+ hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hsdram->State == HAL_SDRAM_STATE_RESET)
+ else if (hsdram->State == HAL_SDRAM_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_SDRAM_MSP_INIT_CB_ID :
- hsdram->MspInitCallback = HAL_SDRAM_MspInit;
- break;
- case HAL_SDRAM_MSP_DEINIT_CB_ID :
- hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -940,12 +943,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+ pSDRAM_DmaCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SDRAM_StateTypeDef state;
-
- if(pCallback == NULL)
+
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -954,20 +958,20 @@
__HAL_LOCK(hsdram);
state = hsdram->State;
- if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
- hsdram->DmaXferCpltCallback = pCallback;
- break;
- case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
- hsdram->DmaXferErrorCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+ hsdram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+ hsdram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -980,15 +984,15 @@
__HAL_UNLOCK(hsdram);
return status;
}
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### SDRAM Control functions #####
@@ -1042,7 +1046,7 @@
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
{
HAL_SDRAM_StateTypeDef state = hsdram->State;
-
+
/* Check the SDRAM controller state */
if (state == HAL_SDRAM_STATE_BUSY)
{
@@ -1075,16 +1079,17 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
+ uint32_t Timeout)
{
HAL_SDRAM_StateTypeDef state = hsdram->State;
-
+
/* Check the SDRAM controller state */
if (state == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
+ else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
{
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
@@ -1193,8 +1198,8 @@
*/
/** @defgroup SDRAM_Exported_Functions_Group4 State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### SDRAM State functions #####
@@ -1227,16 +1232,13 @@
*/
/**
- @cond 0
- */
-/**
* @brief MDMA SDRAM process complete callback.
* @param hmdma : MDMA handle
* @retval None
*/
static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
{
- SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent);
+ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
/* Disable the MDMA channel */
__HAL_MDMA_DISABLE(hmdma);
@@ -1248,7 +1250,7 @@
hsdram->DmaXferCpltCallback(hmdma);
#else
HAL_SDRAM_DMA_XferCpltCallback(hmdma);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
/**
@@ -1258,7 +1260,7 @@
*/
static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
{
- SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent);
+ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
/* Disable the MDMA channel */
__HAL_MDMA_DISABLE(hmdma);
@@ -1270,7 +1272,7 @@
hsdram->DmaXferCpltCallback(hmdma);
#else
HAL_SDRAM_DMA_XferCpltCallback(hmdma);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
/**
@@ -1280,7 +1282,7 @@
*/
static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma)
{
- SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent);
+ SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
/* Disable the MDMA channel */
__HAL_MDMA_DISABLE(hmdma);
@@ -1292,11 +1294,8 @@
hsdram->DmaXferErrorCallback(hmdma);
#else
HAL_SDRAM_DMA_XferErrorCallback(hmdma);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
-/**
- @endcond
- */
/**
* @}
diff --git a/Src/stm32h7xx_hal_smartcard.c b/Src/stm32h7xx_hal_smartcard.c
index 2440595..9004803 100644
--- a/Src/stm32h7xx_hal_smartcard.c
+++ b/Src/stm32h7xx_hal_smartcard.c
@@ -35,7 +35,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@@ -198,23 +199,24 @@
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
- USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
+ USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
-#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
@@ -483,7 +485,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
- HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -618,43 +621,45 @@
switch (CallbackID)
{
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_SMARTCARD_ERROR_CB_ID :
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback*/
break;
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
case HAL_SMARTCARD_MSPINIT_CB_ID :
- hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
- hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -766,7 +771,8 @@
(##) HAL_SMARTCARD_AbortTransmit_IT()
(##) HAL_SMARTCARD_AbortReceive_IT()
- (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+ a set of Abort Complete Callbacks are provided:
(##) HAL_SMARTCARD_AbortCpltCallback()
(##) HAL_SMARTCARD_AbortTransmitCpltCallback()
(##) HAL_SMARTCARD_AbortReceiveCpltCallback()
@@ -774,13 +780,17 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer,
+ Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+ mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -828,7 +838,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -855,8 +865,8 @@
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
- if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
- Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+ tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -864,14 +874,14 @@
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
@@ -1001,7 +1011,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -1158,7 +1168,7 @@
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
@@ -1311,7 +1321,8 @@
*/
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
@@ -1373,8 +1384,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1465,7 +1476,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
@@ -1505,8 +1517,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1533,14 +1545,16 @@
{
uint32_t abortcplt = 1U;
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
- /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+ DMA Abort complete callbacks should be initialised before any call
+ to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hsmartcard->hdmatx != NULL)
{
@@ -1634,8 +1648,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1767,7 +1781,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
@@ -1806,8 +1821,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1832,8 +1847,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -2304,14 +2319,18 @@
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Init the SMARTCARD Callback settings */
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
+ RxFifoFullCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
+ TxFifoEmptyCallback */
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -2327,7 +2346,7 @@
uint32_t tmpreg;
SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
PLL2_ClocksTypeDef pll2_clocks;
PLL3_ClocksTypeDef pll3_clocks;
uint32_t pclk;
@@ -2354,8 +2373,8 @@
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode;
+ tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
+ ((uint32_t)hsmartcard->Init.WordLength));
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -2403,35 +2422,44 @@
{
case SMARTCARD_CLOCKSOURCE_D2PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_D2PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PLL2Q:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PLL3Q:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
- tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) /
+ SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
}
else
{
- tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
}
break;
case SMARTCARD_CLOCKSOURCE_CSI:
- tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
- tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
default:
ret = HAL_ERROR;
@@ -2592,7 +2620,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -2786,8 +2815,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2835,8 +2864,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2897,8 +2926,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -3004,14 +3033,14 @@
/* Disable the Peripheral first to update mode */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* In case of TX only mode, if NACK is enabled, receiver block has been enabled
for Transmit phase. Disable this receiver block. */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
- || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
/* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
__HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
diff --git a/Src/stm32h7xx_hal_smartcard_ex.c b/Src/stm32h7xx_hal_smartcard_ex.c
index 7043575..35505d8 100644
--- a/Src/stm32h7xx_hal_smartcard_ex.c
+++ b/Src/stm32h7xx_hal_smartcard_ex.c
@@ -458,8 +458,8 @@
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
{
@@ -472,8 +472,10 @@
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
- hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+ (uint16_t)denominator[tx_fifo_threshold];
+ hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
diff --git a/Src/stm32h7xx_hal_smbus.c b/Src/stm32h7xx_hal_smbus.c
index 6840ad9..3d0c843 100644
--- a/Src/stm32h7xx_hal_smbus.c
+++ b/Src/stm32h7xx_hal_smbus.c
@@ -203,7 +203,8 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout);
static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
@@ -214,7 +215,8 @@
static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request);
/**
* @}
*/
@@ -226,8 +228,8 @@
*/
/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -579,7 +581,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+ pSMBUS_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -858,8 +861,8 @@
*/
/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -911,7 +914,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
@@ -950,7 +954,8 @@
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
}
else
{
@@ -1010,7 +1015,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
@@ -1050,7 +1056,8 @@
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
}
else
{
@@ -1165,7 +1172,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -1213,7 +1221,8 @@
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
}
else
{
@@ -1259,7 +1268,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -1417,7 +1427,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1526,8 +1537,7 @@
/* Increment Trials */
SMBUS_Trials++;
- }
- while (SMBUS_Trials < Trials);
+ } while (SMBUS_Trials < Trials);
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1549,8 +1559,8 @@
*/
/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/**
* @brief Handle SMBUS event interrupt request.
@@ -1566,7 +1576,12 @@
uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
@@ -1585,7 +1600,12 @@
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
@@ -1604,7 +1624,12 @@
}
/* SMBUS in mode Listener Only --------------------------------------------------*/
- if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
@@ -1744,8 +1769,8 @@
*/
/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -1771,11 +1796,11 @@
}
/**
-* @brief Return the SMBUS error code.
+ * @brief Return the SMBUS error code.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
-* @retval SMBUS Error Code
-*/
+ * @retval SMBUS Error Code
+ */
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
{
return hsmbus->ErrorCode;
@@ -1790,7 +1815,7 @@
*/
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- * @brief Data transfers Private functions
+ * @brief Data transfers Private functions
* @{
*/
@@ -1854,7 +1879,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* REenable the selected SMBUS peripheral */
+ /* Re-enable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
/* Call the corresponding callback to inform upper layer of End of Transfer */
@@ -1941,7 +1966,8 @@
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
@@ -2155,7 +2181,8 @@
HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
- else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
+ else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
+ (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
{
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
@@ -2210,7 +2237,8 @@
{
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
@@ -2554,7 +2582,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2603,7 +2632,8 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2611,12 +2641,16 @@
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
/* update CR2 register */
- MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ MODIFY_REG(hsmbus->Instance->CR2,
+ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
- * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
* @param hsmbus SMBUS handle.
* @retval None
*/
diff --git a/Src/stm32h7xx_hal_spdifrx.c b/Src/stm32h7xx_hal_spdifrx.c
index 1f78727..e0536b6 100644
--- a/Src/stm32h7xx_hal_spdifrx.c
+++ b/Src/stm32h7xx_hal_spdifrx.c
@@ -93,7 +93,7 @@
The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback.
+ Use HAL_SPDIFRX_RegisterCallback() function to register an interrupt callback.
The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks:
(+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback.
diff --git a/Src/stm32h7xx_hal_spi.c b/Src/stm32h7xx_hal_spi.c
index 90efc7a..95f6c25 100644
--- a/Src/stm32h7xx_hal_spi.c
+++ b/Src/stm32h7xx_hal_spi.c
@@ -146,6 +146,7 @@
* @{
*/
#define SPI_DEFAULT_TIMEOUT 100UL
+#define MAX_FIFO_LENGTH 16UL
/**
* @}
*/
@@ -233,7 +234,11 @@
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
+#if (USE_SPI_CRC != 0UL)
+ uint32_t crc_length;
+#else
uint32_t crc_length = 0UL;
+#endif
uint32_t packet_length;
/* Check the SPI handle allocation */
@@ -310,6 +315,10 @@
return HAL_ERROR;
}
}
+ else
+ {
+ crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos;
+ }
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
@@ -350,7 +359,9 @@
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit, CRC calculation state, CRC Length */
- if ((hspi->Init.NSS == SPI_NSS_SOFT) && (hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW))
+ /* SPIx NSS Software Management Configuration */
+ if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
+ ((hspi->Init.Mode == SPI_MODE_SLAVE) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
}
@@ -1327,10 +1338,10 @@
{
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
+
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
return HAL_ERROR;
@@ -1698,7 +1709,11 @@
{
HAL_SPI_StateTypeDef tmp_state;
HAL_StatusTypeDef errorcode = HAL_OK;
-
+ uint32_t max_fifo_length = 0UL;
+ uint32_t tmp_TxXferCount;
+ #if defined (__GNUC__)
+ __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
+ #endif /* __GNUC__ */
uint32_t tmp_mode;
/* Check Direction parameter */
@@ -1740,6 +1755,7 @@
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
+ tmp_TxXferCount = hspi->TxXferCount;
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
@@ -1764,8 +1780,83 @@
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
- /* Enable EOT, RXP, TXP, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
+ /* Fill in the TxFIFO */
+ while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL))
+ {
+ if (max_fifo_length < MAX_FIFO_LENGTH)
+ {
+ /* Transmit data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount--;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ /* Transmit data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)4UL;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+#if defined (__GNUC__)
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+#else
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ tmp_TxXferCount = hspi->TxXferCount;
+ }
+ }
+
+ max_fifo_length++;
+ }
+ else
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+ }
+
+ /* Enable EOT, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
if (hspi->Init.Mode == SPI_MODE_MASTER)
{
@@ -2890,11 +2981,11 @@
{
HAL_SPI_TxCpltCallback(hspi);
}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
else
{
- /* end of the appropriate call */
+ /* End of the appropriate call */
}
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
@@ -3464,7 +3555,7 @@
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
}
-#else
+#else
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
#endif /* USE_HSPI_RELOAD_TRANSFER */
@@ -3507,7 +3598,7 @@
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
}
-#else
+#else
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
#endif /* USE_HSPI_RELOAD_TRANSFER */
@@ -3544,7 +3635,7 @@
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
}
-#else
+#else
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
#endif /* USE_HSPI_RELOAD_TRANSFER */
@@ -3581,7 +3672,7 @@
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
}
-#else
+#else
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
#endif /* USE_HSPI_RELOAD_TRANSFER */
@@ -3623,7 +3714,7 @@
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
}
-#else
+#else
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
#endif /* USE_HSPI_RELOAD_TRANSFER */
@@ -3659,7 +3750,7 @@
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
}
-#else
+#else
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
#endif /* USE_HSPI_RELOAD_TRANSFER */
diff --git a/Src/stm32h7xx_hal_sram.c b/Src/stm32h7xx_hal_sram.c
index 6da1757..daf8e3f 100644
--- a/Src/stm32h7xx_hal_sram.c
+++ b/Src/stm32h7xx_hal_sram.c
@@ -127,20 +127,14 @@
* @{
*/
-/**
- @cond 0
- */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void SRAM_DMACplt (MDMA_HandleTypeDef *hmdma);
+static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
-static void SRAM_DMAError (MDMA_HandleTypeDef *hmdma);
-/**
- @endcond
- */
+static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma);
/* Exported functions --------------------------------------------------------*/
@@ -170,7 +164,8 @@
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if (hsram == NULL)
@@ -184,7 +179,7 @@
hsram->Lock = HAL_UNLOCKED;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- if(hsram->MspInitCallback == NULL)
+ if (hsram->MspInitCallback == NULL)
{
hsram->MspInitCallback = HAL_SRAM_MspInit;
}
@@ -196,7 +191,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/* Initialize SRAM control Interface */
@@ -206,7 +201,8 @@
(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
- (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+ (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
+ hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
@@ -229,7 +225,7 @@
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- if(hsram->MspDeInitCallback == NULL)
+ if (hsram->MspDeInitCallback == NULL)
{
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
}
@@ -239,7 +235,7 @@
#else
/* De-Initialize the low level hardware (MSP) */
HAL_SRAM_MspDeInit(hsram);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/* Configure the SRAM registers with their reset values */
(void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
@@ -344,11 +340,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
- uint8_t * pdestbuff = pDstBuffer;
+ uint8_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@@ -391,11 +388,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
- uint8_t * psrcbuff = pSrcBuffer;
+ uint8_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@@ -437,7 +435,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
@@ -454,11 +453,11 @@
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
- /* Check if the size is a 32-bits mulitple */
+ /* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Read data from memory */
- for (size = BufferSize; size != limit; size-=2U)
+ for (size = BufferSize; size != limit; size -= 2U)
{
*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
pdestbuff++;
@@ -496,11 +495,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
- uint16_t * psrcbuff = pSrcBuffer;
+ uint16_t *psrcbuff = pSrcBuffer;
uint8_t limit;
/* Check the SRAM controller state */
@@ -512,11 +512,11 @@
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
- /* Check if the size is a 32-bits mulitple */
+ /* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Write data to memory */
- for (size = BufferSize; size != limit; size-=2U)
+ for (size = BufferSize; size != limit; size -= 2U)
{
*psramaddress = (uint32_t)(*psrcbuff);
psrcbuff++;
@@ -554,11 +554,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
- __IO uint32_t * psramaddress = pAddress;
- uint32_t * pdestbuff = pDstBuffer;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@@ -601,11 +602,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
- __IO uint32_t * psramaddress = pAddress;
- uint32_t * psrcbuff = pSrcBuffer;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@@ -647,7 +649,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
HAL_SRAM_StateTypeDef state = hsram->State;
@@ -680,7 +683,7 @@
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -695,7 +698,8 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
@@ -720,7 +724,7 @@
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -738,12 +742,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -752,20 +757,20 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = pCallback;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = pCallback;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -791,7 +796,7 @@
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
@@ -800,42 +805,42 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = HAL_SRAM_MspInit;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
- break;
- case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
- hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- break;
- case HAL_SRAM_DMA_XFER_ERR_CB_ID :
- hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(state == HAL_SRAM_STATE_RESET)
+ else if (state == HAL_SRAM_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = HAL_SRAM_MspInit;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -860,12 +865,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -874,20 +880,20 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
- hsram->DmaXferCpltCallback = pCallback;
- break;
- case HAL_SRAM_DMA_XFER_ERR_CB_ID :
- hsram->DmaXferErrorCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -900,15 +906,15 @@
__HAL_UNLOCK(hsram);
return status;
}
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### SRAM Control functions #####
@@ -930,7 +936,7 @@
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ if (hsram->State == HAL_SRAM_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hsram);
@@ -964,7 +970,7 @@
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_READY)
+ if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
@@ -994,8 +1000,8 @@
*/
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### SRAM State functions #####
@@ -1028,16 +1034,13 @@
*/
/**
- @cond 0
- */
-/**
* @brief MDMA SRAM process complete callback.
* @param hmdma : MDMA handle
* @retval None
*/
static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent);
/* Disable the MDMA channel */
__HAL_MDMA_DISABLE(hmdma);
@@ -1049,7 +1052,7 @@
hsram->DmaXferCpltCallback(hmdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hmdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
@@ -1059,7 +1062,7 @@
*/
static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent);
/* Disable the MDMA channel */
__HAL_MDMA_DISABLE(hmdma);
@@ -1071,7 +1074,7 @@
hsram->DmaXferCpltCallback(hmdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hmdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
@@ -1081,7 +1084,7 @@
*/
static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent);
/* Disable the MDMA channel */
__HAL_MDMA_DISABLE(hmdma);
@@ -1093,11 +1096,8 @@
hsram->DmaXferErrorCallback(hmdma);
#else
HAL_SRAM_DMA_XferErrorCallback(hmdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
-/**
- @endcond
- */
/**
* @}
diff --git a/Src/stm32h7xx_hal_swpmi.c b/Src/stm32h7xx_hal_swpmi.c
index f90aec7..839af3b 100644
--- a/Src/stm32h7xx_hal_swpmi.c
+++ b/Src/stm32h7xx_hal_swpmi.c
@@ -1745,7 +1745,7 @@
in the SWPMI CR register */
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait the TXBEF */
diff --git a/Src/stm32h7xx_hal_tim.c b/Src/stm32h7xx_hal_tim.c
index 678efc9..5dc8d35 100644
--- a/Src/stm32h7xx_hal_tim.c
+++ b/Src/stm32h7xx_hal_tim.c
@@ -416,8 +416,15 @@
htim->State = HAL_TIM_STATE_BUSY;
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -471,8 +478,15 @@
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -490,7 +504,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
@@ -549,6 +563,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -556,8 +571,15 @@
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -792,8 +814,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -910,8 +939,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1044,6 +1080,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1064,6 +1101,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1084,6 +1122,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1103,6 +1142,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1124,8 +1164,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1408,8 +1455,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1525,8 +1579,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1659,6 +1720,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1679,6 +1741,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1698,6 +1761,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Capture/Compare 3 request */
@@ -1717,6 +1781,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1738,8 +1803,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2005,7 +2077,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2018,8 +2090,15 @@
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2080,7 +2159,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2126,8 +2205,15 @@
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2225,12 +2311,12 @@
/* Set the TIM channel state */
if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2261,6 +2347,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -2280,6 +2367,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -2299,6 +2387,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -2318,6 +2407,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2333,8 +2423,15 @@
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2593,11 +2690,12 @@
/**
* @brief Starts the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2612,9 +2710,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2629,7 +2727,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2649,11 +2747,12 @@
/**
* @brief Stops the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2665,7 +2764,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -2691,11 +2790,12 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2710,9 +2810,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2727,7 +2827,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2753,11 +2853,12 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2775,7 +2876,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -3047,7 +3148,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3060,7 +3161,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3073,9 +3174,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3165,7 +3266,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3201,7 +3302,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3214,7 +3315,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3227,9 +3328,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3327,7 +3428,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3367,12 +3468,12 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData1 == NULL) && (Length > 0U))
{
@@ -3392,12 +3493,12 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData2 == NULL) && (Length > 0U))
{
@@ -3417,16 +3518,16 @@
else
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3460,6 +3561,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3484,6 +3586,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3509,6 +3612,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -3522,6 +3626,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the Peripheral */
@@ -3600,7 +3705,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -4441,8 +4546,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4458,8 +4564,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4475,8 +4582,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4492,8 +4600,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4509,8 +4618,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4526,8 +4636,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4543,8 +4654,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4570,7 +4682,6 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4579,54 +4690,51 @@
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -4770,8 +4878,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4787,8 +4896,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4804,8 +4914,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4821,8 +4932,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4838,8 +4950,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4855,8 +4968,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4872,8 +4986,9 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4900,7 +5015,6 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4909,54 +5023,51 @@
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -5298,13 +5409,13 @@
case TIM_CLOCKSOURCE_ITR6:
case TIM_CLOCKSOURCE_ITR7:
case TIM_CLOCKSOURCE_ITR8:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
default:
break;
@@ -6270,12 +6381,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
+
return channel_state;
}
@@ -6288,7 +6399,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
+
return htim->DMABurstState;
}
@@ -6352,14 +6463,14 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6368,7 +6479,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6377,7 +6488,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6386,7 +6497,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -6457,7 +6568,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6467,7 +6578,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6477,7 +6588,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6487,7 +6598,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -6672,7 +6783,7 @@
/**
* @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6747,7 +6858,7 @@
/**
* @brief Timer Output Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6823,7 +6934,7 @@
/**
* @brief Timer Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6897,7 +7008,7 @@
/**
* @brief Timer Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6957,7 +7068,7 @@
/**
* @brief Timer Output Compare 5 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
@@ -7010,7 +7121,7 @@
/**
* @brief Timer Output Compare 6 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
@@ -7114,7 +7225,7 @@
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
{
return HAL_ERROR;
}
@@ -7176,11 +7287,11 @@
case TIM_TS_ITR11:
case TIM_TS_ITR12:
case TIM_TS_ITR13:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
default:
break;
diff --git a/Src/stm32h7xx_hal_tim_ex.c b/Src/stm32h7xx_hal_tim_ex.c
index d1cb18c..d929a23 100644
--- a/Src/stm32h7xx_hal_tim_ex.c
+++ b/Src/stm32h7xx_hal_tim_ex.c
@@ -322,9 +322,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -334,14 +334,21 @@
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
+
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -395,9 +402,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -416,8 +423,15 @@
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -474,12 +488,12 @@
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -509,14 +523,22 @@
/* Enable the DMA stream for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -603,7 +625,7 @@
{
return HAL_ERROR;
}
-
+
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
@@ -614,8 +636,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -721,8 +750,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -853,6 +889,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -872,6 +909,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -891,6 +929,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -909,8 +948,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1048,8 +1094,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1153,8 +1206,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1286,6 +1346,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -1305,6 +1366,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1324,6 +1386,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1342,8 +1405,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1439,8 +1509,10 @@
/**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1449,22 +1521,28 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
@@ -1480,8 +1558,10 @@
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1505,8 +1585,10 @@
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1515,8 +1597,10 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1525,22 +1609,28 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -1562,8 +1652,10 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1593,8 +1685,10 @@
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -2042,10 +2136,10 @@
/* Set the break input polarity */
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_AF1 */
htim->Instance->AF1 = tmporx;
@@ -2062,10 +2156,10 @@
/* Set the break input polarity */
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_AF2 */
htim->Instance->AF2 = tmporx;
@@ -2426,12 +2520,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
+
return channel_state;
}
/**
@@ -2498,7 +2592,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -2507,7 +2601,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -2516,7 +2610,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -2525,7 +2619,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -2550,7 +2644,7 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -2573,13 +2667,13 @@
{
/* nothing to do */
}
-
+
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
diff --git a/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c b/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
index 61213a7..39d8881 100644
--- a/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
@@ -6,7 +6,7 @@
*
* This file override the native HAL time base functions (defined as weak)
* to use the RTC ALARM for time base generation:
- * + Intializes the RTC peripheral to increment the seconds registers each 1ms
+ * + Initializes the RTC peripheral to increment the seconds registers each 1ms
* + The alarm is configured to assert an interrupt when the RTC reaches 1ms
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
* + HSE (default), LSE or LSI can be selected as RTC clock source
@@ -100,19 +100,19 @@
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
+ /* Configure LSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
+ /* Configure LSI as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
+ /* Configure HSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
diff --git a/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
index fca84e1..0f0f0ab 100644
--- a/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
@@ -6,7 +6,7 @@
*
* This file overrides the native HAL time base functions (defined as weak)
* to use the RTC WAKEUP for the time base generation:
- * + Intializes the RTC peripheral and configures the wakeup timer to be
+ * + Initializes the RTC peripheral and configures the wakeup timer to be
* incremented each 1ms
* + The wakeup feature is configured to assert an interrupt each 1ms
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
@@ -107,19 +107,19 @@
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
+ /* Configure LSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
+ /* Configure LSI as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
+ /* Configure HSE as RTC clock source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
diff --git a/Src/stm32h7xx_hal_timebase_tim_template.c b/Src/stm32h7xx_hal_timebase_tim_template.c
index 5ac80a2..ec97a3e 100644
--- a/Src/stm32h7xx_hal_timebase_tim_template.c
+++ b/Src/stm32h7xx_hal_timebase_tim_template.c
@@ -6,7 +6,7 @@
*
* This file overrides the native HAL time base functions (defined as weak)
* the TIM time base:
- * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
+ * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
@verbatim
diff --git a/Src/stm32h7xx_hal_uart.c b/Src/stm32h7xx_hal_uart.c
index 0810120..218b9b5 100644
--- a/Src/stm32h7xx_hal_uart.c
+++ b/Src/stm32h7xx_hal_uart.c
@@ -39,7 +39,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
@@ -114,6 +115,10 @@
(+) MspDeInitCallback : UART MspDeInit.
[..]
+ For specific callback RxEventCallback, use dedicated registration/reset functions:
+ respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+
+ [..]
By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
@@ -172,27 +177,23 @@
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+ USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+ USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
-
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
-
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -222,6 +223,15 @@
* @}
*/
+/* Exported Constants --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Constants
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
@@ -645,6 +655,7 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
__HAL_UNLOCK(huart);
@@ -844,55 +855,57 @@
switch (CallbackID)
{
case HAL_UART_TX_HALFCOMPLETE_CB_ID :
- huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_UART_TX_COMPLETE_CB_ID :
- huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_UART_RX_HALFCOMPLETE_CB_ID :
- huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_UART_RX_COMPLETE_CB_ID :
- huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_UART_ERROR_CB_ID :
- huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_UART_ABORT_COMPLETE_CB_ID :
- huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
- huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
break;
case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
- huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
case HAL_UART_WAKEUP_CB_ID :
- huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
break;
case HAL_UART_RX_FIFO_FULL_CB_ID :
- huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_UART_TX_FIFO_EMPTY_CB_ID :
- huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
case HAL_UART_MSPINIT_CB_ID :
- huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_UART_MSPDEINIT_CB_ID :
- huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -932,6 +945,74 @@
return status;
}
+
+/**
+ * @brief Register a User UART Rx Event Callback
+ * To be used instead of the weak predefined callback
+ * @param huart Uart handle
+ * @param pCallback Pointer to the Rx Event Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = pCallback;
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the UART Rx Event Callback
+ * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+ * @param huart Uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+ return status;
+}
+
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@@ -997,16 +1078,23 @@
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+ reception services:
+ (+) HAL_UARTEx_RxEventCallback()
+
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on UART side.
If user wants to abort it, Abort services should be called by user.
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+ user callback is executed.
-@- In the Half duplex communication, it is forbidden to run the transmit
and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
@@ -1049,7 +1137,7 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
huart->TxXferSize = Size;
@@ -1138,8 +1226,9 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
huart->RxXferSize = Size;
@@ -1290,58 +1379,20 @@
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
- huart->RxISR = NULL;
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Configure Rx interrupt processing*/
- if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
- huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ /* Enable the UART Receiver Timeout Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
- else
- {
- huart->RxISR = UART_RxISR_8BIT_FIFOEN;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
- }
- else
- {
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- huart->RxISR = UART_RxISR_16BIT;
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
}
- return HAL_OK;
+ return (UART_Start_Receive_IT(huart, pData, Size));
}
else
{
@@ -1447,53 +1498,20 @@
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- if (huart->hdmarx != NULL)
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- __HAL_UNLOCK(huart);
-
- /* Restore huart->gState to ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_ERROR;
+ /* Enable the UART Receiver Timeout Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
- __HAL_UNLOCK(huart);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
+ return (UART_Start_Receive_DMA(huart, pData, Size));
}
else
{
@@ -1554,7 +1572,7 @@
/* Clear the Overrun flag before resuming the Rx transfer */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -1650,9 +1668,16 @@
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
{
/* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
+ USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Tx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
@@ -1722,6 +1747,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
huart->ErrorCode = HAL_UART_ERROR_NONE;
@@ -1804,6 +1830,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
@@ -1840,6 +1872,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
return HAL_OK;
}
@@ -1863,9 +1896,16 @@
uint32_t abortcplt = 1U;
/* Disable interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+ USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
@@ -1974,6 +2014,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2098,6 +2139,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
@@ -2133,6 +2180,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2157,6 +2205,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2339,6 +2388,93 @@
} /* End if some error occurs */
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ && ((isrflags & USART_ISR_IDLE) != 0U)
+ && ((cr1its & USART_ISR_IDLE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* Check if DMA mode is enabled in UART */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* DMA mode enabled */
+ /* Check received length : If all expected data are received, do nothing,
+ (DMA cplt callback will be called).
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ if ((nb_remaining_rx_data > 0U)
+ && (nb_remaining_rx_data < huart->RxXferSize))
+ {
+ /* Reception is not complete */
+ huart->RxXferCount = nb_remaining_rx_data;
+
+ /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Last bytes received, so no need as the abort is immediate */
+ (void)HAL_DMA_Abort(huart->hdmarx);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ else
+ {
+ /* DMA mode not enabled */
+ /* Check received length : If all expected data are received, do nothing.
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ if ((huart->RxXferCount > 0U)
+ && (nb_rx_data > 0U))
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxEventCallback(huart, nb_rx_data);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ }
+
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
{
@@ -2524,6 +2660,24 @@
}
/**
+ * @brief Reception Event Callback (Rx event notification called after use of advanced reception service).
+ * @param huart UART handle
+ * @param Size Number of data available in application reception buffer (indicates a position in
+ * reception buffer until which, data are available)
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ UNUSED(Size);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -2845,6 +2999,7 @@
huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */
}
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -2893,7 +3048,6 @@
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- tmpreg |= (uint32_t)huart->FifoMode;
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -2978,7 +3132,7 @@
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
- usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
{
huart->Instance->BRR = usartdiv;
@@ -2987,7 +3141,8 @@
{
ret = HAL_ERROR;
}
- } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+ } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+ (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
@@ -3199,7 +3354,7 @@
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -3227,6 +3382,7 @@
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
__HAL_UNLOCK(huart);
@@ -3253,7 +3409,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -3272,7 +3429,8 @@
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -3291,6 +3449,134 @@
return HAL_OK;
}
+/**
+ * @brief Start Receive operation in interrupt mode.
+ * @note This function could be called by all HAL UART API providing reception in Interrupt mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+ huart->RxISR = NULL;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in DMA mode.
+ * @note This function could be called by all HAL UART API providing reception in DMA mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+}
+
/**
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
@@ -3319,8 +3605,15 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
@@ -3403,15 +3696,37 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+
+ /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
}
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
/**
@@ -3423,13 +3738,29 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Half complete callback*/
- huart->RxHalfCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
#else
- /*Call legacy weak Rx Half complete callback*/
- HAL_UART_RxHalfCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
/**
@@ -3534,6 +3865,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3585,6 +3917,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3652,6 +3985,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3664,7 +3998,7 @@
}
/**
- * @brief TX interrrupt handler for 7 or 8 bits data word length .
+ * @brief TX interrupt handler for 7 or 8 bits data word length .
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3693,7 +4027,7 @@
}
/**
- * @brief TX interrrupt handler for 9 bits data word length.
+ * @brief TX interrupt handler for 9 bits data word length.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3725,7 +4059,7 @@
}
/**
- * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3765,7 +4099,7 @@
}
/**
- * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3833,7 +4167,7 @@
}
/**
- * @brief RX interrrupt handler for 7 or 8 bits data word length .
+ * @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
@@ -3864,13 +4198,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -3881,7 +4235,7 @@
}
/**
- * @brief RX interrrupt handler for 9 bits data word length .
+ * @brief RX interrupt handler for 9 bits data word length .
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
@@ -3916,13 +4270,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -3933,7 +4307,7 @@
}
/**
- * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
@@ -3943,25 +4317,74 @@
{
uint16_t uhMask = huart->Mask;
uint16_t uhdata;
- uint16_t nb_rx_data;
+ uint16_t nb_rx_data;
uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
huart->pRxBuffPtr++;
huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Rx process is completed, restore huart->RxState to Ready */
@@ -3970,13 +4393,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
@@ -4005,7 +4448,7 @@
}
/**
- * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
@@ -4016,26 +4459,75 @@
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
uint16_t uhdata;
- uint16_t nb_rx_data;
+ uint16_t nb_rx_data;
uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
tmp = (uint16_t *) huart->pRxBuffPtr ;
*tmp = (uint16_t)(uhdata & uhMask);
huart->pRxBuffPtr += 2U;
huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Rx process is completed, restore huart->RxState to Ready */
@@ -4044,13 +4536,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
diff --git a/Src/stm32h7xx_hal_uart_ex.c b/Src/stm32h7xx_hal_uart_ex.c
index 3a899a1..bd57fec 100644
--- a/Src/stm32h7xx_hal_uart_ex.c
+++ b/Src/stm32h7xx_hal_uart_ex.c
@@ -332,6 +332,41 @@
(+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
(+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+ [..] This subsection also provides a set of additional functions providing enhanced reception
+ services to user. (For example, these functions allow application to handle use cases
+ where number of data to be received is unknown).
+
+ (#) Compared to standard reception services which only consider number of received
+ data elements as reception completion criteria, these functions also consider additional events
+ as triggers for updating reception status to caller :
+ (+) Detection of inactivity period (RX line has not been active for a given period).
+ (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+ for 1 frame time, after last received byte.
+ (++) RX inactivity detected by RTO, i.e. line has been in idle state
+ for a programmable time, after last received byte.
+ (+) Detection that a specific character has been received.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+ or till IDLE event occurs. Reception is handled only during function execution.
+ When function exits, no data reception could occur. HAL status and number of actually received data elements,
+ are returned by function after finishing transfer.
+ (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+ The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+ (#) Blocking mode API:
+ (+) HAL_UARTEx_ReceiveToIdle()
+
+ (#) Non-Blocking mode API with Interrupt:
+ (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+ (#) Non-Blocking mode API with DMA:
+ (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
@endverbatim
* @{
*/
@@ -416,7 +451,7 @@
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Wait until REACK flag is set */
@@ -653,6 +688,259 @@
}
/**
+ * @brief Receive an amount of data in blocking mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note HAL_OK is returned if reception is completed (expected number of data has been received)
+ * or if reception is stopped after IDLE event (less than the expected number of data has been received)
+ * In this case, RxLen output parameter indicates number of data available in reception buffer.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @param RxLen Number of data elements finally received
+ * (could be lower than Size, in case reception ends on IDLE event)
+ * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Initialize output number of received elements */
+ *RxLen = 0U;
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ /* Check if IDLE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+ {
+ /* Clear IDLE flag in ISR */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* If Set, but no data ever received, clear flag without exiting loop */
+ /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+ if (*RxLen > 0U)
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ }
+
+ /* Check if RXNE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+ {
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ /* Increment number of received elements */
+ *RxLen += 1U;
+ huart->RxXferCount--;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set number of received elements in output parameter : RxLen */
+ *RxLen = huart->RxXferSize - huart->RxXferCount;
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+ * number of received data elements.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_IT(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode till either the expected number
+ * of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to DMA services, transferring automatically received data elements in user reception buffer and
+ * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+ * reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_DMA(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @}
*/
@@ -694,8 +982,8 @@
uint8_t tx_fifo_depth;
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
{
@@ -708,8 +996,10 @@
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
- huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
/**
diff --git a/Src/stm32h7xx_hal_usart.c b/Src/stm32h7xx_hal_usart.c
index caf70aa..f27e32f 100644
--- a/Src/stm32h7xx_hal_usart.c
+++ b/Src/stm32h7xx_hal_usart.c
@@ -39,7 +39,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
(Receiver/Transmitter) in the husart handle Init structure.
@@ -532,9 +533,9 @@
}
/**
- * @brief Unregister an UART Callback
- * UART callaback is redirected to the weak predefined callback
- * @param husart uart handle
+ * @brief Unregister an USART Callback
+ * USART callaback is redirected to the weak predefined callback
+ * @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
@@ -562,47 +563,47 @@
switch (CallbackID)
{
case HAL_USART_TX_HALFCOMPLETE_CB_ID :
- husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_USART_TX_COMPLETE_CB_ID :
- husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_USART_RX_HALFCOMPLETE_CB_ID :
- husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_USART_RX_COMPLETE_CB_ID :
- husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_USART_TX_RX_COMPLETE_CB_ID :
- husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
break;
case HAL_USART_ERROR_CB_ID :
- husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_USART_ABORT_COMPLETE_CB_ID :
- husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_USART_RX_FIFO_FULL_CB_ID :
- husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_USART_TX_FIFO_EMPTY_CB_ID :
- husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
case HAL_USART_MSPINIT_CB_ID :
- husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_USART_MSPDEINIT_CB_ID :
- husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -721,13 +722,16 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
+ error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on USART side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -735,7 +739,7 @@
/**
* @brief Simplex send an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -763,7 +767,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->TxXferSize = Size;
@@ -832,7 +836,7 @@
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -861,7 +865,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -943,7 +947,7 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -977,7 +981,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -1092,7 +1096,7 @@
/**
* @brief Send an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1175,7 +1179,7 @@
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1278,7 +1282,7 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1377,7 +1381,7 @@
/**
* @brief Send an amount of data in DMA mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1462,7 +1466,7 @@
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1578,7 +1582,7 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1769,7 +1773,7 @@
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -2092,7 +2096,8 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+ USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -2906,11 +2911,13 @@
break;
case USART_CLOCKSOURCE_PLL2:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate,
+ husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_PLL3:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate,
+ husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
@@ -2968,7 +2975,7 @@
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -3437,7 +3444,8 @@
/* Disable the USART Parity Error Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Clear RxISR function pointer */
@@ -3571,7 +3579,8 @@
/* Disable the USART Parity Error Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Clear RxISR function pointer */
diff --git a/Src/stm32h7xx_hal_usart_ex.c b/Src/stm32h7xx_hal_usart_ex.c
index ac5bade..2bdc87e 100644
--- a/Src/stm32h7xx_hal_usart_ex.c
+++ b/Src/stm32h7xx_hal_usart_ex.c
@@ -503,8 +503,8 @@
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
{
@@ -515,10 +515,14 @@
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
- rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
- tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
- husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+ tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+ husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
/**
diff --git a/Src/stm32h7xx_hal_wwdg.c b/Src/stm32h7xx_hal_wwdg.c
index 94db743..43b55b2 100644
--- a/Src/stm32h7xx_hal_wwdg.c
+++ b/Src/stm32h7xx_hal_wwdg.c
@@ -21,6 +21,13 @@
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) If required by application, an Early Wakeup Interrupt can be triggered
+ in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+ (EWI) can be used if specific safety operations or data logging must
+ be performed before the actual reset is generated. When the downcounter
+ reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+ line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+ disabled except by a system reset.
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
@@ -47,7 +54,6 @@
(++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: approximately 268.43ms
- ==============================================================================
##### How to use this driver #####
==============================================================================
@@ -56,16 +62,16 @@
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
- (+) Set the WWDG prescaler, refresh window and counter value
- using HAL_WWDG_Init() function.
- (+) Start the WWDG using HAL_WWDG_Start() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
- (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
- generated when the counter reaches 0x40, and then start the WWDG using
- HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
- add his own code by customization of callback HAL_WWDG_WakeupCallback.
- Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Configure the WWDG prescaler, refresh window value, counter value and early
+ interrupt status using HAL_WWDG_Init() function. This will automatically
+ enable WWDG and start its downcounter. Time reference can be taken from
+ function exit. Care must be taken to provide a counter value
+ greater than 0x40 to prevent generation of immediate reset.
+ (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+ generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+ triggered by the interrupt service routine, flag will be automatically
+ cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+ can add his own code by customization of callback HAL_WWDG_WakeupCallback.
(+) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
@@ -75,28 +81,28 @@
=============================
[..]
- The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
- @ref HAL_WWDG_RegisterCallback() to register a user callback.
+ HAL_WWDG_RegisterCallback() to register a user callback.
- (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
+ (+) Function HAL_WWDG_RegisterCallback() allows to register following
callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
- the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
+ (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
takes as parameters the HAL peripheral handle and the Callback ID.
This function allows to reset following callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
[..]
- When calling @ref HAL_WWDG_Init function, callbacks are reset to the
+ When calling HAL_WWDG_Init function, callbacks are reset to the
corresponding legacy weak (surcharged) functions:
- @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
[..]
@@ -107,7 +113,7 @@
*** WWDG HAL driver macros list ***
===================================
[..]
- Below the list of most used macros in WWDG HAL driver.
+ Below the list of available macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
@@ -208,7 +214,7 @@
#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@@ -253,7 +259,8 @@
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -314,7 +321,7 @@
return status;
}
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
@@ -382,7 +389,7 @@
#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
}
}
}
diff --git a/Src/stm32h7xx_ll_adc.c b/Src/stm32h7xx_ll_adc.c
index df01887..1ce67c4 100644
--- a/Src/stm32h7xx_ll_adc.c
+++ b/Src/stm32h7xx_ll_adc.c
@@ -317,7 +317,7 @@
* the same ADC common instance to their default reset values.
* @note This function is performing a hard reset, using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* To de-initialize only 1 ADC instance, use
@@ -387,7 +387,7 @@
/* Note: Hardware constraint (refer to description of functions */
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
- /* On this STM32 serie, setting of these features is conditioned to */
+ /* On this STM32 series, setting of these features is conditioned to */
/* ADC state: */
/* All ADC instances of the ADC common group must be disabled. */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
@@ -468,7 +468,7 @@
* is in an unknown state.
* In this case, perform a hard reset using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* Refer to function @ref LL_ADC_CommonDeInit().
@@ -758,10 +758,10 @@
/* ADC instance is in an unknown state */
/* Need to performing a hard reset of ADC instance, using high level */
/* clock source RCC ADC reset. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
status = ERROR;
@@ -918,7 +918,7 @@
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* - Set ADC group regular overrun behavior */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
@@ -978,7 +978,7 @@
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
@@ -1045,7 +1045,7 @@
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
diff --git a/Src/stm32h7xx_ll_comp.c b/Src/stm32h7xx_ll_comp.c
index 38c6c7f..ad5d4d5 100644
--- a/Src/stm32h7xx_ll_comp.c
+++ b/Src/stm32h7xx_ll_comp.c
@@ -55,7 +55,7 @@
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
)
-/* Note: On this STM32 serie, comparator input plus parameters are */
+/* Note: On this STM32 series, comparator input plus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
@@ -70,7 +70,7 @@
|| ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2))
#endif
-/* Note: On this STM32 serie, comparator input minus parameters are */
+/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
diff --git a/Src/stm32h7xx_ll_cordic.c b/Src/stm32h7xx_ll_cordic.c
index da5b22b..7166551 100644
--- a/Src/stm32h7xx_ll_cordic.c
+++ b/Src/stm32h7xx_ll_cordic.c
@@ -25,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
diff --git a/Src/stm32h7xx_ll_dac.c b/Src/stm32h7xx_ll_dac.c
index f5983de..c27d64b 100644
--- a/Src/stm32h7xx_ll_dac.c
+++ b/Src/stm32h7xx_ll_dac.c
@@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
@@ -46,10 +46,9 @@
/** @addtogroup DAC_LL_Private_Macros
* @{
*/
-#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \
- ( \
- ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
- || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \
+ ( ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
)
#if defined (HRTIM1)
@@ -104,56 +103,56 @@
)
#endif
-#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
- ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
+ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \
( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
+ && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
) \
- ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
- ) \
+ ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
+ ) \
)
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
- || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
)
#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \
( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
- || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
+ || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
)
#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \
( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
- || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
+ || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
)
/**
diff --git a/Src/stm32h7xx_ll_dma2d.c b/Src/stm32h7xx_ll_dma2d.c
index 4209a17..0805f00 100644
--- a/Src/stm32h7xx_ll_dma2d.c
+++ b/Src/stm32h7xx_ll_dma2d.c
@@ -25,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
@@ -175,9 +175,12 @@
ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
{
ErrorStatus status = ERROR;
- LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
- uint32_t tmp, tmp1, tmp2;
- uint32_t regMask, regValue;
+ LL_DMA2D_ColorTypeDef dma2d_colorstruct;
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ uint32_t regMask;
+ uint32_t regValue;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -228,12 +231,12 @@
LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
/* DMA2D OCOLR register configuration ------------------------------------------*/
- DMA2D_ColorStruct.ColorMode = DMA2D_InitStruct->ColorMode;
- DMA2D_ColorStruct.OutputBlue = DMA2D_InitStruct->OutputBlue;
- DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
- DMA2D_ColorStruct.OutputRed = DMA2D_InitStruct->OutputRed;
- DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
- LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct);
+ dma2d_colorstruct.ColorMode = DMA2D_InitStruct->ColorMode;
+ dma2d_colorstruct.OutputBlue = DMA2D_InitStruct->OutputBlue;
+ dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
+ dma2d_colorstruct.OutputRed = DMA2D_InitStruct->OutputRed;
+ dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
+ LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct);
status = SUCCESS;
}
@@ -333,9 +336,9 @@
(DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_CSS | DMA2D_FGPFCCR_AM | \
DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
- DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \
- DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \
- DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode));
+ DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \
+ DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \
+ DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode));
/* Configure the foreground color */
LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
diff --git a/Src/stm32h7xx_ll_exti.c b/Src/stm32h7xx_ll_exti.c
index 3d1d792..b9ecde5 100644
--- a/Src/stm32h7xx_ll_exti.c
+++ b/Src/stm32h7xx_ll_exti.c
@@ -111,12 +111,12 @@
LL_EXTI_WriteReg(D3PCR2H, 0x00000000U);
LL_EXTI_WriteReg(D3PCR3H, 0x00000000U);
- /* Interrupt mask register set to default reset values */
+ /* Interrupt mask register reset */
LL_EXTI_WriteReg(IMR1, 0x00000000U);
LL_EXTI_WriteReg(IMR2, 0x00000000U);
LL_EXTI_WriteReg(IMR3, 0x00000000U);
- /* Event mask register set to default reset values */
+ /* Event mask register reset */
LL_EXTI_WriteReg(EMR1, 0x00000000U);
LL_EXTI_WriteReg(EMR2, 0x00000000U);
LL_EXTI_WriteReg(EMR3, 0x00000000U);
diff --git a/Src/stm32h7xx_ll_fmc.c b/Src/stm32h7xx_ll_fmc.c
index 320fcf0..452d5e9 100644
--- a/Src/stm32h7xx_ll_fmc.c
+++ b/Src/stm32h7xx_ll_fmc.c
@@ -16,7 +16,7 @@
==============================================================================
[..] The Flexible memory controller (FMC) includes following memory controllers:
(+) The NOR/PSRAM memory controller
- (+) The NAND memory controller
+ (+) The NAND memory controller
(+) The Synchronous DRAM (SDRAM) controller
[..] The FMC functional block makes the interface with synchronous and asynchronous static
@@ -60,13 +60,13 @@
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
-#if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_SDRAM_MODULE_ENABLED)
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
* @{
*/
-
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -88,14 +88,9 @@
/* --- BWTR Register ---*/
/* BWTR register clear mask */
-#if defined(FMC_BWTRx_BUSTURN)
#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
FMC_BWTRx_ACCMOD))
-#else
-#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
- FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
-#endif /* FMC_BWTRx_BUSTURN */
/* --- PCR Register ---*/
/* PCR register clear mask */
@@ -191,7 +186,8 @@
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
@@ -287,7 +283,8 @@
* @param Bank NORSRAM bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@@ -323,7 +320,8 @@
* @param Bank NORSRAM bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr;
@@ -340,17 +338,17 @@
/* Set FMC_NORSRAM device timing parameters */
MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
- ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
+ ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
+ ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
+ (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
+ (Timing->AccessMode)));
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
{
- tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
}
@@ -370,7 +368,9 @@
* @arg FMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
@@ -383,9 +383,7 @@
assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
-#if defined(FMC_BWTRx_BUSTURN)
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-#endif /* FMC_BWTRx_BUSTURN */
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
@@ -393,12 +391,8 @@
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
-#if defined(FMC_BWTRx_BUSTURN)
Timing->AccessMode |
((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
-#else
- Timing->AccessMode));
-#endif /* FMC_BWTRx_BUSTURN */
}
else
{
@@ -412,8 +406,8 @@
*/
/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FMC_NORSRAM Control functions #####
@@ -497,8 +491,8 @@
*/
/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -552,7 +546,8 @@
* @param Bank NAND bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -582,7 +577,8 @@
* @param Bank NAND bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -703,7 +699,8 @@
* @param Timeout Timeout wait value
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -850,7 +847,8 @@
* @param Bank SDRAM bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
+ FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
@@ -979,7 +977,8 @@
* @param Timeout Timeout wait value
* @retval HAL state
*/
-HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
+HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
+ FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
@@ -989,10 +988,10 @@
assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
/* Set command register */
- SET_BIT(Device->SDCMR, ((Command->CommandMode) |
- (Command->CommandTarget) |
- (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
- ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
+ MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 |
+ FMC_SDCMR_NRFS | FMC_SDCMR_MRD), ((Command->CommandMode) |
+ (Command->CommandTarget) | (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
+ ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
/* Prevent unused argument(s) compilation warning */
UNUSED(Timeout);
return HAL_OK;
@@ -1022,7 +1021,8 @@
* @param AutoRefreshNumber Specifies the auto Refresh number.
* @retval None
*/
-HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
+HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
+ uint32_t AutoRefreshNumber)
{
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
@@ -1086,5 +1086,8 @@
/**
* @}
*/
+/**
+ * @}
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_lptim.c b/Src/stm32h7xx_ll_lptim.c
index ff1ee65..bf08c46 100644
--- a/Src/stm32h7xx_ll_lptim.c
+++ b/Src/stm32h7xx_ll_lptim.c
@@ -48,22 +48,22 @@
* @{
*/
#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
- || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+ || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
@@ -296,8 +296,7 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- }
- while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
diff --git a/Src/stm32h7xx_ll_lpuart.c b/Src/stm32h7xx_ll_lpuart.c
index 8267e41..7ff5441 100644
--- a/Src/stm32h7xx_ll_lpuart.c
+++ b/Src/stm32h7xx_ll_lpuart.c
@@ -153,8 +153,10 @@
/**
* @brief Initialize LPUART registers according to the specified
* parameters in LPUART_InitStruct.
- * @note As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),
- * LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in LPUART configuration registers can only be written when
+ * the LPUART is disabled (USART_CR1_UE bit =0),
+ * LPUART Peripheral should be in disabled state prior calling this function.
+ * Otherwise, ERROR result will be returned.
* @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
* @param LPUARTx LPUART Instance
* @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
@@ -200,7 +202,8 @@
/*---------------------------- LPUART CR3 Configuration -----------------------
* Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
+ * to LPUART_InitStruct->HardwareFlowControl value.
*/
LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
@@ -271,7 +274,7 @@
* @}
*/
-#endif /* defined (LPUART1) */
+#endif /* LPUART1 */
/**
* @}
diff --git a/Src/stm32h7xx_ll_rcc.c b/Src/stm32h7xx_ll_rcc.c
index 282b9ab..68ed42a 100644
--- a/Src/stm32h7xx_ll_rcc.c
+++ b/Src/stm32h7xx_ll_rcc.c
@@ -83,12 +83,12 @@
/** @defgroup RCC_LL_Private_Functions RCC Private functions
* @{
*/
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetSystemClockFreq(void);
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
/**
* @}
@@ -1681,7 +1681,7 @@
* @brief Return SYSTEM clock frequency
* @retval SYSTEM clock frequency (in Hz)
*/
-uint32_t RCC_GetSystemClockFreq(void)
+static uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency = 0U;
LL_PLL_ClocksTypeDef PLL_Clocks;
@@ -1720,7 +1720,7 @@
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK clock frequency (in Hz)
*/
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
@@ -1731,7 +1731,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
@@ -1742,7 +1742,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
@@ -1753,7 +1753,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK3 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK3 clock frequency */
return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
@@ -1764,7 +1764,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK4 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK4 clock frequency */
return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
diff --git a/Src/stm32h7xx_ll_rng.c b/Src/stm32h7xx_ll_rng.c
index d3d3452..a98addf 100644
--- a/Src/stm32h7xx_ll_rng.c
+++ b/Src/stm32h7xx_ll_rng.c
@@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
@@ -53,7 +53,7 @@
#define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \
- ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))
+ ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))
#define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
diff --git a/Src/stm32h7xx_ll_sdmmc.c b/Src/stm32h7xx_ll_sdmmc.c
index 4c2e72d..36c52c3 100644
--- a/Src/stm32h7xx_ll_sdmmc.c
+++ b/Src/stm32h7xx_ll_sdmmc.c
@@ -170,11 +170,6 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
-static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
/* Exported functions --------------------------------------------------------*/
@@ -183,8 +178,8 @@
*/
/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization/de-initialization functions #####
@@ -215,12 +210,12 @@
assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
/* Set SDMMC configuration parameters */
- tmpreg |= (Init.ClockEdge |\
- Init.ClockPowerSave |\
- Init.BusWide |\
- Init.HardwareFlowControl |\
+ tmpreg |= (Init.ClockEdge | \
+ Init.ClockPowerSave | \
+ Init.BusWide | \
+ Init.HardwareFlowControl | \
Init.ClockDiv
- );
+ );
/* Write to SDMMC CLKCR */
MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
@@ -234,8 +229,8 @@
*/
/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### I/O operation functions #####
@@ -278,8 +273,8 @@
*/
/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -367,9 +362,9 @@
SDMMCx->ARG = Command->Argument;
/* Set SDMMC command parameters */
- tmpreg |= (uint32_t)(Command->CmdIndex |\
- Command->Response |\
- Command->WaitForInterrupt |\
+ tmpreg |= (uint32_t)(Command->CmdIndex | \
+ Command->Response | \
+ Command->WaitForInterrupt | \
Command->CPSM);
/* Write to SDMMC CMD register */
@@ -421,7 +416,7 @@
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
{
uint32_t tmpreg = 0;
@@ -439,9 +434,9 @@
SDMMCx->DLEN = Data->DataLength;
/* Set the SDMMC data configuration parameters */
- tmpreg |= (uint32_t)(Data->DataBlockSize |\
- Data->TransferDir |\
- Data->TransferMode |\
+ tmpreg |= (uint32_t)(Data->DataBlockSize | \
+ Data->TransferDir | \
+ Data->TransferMode | \
Data->DPSM);
/* Write to SDMMC DCTRL */
@@ -497,8 +492,8 @@
/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### Commands management functions #####
@@ -511,7 +506,7 @@
*/
/**
- * @brief Send the Data Block Lenght command and check the response
+ * @brief Send the Data Block Length command and check the response
* @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
@@ -793,7 +788,7 @@
* @param addr: Address of the card to be selected
* @retval HAL status
*/
-uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
@@ -1040,6 +1035,31 @@
}
/**
+ * @brief Send the Set Relative Address command to MMC card (not SD card).
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param RCA Card RCA
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD3 SD_CMD_SET_REL_ADDR */
+ sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U);
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
* @brief Send the Status command and check the response.
* @param SDMMCx: Pointer to SDMMC register base
* @param Argument: Command Argument
@@ -1112,7 +1132,7 @@
}
/**
- * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
+ * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
* @param SDMMCx: Pointer to SDMMC register base
* @parame Argument: Argument used for the command
* @retval HAL status
@@ -1181,61 +1201,43 @@
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT);
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT);
return errorstate;
}
-
/**
* @}
*/
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
+
+/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+ * @brief Responses functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Responses management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed responses.
+
+@endverbatim
* @{
*/
-
-/**
- * @brief Checks for error conditions for CMD0.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
-
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
- return SDMMC_ERROR_NONE;
-}
-
/**
* @brief Checks for error conditions for R1 response.
* @param hsd: SD handle
* @param SD_CMD: The sent command index
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
{
uint32_t response_r1;
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
- uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+ uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1244,16 +1246,16 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT |
+ SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
@@ -1268,7 +1270,7 @@
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
/* Check response received is of desired command */
- if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
{
return SDMMC_ERROR_CMD_CRC_FAIL;
}
@@ -1276,79 +1278,79 @@
/* We have received response, retrieve it for analysis */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
- if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+ if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
{
return SDMMC_ERROR_NONE;
}
- else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+ else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
{
return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
}
- else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+ else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
{
return SDMMC_ERROR_ADDR_MISALIGNED;
}
- else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+ else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
{
return SDMMC_ERROR_BLOCK_LEN_ERR;
}
- else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+ else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
{
return SDMMC_ERROR_ERASE_SEQ_ERR;
}
- else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+ else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
{
return SDMMC_ERROR_BAD_ERASE_PARAM;
}
- else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+ else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
{
return SDMMC_ERROR_WRITE_PROT_VIOLATION;
}
- else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+ else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
{
return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
}
- else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+ else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
{
return SDMMC_ERROR_COM_CRC_FAILED;
}
- else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+ else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
{
return SDMMC_ERROR_ILLEGAL_CMD;
}
- else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+ else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
{
return SDMMC_ERROR_CARD_ECC_FAILED;
}
- else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+ else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
{
return SDMMC_ERROR_CC_ERR;
}
- else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+ else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
{
return SDMMC_ERROR_STREAM_READ_UNDERRUN;
}
- else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+ else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
{
return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
}
- else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+ else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
{
return SDMMC_ERROR_CID_CSD_OVERWRITE;
}
- else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+ else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
{
return SDMMC_ERROR_WP_ERASE_SKIP;
}
- else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+ else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
{
return SDMMC_ERROR_CARD_ECC_DISABLED;
}
- else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+ else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
{
return SDMMC_ERROR_ERASE_RESET;
}
- else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+ else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
{
return SDMMC_ERROR_AKE_SEQ_ERR;
}
@@ -1363,12 +1365,12 @@
* @param hsd: SD handle
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
{
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1377,8 +1379,8 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
@@ -1407,12 +1409,12 @@
* @param hsd: SD handle
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
{
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1421,10 +1423,10 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
@@ -1447,14 +1449,14 @@
* address RCA
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
{
uint32_t response_r1;
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1463,16 +1465,16 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
@@ -1484,7 +1486,7 @@
}
/* Check response received is of desired command */
- if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
{
return SDMMC_ERROR_CMD_CRC_FAIL;
}
@@ -1495,17 +1497,18 @@
/* We have received response, retrieve it. */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
- if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+ if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
+ SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
{
- *pRCA = (uint16_t) (response_r1 >> 16);
+ *pRCA = (uint16_t)(response_r1 >> 16);
return SDMMC_ERROR_NONE;
}
- else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+ else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
{
return SDMMC_ERROR_ILLEGAL_CMD;
}
- else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+ else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
{
return SDMMC_ERROR_COM_CRC_FAILED;
}
@@ -1520,12 +1523,12 @@
* @param hsd: SD handle
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
{
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1534,10 +1537,10 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
@@ -1545,7 +1548,7 @@
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
@@ -1557,7 +1560,7 @@
/* Nothing to do */
}
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
@@ -1571,6 +1574,41 @@
* @}
*/
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Checks for error conditions for CMD0.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @}
+ */
+
#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
/**
* @}
diff --git a/Src/stm32h7xx_ll_spi.c b/Src/stm32h7xx_ll_spi.c
index 44a95c1..57f63a7 100644
--- a/Src/stm32h7xx_ll_spi.c
+++ b/Src/stm32h7xx_ll_spi.c
@@ -371,6 +371,12 @@
LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
}
+ /* Checks to setup Internal SS signal to the active level in Slave Mode */
+ if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_SLAVE))
+ {
+ LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
+ }
+
/*---------------------------- SPIx CFG2 Configuration ------------------------
* Configure SPIx CFG2 with parameters:
* - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
@@ -656,7 +662,7 @@
i2sdiv = tmp / 2UL;
}
- /* Test if the obtain values are forbiden or out of range */
+ /* Test if the obtain values are forbidden or out of range */
if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
{
/* Set the default values */
diff --git a/Src/stm32h7xx_ll_usart.c b/Src/stm32h7xx_ll_usart.c
index cd044ca..2dc28f0 100644
--- a/Src/stm32h7xx_ll_usart.c
+++ b/Src/stm32h7xx_ll_usart.c
@@ -66,9 +66,6 @@
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
-#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
@@ -231,8 +228,9 @@
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@@ -283,7 +281,8 @@
/*---------------------------- USART CR3 Configuration ---------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ * USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
@@ -356,9 +355,6 @@
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-
- /* Check BRR is lower than or equal to 0xFFFF */
- assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
/*---------------------------- USART PRESC Configuration -----------------------
@@ -395,13 +391,15 @@
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - SUCCESS: USART registers related to Clock settings are initialized according
+ * to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
@@ -416,37 +414,25 @@
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
- /*---------------------------- USART CR2 Configuration -----------------------*/
- /* If Clock signal has to be output */
- if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
- {
- /* Deactivate Clock signal delivery :
- * - Disable Clock Output: USART_CR2_CLKEN cleared
- */
- LL_USART_DisableSCLKOutput(USARTx);
- }
- else
- {
- /* Ensure USART instance is USART capable */
- assert_param(IS_USART_INSTANCE(USARTx));
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
- /* Check clock related parameters */
- assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
- assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
- assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Clock signal related bits) with parameters:
- * - Enable Clock Output: USART_CR2_CLKEN set
- * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
- * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
- * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
- */
- MODIFY_REG(USARTx->CR2,
- USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
- USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
- }
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
/* Else (USART not in Disabled state => return ERROR */
else
@@ -467,9 +453,12 @@
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
- USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
}
/**
diff --git a/Src/stm32h7xx_ll_usb.c b/Src/stm32h7xx_ll_usb.c
index 986ba4f..4894066 100644
--- a/Src/stm32h7xx_ll_usb.c
+++ b/Src/stm32h7xx_ll_usb.c
@@ -61,8 +61,8 @@
*/
/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization/de-initialization functions #####
@@ -96,7 +96,8 @@
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
}
- /* Reset after a PHY select */
+
+ /* Reset after a PHY select */
ret = USB_CoreReset(USBx);
}
else /* FS interface (embedded Phy) */
@@ -104,7 +105,7 @@
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
- /* Reset after a PHY select and set Host mode */
+ /* Reset after a PHY select */
ret = USB_CoreReset(USBx);
if (cfg.battery_charging_enable == 0U)
@@ -121,6 +122,10 @@
if (cfg.dma_enable == 1U)
{
+ /* make sure to reserve 18 fifo Locations for DMA buffers */
+ USBx->GDFIFOCFG &= ~(0xFFFFU << 16);
+ USBx->GDFIFOCFG |= 0x3EEU << 16;
+
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
}
@@ -229,7 +234,7 @@
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
@@ -237,13 +242,12 @@
}
/**
- * @brief USB_SetCurrentMode : Set functional mode
+ * @brief USB_SetCurrentMode Set functional mode
* @param USBx Selected device
- * @param mode current core mode
+ * @param mode current core mode
* This parameter can be one of these values:
- * @arg USB_DEVICE_MODE: Peripheral mode
- * @arg USB_HOST_MODE: Host mode
- * @arg USB_DRD_MODE: Dual Role Device mode
+ * @arg USB_DEVICE_MODE Peripheral mode
+ * @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
@@ -268,7 +272,7 @@
}
/**
- * @brief USB_DevInit : Initializes the USB_OTG controller registers
+ * @brief USB_DevInit Initializes the USB_OTG controller registers
* for device mode
* @param USBx Selected device
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
@@ -442,8 +446,7 @@
{
return HAL_TIMEOUT;
}
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
return HAL_OK;
}
@@ -465,8 +468,7 @@
{
return HAL_TIMEOUT;
}
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
return HAL_OK;
}
@@ -495,8 +497,8 @@
* @param USBx Selected device
* @retval speed device speed
* This parameter can be one of these values:
- * @arg PCD_SPEED_HIGH: High speed mode
- * @arg PCD_SPEED_FULL: Full speed mode
+ * @arg USBD_HS_SPEED: High speed mode
+ * @arg USBD_FS_SPEED: Full speed mode
*/
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
@@ -935,10 +937,11 @@
* 1 : DMA feature used
* @retval HAL status
*/
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+ uint8_t ch_ep_num, uint16_t len, uint8_t dma)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t *pSrc = (uint32_t *)src;
+ uint8_t *pSrc = src;
uint32_t count32b, i;
if (dma == 0U)
@@ -948,6 +951,9 @@
{
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
pSrc++;
+ pSrc++;
+ pSrc++;
+ pSrc++;
}
}
@@ -964,14 +970,34 @@
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t *pDest = (uint32_t *)dest;
+ uint8_t *pDest = dest;
+ uint32_t pData;
uint32_t i;
- uint32_t count32b = ((uint32_t)len + 3U) / 4U;
+ uint32_t count32b = (uint32_t)len >> 2U;
+ uint16_t remaining_bytes = len % 4U;
for (i = 0U; i < count32b; i++)
{
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
pDest++;
+ pDest++;
+ pDest++;
+ pDest++;
+ }
+
+ /* When Number of data is not word aligned, read the remaining byte */
+ if (remaining_bytes != 0U)
+ {
+ i = 0U;
+ __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
+
+ do
+ {
+ *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
+ i++;
+ pDest++;
+ remaining_bytes--;
+ } while (remaining_bytes != 0U);
}
return ((void *)pDest);
@@ -1095,7 +1121,7 @@
}
/**
- * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+ * @brief USB_DevConnect : Connect the USB device by enabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
@@ -1103,14 +1129,16 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
+ /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
- HAL_Delay(3U);
return HAL_OK;
}
/**
- * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
@@ -1118,8 +1146,10 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
+ /* In case phy is stopped, ensure to ungate and restore the phy CLK */
+ USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
+
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
- HAL_Delay(3U);
return HAL_OK;
}
@@ -1212,7 +1242,7 @@
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
* @param USBx Selected device
- * @param interrupt interrupt flag
+ * @param interrupt flag
* @retval None
*/
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
@@ -1304,8 +1334,7 @@
{
return HAL_TIMEOUT;
}
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
/* Core Soft Reset */
count = 0U;
@@ -1317,8 +1346,7 @@
{
return HAL_TIMEOUT;
}
- }
- while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
return HAL_OK;
}
@@ -1450,7 +1478,7 @@
}
/**
-* @brief USB_OTG_ResetPort : Reset Host Port
+ * @brief USB_OTG_ResetPort : Reset Host Port
* @param USBx Selected device
* @retval HAL status
* @note (1)The application must wait at least 10 ms
@@ -1479,10 +1507,10 @@
* @brief USB_DriveVbus : activate or de-activate vbus
* @param state VBUS state
* This parameter can be one of these values:
- * 0 : VBUS Active
- * 1 : VBUS Inactive
+ * 0 : Deactivate VBUS
+ * 1 : Activate VBUS
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1526,7 +1554,7 @@
* @brief Return Host Current Frame number
* @param USBx Selected device
* @retval current frame number
-*/
+ */
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1555,20 +1583,17 @@
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
* @param mps Max Packet Size
- * This parameter can be a value from 0 to32K
+ * This parameter can be a value from 0 to 32K
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
+ uint8_t epnum, uint8_t dev_address, uint8_t speed,
+ uint8_t ep_type, uint16_t mps)
{
HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t HCcharEpDir, HCcharLowSpeed;
+ uint32_t HostCoreSpeed;
/* Clear old interrupt conditions for this host channel. */
USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
@@ -1593,7 +1618,8 @@
{
if ((USBx->CID & (0x1U << 8)) != 0U)
{
- USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
+ USB_OTG_HCINTMSK_ACKM;
}
}
break;
@@ -1647,7 +1673,10 @@
HCcharEpDir = 0U;
}
- if (speed == HPRT0_PRTSPD_LOW_SPEED)
+ HostCoreSpeed = USB_GetHostSpeed(USBx);
+
+ /* LS device plugged to HUB */
+ if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
{
HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
}
@@ -1683,7 +1712,7 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)hc->ch_num;
- static __IO uint32_t tmpreg = 0U;
+ __IO uint32_t tmpreg;
uint8_t is_oddframe;
uint16_t len_words;
uint16_t num_packets;
@@ -1691,20 +1720,20 @@
if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
{
+ /* in DMA mode host Core automatically issues ping in case of NYET/NAK */
+ if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)))
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
+ USB_OTG_HCINTMSK_ACKM |
+ USB_OTG_HCINTMSK_NAKM);
+ }
+
if ((dma == 0U) && (hc->do_ping == 1U))
{
(void)USB_DoPing(USBx, hc->ch_num);
return HAL_OK;
}
- else if (dma == 1U)
- {
- USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
- hc->do_ping = 0U;
- }
- else
- {
- /* ... */
- }
+
}
/* Compute the expected number of packets associated to the transfer */
@@ -1715,20 +1744,29 @@
if (num_packets > max_hc_pkt_count)
{
num_packets = max_hc_pkt_count;
- hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
}
}
else
{
num_packets = 1U;
}
+
+ /*
+ * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
+ * max_packet size.
+ */
if (hc->ep_is_in != 0U)
{
- hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+ }
+ else
+ {
+ hc->XferSize = hc->xfer_len;
}
/* Initialize the HCTSIZn register */
- USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
+ USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
(((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
(((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
@@ -1758,45 +1796,47 @@
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
- if (dma == 0U) /* Slave mode */
+ if (dma != 0U) /* dma mode */
{
- if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+ return HAL_OK;
+ }
+
+ if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+ {
+ switch (hc->ep_type)
{
- switch (hc->ep_type)
- {
- /* Non periodic transfer */
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
+ /* Non periodic transfer */
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
- len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
- /* check if there is enough space in FIFO space */
- if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
- {
- /* need to process data in nptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
- }
- break;
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+ {
+ /* need to process data in nptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+ }
+ break;
- /* Periodic transfer */
- case EP_TYPE_INTR:
- case EP_TYPE_ISOC:
- len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
- /* check if there is enough space in FIFO space */
- if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
- {
- /* need to process data in ptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
- }
- break;
+ /* Periodic transfer */
+ case EP_TYPE_INTR:
+ case EP_TYPE_ISOC:
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+ {
+ /* need to process data in ptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+ }
+ break;
- default:
- break;
- }
-
- /* Write packet into the Tx FIFO. */
- (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
+ default:
+ break;
}
+
+ /* Write packet into the Tx FIFO. */
+ (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
}
return HAL_OK;
@@ -1827,29 +1867,38 @@
uint32_t hcnum = (uint32_t)hc_num;
uint32_t count = 0U;
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+ uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
+
+ if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
+ (ChannelEna == 0U))
+ {
+ return HAL_OK;
+ }
/* Check for space in the request queue to issue the halt. */
if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
- if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+ if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
{
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
+ if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
{
- if (++count > 1000U)
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+ do
{
- break;
- }
+ if (++count > 1000U)
+ {
+ break;
+ }
+ } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
- while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
- }
- else
- {
- USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ else
+ {
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ }
}
}
else
@@ -1867,8 +1916,7 @@
{
break;
}
- }
- while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
else
{
@@ -1948,8 +1996,7 @@
{
break;
}
- }
- while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
/* Clear any pending Host interrupts */
diff --git a/Src/stm32h7xx_ll_utils.c b/Src/stm32h7xx_ll_utils.c
index a24c6be..00c3975 100644
--- a/Src/stm32h7xx_ll_utils.c
+++ b/Src/stm32h7xx_ll_utils.c
@@ -272,7 +272,7 @@
* @note CPU_Frequency can be calculated thanks to RCC helper macro or function
* @ref LL_RCC_GetSystemClocksFreq
* LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
- * and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
+ * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency.
* @retval None
*/
#else
@@ -458,7 +458,7 @@
* @note CPU_Frequency can be calculated thanks to RCC helper macro or function
* @ref LL_RCC_GetSystemClocksFreq
* LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
- * and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
+ * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency.
* @retval None
*/
#else
