Release v1.10.1
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 93a925d..48aff55 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -38,6 +37,14 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+#if defined(STM32U5)
+#define CRYP_DATATYPE_32B CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
+#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
+#endif /* STM32U5 */
/**
* @}
*/
@@ -206,6 +213,20 @@
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/**
* @}
*/
@@ -235,11 +256,18 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -382,8 +410,6 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
-
-
/**
* @}
*/
@@ -471,15 +497,24 @@
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
#endif
#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U5 */
/**
* @}
@@ -522,6 +557,7 @@
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+
/**
* @}
*/
@@ -596,12 +632,12 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -617,6 +653,20 @@
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -854,6 +904,20 @@
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
+#endif /* STM32U5 */
/**
* @}
*/
@@ -1192,6 +1256,10 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
/**
* @}
*/
@@ -1380,6 +1448,20 @@
*/
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+ * @{
+ */
+#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+ for compatibility with legacy code */
+/**
+ * @}
+ */
+
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
+
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1398,6 +1480,29 @@
* @}
*/
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+ * @}
+ */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+ * @{
+ */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
+/**
+ *
+ * @}
+ */
+#endif /* STM32F2 */
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{
*/
@@ -3330,6 +3435,31 @@
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#endif
/**
* @}
@@ -3347,7 +3477,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3404,13 +3534,22 @@
* @}
*/
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
* @{
*/
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
+#endif
+
#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
@@ -3753,5 +3892,4 @@
#endif /* STM32_HAL_LEGACY */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index 4711b65..3ae73f0 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -8,13 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -54,4 +53,4 @@
#endif /* __STM32_ASSERT_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_hal.h b/Inc/stm32h7xx_hal.h
index 95a44bf..33af192 100644
--- a/Inc/stm32h7xx_hal.h
+++ b/Inc/stm32h7xx_hal.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1079,12 +1078,12 @@
#if defined(SYSCFG_CCCR_NCC_MMC)
void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
#endif /* SYSCFG_CCCR_NCC_MMC */
-void HAL_EnableDBGSleepMode(void);
-void HAL_DisableDBGSleepMode(void);
-void HAL_EnableDBGStopMode(void);
-void HAL_DisableDBGStopMode(void);
-void HAL_EnableDBGStandbyMode(void);
-void HAL_DisableDBGStandbyMode(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
#if defined(DUAL_CORE)
void HAL_EnableDomain2DBGSleepMode(void);
void HAL_DisableDomain2DBGSleepMode(void);
@@ -1140,4 +1139,4 @@
#endif /* STM32H7xx_HAL_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_hal_adc.h b/Inc/stm32h7xx_hal_adc.h
index 155aaa7..b9ec800 100644
--- a/Inc/stm32h7xx_hal_adc.h
+++ b/Inc/stm32h7xx_hal_adc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -131,8 +130,8 @@
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
- and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group,
- use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+ and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group,
+ use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
@@ -2032,4 +2031,3 @@
#endif /* STM32H7xx_HAL_ADC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_adc_ex.h b/Inc/stm32h7xx_hal_adc_ex.h
index ae18507..9e00e15 100644
--- a/Inc/stm32h7xx_hal_adc_ex.h
+++ b/Inc/stm32h7xx_hal_adc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -250,8 +249,10 @@
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#if defined(HRTIM1)
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
+#endif /* HRTIM1 */
#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */
@@ -1044,6 +1045,7 @@
* @param __INJTRIG__ programmed ADC injected conversions external trigger.
* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
*/
+#if defined (HRTIM1)
#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
@@ -1060,9 +1062,36 @@
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
\
((__INJTRIG__) == ADC_SOFTWARE_START) )
-
+#else
+#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
+ \
+ ((__INJTRIG__) == ADC_SOFTWARE_START) )
+#endif /* HRTIM */
/**
* @brief Verify the ADC edge trigger setting for injected group.
* @param __EDGE__ programmed ADC edge trigger setting.
@@ -1349,4 +1378,3 @@
#endif /* STM32H7xx_HAL_ADC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_cec.h b/Inc/stm32h7xx_hal_cec.h
index e4ff48d..dded758 100644
--- a/Inc/stm32h7xx_hal_cec.h
+++ b/Inc/stm32h7xx_hal_cec.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -121,14 +120,14 @@
* b6 Error information
* 0 : No Error
* 1 : Error
- * b5 IP initialization status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized. HAL CEC Init function already called)
+ * b5 CEC peripheral initialization status
+ * 0 : Reset (peripheral not initialized)
+ * 1 : Init done (peripheral initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -138,9 +137,9 @@
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initialization status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized)
+ * b5 CEC peripheral initialization status
+ * 0 : Reset (peripheral not initialized)
+ * 1 : Init done (peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -791,4 +790,3 @@
#endif /* STM32H7xxHAL_CEC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_comp.h b/Inc/stm32h7xx_hal_comp.h
index 1db50aa..ba42ed1 100644
--- a/Inc/stm32h7xx_hal_comp.h
+++ b/Inc/stm32h7xx_hal_comp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -951,4 +950,4 @@
#endif /* STM32H7xx_HAL_COMP_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_hal_conf_template.h b/Inc/stm32h7xx_hal_conf_template.h
index 05bf9c5..5740000 100644
--- a/Inc/stm32h7xx_hal_conf_template.h
+++ b/Inc/stm32h7xx_hal_conf_template.h
@@ -8,13 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -510,4 +509,4 @@
#endif /* STM32H7xx_HAL_CONF_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_hal_cordic.h b/Inc/stm32h7xx_hal_cordic.h
index 04e2d79..7f8d5d9 100644
--- a/Inc/stm32h7xx_hal_cordic.h
+++ b/Inc/stm32h7xx_hal_cordic.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -608,5 +607,3 @@
#endif
#endif /* STM32H7xx_HAL_CORDIC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_cortex.h b/Inc/stm32h7xx_hal_cortex.h
index 17b111c..2645c28 100644
--- a/Inc/stm32h7xx_hal_cortex.h
+++ b/Inc/stm32h7xx_hal_cortex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -458,4 +457,3 @@
#endif /* STM32H7xx_HAL_CORTEX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_crc.h b/Inc/stm32h7xx_hal_crc.h
index e1ebe4c..f41b123 100644
--- a/Inc/stm32h7xx_hal_crc.h
+++ b/Inc/stm32h7xx_hal_crc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -60,19 +59,22 @@
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
- X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
+ X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
- If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
+ CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
- 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
- If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
+ otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
- respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
- e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
- No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
+ respectively equal to 7, 8, 16 or 32. This field is written in normal,
+ representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
+ is written 0x65. No need to specify it if DefaultPolynomialUse is set to
+ DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@@ -87,14 +89,18 @@
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
- @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
- @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
- @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+ @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
+ becomes 0x58D43CB2
+ @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
+ 0x1A2B3C4D becomes 0xD458B23C
+ @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
+ becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
- @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
+ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
+ into 0x22CC4488 */
} CRC_InitTypeDef;
/**
@@ -112,12 +118,16 @@
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
- @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
- @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
- @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
+ (8-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
+ half-words (16-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
+ (32-bit data)
- Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
- must occur if InputBufferFormat is not one of the three values listed above */
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
+ error must occur if InputBufferFormat is not one of the three values listed
+ above */
} CRC_HandleTypeDef;
/**
* @}
@@ -199,15 +209,6 @@
* @}
*/
-/** @defgroup CRC_Aliases CRC API aliases
- * @{
- */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-/**
- * @}
- */
-
/**
* @}
*/
@@ -339,5 +340,3 @@
#endif
#endif /* STM32H7xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_crc_ex.h b/Inc/stm32h7xx_hal_crc_ex.h
index 0ca334f..bc70226 100644
--- a/Inc/stm32h7xx_hal_crc_ex.h
+++ b/Inc/stm32h7xx_hal_crc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -149,5 +148,3 @@
#endif
#endif /* STM32H7xx_HAL_CRC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_cryp.h b/Inc/stm32h7xx_hal_cryp.h
index 619c862..7692547 100644
--- a/Inc/stm32h7xx_hal_cryp.h
+++ b/Inc/stm32h7xx_hal_cryp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -565,4 +564,3 @@
#endif /* STM32H7xx_HAL_CRYP_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_cryp_ex.h b/Inc/stm32h7xx_hal_cryp_ex.h
index 117598a..8820e0b 100644
--- a/Inc/stm32h7xx_hal_cryp_ex.h
+++ b/Inc/stm32h7xx_hal_cryp_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -120,4 +119,3 @@
#endif /* STM32H7xx_HAL_CRYP_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dac.h b/Inc/stm32h7xx_hal_dac.h
index fb2ff1b..1c48323 100644
--- a/Inc/stm32h7xx_hal_dac.h
+++ b/Inc/stm32h7xx_hal_dac.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -79,17 +78,19 @@
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+
+
+ void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -136,9 +137,7 @@
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
-
} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -151,10 +150,12 @@
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
+
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
@@ -240,7 +241,9 @@
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
+
#define DAC_CHANNEL_2 0x00000010U
+
/**
* @}
*/
@@ -260,8 +263,10 @@
* @{
*/
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
+
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
+
/**
* @}
*/
@@ -270,8 +275,10 @@
* @{
*/
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
+
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
+
/**
* @}
*/
@@ -351,12 +358,14 @@
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
+
/** @brief Set DHR12R2 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
+
/** @brief Set DHR12RD alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
@@ -541,7 +550,5 @@
#endif
-#endif /*STM32H7xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32H7xx_HAL_DAC_H */
diff --git a/Inc/stm32h7xx_hal_dac_ex.h b/Inc/stm32h7xx_hal_dac_ex.h
index d1dbf4a..8fcd75a 100644
--- a/Inc/stm32h7xx_hal_dac_ex.h
+++ b/Inc/stm32h7xx_hal_dac_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -268,6 +267,5 @@
}
#endif
-#endif /*STM32H7xx_HAL_DAC_EX_H */
+#endif /* STM32H7xx_HAL_DAC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dcmi.h b/Inc/stm32h7xx_hal_dcmi.h
index 244fc27..e844fbb 100644
--- a/Inc/stm32h7xx_hal_dcmi.h
+++ b/Inc/stm32h7xx_hal_dcmi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -668,4 +667,3 @@
#endif /* STM32H7xx_HAL_DCMI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_def.h b/Inc/stm32h7xx_hal_def.h
index f7e3c13..69101d6 100644
--- a/Inc/stm32h7xx_hal_def.h
+++ b/Inc/stm32h7xx_hal_def.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -218,4 +217,4 @@
#endif /* STM32H7xx_HAL_DEF */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_hal_dfsdm.h b/Inc/stm32h7xx_hal_dfsdm.h
index 189efd0..bce3184 100644
--- a/Inc/stm32h7xx_hal_dfsdm.h
+++ b/Inc/stm32h7xx_hal_dfsdm.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -870,4 +869,3 @@
#endif /* STM32H7xx_HAL_DFSDM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dfsdm_ex.h b/Inc/stm32h7xx_hal_dfsdm_ex.h
index f9cd61c..6252deb 100644
--- a/Inc/stm32h7xx_hal_dfsdm_ex.h
+++ b/Inc/stm32h7xx_hal_dfsdm_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -90,4 +89,3 @@
#endif /* STM32H7xx_HAL_DFSDM_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dma.h b/Inc/stm32h7xx_hal_dma.h
index 7da4420..1c299d5 100644
--- a/Inc/stm32h7xx_hal_dma.h
+++ b/Inc/stm32h7xx_hal_dma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1324,4 +1323,3 @@
#endif /* STM32H7xx_HAL_DMA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dma2d.h b/Inc/stm32h7xx_hal_dma2d.h
index d5acb3f..00f205b 100644
--- a/Inc/stm32h7xx_hal_dma2d.h
+++ b/Inc/stm32h7xx_hal_dma2d.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -342,15 +341,6 @@
* @}
*/
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
- * @{
- */
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
- for compatibility with legacy code */
-/**
- * @}
- */
-
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D common Callback ID enumeration definition
@@ -723,6 +713,3 @@
#endif
#endif /* STM32H7xx_HAL_DMA2D_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dma_ex.h b/Inc/stm32h7xx_hal_dma_ex.h
index 481a204..cde5755 100644
--- a/Inc/stm32h7xx_hal_dma_ex.h
+++ b/Inc/stm32h7xx_hal_dma_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -309,4 +308,3 @@
#endif /* STM32H7xx_HAL_DMA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dsi.h b/Inc/stm32h7xx_hal_dsi.h
index 06d9ae5..ec36c46 100644
--- a/Inc/stm32h7xx_hal_dsi.h
+++ b/Inc/stm32h7xx_hal_dsi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -40,6 +39,9 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup DSI_Exported_Types DSI Exported Types
+ * @{
+ */
/**
* @brief DSI Init Structure definition
*/
@@ -61,14 +63,14 @@
*/
typedef struct
{
- uint32_t PLLNDIV; /*!< PLL Loop Division Factor
- This parameter must be a value between 10 and 125 */
+ uint32_t PLLNDIV; /*!< PLL Loop Division Factor
+ This parameter must be a value between 10 and 125 */
- uint32_t PLLIDF; /*!< PLL Input Division Factor
- This parameter can be any value of @ref DSI_PLL_IDF */
+ uint32_t PLLIDF; /*!< PLL Input Division Factor
+ This parameter can be any value of @ref DSI_PLL_IDF */
- uint32_t PLLODF; /*!< PLL Output Division Factor
- This parameter can be any value of @ref DSI_PLL_ODF */
+ uint32_t PLLODF; /*!< PLL Output Division Factor
+ This parameter can be any value of @ref DSI_PLL_ODF */
} DSI_PLLInitTypeDef;
@@ -346,6 +348,9 @@
typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DSI_Exported_Constants DSI Exported Constants
@@ -700,8 +705,8 @@
#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
-#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
- DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
+#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
+ DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
DSI_FLOW_CONTROL_EOTP_TX)
/**
* @}
@@ -841,18 +846,18 @@
* @{
*/
#define HAL_DSI_ERROR_NONE 0U
-#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
-#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
-#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
-#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
-#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
-#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
-#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
-#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
-#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
-#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
+#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */
+#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
+#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */
+#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */
+#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
+#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
+#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
+#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
+#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
+#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
-#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
+#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/**
* @}
@@ -912,6 +917,7 @@
* @}
*/
+
/**
* @}
*/
@@ -955,11 +961,11 @@
* @retval None.
*/
#define __HAL_DSI_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
- /* Delay after an DSI Host disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -968,11 +974,11 @@
* @retval None.
*/
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper enabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -981,11 +987,11 @@
* @retval None.
*/
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper disabling*/ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper disabling*/ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -994,11 +1000,11 @@
* @retval None.
*/
#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- /* Delay after an DSI PLL enabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1007,11 +1013,11 @@
* @retval None.
*/
#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- /* Delay after an DSI PLL disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1033,11 +1039,11 @@
* @retval None.
*/
#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
- /* Delay after an DSI regulator disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1121,23 +1127,41 @@
/** @defgroup DSI_Exported_Functions DSI Exported Functions
* @{
*/
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
-
-void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
-
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
pDSI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @defgroup DSI_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
@@ -1190,40 +1214,28 @@
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ * @{
+ */
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
-HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+
+/**
+ * @}
+ */
+
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
-/** @defgroup DSI_Private_Types DSI Private Types
- * @{
- */
-
-/**
- * @}
- */
-
/* Private defines -----------------------------------------------------------*/
-/** @defgroup DSI_Private_Defines DSI Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
/* Private variables ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Variables DSI Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
/* Private constants ---------------------------------------------------------*/
/** @defgroup DSI_Private_Constants DSI Private Constants
* @{
@@ -1249,45 +1261,73 @@
((ODF) == DSI_PLL_OUT_DIV2) || \
((ODF) == DSI_PLL_OUT_DIV4) || \
((ODF) == DSI_PLL_OUT_DIV8))
-#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
-#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\
+ || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\
+ || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
-#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
-#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
-#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
-#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\
+ || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
+#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
+ || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
+ || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
+ || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
((VideoModeType) == DSI_VID_MODE_BURST))
-#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
+#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\
+ || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
-#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
+#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\
+ || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
-#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
+#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\
+ || ((LPVActive) == DSI_LP_VACT_ENABLE))
#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
-#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
-#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
+#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\
+ || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
+#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\
+ || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
-#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
-#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
-#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
-#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
-#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
-#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
-#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
-#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
-#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
-#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
-#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
-#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
-#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
-#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
-#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
+#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\
+ || ((TEPolarity) == DSI_TE_FALLING_EDGE))
+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\
+ || ((AutomaticRefresh) == DSI_AR_ENABLE))
+#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\
+ || ((VSPolarity) == DSI_VSYNC_RISING))
+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\
+ || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\
+ || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\
+ || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
+#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\
+ || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
+#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\
+ || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
+#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\
+ || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
+#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\
+ || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
+#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\
+ || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
+#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\
+ || ((LP_GLW) == DSI_LP_GLW_ENABLE))
+#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\
+ || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
+#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\
+ || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
+#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\
+ || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
+#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\
+ || ((LP_DLW) == DSI_LP_DLW_ENABLE))
+#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\
+ || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
@@ -1299,10 +1339,14 @@
((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
-#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
+#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \
+ ((CommDelay) == DSI_SLEW_RATE_LPTX) || \
+ ((CommDelay) == DSI_HS_DELAY))
#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
-#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
-#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
+#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\
+ || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
+#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \
+ ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
((Timing) == DSI_TLPX_CLK ) || \
((Timing) == DSI_THS_EXIT ) || \
@@ -1317,24 +1361,6 @@
* @}
*/
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Functions DSI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
/**
* @}
*/
@@ -1349,5 +1375,3 @@
#endif
#endif /* STM32H7xx_HAL_DSI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_dts.h b/Inc/stm32h7xx_hal_dts.h
index 63815fb..f30de77 100644
--- a/Inc/stm32h7xx_hal_dts.h
+++ b/Inc/stm32h7xx_hal_dts.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -480,4 +479,3 @@
#endif /* __STM32H7xx_HAL_DTS_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_eth.h b/Inc/stm32h7xx_hal_eth.h
index 354ce3f..345e803 100644
--- a/Inc/stm32h7xx_hal_eth.h
+++ b/Inc/stm32h7xx_hal_eth.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1684,4 +1683,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_eth_ex.h b/Inc/stm32h7xx_hal_eth_ex.h
index cec3887..f286d00 100644
--- a/Inc/stm32h7xx_hal_eth_ex.h
+++ b/Inc/stm32h7xx_hal_eth_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -354,4 +353,3 @@
#endif /* STM32H7xx_HAL_ETH_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_exti.h b/Inc/stm32h7xx_hal_exti.h
index f31cacf..91d7d95 100644
--- a/Inc/stm32h7xx_hal_exti.h
+++ b/Inc/stm32h7xx_hal_exti.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -536,4 +535,3 @@
#endif /* STM32H7xx_HAL_EXTI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_fdcan.h b/Inc/stm32h7xx_hal_fdcan.h
index ecc6290..c74096f 100644
--- a/Inc/stm32h7xx_hal_fdcan.h
+++ b/Inc/stm32h7xx_hal_fdcan.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -479,7 +478,7 @@
This parameter can be a value of @ref FDCAN_TT_time_master */
uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
- numerator : TUR = (Numerator ± SDL) / Denominator.
+ numerator : TUR = (Numerator +/- SDL) / Denominator.
With : SDL = 2^(SyncDevLimit+5).
This parameter must be a number between 0 and 7 */
@@ -514,7 +513,7 @@
This parameter is ignored if OperationMode is set to
FDCAN_TT_COMMUNICATION_LEVEL0 */
- uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix.
+ uint32_t BasicCyclesNbr; /*!< Specifies the number of basic cycles in the system matrix.
This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */
uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
@@ -529,7 +528,7 @@
This parameter must be a number between 0 and 4095 */
uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator.
- It is adviced to set this parameter to the largest applicable value.
+ It is advised to set this parameter to the largest applicable value.
This parameter must be a number between 0x10000 and 0x1FFFF */
uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator.
@@ -641,7 +640,7 @@
- 0 : No Gap in schedule
- 1 : Gap time after Basic Cycle has started */
- uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced.
+ uint32_t WaitForEvt; /*!< Specifies whether a Gap is announced.
This parameter can be:
- 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
- 1 : Reference message with Next_is_Gap = 1 received */
@@ -1259,21 +1258,21 @@
* @{
*/
#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
-#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */
-#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */
-#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */
-#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */
-#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */
-#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */
-#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */
-#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */
-#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
-#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
-#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
-#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
-#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
-#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
-#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */
+#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */
+#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */
+#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */
+#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */
+#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */
+#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */
+#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
/**
* @}
*/
@@ -2414,4 +2413,3 @@
#endif /* STM32H7xx_HAL_FDCAN_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_flash.h b/Inc/stm32h7xx_hal_flash.h
index 8a47e0b..a4773b5 100644
--- a/Inc/stm32h7xx_hal_flash.h
+++ b/Inc/stm32h7xx_hal_flash.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -861,4 +859,3 @@
#endif /* STM32H7xx_HAL_FLASH_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_flash_ex.h b/Inc/stm32h7xx_hal_flash_ex.h
index 96119b9..f822f09 100644
--- a/Inc/stm32h7xx_hal_flash_ex.h
+++ b/Inc/stm32h7xx_hal_flash_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -359,6 +357,8 @@
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
+
+/* Unused FLASH Latency defines */
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
@@ -1012,4 +1012,3 @@
#endif /* STM32H7xx_HAL_FLASH_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_fmac.h b/Inc/stm32h7xx_hal_fmac.h
index 8eb9941..25b760f 100644
--- a/Inc/stm32h7xx_hal_fmac.h
+++ b/Inc/stm32h7xx_hal_fmac.h
@@ -2,18 +2,16 @@
******************************************************************************
* @file stm32h7xx_hal_fmac.h
* @author MCD Application Team
- * @brief This file contains all the functions prototypes for the FMAC firmware
- * library.
+ * @brief Header for stm32h7xx_hal_fmac.c module
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -82,14 +80,16 @@
uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
- In case of early interruption of the filter operation, its value will be updated. */
+ In case of early interruption of the filter operation,
+ its value will be updated. */
int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
- In case of early interruption of the filter operation, its value will be updated. */
+ In case of early interruption of the filter operation,
+ its value will be updated. */
DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
@@ -136,7 +136,7 @@
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/**
- * @brief FMAC Callback ID structure definition
+ * @brief FMAC Callback ID enumeration definition
*/
typedef enum
{
@@ -165,33 +165,38 @@
typedef struct
{
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
- Ignored if InputBufferSize is set to 0 (previous configuration kept).
- NB: the buffers can overlap or even coincide exactly. */
+ Ignored if InputBufferSize is set to 0
+ (previous configuration kept).
+ Note: the buffers can overlap or even coincide exactly. */
- uint8_t InputBufferSize; /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
- in the buffer is inferior to this threshold.
- This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+ in the buffer is lower than this threshold.
+ This parameter can be a value
+ of @ref FMAC_Data_Buffer_Threshold. */
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
- Ignored if CoeffBufferSize is set to 0 (previous configuration kept).
- NB: the buffers can overlap or even coincide exactly. */
+ Ignored if CoeffBufferSize is set to 0
+ (previous configuration kept).
+ Note: the buffers can overlap or even coincide exactly. */
- uint8_t CoeffBufferSize; /*!< Number of 16-bit addresses allocated to the coefficient buffer.
+ uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
0 if a previous configuration should be kept. */
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
- Ignored if OuputBufferSize is set to 0 (previous configuration kept).
- NB: the buffers can overlap or even coincide exactly. */
+ Ignored if OuputBufferSize is set to 0
+ (previous configuration kept).
+ Note: the buffers can overlap or even coincide exactly. */
- uint8_t OutputBufferSize; /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
- in the buffer is inferior to this threshold.
- This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+ in the buffer is lower than this threshold.
+ This parameter can be a value
+ of @ref FMAC_Data_Buffer_Threshold. */
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
If not needed, it should be set to NULL. */
@@ -199,21 +204,25 @@
uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
- If not needed (re-use of a previously loaded buffer), it should be set to NULL. */
+ If not needed (re-use of a previously loaded buffer),
+ it should be set to NULL. */
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
- uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None.
+ uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
- uint32_t Clip; /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded).
+ uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping
+ is done when the clipping feature is disabled
+ and saturation is done when the clipping feature is enabled.
This parameter can be a value of @ref FMAC_Clip_State. */
uint32_t Filter; /*!< Filter type.
- This parameter can be a value of @ref FMAC_Functions (filter related values). */
+ This parameter can be a value
+ of @ref FMAC_Functions (filter related values). */
uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
@@ -238,17 +247,17 @@
/** @defgroup FMAC_Error_Code FMAC Error code
* @{
*/
-#define HAL_FMAC_ERROR_NONE 0x00000000UL /*!< No error */
-#define HAL_FMAC_ERROR_SAT 0x00000001UL /*!< Saturation error */
-#define HAL_FMAC_ERROR_UNFL 0x00000002UL /*!< Underflow error */
-#define HAL_FMAC_ERROR_OVFL 0x00000004UL /*!< Overflow error */
-#define HAL_FMAC_ERROR_DMA 0x00000008UL /*!< DMA error */
-#define HAL_FMAC_ERROR_RESET 0x00000010UL /*!< Reset error */
-#define HAL_FMAC_ERROR_PARAM 0x00000020UL /*!< Parameter error */
+#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
+#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
+#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
+#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
+#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
+#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
-#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040UL /*!< Invalid Callback error */
+#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
-#define HAL_FMAC_ERROR_TIMEOUT 0x00000080UL /*!< Timeout error */
+#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
/**
* @}
@@ -257,11 +266,11 @@
/** @defgroup FMAC_Functions FMAC Functions
* @{
*/
-#define FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
-#define FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
-#define FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
-#define FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
-#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
+#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
+#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
+#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
+#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
+#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
/**
* @}
*/
@@ -270,15 +279,19 @@
* @{
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
*/
-#define FMAC_THRESHOLD_1 0x00000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */
-#define FMAC_THRESHOLD_2 0x01000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */
-#define FMAC_THRESHOLD_4 0x02000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */
-#define FMAC_THRESHOLD_8 0x03000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */
-#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFUL /*!< The configured threshold value shouldn't be changed */
+#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 1. */
+#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 2. */
+#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 4. */
+#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 8. */
+#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
/**
* @}
*/
@@ -287,7 +300,7 @@
* @{
*/
#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
-#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through the FMAC DMA */
+#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
/**
@@ -297,7 +310,7 @@
/** @defgroup FMAC_Clip_State FMAC Clip State
* @{
*/
-#define FMAC_CLIP_DISABLED 0x00000000UL /*!< Clipping disabled */
+#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
/**
* @}
@@ -327,52 +340,20 @@
* @}
*/
-/** @defgroup FMAC_DMAR DMA Read Request Enable bit
+/**
+ * @}
+ */
+
+
+/* External variables --------------------------------------------------------*/
+/** @defgroup FMAC_External_variables FMAC External variables
* @{
*/
-#define FMAC_DMA_REN FMAC_CR_DMAREN /*!< DMA Read Requests Enable */
/**
* @}
*/
-/** @defgroup FMAC_DMAW DMA Write Request Enable bit
- * @{
- */
-#define FMAC_DMA_WEN FMAC_CR_DMAWEN /*!< DMA Write Channel Enable */
-/**
- * @}
- */
-
-/** @defgroup FMAC_DMAS DMA START bit
- * @{
- */
-#define FMAC_START FMAC_PARAM_START /*!< DMA Start */
-/**
- * @}
- */
-
-/** @defgroup FMAC_TimeOut_Value FMAC polling-based communications time-out value
- * @{
- */
-#define HAL_FMAC_TIMEOUT_VALUE 1000UL /*!< FMAC polling-based communications time-out value */
-/**
- * @}
- */
-
-/** @defgroup FMAC_Reset_TimeOut_Value FMAC reset time-out value
- * @{
- */
-#define HAL_FMAC_RESET_TIMEOUT_VALUE 500UL /*!< FMAC reset time-out value */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
* @{
*/
@@ -392,10 +373,10 @@
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
/**
- * @brief Enable the FMAC interrupt when result is ready
+ * @brief Enable the specified FMAC interrupt
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC Interrupt.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_IT_RIEN Read interrupt enable
* @arg @ref FMAC_IT_WIEN Write interrupt enable
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
@@ -410,7 +391,7 @@
* @brief Disable the FMAC interrupt
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC Interrupt.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_IT_RIEN Read interrupt enable
* @arg @ref FMAC_IT_WIEN Write interrupt enable
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
@@ -424,7 +405,7 @@
/** @brief Check whether the specified FMAC interrupt occurred or not.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to check.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
@@ -446,7 +427,7 @@
/** @brief Check whether the specified FMAC status flag is set or not.
* @param __HANDLE__ FMAC handle.
* @param __FLAG__ FMAC flag to check.
- * This parameter can be one of the following values:
+ * This parameter can be any combination of the following values:
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
@@ -483,8 +464,8 @@
* @}
*/
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup FMAC_Private_Macros
+/* Private Macros-----------------------------------------------------------*/
+/** @addtogroup FMAC_Private_Macros FMAC Private Macros
* @{
*/
@@ -500,7 +481,7 @@
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
/**
- * @brief Verify the FMAC load function.
+ * @brief Verify the FMAC load function used for input data, output data or coefficients.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
@@ -509,7 +490,7 @@
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
/**
- * @brief Verify the FMAC load function.
+ * @brief Verify the FMAC load function used with N values as input or output data.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
@@ -517,7 +498,7 @@
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
/**
- * @brief Verify the FMAC load function.
+ * @brief Verify the FMAC load function used with N + M values as coefficients.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
@@ -593,6 +574,21 @@
((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
/**
+ * @brief Check whether the threshold is applicable.
+ * @param __SIZE__ Size of the matching buffer.
+ * @param __WM__ Watermark value.
+ * @param __ACCESS__ Access to the buffer (polling, it, dma, none).
+ * @retval THRESHOLD
+ */
+#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
+ (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
+ ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
+ ((__WM__) == FMAC_THRESHOLD_1))|| \
+ ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+
+/**
* @}
*/
@@ -624,8 +620,8 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
-HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize);
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
@@ -692,5 +688,3 @@
#endif
#endif /* STM32H7xx_HAL_FMAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_gfxmmu.h b/Inc/stm32h7xx_hal_gfxmmu.h
index 8248bed..819f3ea 100644
--- a/Inc/stm32h7xx_hal_gfxmmu.h
+++ b/Inc/stm32h7xx_hal_gfxmmu.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -450,4 +449,3 @@
#endif /* STM32H7xx_HAL_GFXMMU_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_gpio.h b/Inc/stm32h7xx_hal_gpio.h
index 52f8ecd..1cd9178 100644
--- a/Inc/stm32h7xx_hal_gpio.h
+++ b/Inc/stm32h7xx_hal_gpio.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -108,29 +107,26 @@
/** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode
- * Elements values convention: 0xX0yz00YZ
- * - X : GPIO mode or EXTI Mode
- * - y : External IT or Event trigger detection
- * - z : IO configuration on External IT or Event
- * - Y : Output type (Push Pull or Open Drain)
- * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * Elements values convention: 0x00WX00YZ
+ * - W : EXTI trigger detection on 3 bits
+ * - X : EXTI mode (IT or Event) on 2 bits
+ * - Y : Output type (Push Pull or Open Drain) on 1 bit
+ * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
-#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
+#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING (0x11110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING (0x11210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING (0x11310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define GPIO_MODE_EVT_RISING (0x11120000U) /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING (0x11220000U) /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING (0x11320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -286,7 +282,25 @@
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
-
+#define GPIO_MODE_Pos 0u
+#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
+#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
+#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
+#define MODE_AF (0x2uL << GPIO_MODE_Pos)
+#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos 4u
+#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos 16u
+#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
+#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
+#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos 20u
+#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
+#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos)
/**
* @}
*/
@@ -343,4 +357,3 @@
#endif /* STM32H7xx_HAL_GPIO_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_gpio_ex.h b/Inc/stm32h7xx_hal_gpio_ex.h
index dc56483..7a8edd3 100644
--- a/Inc/stm32h7xx_hal_gpio_ex.h
+++ b/Inc/stm32h7xx_hal_gpio_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -486,4 +485,3 @@
#endif /* STM32H7xx_HAL_GPIO_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_hash.h b/Inc/stm32h7xx_hal_hash.h
index 605ee83..15b1213 100644
--- a/Inc/stm32h7xx_hal_hash.h
+++ b/Inc/stm32h7xx_hal_hash.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -22,7 +21,7 @@
#define STM32H7xx_HAL_HASH_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,7 +50,7 @@
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
- uint8_t* pKey; /*!< The key is used only in HMAC operation. */
+ uint8_t *pKey; /*!< The key is used only in HMAC operation. */
} HASH_InitTypeDef;
@@ -66,7 +65,7 @@
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
-}HAL_HASH_StateTypeDef;
+} HAL_HASH_StateTypeDef;
/**
* @brief HAL phase structures definition
@@ -81,7 +80,7 @@
(step 2 consists in entering the message text) */
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
(step 3 consists in entering the outer hash function key) */
-}HAL_HASH_PhaseTypeDef;
+} HAL_HASH_PhaseTypeDef;
/**
* @brief HAL HASH mode suspend definitions
@@ -90,7 +89,7 @@
{
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
-}HAL_HASH_SuspendTypeDef;
+} HAL_HASH_SuspendTypeDef;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
/**
@@ -103,7 +102,7 @@
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
-}HAL_HASH_CallbackIDTypeDef;
+} HAL_HASH_CallbackIDTypeDef;
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -155,15 +154,15 @@
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
+ void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
- void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
+ void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
- void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
+ void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
- void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
+ void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
- void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+ void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
} HASH_HandleTypeDef;
@@ -172,7 +171,7 @@
/**
* @brief HAL HASH Callback pointer definition
*/
-typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
@@ -247,13 +246,6 @@
/**
* @}
*/
-/** @defgroup HASH_alias HASH API alias
- * @{
- */
-#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
-/**
- * @}
- */
/** @defgroup HASH_Error_Definition HASH Error Definition
* @{
@@ -288,8 +280,8 @@
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
- ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
/** @brief Clear the specified HASH flag.
@@ -366,7 +358,7 @@
* @brief Set the number of valid bits in the last word written in data register DIN.
* @param __SIZE__ size in bytes of last data written in Data register.
* @retval None
-*/
+ */
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
/**
@@ -389,8 +381,8 @@
* @retval Digest length
*/
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
- ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
/**
* @brief Return number of words already pushed in the FIFO.
* @retval Number of words already pushed in the FIFO
@@ -424,7 +416,8 @@
* @param __SIZE__ input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
+ || (((__SIZE__) % 4U) == 0U))
/**
* @brief Ensure that handle phase is set to HASH processing.
* @param __HANDLE__ HASH handle.
@@ -467,7 +460,8 @@
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
@@ -482,12 +476,16 @@
/* HASH processing using polling *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
@@ -499,12 +497,16 @@
*/
/* HASH processing using IT **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
@@ -516,9 +518,9 @@
/* HASH processing using DMA *************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -529,8 +531,10 @@
*/
/* HASH-MAC processing using polling *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout);
/**
* @}
@@ -540,8 +544,10 @@
* @{
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -567,8 +573,8 @@
/* Peripheral State methods **************************************************/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
@@ -588,14 +594,18 @@
*/
/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
/**
@@ -618,4 +628,3 @@
#endif /* STM32H7xx_HAL_HASH_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_hash_ex.h b/Inc/stm32h7xx_hal_hash_ex.h
index 2d8459d..78fc650 100644
--- a/Inc/stm32h7xx_hal_hash_ex.h
+++ b/Inc/stm32h7xx_hal_hash_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -22,7 +21,7 @@
#define STM32H7xx_HAL_HASH_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -51,12 +50,16 @@
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -66,12 +69,16 @@
* @{
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -81,9 +88,9 @@
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
@@ -92,8 +99,10 @@
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout);
/**
* @}
*/
@@ -102,8 +111,10 @@
* @{
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer);
/**
* @}
@@ -162,4 +173,3 @@
#endif /* STM32H7xx_HAL_HASH_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_hcd.h b/Inc/stm32h7xx_hal_hcd.h
index 8286262..6443015 100644
--- a/Inc/stm32h7xx_hal_hcd.h
+++ b/Inc/stm32h7xx_hal_hcd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -111,11 +110,16 @@
#define HCD_SPEED_HIGH USBH_HS_SPEED
#define HCD_SPEED_FULL USBH_FSLS_SPEED
#define HCD_SPEED_LOW USBH_FSLS_SPEED
+/**
+ * @}
+ */
+/** @defgroup HCD_Device_Speed HCD Device Speed
+ * @{
+ */
#define HCD_DEVICE_SPEED_HIGH 0U
#define HCD_DEVICE_SPEED_FULL 1U
#define HCD_DEVICE_SPEED_LOW 2U
-
/**
* @}
*/
@@ -153,7 +157,8 @@
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
@@ -296,11 +301,11 @@
/* Private functions prototypes ----------------------------------------------*/
/**
- * @}
- */
+ * @}
+ */
/**
- * @}
- */
+ * @}
+ */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus
@@ -308,5 +313,3 @@
#endif
#endif /* STM32H7xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_hrtim.h b/Inc/stm32h7xx_hal_hrtim.h
index 798ad82..4b418f2 100644
--- a/Inc/stm32h7xx_hal_hrtim.h
+++ b/Inc/stm32h7xx_hal_hrtim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -996,7 +995,7 @@
/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
* @{
* @brief Constants defining the events that can be selected to configure the
- * set crossbar of a timer output
+ * reset crossbar of a timer output
*/
#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
@@ -1010,15 +1009,15 @@
#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
@@ -1137,21 +1136,21 @@
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
/**
* @}
*/
@@ -1346,10 +1345,10 @@
* @brief Constants defining the source and event to be sent on the
* synchronization outputs
*/
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
/**
* @}
*/
@@ -3642,5 +3641,3 @@
#endif
#endif /* STM32H7xx_HAL_HRTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_hsem.h b/Inc/stm32h7xx_hal_hsem.h
index df57b77..45f6e07 100644
--- a/Inc/stm32h7xx_hal_hsem.h
+++ b/Inc/stm32h7xx_hal_hsem.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -130,12 +129,12 @@
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
-/* HSEM Check semaphore state Taken or not **********************************/
-uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
/* HSEM Release **************************************************************/
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
/* HSEM Release All************************************************************/
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
+/* HSEM Check semaphore state Taken or not **********************************/
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
/**
* @}
@@ -210,5 +209,3 @@
#endif
#endif /* STM32H7xx_HAL_HSEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_i2c.h b/Inc/stm32h7xx_hal_i2c.h
index 9962ac1..0b882ac 100644
--- a/Inc/stm32h7xx_hal_i2c.h
+++ b/Inc/stm32h7xx_hal_i2c.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -48,29 +47,30 @@
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter calculated by referring to I2C initialization
- section in Reference manual */
+ This parameter calculated by referring to I2C initialization section
+ in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
+ This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
- This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+ This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
+ This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
+ mode is selected.
+ This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
@@ -200,7 +200,8 @@
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
- HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
+ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+ /*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
@@ -217,20 +218,32 @@
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
- void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
- void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
- void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
- void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
- void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
- void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
- void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
- void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Error callback */
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Abort callback */
- void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+ /*!< I2C Slave Address Match callback */
- void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
- void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+ /*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
@@ -259,8 +272,11 @@
/**
* @brief HAL I2C Callback pointer definition
*/
-typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
-typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
+/*!< pointer to an I2C callback function */
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
+ uint16_t AddrMatchCode);
+/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
@@ -440,14 +456,14 @@
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
@@ -542,26 +558,27 @@
*
* @retval None
*/
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
+ ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+ ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
-#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
-#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
@@ -601,12 +618,14 @@
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
@@ -757,10 +776,14 @@
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
- (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+ I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+ I2C_CR2_RD_WRN)))
-#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
-#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
+ >> 16U))
+#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
+ >> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
@@ -772,10 +795,15 @@
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+ (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
+ (~I2C_CR2_RD_WRN)))
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
@@ -805,5 +833,3 @@
#endif /* STM32H7xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_i2c_ex.h b/Inc/stm32h7xx_hal_i2c_ex.h
index 7909980..e701b8b 100644
--- a/Inc/stm32h7xx_hal_i2c_ex.h
+++ b/Inc/stm32h7xx_hal_i2c_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -67,7 +66,7 @@
#define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */
#else
#define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */
-#endif
+#endif /* SYSCFG_PMCR_I2C5_FMP */
/**
* @}
*/
@@ -90,7 +89,7 @@
* @{
*/
-/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
+/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
@@ -100,7 +99,7 @@
* @}
*/
-/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
@@ -109,7 +108,7 @@
* @}
*/
-/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
@@ -118,7 +117,6 @@
* @}
*/
-
/**
* @}
*/
@@ -141,7 +139,6 @@
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
@@ -150,28 +147,6 @@
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
-#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
-#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
-#elif defined(SYSCFG_PMCR_I2C1_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
-#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
/**
* @}
*/
@@ -198,5 +173,3 @@
#endif
#endif /* STM32H7xx_HAL_I2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_i2s.h b/Inc/stm32h7xx_hal_i2s.h
index 66762f4..060f5b6 100644
--- a/Inc/stm32h7xx_hal_i2s.h
+++ b/Inc/stm32h7xx_hal_i2s.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -122,7 +121,7 @@
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
-
+
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
@@ -324,12 +323,12 @@
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
-#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
-#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
-#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
-#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
-#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
-#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
+#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
+#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
+#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
+#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
+#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
+#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
/**
@@ -357,7 +356,7 @@
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
@@ -415,7 +414,8 @@
* @arg I2S_IT_ERR : Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
@@ -469,7 +469,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
@@ -498,7 +499,7 @@
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
- uint16_t Size);
+ uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
@@ -557,7 +558,9 @@
* @arg I2S_FLAG_FRE : TI mode frame format error flag
* @retval SET or RESET.
*/
-#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
+ & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\
+ ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __IER__ copy of I2S IER register.
@@ -571,7 +574,8 @@
* @arg I2S_IT_ERR : Error interrupt enable
* @retval SET or RESET.
*/
-#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__)\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
@@ -592,9 +596,9 @@
#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
-
+
#define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
- ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
+ ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
@@ -612,7 +616,7 @@
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
- ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
((__CPOL__) == I2S_CPOL_HIGH))
@@ -648,4 +652,3 @@
#endif /* STM32H7xx_HAL_I2S_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_i2s_ex.h b/Inc/stm32h7xx_hal_i2s_ex.h
index 0f74507..231781d 100644
--- a/Inc/stm32h7xx_hal_i2s_ex.h
+++ b/Inc/stm32h7xx_hal_i2s_ex.h
@@ -6,17 +6,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
-
+
/**
******************************************************************************
===== I2S FULL DUPLEX FEATURE =====
@@ -25,4 +24,3 @@
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_irda.h b/Inc/stm32h7xx_hal_irda.h
index 869f840..f789217 100644
--- a/Inc/stm32h7xx_hal_irda.h
+++ b/Inc/stm32h7xx_hal_irda.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -126,7 +125,7 @@
IRDA_CLOCKSOURCE_D2PCLK1 = 0x11U, /*!< Domain2 PCLK1 clock source */
IRDA_CLOCKSOURCE_D2PCLK2 = 0x12U, /*!< Domain2 PCLK2 clock source */
IRDA_CLOCKSOURCE_PLL2Q = 0x14U, /*!< PLL2Q clock source */
- IRDA_CLOCKSOURCE_PLL3Q = 0x18U, /*!< PCLK2 clock source */
+ IRDA_CLOCKSOURCE_PLL3Q = 0x18U, /*!< PLL3Q clock source */
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
IRDA_CLOCKSOURCE_CSI = 0x08U, /*!< CSI clock source */
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
@@ -146,7 +145,7 @@
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
@@ -830,11 +829,11 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
@@ -893,4 +892,3 @@
#endif /* STM32H7xx_HAL_IRDA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_irda_ex.h b/Inc/stm32h7xx_hal_irda_ex.h
index c1a2f20..a7a1ea3 100644
--- a/Inc/stm32h7xx_hal_irda_ex.h
+++ b/Inc/stm32h7xx_hal_irda_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -647,4 +646,3 @@
#endif /* STM32H7xx_HAL_IRDA_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_iwdg.h b/Inc/stm32h7xx_hal_iwdg.h
index 93d3025..895c33b 100644
--- a/Inc/stm32h7xx_hal_iwdg.h
+++ b/Inc/stm32h7xx_hal_iwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -236,5 +235,3 @@
#endif
#endif /* STM32H7xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_jpeg.h b/Inc/stm32h7xx_hal_jpeg.h
index 16176c3..d2ecdf8 100644
--- a/Inc/stm32h7xx_hal_jpeg.h
+++ b/Inc/stm32h7xx_hal_jpeg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -652,4 +651,3 @@
#endif /* STM32H7xx_HAL_JPEG_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_lptim.h b/Inc/stm32h7xx_hal_lptim.h
index 7275614..eeeb225 100644
--- a/Inc/stm32h7xx_hal_lptim.h
+++ b/Inc/stm32h7xx_hal_lptim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -96,30 +95,30 @@
*/
typedef struct
{
- LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
+ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
- LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
+ LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
- LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
+ LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
- uint32_t OutputPolarity; /*!< Specifies the Output polarity.
- This parameter can be a value of @ref LPTIM_Output_Polarity */
+ uint32_t OutputPolarity; /*!< Specifies the Output polarity.
+ This parameter can be a value of @ref LPTIM_Output_Polarity */
- uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
- values is done immediately or after the end of current period.
- This parameter can be a value of @ref LPTIM_Updating_Mode */
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
+ values is done immediately or after the end of current period.
+ This parameter can be a value of @ref LPTIM_Updating_Mode */
- uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
- or each external event.
- This parameter can be a value of @ref LPTIM_Counter_Source */
+ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
+ or each external event.
+ This parameter can be a value of @ref LPTIM_Counter_Source */
- uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
- This parameter can be a value of @ref LPTIM_Input1_Source */
+ uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
+ This parameter can be a value of @ref LPTIM_Input1_Source */
- uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
- Note: This parameter is used only for encoder feature so is used only
- for LPTIM1 instance.
- This parameter can be a value of @ref LPTIM_Input2_Source */
+ uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
+ Note: This parameter is used only for encoder feature so is used only
+ for LPTIM1 instance.
+ This parameter can be a value of @ref LPTIM_Input2_Source */
} LPTIM_InitTypeDef;
/**
@@ -808,5 +807,3 @@
#endif
#endif /* STM32H7xx_HAL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_ltdc.h b/Inc/stm32h7xx_hal_ltdc.h
index 3785b57..17f73a8 100644
--- a/Inc/stm32h7xx_hal_ltdc.h
+++ b/Inc/stm32h7xx_hal_ltdc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -684,5 +683,3 @@
#endif
#endif /* STM32H7xx_HAL_LTDC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_ltdc_ex.h b/Inc/stm32h7xx_hal_ltdc_ex.h
index f95a18c..15e9adf 100644
--- a/Inc/stm32h7xx_hal_ltdc_ex.h
+++ b/Inc/stm32h7xx_hal_ltdc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -82,5 +81,3 @@
#endif
#endif /* STM32H7xx_HAL_LTDC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_mdios.h b/Inc/stm32h7xx_hal_mdios.h
index f4954b4..50c61f4 100644
--- a/Inc/stm32h7xx_hal_mdios.h
+++ b/Inc/stm32h7xx_hal_mdios.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -607,4 +606,3 @@
#endif /* STM32H7xx_HAL_MDIOS_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_mdma.h b/Inc/stm32h7xx_hal_mdma.h
index 2e5f8e1..a39cc0d 100644
--- a/Inc/stm32h7xx_hal_mdma.h
+++ b/Inc/stm32h7xx_hal_mdma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -867,4 +866,3 @@
#endif /* STM32H7xx_HAL_MDMA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_mmc.h b/Inc/stm32h7xx_hal_mmc.h
index db25542..f8f0daf 100644
--- a/Inc/stm32h7xx_hal_mmc.h
+++ b/Inc/stm32h7xx_hal_mmc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -64,15 +63,18 @@
*/
typedef uint32_t HAL_MMC_CardStateTypeDef;
-#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
-#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
-#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
-#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
-#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
-#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
-#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
-#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
-#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
+#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready (can't be checked by CMD13) */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
+#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
+#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
+#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
+#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
+#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
+#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */
+#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */
/**
* @}
*/
@@ -342,9 +344,9 @@
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
-#define eMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
+#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
+#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
+#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
@@ -729,6 +731,14 @@
* @}
*/
+/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
/* Private types -------------------------------------------------------------*/
/** @defgroup MMC_Private_Types MMC Private Types
* @{
@@ -812,5 +822,3 @@
#endif /* STM32H7xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_mmc_ex.h b/Inc/stm32h7xx_hal_mmc_ex.h
index 256f986..2157495 100644
--- a/Inc/stm32h7xx_hal_mmc_ex.h
+++ b/Inc/stm32h7xx_hal_mmc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -111,5 +110,3 @@
#endif /* STM32H7xx_HAL_MMCEx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_nand.h b/Inc/stm32h7xx_hal_nand.h
index 3141ec9..fdf845a 100644
--- a/Inc/stm32h7xx_hal_nand.h
+++ b/Inc/stm32h7xx_hal_nand.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -324,8 +323,10 @@
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \
- ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + \
+ (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize))) * \
+ ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
@@ -374,5 +375,3 @@
#endif
#endif /* STM32H7xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_nor.h b/Inc/stm32h7xx_hal_nor.h
index d614cb0..1ef78f4 100644
--- a/Inc/stm32h7xx_hal_nor.h
+++ b/Inc/stm32h7xx_hal_nor.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -323,5 +322,3 @@
#endif
#endif /* STM32H7xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_opamp.h b/Inc/stm32h7xx_hal_opamp.h
index 006ff5a..95a36b0 100644
--- a/Inc/stm32h7xx_hal_opamp.h
+++ b/Inc/stm32h7xx_hal_opamp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -455,4 +454,3 @@
#endif /* STM32H7xx_HAL_OPAMP_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_opamp_ex.h b/Inc/stm32h7xx_hal_opamp_ex.h
index 855ebc4..a08d563 100644
--- a/Inc/stm32h7xx_hal_opamp_ex.h
+++ b/Inc/stm32h7xx_hal_opamp_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -80,4 +79,3 @@
#endif /* STM32H7xx_HAL_OPAMP_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_ospi.h b/Inc/stm32h7xx_hal_ospi.h
index 6d7471f..1bcce97 100644
--- a/Inc/stm32h7xx_hal_ospi.h
+++ b/Inc/stm32h7xx_hal_ospi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -259,7 +258,7 @@
This parameter can be a value of @ref OSPIM_IOPort */
uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
This parameter can be a value of @ref OSPIM_IOPort */
- uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
+ uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
This parameter can be a value between 1 and 256 */
}OSPIM_CfgTypeDef;
@@ -1030,9 +1029,6 @@
#define IS_OSPI_CKCSHT(CLK_NB) ((CLK_NB) <= 7U)
-#define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
- ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
-
#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
@@ -1079,5 +1075,3 @@
#endif
#endif /* STM32H7xx_HAL_OSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_otfdec.h b/Inc/stm32h7xx_hal_otfdec.h
index 3a49ef2..4c58805 100644
--- a/Inc/stm32h7xx_hal_otfdec.h
+++ b/Inc/stm32h7xx_hal_otfdec.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -475,5 +474,4 @@
#endif /* STM32H7xx_HAL_OTFDEC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_pcd.h b/Inc/stm32h7xx_hal_pcd.h
index 7236566..e9c220b 100644
--- a/Inc/stm32h7xx_hal_pcd.h
+++ b/Inc/stm32h7xx_hal_pcd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -194,16 +193,20 @@
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+ *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
+ ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@@ -353,12 +356,13 @@
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
-
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
@@ -401,27 +405,27 @@
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#ifndef USB_OTG_DOEPINT_OTEPSPR
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
#ifndef USB_OTG_DOEPINT_NAK
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_NAK */
#ifndef USB_OTG_DOEPMSK_NAKM
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NAKM */
#ifndef USB_OTG_DOEPINT_STPKTRX
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_STPKTRX */
#ifndef USB_OTG_DOEPMSK_NYETM
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NYETM */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* Private macros ------------------------------------------------------------*/
@@ -447,5 +451,3 @@
#endif
#endif /* STM32H7xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_pcd_ex.h b/Inc/stm32h7xx_hal_pcd_ex.h
index babeda7..9cfa012 100644
--- a/Inc/stm32h7xx_hal_pcd_ex.h
+++ b/Inc/stm32h7xx_hal_pcd_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -23,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@@ -83,9 +82,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32H7xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_pssi.h b/Inc/stm32h7xx_hal_pssi.h
index cd50234..78d6fcc 100644
--- a/Inc/stm32h7xx_hal_pssi.h
+++ b/Inc/stm32h7xx_hal_pssi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -501,6 +500,3 @@
#endif
#endif /* STM32H7xx_HAL_PSSI_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_pwr.h b/Inc/stm32h7xx_hal_pwr.h
index 9dbf404..91a9054 100644
--- a/Inc/stm32h7xx_hal_pwr.h
+++ b/Inc/stm32h7xx_hal_pwr.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -808,4 +807,3 @@
#endif /* STM32H7xx_HAL_PWR_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_pwr_ex.h b/Inc/stm32h7xx_hal_pwr_ex.h
index 12f557a..61c7609 100644
--- a/Inc/stm32h7xx_hal_pwr_ex.h
+++ b/Inc/stm32h7xx_hal_pwr_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -788,4 +787,3 @@
#endif /* STM32H7xx_HAL_PWR_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_qspi.h b/Inc/stm32h7xx_hal_qspi.h
index 4379cbe..39eb5fa 100644
--- a/Inc/stm32h7xx_hal_qspi.h
+++ b/Inc/stm32h7xx_hal_qspi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -453,7 +452,7 @@
* @{
*/
/** @brief Reset QSPI handle state.
- * @param __HANDLE__ : QSPI handle.
+ * @param __HANDLE__ QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@@ -467,20 +466,20 @@
#endif
/** @brief Enable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __HANDLE__ specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __HANDLE__ specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -493,8 +492,8 @@
/** @brief Disable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -506,8 +505,8 @@
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -520,8 +519,8 @@
/**
* @brief Check whether the selected QSPI flag is set or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI flag to check.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
@@ -534,8 +533,8 @@
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
@@ -736,12 +735,10 @@
* @}
*/
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
+#endif /* defined(QUADSPI) */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_QSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_ramecc.h b/Inc/stm32h7xx_hal_ramecc.h
index 1046ca8..c15ca58 100644
--- a/Inc/stm32h7xx_hal_ramecc.h
+++ b/Inc/stm32h7xx_hal_ramecc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -355,4 +354,3 @@
#endif /* STM32H7xx_HAL_RAMECC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_rcc.h b/Inc/stm32h7xx_hal_rcc.h
index 6a589ee..9b4eb60 100644
--- a/Inc/stm32h7xx_hal_rcc.h
+++ b/Inc/stm32h7xx_hal_rcc.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -8265,4 +8263,3 @@
#endif /* STM32H7xx_HAL_RCC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_rcc_ex.h b/Inc/stm32h7xx_hal_rcc_ex.h
index a08e3db..590d486 100644
--- a/Inc/stm32h7xx_hal_rcc_ex.h
+++ b/Inc/stm32h7xx_hal_rcc_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -4475,4 +4473,3 @@
#endif /* STM32H7xx_HAL_RCC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_rng.h b/Inc/stm32h7xx_hal_rng.h
index fc4de1a..ed7fe5e 100644
--- a/Inc/stm32h7xx_hal_rng.h
+++ b/Inc/stm32h7xx_hal_rng.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -392,4 +391,3 @@
#endif /* STM32H7xx_HAL_RNG_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_rng_ex.h b/Inc/stm32h7xx_hal_rng_ex.h
index 1f7fc84..028f71e 100644
--- a/Inc/stm32h7xx_hal_rng_ex.h
+++ b/Inc/stm32h7xx_hal_rng_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -35,19 +34,19 @@
#if defined(RNG)
#if defined(RNG_CR_CONDRST)
-/** @defgroup RNGEx RNGEx
+/** @defgroup RNG_Ex RNG_Ex
* @brief RNG Extension HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
- * @brief RNGEx Exported types
+/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types
+ * @brief RNG_Ex Exported types
* @{
*/
/**
- * @brief RNGEX Configuration Structure definition
+ * @brief RNG_Ex Configuration Structure definition
*/
typedef struct
@@ -56,9 +55,9 @@
uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */
uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */
uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can
- be a value of @ref RNGEX_Clock_Divider_Factor */
+ be a value of @ref RNG_Ex_Clock_Divider_Factor */
uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a
- value of @ref RNGEX_NIST_Compliance */
+ value of @ref RNG_Ex_NIST_Compliance */
} RNG_ConfigTypeDef;
/**
@@ -66,11 +65,11 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants
+/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants
* @{
*/
-/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal
+/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal
* programmable divider acting on the incoming RNG clock
* @{
*/
@@ -109,7 +108,7 @@
* @}
*/
-/** @defgroup RNGEX_NIST_Compliance NIST Compliance configuration
+/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration
* @{
*/
#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/
@@ -124,7 +123,7 @@
*/
/* Private types -------------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Types RNGEx Private Types
+/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types
* @{
*/
@@ -133,7 +132,7 @@
*/
/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
+/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables
* @{
*/
@@ -142,7 +141,7 @@
*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants
* @{
*/
@@ -151,7 +150,7 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
+/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros
* @{
*/
@@ -188,7 +187,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
+/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions
* @{
*/
@@ -197,11 +196,11 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
+/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
* @{
*/
-/** @addtogroup RNGEx_Exported_Functions_Group1
+/** @addtogroup RNG_Ex_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
@@ -212,7 +211,7 @@
* @}
*/
-/** @addtogroup RNGEx_Exported_Functions_Group2
+/** @addtogroup RNG_Ex_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
@@ -245,6 +244,5 @@
#endif
-#endif /* STM32H7xx_HAL_RNGEX_H */
+#endif /* STM32H7xx_HAL_RNG_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_rtc.h b/Inc/stm32h7xx_hal_rtc.h
index 99c0dd1..9bebc96 100644
--- a/Inc/stm32h7xx_hal_rtc.h
+++ b/Inc/stm32h7xx_hal_rtc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -908,7 +907,7 @@
*/
#define __HAL_RTC_ALARM_EXTID2_DISABLE_EVENT() (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
@@ -983,7 +982,7 @@
* @retval None
*/
#define __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG() (EXTI_D2->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
-#endif
+#endif /* DUAL_CORE */
/**
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
* @retval None
@@ -1239,4 +1238,3 @@
#endif /* STM32H7xx_HAL_RTC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_rtc_ex.h b/Inc/stm32h7xx_hal_rtc_ex.h
index 833ae6f..f5798de 100644
--- a/Inc/stm32h7xx_hal_rtc_ex.h
+++ b/Inc/stm32h7xx_hal_rtc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -2090,4 +2089,3 @@
#endif /* STM32H7xx_HAL_RTC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_sai.h b/Inc/stm32h7xx_hal_sai.h
index 7db7eb8..892daa2 100644
--- a/Inc/stm32h7xx_hal_sai.h
+++ b/Inc/stm32h7xx_hal_sai.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -984,4 +983,3 @@
#endif /* STM32H7xx_HAL_SAI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_sai_ex.h b/Inc/stm32h7xx_hal_sai_ex.h
index d323c59..a946aea 100644
--- a/Inc/stm32h7xx_hal_sai_ex.h
+++ b/Inc/stm32h7xx_hal_sai_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -102,4 +101,3 @@
#endif /* STM32H7xx_HAL_SAI_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_sd.h b/Inc/stm32h7xx_hal_sd.h
index 83c97ab..d465de6 100644
--- a/Inc/stm32h7xx_hal_sd.h
+++ b/Inc/stm32h7xx_hal_sd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -298,7 +297,7 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
+/** @defgroup SD_Exported_Constants SD Exported Constants
* @{
*/
@@ -799,5 +798,3 @@
#endif /* STM32H7xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_sd_ex.h b/Inc/stm32h7xx_hal_sd_ex.h
index 9c71954..450e7df 100644
--- a/Inc/stm32h7xx_hal_sd_ex.h
+++ b/Inc/stm32h7xx_hal_sd_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -109,5 +108,3 @@
#endif /* stm32h7xx_HAL_SD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_sdram.h b/Inc/stm32h7xx_hal_sdram.h
index ba189d4..cee1ffd 100644
--- a/Inc/stm32h7xx_hal_sdram.h
+++ b/Inc/stm32h7xx_hal_sdram.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -235,5 +234,3 @@
#endif
#endif /* STM32H7xx_HAL_SDRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_smartcard.h b/Inc/stm32h7xx_hal_smartcard.h
index 1c7aee8..3aaaa7d 100644
--- a/Inc/stm32h7xx_hal_smartcard.h
+++ b/Inc/stm32h7xx_hal_smartcard.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -202,7 +201,7 @@
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
@@ -1345,13 +1344,13 @@
* @{
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -1403,4 +1402,3 @@
#endif /* STM32H7xx_HAL_SMARTCARD_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_smartcard_ex.h b/Inc/stm32h7xx_hal_smartcard_ex.h
index d6650a1..3910005 100644
--- a/Inc/stm32h7xx_hal_smartcard_ex.h
+++ b/Inc/stm32h7xx_hal_smartcard_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -335,4 +334,3 @@
#endif /* STM32H7xx_HAL_SMARTCARD_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_smbus.h b/Inc/stm32h7xx_hal_smbus.h
index 426760d..0a543d4 100644
--- a/Inc/stm32h7xx_hal_smbus.h
+++ b/Inc/stm32h7xx_hal_smbus.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -48,42 +47,43 @@
typedef struct
{
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
+ This parameter calculated by referring to SMBUS initialization section
+ in Reference manual */
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
- This parameter can be a value of @ref SMBUS_Analog_Filter */
+ This parameter can be a value of @ref SMBUS_Analog_Filter */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
+ This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
- This parameter can be a value of @ref SMBUS_addressing_mode */
+ This parameter can be a value of @ref SMBUS_addressing_mode */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+ This parameter can be a value of @ref SMBUS_dual_addressing_mode */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
+ This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref SMBUS_own_address2_masks. */
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
+ if dual addressing mode is selected
+ This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+ This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref SMBUS_nostretch_mode */
+ This parameter can be a value of @ref SMBUS_nostretch_mode */
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
- This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+ This parameter can be a value of @ref SMBUS_packet_error_check_mode */
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
- This parameter can be a value of @ref SMBUS_peripheral_mode */
+ This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
- (Enable bits and different timeout values)
- This parameter calculated by referring to SMBUS initialization
- section in Reference manual */
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to SMBUS initialization section
+ in Reference manual */
} SMBUS_InitTypeDef;
/**
* @}
@@ -102,7 +102,7 @@
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
-#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
*/
@@ -121,7 +121,7 @@
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
@@ -159,17 +159,26 @@
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
- void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
- void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
- void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
- void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
- void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
- void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
+ void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Error callback */
- void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
+ void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+ /*!< SMBUS Slave Address Match callback */
- void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
- void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
+ void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+ /*!< SMBUS Msp DeInit callback */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef;
@@ -195,8 +204,11 @@
/**
* @brief HAL SMBUS Callback pointer definition
*/
-typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
-typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
+typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
+/*!< pointer to an SMBUS callback function */
+typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+ uint16_t AddrMatchCode);
+/*!< pointer to an SMBUS Address Match callback function */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
@@ -358,9 +370,10 @@
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
-#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \
- SMBUS_IT_TXI)
-#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
+ SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
+ SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
/**
@@ -408,14 +421,14 @@
* @retval None
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-#endif
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -491,12 +504,14 @@
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
- (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+ (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+ ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
+ * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
@@ -509,7 +524,9 @@
*
* @retval None
*/
-#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
+ ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+ ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -574,43 +591,52 @@
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
- ((MODE) == SMBUS_AUTOEND_MODE) || \
- ((MODE) == SMBUS_SOFTEND_MODE) || \
- ((MODE) == SMBUS_SENDPEC_MODE) || \
- ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == SMBUS_SENDPEC_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
+ SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
- ((REQUEST) == SMBUS_GENERATE_START_READ) || \
- ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
- ((REQUEST) == SMBUS_FIRST_FRAME) || \
- ((REQUEST) == SMBUS_NEXT_FRAME) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
-#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
- (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
- (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
+ (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
+ I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+ I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+ I2C_CR2_RD_WRN)))
-#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+ (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+ (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & \
+ (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
+ (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
@@ -629,6 +655,7 @@
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
@@ -648,11 +675,14 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID,
pSMBUS_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID);
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+ pSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
@@ -678,10 +708,10 @@
* @{
*/
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
@@ -757,5 +787,3 @@
#endif /* STM32H7xx_HAL_SMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_spdifrx.h b/Inc/stm32h7xx_hal_spdifrx.h
index 66176ec..4d22787 100644
--- a/Inc/stm32h7xx_hal_spdifrx.h
+++ b/Inc/stm32h7xx_hal_spdifrx.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -602,5 +601,3 @@
#endif /* __STM32H7xx_HAL_SPDIFRX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_spi.h b/Inc/stm32h7xx_hal_spi.h
index fb4e2c5..b53b0b4 100644
--- a/Inc/stm32h7xx_hal_spi.h
+++ b/Inc/stm32h7xx_hal_spi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -63,7 +62,8 @@
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_Management */
+ This parameter can be a value of
+ @ref SPI_Slave_Select_Management */
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
@@ -81,40 +81,45 @@
This parameter can be a value of @ref SPI_CRC_Calculation */
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
+ This parameter must be an odd number between
+ Min_Data = 0 and Max_Data = 65535 */
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
This parameter can be a value of @ref SPI_CRC_length */
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
This parameter can be a value of @ref SPI_NSSP_Mode
- This mode is activated by the SSOM bit in the SPIx_CR2 register and
- it takes effect only if the SPI interface is configured as Motorola SPI
- master (FRF=0). */
+ This mode is activated by the SSOM bit in the SPIx_CR2 register
+ and it takes effect only if the SPI interface is configured
+ as Motorola SPI master (FRF=0). */
- uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is
- considered as active one.
+ uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal
+ (present on SS pin) is considered as active one.
This parameter can be a value of @ref SPI_NSS_Polarity */
uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref SPI_Fifo_Threshold */
- uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
- This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
+ uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for
+ the CRC calculation. This parameter can be a value of
+ @ref SPI_CRC_Calculation_Initialization_Pattern */
- uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
- This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
+ uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for
+ the CRC calculation. This parameter can be a value of
+ @ref SPI_CRC_Calculation_Initialization_Pattern */
- uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
- additionally between active edge of SS and first data transaction start in master mode.
+ uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle
+ periods, inserted additionally between active edge of SS
+ and first data transaction start in master mode.
This parameter can be a value of @ref SPI_Master_SS_Idleness */
- uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
- two consecutive data frames in master mode
- This parameter can be a value of @ref SPI_Master_InterData_Idleness */
+ uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods)
+ inserted between two consecutive data frames in master mode.
+ This parameter can be a value of
+ @ref SPI_Master_InterData_Idleness */
- uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management
- in order to avoid overrun condition.
+ uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode
+ and automatic management in order to avoid overrun condition.
This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
@@ -122,7 +127,6 @@
uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
This parameter can be a value of @ref SPI_IO_Swap */
-
} SPI_InitTypeDef;
/**
@@ -157,7 +161,7 @@
uint32_t Requested; /*!< SPI reload request */
} SPI_ReloadTypeDef;
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
/**
* @brief SPI handle Structure definition
@@ -195,12 +199,12 @@
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
__IO uint32_t ErrorCode; /*!< SPI Error code */
-
+
#if defined(USE_SPI_RELOAD_TRANSFER)
SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */
-
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+#endif /* USE_SPI_RELOAD_TRANSFER */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
@@ -270,14 +274,15 @@
#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */
#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */
#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */
#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */
#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */
#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */
-#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */
+#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */
#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */
+#define HAL_SPI_ERROR_RELOAD (0x00000800UL) /*!< Reload error */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
-#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */
+#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
@@ -569,16 +574,6 @@
* @}
*/
-/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
- * @{
- */
-#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
-#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
-#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
-/**
- * @}
- */
-
/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
* @{
*/
@@ -589,6 +584,16 @@
* @}
*/
+/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
+ * @{
+ */
+#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
+#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
+#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
+/**
+ * @}
+ */
+
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
@@ -633,10 +638,10 @@
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
*/
-#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
-#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
-#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
-#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
+#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
+#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
+#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
/**
* @}
*/
@@ -663,7 +668,7 @@
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI Handle.
@@ -726,7 +731,8 @@
* @arg SPI_IT_ERR : Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__: specifies the SPI Handle.
@@ -842,7 +848,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
@@ -859,17 +866,20 @@
uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
#if defined(USE_SPI_RELOAD_TRANSFER)
HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData,
+ uint8_t *pRxData, uint16_t Size);
+#endif /* USE_SPI_RELOAD_TRANSFER */
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
@@ -936,15 +946,13 @@
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
- ((MODE) == SPI_DIRECTION_2LINES)|| \
- ((MODE) == SPI_DIRECTION_1LINE) || \
- ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
- ((MODE) == SPI_DIRECTION_2LINES)|| \
- ((MODE) == SPI_DIRECTION_1LINE) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
((DATASIZE) == SPI_DATASIZE_31BIT) || \
@@ -1059,7 +1067,8 @@
((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
((LENGTH) == SPI_CRC_LENGTH_4BIT))
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL)
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL)
+
#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
@@ -1068,6 +1077,7 @@
#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
+
/**
* @}
*/
@@ -1089,4 +1099,3 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_spi_ex.h b/Inc/stm32h7xx_hal_spi_ex.h
index c9c579e..9e583fa 100644
--- a/Inc/stm32h7xx_hal_spi_ex.h
+++ b/Inc/stm32h7xx_hal_spi_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -37,8 +36,32 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Types SPIEx Exported Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPIEx_Exported_Functions
* @{
@@ -51,7 +74,11 @@
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+ uint32_t UnderrunBehaviour);
+/**
+ * @}
+ */
/**
* @}
*/
@@ -64,14 +91,9 @@
* @}
*/
-/**
- * @}
- */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_SPI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_sram.h b/Inc/stm32h7xx_hal_sram.h
index 6384026..4c17a6a 100644
--- a/Inc/stm32h7xx_hal_sram.h
+++ b/Inc/stm32h7xx_hal_sram.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -229,5 +228,3 @@
#endif
#endif /* STM32H7xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_swpmi.h b/Inc/stm32h7xx_hal_swpmi.h
index f41ac10..4180c71 100644
--- a/Inc/stm32h7xx_hal_swpmi.h
+++ b/Inc/stm32h7xx_hal_swpmi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -22,7 +21,7 @@
#define STM32H7xx_HAL_SWPMI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -62,7 +61,7 @@
uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
-}SWPMI_InitTypeDef;
+} SWPMI_InitTypeDef;
/**
@@ -78,7 +77,7 @@
HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_SWPMI_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_SWPMI_STATE_ERROR = 0x04 /*!< Error */
-}HAL_SWPMI_StateTypeDef;
+} HAL_SWPMI_StateTypeDef;
/**
* @brief SWPMI handle Structure definition
@@ -116,16 +115,16 @@
__IO uint32_t ErrorCode; /*!< SWPMI Error code */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
- void (*RxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */
- void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */
- void (*TxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */
- void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */
- void (*ErrorCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */
- void (*MspInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */
- void (*MspDeInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */
+ void (*RxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */
+ void (*RxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */
+ void (*TxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */
+ void (*TxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */
+ void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */
+ void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */
+ void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */
#endif
-}SWPMI_HandleTypeDef;
+} SWPMI_HandleTypeDef;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
/**
@@ -140,7 +139,7 @@
HAL_SWPMI_ERROR_CB_ID = 0x04U, /*!< SWPMI error callback ID */
HAL_SWPMI_MSPINIT_CB_ID = 0x05U, /*!< SWPMI MSP init callback ID */
HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U /*!< SWPMI MSP de-init callback ID */
-}HAL_SWPMI_CallbackIDTypeDef;
+} HAL_SWPMI_CallbackIDTypeDef;
/**
* @brief SWPMI callback pointer definition
@@ -298,7 +297,7 @@
/** @brief Check whether the specified SWPMI flag is set or not.
* @param __HANDLE__ specifies the SWPMI Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SWPMI_FLAG_RXBFF Receive buffer full flag.
* @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag.
@@ -318,7 +317,7 @@
/** @brief Clear the specified SWPMI ISR flag.
* @param __HANDLE__ specifies the SWPMI Handle.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg SWPMI_FLAG_RXBFF Receive buffer full flag.
* @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag.
@@ -516,5 +515,3 @@
#endif
#endif /* STM32H7xx_HAL_SWPMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_tim.h b/Inc/stm32h7xx_hal_tim.h
index 2e93e31..11a1165 100644
--- a/Inc/stm32h7xx_hal_tim.h
+++ b/Inc/stm32h7xx_hal_tim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -65,8 +64,10 @@
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
@@ -218,7 +219,8 @@
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ This parameter must be 0: When OCRef clear feature is used with ETR source,
+ ETR prescaler must be off */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef;
@@ -268,28 +270,36 @@
*/
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t BreakFilter; /*!< Specifies the break input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Break2State; /*!< TIM Break2 State
- This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
- uint32_t Break2Polarity; /*!< TIM Break2 input polarity
- This parameter can be a value of @ref TIM_Break2_Polarity */
- uint32_t Break2Filter; /*!< TIM break2 input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+ uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+ uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+ uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+ uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+#if defined(TIM_BDTR_BKBID)
+ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
+
+#endif /* TIM_BDTR_BKBID */
+ uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
+
+ uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+#if defined(TIM_BDTR_BKBID)
+ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
+
+#endif /* TIM_BDTR_BKBID */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
} TIM_BreakDeadTimeConfigTypeDef;
/**
@@ -660,10 +670,8 @@
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
@@ -884,6 +892,17 @@
/**
* @}
*/
+#if defined(TIM_BDTR_BKBID)
+
+/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
+#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
+/**
+ * @}
+ */
+#endif /*TIM_BDTR_BKBID */
/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
* @{
@@ -902,24 +921,34 @@
/**
* @}
*/
+#if defined(TIM_BDTR_BKBID)
+
+/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
+#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BKBID */
/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
- (if none of the break inputs BRK and BRK2 is active) */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/
-/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
* @{
*/
-#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
+#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
/**
* @}
*/
@@ -1218,7 +1247,8 @@
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+ * disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
@@ -1385,7 +1415,8 @@
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
- * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+ * in an atomic way.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
@@ -1412,8 +1443,8 @@
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+ * or Encoder mode.
*/
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
@@ -1427,7 +1458,8 @@
/**
* @brief Set the TIM Counter Register value on runtime.
- * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+ * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
+ * case of 32 bits counter TIM instance.
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
@@ -1489,7 +1521,8 @@
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+ * function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@@ -1888,12 +1921,24 @@
#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+#if defined(TIM_BDTR_BKBID)
+
+#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+#endif /* TIM_BDTR_BKBID */
#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
((__STATE__) == TIM_BREAK2_DISABLE))
#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+#if defined(TIM_BDTR_BKBID)
+
+#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+#endif /* TIM_BDTR_BKBID */
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
@@ -2072,13 +2117,19 @@
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \
- } while(0)
+ (__HANDLE__)->ChannelState[0] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[1] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[2] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[3] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[4] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelState[5] = \
+ (__CHANNEL_STATE__); \
+ } while(0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
@@ -2093,11 +2144,15 @@
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
- } while(0)
+ (__HANDLE__)->ChannelNState[0] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[1] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[2] = \
+ (__CHANNEL_STATE__); \
+ (__HANDLE__)->ChannelNState[3] = \
+ (__CHANNEL_STATE__); \
+ } while(0)
/**
* @}
@@ -2271,14 +2326,14 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
- uint32_t DataLength);
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
- uint32_t DataLength);
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -2376,5 +2431,3 @@
#endif
#endif /* STM32H7xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_tim_ex.h b/Inc/stm32h7xx_hal_tim_ex.h
index 6d15c05..026d01d 100644
--- a/Inc/stm32h7xx_hal_tim_ex.h
+++ b/Inc/stm32h7xx_hal_tim_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -73,8 +72,7 @@
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
-}
-TIMEx_BreakInputConfigTypeDef;
+} TIMEx_BreakInputConfigTypeDef;
#endif /* TIM_BREAK_INPUT_SUPPORT */
/**
@@ -143,8 +141,8 @@
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
-#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
-#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
+#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
+#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
/**
* @}
*/
@@ -163,8 +161,8 @@
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
-#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
+#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
/**
* @}
*/
@@ -172,8 +170,8 @@
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
/**
* @}
*/
@@ -468,6 +466,11 @@
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+#if defined(TIM_BDTR_BKBID)
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+#endif /* TIM_BDTR_BKBID */
/**
* @}
*/
@@ -502,7 +505,7 @@
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
@@ -526,5 +529,3 @@
#endif /* STM32H7xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_uart.h b/Inc/stm32h7xx_hal_uart.h
index 103cb1b..b20dec2 100644
--- a/Inc/stm32h7xx_hal_uart.h
+++ b/Inc/stm32h7xx_hal_uart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -217,7 +216,7 @@
UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
@@ -1141,10 +1140,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
} while(0U)
/** @brief Disable CTS flow control.
@@ -1160,10 +1159,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
} while(0U)
/** @brief Enable RTS flow control.
@@ -1179,10 +1178,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
} while(0U)
/** @brief Disable RTS flow control.
@@ -1198,10 +1197,10 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0U)
/**
* @}
@@ -1612,11 +1611,11 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
@@ -1707,8 +1706,6 @@
/* Prescaler Table used in BRR computation macros.
Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
extern const uint16_t UARTPrescTable[12];
-
-
/**
* @}
*/
@@ -1727,4 +1724,3 @@
#endif /* STM32H7xx_HAL_UART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_uart_ex.h b/Inc/stm32h7xx_hal_uart_ex.h
index eb437f3..b60f954 100644
--- a/Inc/stm32h7xx_hal_uart_ex.h
+++ b/Inc/stm32h7xx_hal_uart_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -867,4 +866,3 @@
#endif /* STM32H7xx_HAL_UART_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_usart.h b/Inc/stm32h7xx_hal_usart.h
index 6092ebe..2f80874 100644
--- a/Inc/stm32h7xx_hal_usart.h
+++ b/Inc/stm32h7xx_hal_usart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -127,7 +126,7 @@
USART_InitTypeDef Init; /*!< USART communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
uint16_t TxXferSize; /*!< USART Tx Transfer size */
@@ -1113,17 +1112,17 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
@@ -1175,4 +1174,3 @@
#endif /* STM32H7xx_HAL_USART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_usart_ex.h b/Inc/stm32h7xx_hal_usart_ex.h
index 7691326..4cf7061 100644
--- a/Inc/stm32h7xx_hal_usart_ex.h
+++ b/Inc/stm32h7xx_hal_usart_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -281,4 +280,3 @@
#endif /* STM32H7xx_HAL_USART_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_hal_wwdg.h b/Inc/stm32h7xx_hal_wwdg.h
index 061a62f..8f2e4dc 100644
--- a/Inc/stm32h7xx_hal_wwdg.h
+++ b/Inc/stm32h7xx_hal_wwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -192,7 +191,7 @@
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
+ * @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
@@ -305,5 +304,3 @@
#endif
#endif /* STM32H7xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_adc.h b/Inc/stm32h7xx_ll_adc.h
index f12b52a..b6f949f 100644
--- a/Inc/stm32h7xx_ll_adc.h
+++ b/Inc/stm32h7xx_ll_adc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1141,8 +1140,10 @@
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#if defined(HRTIM1)
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
+#endif /* HRTIM1 */
#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
@@ -2739,6 +2740,65 @@
}
/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Add paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Remove paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
+ * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
+ * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
* @}
*/
@@ -2927,7 +2987,7 @@
#elif defined(ADC_VER_V5_V90)
if (ADCx == ADC3)
{
- MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, (((Resolution & 0x10UL) | 0x08UL | (Resolution & 0x04UL)) & 0x00000018UL));
+ MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, ((__LL_ADC12_RESOLUTION_TO_ADC3(Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL));
}
else
{
@@ -8214,4 +8274,3 @@
#endif /* STM32H7xx_LL_ADC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_bdma.h b/Inc/stm32h7xx_ll_bdma.h
index 36910f2..996eb75 100644
--- a/Inc/stm32h7xx_ll_bdma.h
+++ b/Inc/stm32h7xx_ll_bdma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1817,6 +1816,10 @@
/**
* @brief Clear Channel 0 global interrupt flag.
+ * @note Do not Clear Channel 0 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0,
+ LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0
* @param BDMAx BDMA Instance
* @retval None
@@ -1828,6 +1831,10 @@
/**
* @brief Clear Channel 1 global interrupt flag.
+ * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
+ LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1
* @param BDMAx BDMA Instance
* @retval None
@@ -1839,6 +1846,10 @@
/**
* @brief Clear Channel 2 global interrupt flag.
+ * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
+ LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2
* @param BDMAx BDMA Instance
* @retval None
@@ -1850,6 +1861,10 @@
/**
* @brief Clear Channel 3 global interrupt flag.
+ * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
+ LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3
* @param BDMAx BDMA Instance
* @retval None
@@ -1861,6 +1876,10 @@
/**
* @brief Clear Channel 4 global interrupt flag.
+ * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
+ LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4
* @param BDMAx BDMA Instance
* @retval None
@@ -1872,6 +1891,10 @@
/**
* @brief Clear Channel 5 global interrupt flag.
+ * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
+ LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5
* @param BDMAx BDMA Instance
* @retval None
@@ -1883,6 +1906,10 @@
/**
* @brief Clear Channel 6 global interrupt flag.
+ * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
+ LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6
* @param BDMAx BDMA Instance
* @retval None
@@ -1894,6 +1921,10 @@
/**
* @brief Clear Channel 7 global interrupt flag.
+ * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
+ LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7
* @param BDMAx BDMA Instance
* @retval None
@@ -2417,4 +2448,3 @@
#endif /* STM32H7xx_LL_BDMA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_bus.h b/Inc/stm32h7xx_ll_bus.h
index 022cf6d..83bde47 100644
--- a/Inc/stm32h7xx_ll_bus.h
+++ b/Inc/stm32h7xx_ll_bus.h
@@ -25,14 +25,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -6830,4 +6828,4 @@
#endif /* STM32H7xx_LL_BUS_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_ll_comp.h b/Inc/stm32h7xx_ll_comp.h
index beedbac..5d1a7f3 100644
--- a/Inc/stm32h7xx_ll_comp.h
+++ b/Inc/stm32h7xx_ll_comp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -848,4 +847,4 @@
#endif /* __STM32H7xx_LL_COMP_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_ll_cordic.h b/Inc/stm32h7xx_ll_cordic.h
index 848a5dc..6cf2931 100644
--- a/Inc/stm32h7xx_ll_cordic.h
+++ b/Inc/stm32h7xx_ll_cordic.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -782,5 +781,3 @@
#endif
#endif /* STM32H7xx_LL_CORDIC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_cortex.h b/Inc/stm32h7xx_ll_cortex.h
index 4313732..4917f65 100644
--- a/Inc/stm32h7xx_ll_cortex.h
+++ b/Inc/stm32h7xx_ll_cortex.h
@@ -10,7 +10,7 @@
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
- (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
@@ -21,13 +21,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -666,4 +665,3 @@
#endif /* STM32H7xx_LL_CORTEX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_crc.h b/Inc/stm32h7xx_ll_crc.h
index d55593f..6c6de8f 100644
--- a/Inc/stm32h7xx_ll_crc.h
+++ b/Inc/stm32h7xx_ll_crc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -236,7 +235,7 @@
}
/**
- * @brief Configure the reversal of the bit order of the Output data
+ * @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
@@ -460,5 +459,3 @@
#endif
#endif /* STM32H7xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_crs.h b/Inc/stm32h7xx_ll_crs.h
index 85e0fe7..86ce847 100644
--- a/Inc/stm32h7xx_ll_crs.h
+++ b/Inc/stm32h7xx_ll_crs.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -779,5 +778,3 @@
#endif
#endif /* STM32H7xx_LL_CRS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_dac.h b/Inc/stm32h7xx_ll_dac.h
index d0c7421..f4a2efd 100644
--- a/Inc/stm32h7xx_ll_dac.h
+++ b/Inc/stm32h7xx_ll_dac.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -68,12 +67,14 @@
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
+
#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 28 bits) */
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
+
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
@@ -81,9 +82,11 @@
| DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
+
#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
DORx channel 2 (shifted left of 5 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+
#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
SHSRx channel 2 (shifted left of 6 bits) */
@@ -229,6 +232,7 @@
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
+
/**
* @}
*/
@@ -238,7 +242,9 @@
* @{
*/
#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+
#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+
/**
* @}
*/
@@ -1644,6 +1650,7 @@
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
* @{
*/
+
/**
* @brief Get DAC calibration offset flag for DAC channel 1
* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
@@ -1679,7 +1686,6 @@
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
}
-
/**
* @brief Get DAC busy writing sample time flag for DAC channel 2
* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
@@ -1858,4 +1864,3 @@
#endif /* STM32H7xx_LL_DAC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_delayblock.h b/Inc/stm32h7xx_ll_delayblock.h
index 78b7bb1..b805ea2 100644
--- a/Inc/stm32h7xx_ll_delayblock.h
+++ b/Inc/stm32h7xx_ll_delayblock.h
@@ -6,16 +6,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_LL_DLYB_H
@@ -85,4 +84,3 @@
#endif /* STM32H7xx_LL_DLYB_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_dma.h b/Inc/stm32h7xx_ll_dma.h
index 5dae9e1..4d18318 100644
--- a/Inc/stm32h7xx_ll_dma.h
+++ b/Inc/stm32h7xx_ll_dma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -3281,4 +3280,3 @@
#endif /* __STM32H7xx_LL_DMA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_dma2d.h b/Inc/stm32h7xx_ll_dma2d.h
index 583a04e..daea475 100644
--- a/Inc/stm32h7xx_ll_dma2d.h
+++ b/Inc/stm32h7xx_ll_dma2d.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -2230,5 +2229,3 @@
#endif
#endif /* STM32H7xx_LL_DMA2D_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_dmamux.h b/Inc/stm32h7xx_ll_dmamux.h
index 9592307..bf4cffa 100644
--- a/Inc/stm32h7xx_ll_dmamux.h
+++ b/Inc/stm32h7xx_ll_dmamux.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -2435,4 +2434,3 @@
#endif /* __STM32H7xx_LL_DMAMUX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_exti.h b/Inc/stm32h7xx_ll_exti.h
index 1e25e01..885f22d 100644
--- a/Inc/stm32h7xx_ll_exti.h
+++ b/Inc/stm32h7xx_ll_exti.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -3284,4 +3283,3 @@
#endif /* __STM32H7xx_LL_EXTI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_fmac.h b/Inc/stm32h7xx_ll_fmac.h
index 4bc018c..b489388 100644
--- a/Inc/stm32h7xx_ll_fmac.h
+++ b/Inc/stm32h7xx_ll_fmac.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -38,20 +37,6 @@
* @{
*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup FMAC_LL_Private_Macros FMAC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -63,11 +48,11 @@
* @brief Flag defines which can be used with LL_FMAC_ReadReg function
* @{
*/
-#define LL_FMAC_SR_SAT FMAC_SR_SAT
-#define LL_FMAC_SR_UNFL FMAC_SR_UNFL
-#define LL_FMAC_SR_OVFL FMAC_SR_OVFL
-#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL
-#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY
+#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
+#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
+#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
+#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
+#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
/**
* @}
*/
@@ -76,11 +61,11 @@
* @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
* @{
*/
-#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN
-#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN
-#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN
-#define LL_FMAC_CR_WIEN FMAC_CR_WIEN
-#define LL_FMAC_CR_RIEN FMAC_CR_RIEN
+#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
+#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
+#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
+#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
+#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
/**
* @}
*/
@@ -89,10 +74,10 @@
* @brief Watermark defines that can be used for buffer full (input) or buffer empty (output)
* @{
*/
-#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000UL /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
-#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000UL /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
-#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000UL /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
-#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000UL /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
+#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
+#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
+#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
+#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
/**
* @}
*/
@@ -100,11 +85,20 @@
/** @defgroup FMAC_LL_EC_FUNC FMAC functions
* @{
*/
-#define LL_FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
-#define LL_FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
-#define LL_FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
-#define LL_FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
-#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
+#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
+#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
+#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
+#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
+#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
+/**
+ * @}
+ */
+
+/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing
+ * @{
+ */
+#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */
+#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */
/**
* @}
*/
@@ -113,7 +107,8 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* External variables --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
* @{
*/
@@ -177,7 +172,7 @@
* @brief Return X1 full watermark.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark
* @param FMACx FMAC instance
- * @retval Returned value can be one of the following values:
+ * @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
@@ -192,7 +187,8 @@
* @brief Configure X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize
* @param FMACx FMAC instance
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -204,7 +200,8 @@
* @brief Return X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
* @param FMACx FMAC instance
- * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @retval uint8_t Number of 16-bit words allocated to the input buffer
+ * (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
{
@@ -215,7 +212,8 @@
* @brief Configure X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+ * @param Base Base address of the input buffer (X1) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -227,7 +225,8 @@
* @brief Return X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+ * @retval uint8_t Base address of the input buffer (X1) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
{
@@ -238,7 +237,8 @@
* @brief Configure X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize
* @param FMACx FMAC instance
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -250,7 +250,8 @@
* @brief Return X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
* @param FMACx FMAC instance
- * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
+ * (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
{
@@ -261,7 +262,8 @@
* @brief Configure X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+ * @param Base Base address of the coefficient buffer (X2) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -273,7 +275,8 @@
* @brief Return X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+ * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
{
@@ -300,7 +303,7 @@
* @brief Return Y empty watermark.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark
* @param FMACx FMAC instance
- * @retval Returned value can be one of the following values:
+ * @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
@@ -315,7 +318,8 @@
* @brief Configure Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize
* @param FMACx FMAC instance
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -327,7 +331,8 @@
* @brief Return Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
* @param FMACx FMAC instance
- * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @retval uint8_t Number of 16-bit words allocated to the output buffer
+ * (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
{
@@ -338,7 +343,8 @@
* @brief Configure Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+ * @param Base Base address of the output buffer (Y) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -350,7 +356,8 @@
* @brief Return Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+ * @retval uint8_t Base address of the output buffer (Y) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
{
@@ -383,7 +390,7 @@
* @brief Check the state of FMAC processing.
* @rmtoll PARAM START LL_FMAC_IsEnabledStart
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
{
@@ -411,7 +418,7 @@
* @brief Return function.
* @rmtoll PARAM FUNC LL_FMAC_GetFunction
* @param FMACx FMAC instance
- * @retval Returned value can be one of the following values:
+ * @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
@@ -427,7 +434,8 @@
* @brief Configure input parameter R.
* @rmtoll PARAM R LL_FMAC_SetParamR
* @param FMACx FMAC instance
- * @param Param 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @param Param Parameter R (gain, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
@@ -439,7 +447,7 @@
* @brief Return input parameter R.
* @rmtoll PARAM R LL_FMAC_GetParamR
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
{
@@ -450,7 +458,8 @@
* @brief Configure input parameter Q.
* @rmtoll PARAM Q LL_FMAC_SetParamQ
* @param FMACx FMAC instance
- * @param Param 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+ * @param Param Parameter Q (vector length, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
@@ -462,7 +471,7 @@
* @brief Return input parameter Q.
* @rmtoll PARAM Q LL_FMAC_GetParamQ
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+ * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
{
@@ -473,23 +482,25 @@
* @brief Configure input parameter P.
* @rmtoll PARAM P LL_FMAC_SetParamP
* @param FMACx FMAC instance
- * @param Param 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+ * @param Param Parameter P (vector length, number of filter taps, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
{
- MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param) << FMAC_PARAM_P_Pos);
+ MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param));
}
/**
* @brief Return input parameter P.
* @rmtoll PARAM P LL_FMAC_GetParamP
* @param FMACx FMAC instance
- * @retval 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+ * @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
{
- return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P) >> FMAC_PARAM_P_Pos);
+ return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
}
/**
@@ -512,21 +523,10 @@
}
/**
- * @brief Interrupt the FMAC reset.
- * @rmtoll CR RESET LL_FMAC_DisableReset
- * @param FMACx FMAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_FMAC_DisableReset(FMAC_TypeDef *FMACx)
-{
- CLEAR_BIT(FMACx->CR, FMAC_CR_RESET);
-}
-
-/**
* @brief Check the state of the FMAC reset.
* @rmtoll CR RESET LL_FMAC_IsEnabledReset
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
{
@@ -567,7 +567,7 @@
* @brief Check Clipping State.
* @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
{
@@ -608,7 +608,7 @@
* @brief Check FMAC DMA write channel request state.
* @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
@@ -641,7 +641,7 @@
* @brief Check FMAC DMA read channel request state.
* @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
{
@@ -682,7 +682,7 @@
* @brief Check FMAC saturation error interrupt state.
* @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
{
@@ -715,7 +715,7 @@
* @brief Check FMAC underflow error interrupt state.
* @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
{
@@ -748,7 +748,7 @@
* @brief Check FMAC overflow error interrupt state.
* @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
{
@@ -781,7 +781,7 @@
* @brief Check FMAC write interrupt state.
* @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
{
@@ -814,7 +814,7 @@
* @brief Check FMAC read interrupt state.
* @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
{
@@ -833,7 +833,7 @@
* @brief Check FMAC saturation error flag state.
* @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
{
@@ -844,7 +844,7 @@
* @brief Check FMAC underflow error flag state.
* @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
{
@@ -855,7 +855,7 @@
* @brief Check FMAC overflow error flag state.
* @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
{
@@ -866,7 +866,7 @@
* @brief Check FMAC X1 buffer full flag state.
* @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
{
@@ -877,7 +877,7 @@
* @brief Check FMAC Y buffer empty flag state.
* @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY
* @param FMACx FMAC instance
- * @retval State of bit (1 or 0).
+ * @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
{
@@ -896,7 +896,8 @@
* @brief Write 16-bit input data for the FMAC processing.
* @rmtoll WDATA WDATA LL_FMAC_WriteData
* @param FMACx FMAC instance
- * @param InData 0x0000 .. 0xFFFF: 16-bit value to be provided as input data for FMAC processing.
+ * @param InData 16-bit value to be provided as input data for FMAC processing.
+ * This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
@@ -908,7 +909,7 @@
* @brief Return 16-bit output data of FMAC processing.
* @rmtoll RDATA RDATA LL_FMAC_ReadData
* @param FMACx FMAC instance
- * @retval 0x0000 .. 0xFFFF: 16-bit output data of FMAC processing.
+ * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
*/
__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
{
@@ -934,14 +935,17 @@
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
- * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+ * @param Base Base address of the input buffer (X1) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
- Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
+ Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
}
/**
@@ -949,14 +953,17 @@
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n
* X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2
* @param FMACx FMAC instance
- * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+ * @param Base Base address of the coefficient buffer (X2) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
- (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
+ (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
}
/**
@@ -970,14 +977,17 @@
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
- * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
- * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+ * @param Base Base address of the output buffer (Y) within the internal memory.
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+ * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
- Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
+ Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
}
/**
@@ -988,23 +998,29 @@
* PARAM Q LL_FMAC_ConfigFunc\n
* PARAM R LL_FMAC_ConfigFunc
* @param FMACx FMAC instance
- * @param Start 0x00 .. 0x01: Enable or disable FMAC processing.
+ * @param Start This parameter can be one of the following values:
+ * @arg @ref LL_FMAC_PROCESSING_STOP
+ * @arg @ref LL_FMAC_PROCESSING_START
* @param Function This parameter can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
- * @param ParamP 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
- * @param ParamQ 0x00 .. 0xFF: Parameter Q (vector length, etc.).
- * @param ParamR 0x00 .. 0xFF: Parameter R (gain, etc.).
+ * @param ParamP Parameter P (vector length, number of filter taps, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param ParamQ Parameter Q (vector length, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @param ParamR Parameter R (gain, etc.).
+ * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
uint8_t ParamQ, uint8_t ParamR)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
- (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
+ (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) |
+ (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
}
/**
@@ -1045,5 +1061,3 @@
#endif
#endif /* STM32H7xx_LL_FMAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_fmc.h b/Inc/stm32h7xx_ll_fmc.h
index 687775a..aab1b3c 100644
--- a/Inc/stm32h7xx_ll_fmc.h
+++ b/Inc/stm32h7xx_ll_fmc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -598,11 +597,13 @@
* @}
*/
+#if defined(FMC_BCR1_WFDIS)
/** @defgroup FMC_Write_FIFO FMC Write FIFO
* @{
*/
#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
+ #endif /* FMC_BCR1_WFDIS */
/**
* @}
*/
@@ -1159,5 +1160,3 @@
#endif
#endif /* STM32H7xx_LL_FMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_gpio.h b/Inc/stm32h7xx_ll_gpio.h
index cf032aa..b51f9d3 100644
--- a/Inc/stm32h7xx_ll_gpio.h
+++ b/Inc/stm32h7xx_ll_gpio.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -983,4 +982,3 @@
#endif /* STM32H7xx_LL_GPIO_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_hrtim.h b/Inc/stm32h7xx_ll_hrtim.h
index 36a1235..f037e4f 100644
--- a/Inc/stm32h7xx_ll_hrtim.h
+++ b/Inc/stm32h7xx_ll_hrtim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -377,10 +376,10 @@
* @{
* @brief Constants defining the source and event to be sent on the synchronization output.
*/
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
/**
* @}
*/
@@ -10474,6 +10473,4 @@
#endif /* STM32H7xx_LL_HRTIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32h7xx_ll_hsem.h b/Inc/stm32h7xx_ll_hsem.h
index 1e5953c..cff88b5 100644
--- a/Inc/stm32h7xx_ll_hsem.h
+++ b/Inc/stm32h7xx_ll_hsem.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -63,6 +62,7 @@
* @}
*/
+
/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_HSEM_ReadReg function
* @{
@@ -238,7 +238,7 @@
*/
__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
{
- return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
+ return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
}
/**
@@ -292,6 +292,8 @@
/**
* @brief Release all semaphore with the same core id.
* @rmtoll CR KEY LL_HSEM_ResetAllLock
+ * @rmtoll CR SEC LL_HSEM_ResetAllLock
+ * @rmtoll CR PRIV LL_HSEM_ResetAllLock
* @param HSEMx HSEM Instance.
* @param key Key value.
* @param core This parameter can be one of the following values:
@@ -898,5 +900,3 @@
#endif
#endif /* __STM32H7xx_LL_HSEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_i2c.h b/Inc/stm32h7xx_ll_i2c.h
index c698b7a..a93b97f 100644
--- a/Inc/stm32h7xx_ll_i2c.h
+++ b/Inc/stm32h7xx_ll_i2c.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -69,38 +68,46 @@
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetMode(). */
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
This parameter must be set by referring to the STM32CubeMX Tool and
the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetTiming(). */
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
- This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+ This feature can be modified afterwards using unitary functions
+ @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetDigitalFilter(). */
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetOwnAddress1(). */
- uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
+ match code or next received byte.
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
- This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_AcknowledgeNextData(). */
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2C_SetOwnAddress1(). */
} LL_I2C_InitTypeDef;
/**
* @}
@@ -170,10 +177,11 @@
/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
* @{
*/
-#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
-#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
-#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
+ (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
/**
* @}
*/
@@ -208,14 +216,15 @@
/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
* @{
*/
-#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
-#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
+#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
+ All Address2 are acknowledged. */
/**
* @}
*/
@@ -250,14 +259,21 @@
/** @defgroup I2C_LL_EC_MODE Transfer End Mode
* @{
*/
-#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
-#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
-#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
-#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
+#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
+ with no HW PEC comparison. */
+#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
+ with no HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
+ with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
+ with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
+ with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Software end mode with HW PEC comparison. */
/**
* @}
*/
@@ -265,14 +281,23 @@
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
-#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
-#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
+#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
+/*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+/*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
+ I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
+/*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
@@ -280,8 +305,10 @@
/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
* @{
*/
-#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
-#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
+ slave enters receiver mode. */
+#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
+ slave enters transmitter mode.*/
/**
* @}
*/
@@ -289,8 +316,10 @@
/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
-#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
+ transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
+ reception */
/**
* @}
*/
@@ -298,8 +327,10 @@
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
* @{
*/
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
+ SCL low level timeout. */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
+ both SCL and SDA high level timeout.*/
/**
* @}
*/
@@ -307,9 +338,12 @@
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
* @{
*/
-#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
-#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
-#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
+ enable bit */
+#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
+ I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
+(extended clock) enable bits */
/**
* @}
*/
@@ -353,18 +387,22 @@
/**
* @brief Configure the SDA setup, hold time and the SCL high, low period.
* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
- * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
- * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
- * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
- * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ (tscldel = (SCLDEL+1)xtpresc)
+ * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ (tsdadel = SDADELxtpresc)
+ * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+ (tsclh = (SCLH+1)xtpresc)
+ * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+ (tscll = (SCLL+1)xtpresc)
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
-#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
- ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
- (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
- (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
- (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
- (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
/**
* @}
*/
@@ -428,7 +466,8 @@
* @param AnalogFilter This parameter can be one of the following values:
* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
- * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+ and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
@@ -444,7 +483,8 @@
* This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
* @param I2Cx I2C Instance.
- * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+ and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
@@ -664,7 +704,7 @@
/**
* @brief Enable Wakeup from STOP.
- * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when Digital Filter is disabled.
* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
@@ -678,7 +718,7 @@
/**
* @brief Disable Wakeup from STOP.
- * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -691,7 +731,7 @@
/**
* @brief Check if Wakeup from STOP is enabled or disabled.
- * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -941,7 +981,7 @@
/**
* @brief Configure peripheral mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
* CR1 SMBDEN LL_I2C_SetMode
@@ -960,7 +1000,7 @@
/**
* @brief Get peripheral mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
* CR1 SMBDEN LL_I2C_GetMode
@@ -978,7 +1018,7 @@
/**
* @brief Enable SMBus alert (Host or Device mode)
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is drived low and
@@ -996,7 +1036,7 @@
/**
* @brief Disable SMBus alert (Host or Device mode)
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
@@ -1014,7 +1054,7 @@
/**
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
* @param I2Cx I2C Instance.
@@ -1027,7 +1067,7 @@
/**
* @brief Enable SMBus Packet Error Calculation (PEC).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1040,7 +1080,7 @@
/**
* @brief Disable SMBus Packet Error Calculation (PEC).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1053,7 +1093,7 @@
/**
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
* @param I2Cx I2C Instance.
@@ -1066,7 +1106,7 @@
/**
* @brief Configure the SMBus Clock Timeout.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
@@ -1089,7 +1129,7 @@
/**
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
@@ -1104,7 +1144,7 @@
/**
* @brief Get the SMBus Clock TimeoutA setting.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
* @param I2Cx I2C Instance.
@@ -1117,7 +1157,7 @@
/**
* @brief Set the SMBus Clock TimeoutA mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
@@ -1134,7 +1174,7 @@
/**
* @brief Get the SMBus Clock TimeoutA mode.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
@@ -1149,7 +1189,7 @@
/**
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutB is disabled.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
@@ -1164,7 +1204,7 @@
/**
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
* @param I2Cx I2C Instance.
@@ -1177,7 +1217,7 @@
/**
* @brief Enable the SMBus Clock Timeout.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
@@ -1195,7 +1235,7 @@
/**
* @brief Disable the SMBus Clock Timeout.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
@@ -1213,7 +1253,7 @@
/**
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
@@ -1226,7 +1266,8 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
- return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
+ return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
+ (ClockTimeout)) ? 1UL : 0UL);
}
/**
@@ -1443,7 +1484,7 @@
/**
* @brief Enable Error interrupts.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1463,7 +1504,7 @@
/**
* @brief Disable Error interrupts.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1645,7 +1686,7 @@
/**
* @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When the received PEC does not match with the PEC register content.
@@ -1660,7 +1701,7 @@
/**
* @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When a timeout or extended clock timeout occurs.
@@ -1675,7 +1716,7 @@
/**
* @brief Indicate the status of SMBus alert flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When SMBus host configuration, SMBus alert enabled and
@@ -1782,7 +1823,7 @@
/**
* @brief Clear SMBus PEC error flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
* @param I2Cx I2C Instance.
@@ -1795,7 +1836,7 @@
/**
* @brief Clear SMBus Timeout detection flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
@@ -1808,7 +1849,7 @@
/**
* @brief Clear SMBus Alert flag.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
* @param I2Cx I2C Instance.
@@ -1923,7 +1964,8 @@
}
/**
- * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
+ or next received byte.
* @note Usage in Slave mode only.
* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
* @param I2Cx I2C Instance.
@@ -1964,7 +2006,8 @@
/**
* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
* @note The master sends the complete 10bit slave address read sequence :
- * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
+ in Read direction.
* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
* @param I2Cx I2C Instance.
* @retval None
@@ -2125,9 +2168,10 @@
/**
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
- * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
+ or an Address Matched is received.
* This bit has no effect when RELOAD bit is set.
* This bit has no effect in device mode when SBC bit is not set.
* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
@@ -2141,7 +2185,7 @@
/**
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
* @param I2Cx I2C Instance.
@@ -2154,7 +2198,7 @@
/**
* @brief Get the SMBus Packet Error byte calculated.
- * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
@@ -2226,5 +2270,3 @@
#endif
#endif /* STM32H7xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_iwdg.h b/Inc/stm32h7xx_ll_iwdg.h
index 8e22e3d..d34acc2 100644
--- a/Inc/stm32h7xx_ll_iwdg.h
+++ b/Inc/stm32h7xx_ll_iwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -337,5 +336,3 @@
#endif
#endif /* STM32H7xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_lptim.h b/Inc/stm32h7xx_ll_lptim.h
index a2ee75c..25a174e 100644
--- a/Inc/stm32h7xx_ll_lptim.h
+++ b/Inc/stm32h7xx_ll_lptim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -67,22 +66,26 @@
uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
- This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_SetClockSource().*/
uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
- This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
+ This feature can be modified afterwards using using unitary
+ function @ref LL_LPTIM_SetPrescaler().*/
uint32_t Waveform; /*!< Specifies the waveform shape.
This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
- This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_ConfigOutput().*/
uint32_t Polarity; /*!< Specifies waveform polarity.
This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_LPTIM_ConfigOutput().*/
} LL_LPTIM_InitTypeDef;
/**
@@ -199,14 +202,14 @@
#define LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U /*!<External input trigger is connected to LPTIM2 output*/
#define LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to LPTIM3 output*/
#define LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to LPTIM4 output*/
-#define LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPTIM5 output*/
+#define LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPTIM5 output*/
#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI1 FS A output*/
-#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI1 FS B output*/
+#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI1 FS B output*/
#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI2 FS A output*/
-#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2 FS B output*/
-#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI4 FS A output*/
+#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2 FS B output*/
+#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI4 FS A output*/
#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI4 FS B output*/
-#define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to DFSDM2_BRK[0] */
+#define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to DFSDM2_BRK[0] */
/**
* @}
*/
@@ -934,7 +937,8 @@
}
/**
- * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+ * @brief Configure the active edge or edges used by the counter when
+ the LPTIM is clocked by an external clock source.
* @note This function must be called when the LPTIM instance is disabled.
* @note When both external clock signal edges are considered active ones,
* the LPTIM must also be clocked by an internal clock source with a
@@ -1152,7 +1156,8 @@
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
+ completed. If so, a new one can be initiated.
* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1174,7 +1179,8 @@
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
+ completed. If so, a new one can be initiated.
* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1196,7 +1202,8 @@
}
/**
- * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+ * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
+ operates in encoder mode).
* @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1218,7 +1225,8 @@
}
/**
- * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+ * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
+ operates in encoder mode).
* @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
@@ -1490,5 +1498,3 @@
#endif
#endif /* STM32H7xx_LL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_lpuart.h b/Inc/stm32h7xx_ll_lpuart.h
index 64e17f9..3fef9da 100644
--- a/Inc/stm32h7xx_ll_lpuart.h
+++ b/Inc/stm32h7xx_ll_lpuart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -159,7 +158,6 @@
#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
-#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
@@ -577,7 +575,7 @@
*/
__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
- MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
@@ -612,7 +610,7 @@
*/
__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
- MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
@@ -655,8 +653,8 @@
*/
__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
- (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
@@ -669,7 +667,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
@@ -681,7 +679,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
@@ -704,7 +702,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
@@ -715,7 +713,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
@@ -726,7 +724,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
@@ -737,7 +735,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
@@ -755,7 +753,7 @@
*/
__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
{
- MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+ ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
@@ -872,7 +870,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
@@ -883,7 +881,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
@@ -1876,17 +1874,6 @@
}
/**
- * @brief Clear TX FIFO Empty Flag
- * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
- * @param LPUARTx LPUART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
-{
- WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
-}
-
-/**
* @brief Clear Transmission Complete Flag
* @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
* @param LPUARTx LPUART Instance
@@ -1946,7 +1933,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
@@ -1960,7 +1947,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
@@ -1971,7 +1958,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
@@ -1985,7 +1972,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
@@ -1996,7 +1983,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -2007,7 +1994,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
/**
@@ -2018,7 +2005,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
@@ -2029,7 +2016,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
/**
@@ -2044,7 +2031,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
@@ -2055,7 +2042,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
@@ -2066,7 +2053,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
}
/**
@@ -2077,7 +2064,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
@@ -2088,7 +2075,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
/**
@@ -2099,7 +2086,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
@@ -2113,7 +2100,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
@@ -2124,7 +2111,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
@@ -2138,7 +2125,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
@@ -2149,7 +2136,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -2160,7 +2147,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
/**
@@ -2171,7 +2158,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
@@ -2182,7 +2169,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
/**
@@ -2197,7 +2184,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
@@ -2208,7 +2195,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
@@ -2219,7 +2206,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
}
/**
@@ -2230,7 +2217,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
@@ -2241,7 +2228,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
/**
@@ -2409,7 +2396,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -2420,7 +2407,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -2442,7 +2429,7 @@
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
{
- SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -2453,7 +2440,7 @@
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
{
- CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -2661,4 +2648,3 @@
#endif /* STM32H7xx_LL_LPUART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_mdma.h b/Inc/stm32h7xx_ll_mdma.h
index 38d08f2..8b80c7d 100644
--- a/Inc/stm32h7xx_ll_mdma.h
+++ b/Inc/stm32h7xx_ll_mdma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -4357,4 +4356,3 @@
#endif /* STM32H7xx_LL_MDMA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_opamp.h b/Inc/stm32h7xx_ll_opamp.h
index b6d4d3e..abc4d30 100644
--- a/Inc/stm32h7xx_ll_opamp.h
+++ b/Inc/stm32h7xx_ll_opamp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -255,7 +254,7 @@
*/
/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
- * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+ * @note Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
@@ -822,4 +821,4 @@
#endif /* __STM32H7xx_LL_OPAMP_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32h7xx_ll_pwr.h b/Inc/stm32h7xx_ll_pwr.h
index a7f8205..be137a4 100644
--- a/Inc/stm32h7xx_ll_pwr.h
+++ b/Inc/stm32h7xx_ll_pwr.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -2300,4 +2299,3 @@
#endif /* STM32H7xx_LL_PWR_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_rcc.h b/Inc/stm32h7xx_ll_rcc.h
index 2ab40eb..867db85 100644
--- a/Inc/stm32h7xx_ll_rcc.h
+++ b/Inc/stm32h7xx_ll_rcc.h
@@ -8,14 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -6409,4 +6407,3 @@
#endif /* STM32H7xx_LL_RCC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_rng.h b/Inc/stm32h7xx_ll_rng.h
index 1b98dd0..6863989 100644
--- a/Inc/stm32h7xx_ll_rng.h
+++ b/Inc/stm32h7xx_ll_rng.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -679,4 +678,3 @@
#endif /* __STM32H7xx_LL_RNG_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_rtc.h b/Inc/stm32h7xx_ll_rtc.h
index 230b1e3..ff0477b 100644
--- a/Inc/stm32h7xx_ll_rtc.h
+++ b/Inc/stm32h7xx_ll_rtc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -3776,7 +3775,7 @@
}
#endif /* RTC_BKP0R */
-#if defined(TAMP_BKP0R_BKP)
+#if defined(TAMP_BKP0R)
/**
* @brief Writes a data in a specified Backup data register.
* @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister
@@ -3877,7 +3876,7 @@
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
}
-#endif /* TAMP_BKP0R_BKP */
+#endif /* TAMP_BKP0R */
/**
* @}
@@ -5375,4 +5374,3 @@
#endif /* STM32H7xx_LL_RTC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_sdmmc.h b/Inc/stm32h7xx_ll_sdmmc.h
index fd210d3..abac581 100644
--- a/Inc/stm32h7xx_ll_sdmmc.h
+++ b/Inc/stm32h7xx_ll_sdmmc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -135,13 +134,11 @@
#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the */
- /*!< number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock */
- /*!< command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
@@ -152,8 +149,7 @@
#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out */
- /*!< of erase sequence command was received */
+#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
@@ -172,12 +168,10 @@
#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its */
- /*!< operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information */
- /*!< and asks the card whether card supports voltage. */
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
@@ -185,18 +179,14 @@
#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands */
- /*!< (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
/*!< for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */
- /*!< fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by */
- /*!< STOP_TRANSMISSION command. */
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */
#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */
- /*!< fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
@@ -205,38 +195,35 @@
#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command */
- /*!< system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. */
- /*!< Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by */
- /*!< the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather */
- /*!< than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card */
- /*!< for general purpose/application specific commands. */
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */
+#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */
#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus */
- /*!< widths are given in SCR register. */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */
#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with */
- /*!< 32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to */
- /*!< send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
/**
+ * @brief Following commands are MMC Specific commands.
+ */
+#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */
+
+/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
@@ -303,8 +290,9 @@
#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
+#ifndef SDMMC_DATATIMEOUT
#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
-
+#endif /* SDMMC_DATATIMEOUT */
#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
@@ -702,10 +690,10 @@
#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
-#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4)
+#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4)
/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
-#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)
+#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2)
/**
* @}
*/
@@ -1074,6 +1062,7 @@
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
@@ -1122,5 +1111,3 @@
#endif
#endif /* STM32H7xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_spi.h b/Inc/stm32h7xx_ll_spi.h
index 4dd1c2d..fc6bbed 100644
--- a/Inc/stm32h7xx_ll_spi.h
+++ b/Inc/stm32h7xx_ll_spi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -43,10 +42,18 @@
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
* @{
*/
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_Exported_Types SPI Exported Types
+ * @{
+ */
/**
* @brief SPI Init structures definition
@@ -56,53 +63,68 @@
uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetTransferDirection().*/
uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_LL_EC_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetMode().*/
uint32_t DataWidth; /*!< Specifies the SPI data width.
This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetDataWidth().*/
uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_LL_EC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetClockPolarity().*/
uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_LL_EC_PHASE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetClockPhase().*/
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
+ or by software using the SSI bit.
+
This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetNSSMode().*/
- uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
+ the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+ @note The communication clock is derived from the master clock.
+ The slave clock does not need to be set.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetBaudRatePrescaler().*/
uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetTransferBitOrder().*/
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
- This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+ This feature can be modified afterwards using unitary functions
+ @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF.
+ This parameter must be a number between Min_Data = 0x00
+ and Max_Data = 0xFFFFFFFF.
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_SPI_SetCRCPolynomial().*/
} LL_SPI_InitTypeDef;
@@ -195,7 +217,8 @@
#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
-#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
+ | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
/**
* @}
*/
@@ -218,7 +241,8 @@
#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
-#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
+ | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
/**
* @}
*/
@@ -348,7 +372,8 @@
#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
+ | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
@@ -356,15 +381,20 @@
#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
-#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
-#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
+ | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
+ | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
/**
* @}
*/
@@ -387,7 +417,8 @@
#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
-#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
+ | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
/**
* @}
*/
@@ -419,7 +450,8 @@
#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
+ | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
@@ -427,15 +459,20 @@
#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
-#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
-#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
+ | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
+ | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
/**
* @}
*/
@@ -453,10 +490,10 @@
/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
* @{
*/
-#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
-#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
-#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
-#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
+#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
+#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
+#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
/**
* @}
*/
@@ -1253,7 +1290,8 @@
/**
* @brief Set Transfer Mode
- * @note This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection.
+ * @note This configuration can not be changed when SPI is enabled except for half duplex direction
+ * using LL_SPI_SetHalfDuplexDirection.
* @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
* CFG2 COMM LL_SPI_SetTransferDirection
* @param SPIx SPI Instance
@@ -2442,7 +2480,7 @@
*spitxdr = TxData;
#else
SPIx->TXDR = TxData;
-#endif
+#endif /* __GNUC__ */
}
/**
@@ -2569,37 +2607,44 @@
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_LL_EC_MODE
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2S_SetTransferMode().*/
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_STANDARD
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2S_SetStandard().*/
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2S_SetDataFormat().*/
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
- This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+ This feature can be modified afterwards using unitary functions
+ @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
- Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
- and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+ Audio Frequency can be modified afterwards using Reference manual formulas
+ to calculate Prescaler Linear, Parity and unitary functions
+ @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity()
+ to set it.*/
uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_LL_EC_POLARITY
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_I2S_SetClockPolarity().*/
} LL_I2S_InitTypeDef;
@@ -2671,8 +2716,8 @@
/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
* @{
*/
-#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
-#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
/**
* @}
*/
@@ -3708,5 +3753,3 @@
#endif
#endif /* STM32H7xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_swpmi.h b/Inc/stm32h7xx_ll_swpmi.h
index efe1daa..c2b31d6 100644
--- a/Inc/stm32h7xx_ll_swpmi.h
+++ b/Inc/stm32h7xx_ll_swpmi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1238,5 +1237,3 @@
#endif
#endif /* STM32H7xx_LL_SWPMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_system.h b/Inc/stm32h7xx_ll_system.h
index b4326b5..e42fe8c 100644
--- a/Inc/stm32h7xx_ll_system.h
+++ b/Inc/stm32h7xx_ll_system.h
@@ -3,6 +3,18 @@
* @file stm32h7xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,17 +28,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -2439,4 +2440,3 @@
#endif /* __STM32H7xx_LL_SYSTEM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_tim.h b/Inc/stm32h7xx_ll_tim.h
index 4ec1297..adf998e 100644
--- a/Inc/stm32h7xx_ll_tim.h
+++ b/Inc/stm32h7xx_ll_tim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -201,24 +200,29 @@
uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetPrescaler().*/
uint32_t CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetCounterMode().*/
uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must
+ be a number between 0x0000 and 0xFFFFFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetAutoReload().*/
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetClockDivision().*/
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
@@ -226,10 +230,13 @@
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+ GP timers: this parameter must be a number between Min_Data = 0x00 and
+ Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+ Max_Data = 0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
/**
@@ -240,43 +247,51 @@
uint32_t OCMode; /*!< Specifies the output mode.
This parameter can be a value of @ref TIM_LL_EC_OCMODE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetMode().*/
uint32_t OCState; /*!< Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+ This feature can be modified afterwards using unitary function
+ LL_TIM_OC_SetCompareCHx (x=1..6).*/
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetPolarity().*/
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetIdleState().*/
} LL_TIM_OC_InitTypeDef;
/**
@@ -289,22 +304,26 @@
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t ICActiveInput; /*!< Specifies the input.
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t ICFilter; /*!< Specifies the input capture filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
} LL_TIM_IC_InitTypeDef;
@@ -316,47 +335,56 @@
uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetEncoderMode().*/
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
} LL_TIM_ENCODER_InitTypeDef;
@@ -369,26 +397,31 @@
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
Prescaler must be set to get a maximum counter period longer than the
time interval between 2 consecutive changes on the Hall inputs.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+ This parameter can be a value of
+ @ref TIM_LL_EC_IC_FILTER.
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_IC_SetFilter().*/
uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
A positive pulse (TRGO event) is generated with a programmable delay every time
a change occurs on the Hall inputs.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetCompareCH2().*/
} LL_TIM_HALLSENSOR_InitTypeDef;
/**
@@ -399,79 +432,125 @@
uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref TIM_LL_EC_OSSR
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
This parameter can be a value of @ref TIM_LL_EC_OSSI
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_SetOffStates()
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+ @note This bit-field cannot be modified as long as LOCK level 2 has been
+ programmed. */
uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
- @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
- has been written, their content is frozen until the next reset.*/
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+ register has been written, their content is frozen until the next reset.*/
uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_OC_SetDeadTime()
- @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+ programmed. */
uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+#if defined(TIM_BDTR_BKBID)
+ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_ConfigBRK()
+
+ @note Bidirectional break input is only supported by advanced timers instances.
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+#endif /*TIM_BDTR_BKBID */
uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+ This feature can be modified afterwards using unitary function
+ @ref LL_TIM_ConfigBRK2()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+#if defined(TIM_BDTR_BKBID)
+ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_ConfigBRK2()
+
+ @note Bidirectional break input is only supported by advanced timers instances.
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
+
+#endif /*TIM_BDTR_BKBID */
uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+ This feature can be modified afterwards using unitary functions
+ @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+ @note This bit-field can not be modified as long as LOCK level 1 has been
+ programmed. */
} LL_TIM_BDTR_InitTypeDef;
/**
@@ -1059,6 +1138,26 @@
*/
#endif /* TIM_BREAK_INPUT_SUPPORT */
+#if defined(TIM_BDTR_BKBID)
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+ * @{
+ */
+#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+ * @{
+ */
+#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
+/**
+ * @}
+ */
+
+#endif /*TIM_BDTR_BKBID */
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
* @{
*/
@@ -1083,10 +1182,10 @@
#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
-#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
+#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
-#endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
+#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
/**
* @}
@@ -1310,10 +1409,17 @@
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
+ (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
+ (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
/**
@@ -1338,7 +1444,8 @@
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
- * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
+ * active/inactive delay.
* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
@@ -1350,7 +1457,8 @@
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
- * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
+ * (when the timer operates in one pulse mode).
* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
@@ -1607,7 +1715,8 @@
}
/**
- * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
+ * (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
@@ -1625,7 +1734,8 @@
}
/**
- * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
+ * generators (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
@@ -1767,7 +1877,8 @@
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
- * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+ * in an atomic way.
* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
* @param TIMx Timer instance
* @retval None
@@ -2072,7 +2183,7 @@
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
/**
@@ -2111,7 +2222,7 @@
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
/**
@@ -2489,7 +2600,8 @@
}
/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+ * the Ocx and OCxN signals).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
@@ -2756,7 +2868,8 @@
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
- ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
+ << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
(Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
}
@@ -3477,6 +3590,56 @@
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
}
+#if defined(TIM_BDTR_BKBID)
+/**
+ * @brief Configure the break input.
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Bidirectional mode is only supported by advanced timer instances.
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance is an advanced-control timer.
+ * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+ * in input mode and in open drain output mode. Any active Break event will
+ * assert a low logic level on the Break input to indicate an internal break
+ * event to external devices.
+ * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+ * LL_TIM_BREAK_AFMODE_INPUT.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
+ * BDTR BKF LL_TIM_ConfigBRK\n
+ * BDTR BKBID LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @param BreakFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+ * @param BreakAFMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+ * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+ uint32_t BreakAFMode)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+#else
/**
* @brief Configure the break input.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
@@ -3512,6 +3675,36 @@
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
}
+#endif /* TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+ * @brief Disarm the break input (when it operates in bidirectional mode).
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+ * @brief Re-arm the break input (when it operates in bidirectional mode).
+ * @note The Break input is automatically armed as soon as MOE bit is set.
+ * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
/**
* @brief Enable the break 2 function.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
@@ -3538,6 +3731,56 @@
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
}
+#if defined(TIM_BDTR_BKBID)
+/**
+ * @brief Configure the break 2 input.
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @note Bidirectional mode is only supported by advanced timer instances.
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance is an advanced-control timer.
+ * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+ * in input mode and in open drain output mode. Any active Break event will
+ * assert a low logic level on the Break 2 input to indicate an internal break
+ * event to external devices.
+ * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+ * LL_TIM_BREAK2_AFMODE_INPUT.
+ * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
+ * BDTR BK2F LL_TIM_ConfigBRK2\n
+ * BDTR BK2BID LL_TIM_ConfigBRK2
+ * @param TIMx Timer instance
+ * @param Break2Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+ * @param Break2Filter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+ * @param Break2AFMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+ * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+ uint32_t Break2AFMode)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+#else
/**
* @brief Configure the break 2 input.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
@@ -3572,6 +3815,36 @@
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
}
+#endif /*TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+ * @brief Disarm the break 2 input (when it operates in bidirectional mode).
+ * @note The break 2 input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output.
+ * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+ * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
+ * @note The Break 2 input is automatically armed as soon as MOE bit is set.
+ * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
@@ -3796,13 +4069,13 @@
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
- * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
* @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
- *
+ *
* @param DMABurstLength This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
@@ -4175,7 +4448,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+ * (Capture/Compare 1 interrupt is pending).
* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4197,7 +4471,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+ * (Capture/Compare 2 over-capture interrupt is pending).
* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4219,7 +4494,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+ * (Capture/Compare 3 over-capture interrupt is pending).
* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4241,7 +4517,8 @@
}
/**
- * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+ * (Capture/Compare 4 over-capture interrupt is pending).
* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
@@ -4548,7 +4825,7 @@
* @}
*/
-/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
* @{
*/
/**
@@ -4934,4 +5211,3 @@
#endif
#endif /* __STM32H7xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_usart.h b/Inc/stm32h7xx_ll_usart.h
index 4a164ba..5ff3e38 100644
--- a/Inc/stm32h7xx_ll_usart.h
+++ b/Inc/stm32h7xx_ll_usart.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -712,7 +711,7 @@
*/
__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
@@ -751,7 +750,7 @@
*/
__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
@@ -798,8 +797,8 @@
*/
__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
- (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
@@ -814,7 +813,7 @@
*/
__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_UESM);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
@@ -828,7 +827,7 @@
*/
__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
@@ -852,7 +851,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
@@ -863,7 +862,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
@@ -874,7 +873,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
@@ -885,7 +884,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
@@ -903,7 +902,7 @@
*/
__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
{
- MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+ ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
@@ -1022,7 +1021,7 @@
*/
__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_MME);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
@@ -1033,7 +1032,7 @@
*/
__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
@@ -2094,7 +2093,7 @@
*/
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -2241,7 +2240,7 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -2270,7 +2269,7 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
- MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
}
/**
@@ -3459,7 +3458,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
@@ -3475,7 +3474,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
@@ -3486,7 +3485,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
@@ -3502,7 +3501,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
@@ -3513,7 +3512,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -3524,7 +3523,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
@@ -3535,7 +3534,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
@@ -3548,7 +3547,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
/**
@@ -3561,7 +3560,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
@@ -3572,7 +3571,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
/**
@@ -3600,7 +3599,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
@@ -3613,7 +3612,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
@@ -3626,7 +3625,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
/**
@@ -3639,7 +3638,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
/**
@@ -3652,7 +3651,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
/**
@@ -3665,7 +3664,7 @@
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
/**
@@ -3676,7 +3675,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
@@ -3692,7 +3691,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
@@ -3703,7 +3702,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
@@ -3719,7 +3718,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
@@ -3730,7 +3729,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
@@ -3741,7 +3740,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
@@ -3752,7 +3751,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
@@ -3765,7 +3764,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
/**
@@ -3778,7 +3777,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
@@ -3791,7 +3790,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
/**
@@ -3819,7 +3818,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
@@ -3832,7 +3831,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
@@ -3845,7 +3844,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
/**
@@ -3858,7 +3857,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
/**
@@ -3871,7 +3870,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
/**
@@ -3884,7 +3883,7 @@
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
/**
@@ -4118,7 +4117,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -4129,7 +4128,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
@@ -4151,7 +4150,7 @@
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -4162,7 +4161,7 @@
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
@@ -4400,4 +4399,3 @@
#endif /* STM32H7xx_LL_USART_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_usb.h b/Inc/stm32h7xx_ll_usb.h
index 5ee7cf7..0559722 100644
--- a/Inc/stm32h7xx_ll_usb.h
+++ b/Inc/stm32h7xx_ll_usb.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -23,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@@ -80,6 +79,7 @@
HC_DATATGLERR
} USB_OTG_HCStateTypeDef;
+
/**
* @brief USB Instance Initialization Structure definition
*/
@@ -94,14 +94,15 @@
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed */
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY */
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@@ -131,7 +132,7 @@
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type_ */
+ This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
@@ -168,15 +169,16 @@
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t speed; /*!< USB Host speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ uint8_t speed; /*!< USB Host Channel speed.
+ This parameter can be any value of @ref HCD_Device_Speed:
+ (HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_EP_Type_ */
+ This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
@@ -186,7 +188,7 @@
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
- uint32_t XferSize; /*!< OTG Channel transfer size. */
+ uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */
@@ -316,10 +318,10 @@
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
-#define EP_MPS_64 0U
-#define EP_MPS_32 1U
-#define EP_MPS_16 2U
-#define EP_MPS_8 3U
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
/**
* @}
*/
@@ -393,19 +395,36 @@
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
+#define TEST_J 1U
+#define TEST_K 2U
+#define TEST_SE0_NAK 3U
+#define TEST_PACKET 4U
+#define TEST_FORCE_EN 5U
+
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
-#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ + USB_OTG_HOST_CHANNEL_BASE\
+ + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#define EP_ADDR_MSK 0xFU
+
+#ifndef USE_USB_DOUBLE_BUFFER
+#define USE_USB_DOUBLE_BUFFER 1U
+#endif /* USE_USB_DOUBLE_BUFFER */
/**
* @}
*/
@@ -451,6 +470,7 @@
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
@@ -505,9 +525,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32H7xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_utils.h b/Inc/stm32h7xx_ll_utils.h
index 2833148..635ea59 100644
--- a/Inc/stm32h7xx_ll_utils.h
+++ b/Inc/stm32h7xx_ll_utils.h
@@ -3,6 +3,16 @@
* @file stm32h7xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
+ ******************************************************************************
+ * @attention
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,17 +26,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -400,4 +399,3 @@
#endif /* STM32H7xx_LL_UTILS_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32h7xx_ll_wwdg.h b/Inc/stm32h7xx_ll_wwdg.h
index 489cf3e..eef033d 100644
--- a/Inc/stm32h7xx_ll_wwdg.h
+++ b/Inc/stm32h7xx_ll_wwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -327,5 +326,3 @@
#endif
#endif /* STM32H7xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/License.md b/License.md
index f8a5385..479c4f6 100644
--- a/License.md
+++ b/License.md
@@ -1,3 +1,27 @@
-# Copyright (c) 2017 STMicroelectronics
+Copyright 2017 STMicroelectronics.
+All rights reserved.
-This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
\ No newline at end of file
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/README.md b/README.md
index 6d10da2..2aa2da5 100644
--- a/README.md
+++ b/README.md
@@ -10,7 +10,7 @@
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
* The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
* The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
- * A consistent set of middleware components such as RTOS, USB, FatFS, graphics, touch sensing library...
+ * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
* A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
Two models of publication are proposed for the STM32Cube embedded software:
@@ -21,14 +21,7 @@
This **stm32h7xx_hal_driver** MCU component repo is one element of the STM32CubeH7 MCU embedded software package, providing the **HAL-LL Drivers** part.
-## License
-
-Copyright (c) 2017 STMicroelectronics.
-
-This software component is licensed by STMicroelectronics under BSD-3-Clause license. You may not use this file except in compliance with the License.
-You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause).
-
-## Release note
+# Release note
Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32h7xx_hal_driver/blob/master/Release_Notes.html).
@@ -45,11 +38,12 @@
Tag v1.8.0 | Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next HAL tag)
Tag v1.9.0 | Tag v1.9.0 | Tag v5.4.0 | Tag v1.8.0 (and following, if any, till next HAL tag)
Tag v1.10.0 | Tag v1.10.0 | Tag v5.6.0 | Tag v1.9.0 (and following, if any, till next HAL tag)
+Tag v1.10.1 | Tag v1.10.1 | Tag v5.6.0 | Tag v1.9.1 (and following, if any, till next HAL tag)
The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7).
## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32h7xx_hal_driver/issues/new).
+If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32h7xx_hal_driver/issues/new/choose).
For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index 28e3c2a..71a7899 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -5,11 +5,14 @@
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for STM32H7xx HAL Drivers</title>
- <style type="text/css">
- code{white-space: pre-wrap;}
- span.smallcaps{font-variant: small-caps;}
- span.underline{text-decoration: underline;}
- div.column{display: inline-block; vertical-align: top; width: 50%;}
+ <style>
+ code{white-space: pre-wrap;}
+ span.smallcaps{font-variant: small-caps;}
+ span.underline{text-decoration: underline;}
+ div.column{display: inline-block; vertical-align: top; width: 50%;}
+ div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
+ ul.task-list{list-style: none;}
+ .display.math{display: block; text-align: center; margin: 0.5rem auto;}
</style>
<link rel="stylesheet" href="_htmresc/mini-st.css" />
<!--[if lt IE 9]>
@@ -29,22 +32,202 @@
</center>
</div>
</div>
-<h1 id="license"><strong>License</strong></h1>
-This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
-<center>
-<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
-</center>
+<h1 id="purpose">Purpose</h1>
+<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
+<p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
+<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
+<ul>
+<li>New set of inline functions for direct and atomic register access</li>
+<li>One-shot operations that can be used by the HAL drivers or from application level</li>
+<li>Full independence from HAL and standalone usage (without HAL drivers)</li>
+<li>Full features coverage of all the supported peripherals</li>
+</ul>
</div>
-<div class="col-sm-12 col-lg-8">
-<h1 id="update-history"><strong>Update History</strong></h1>
+<section id="update-history" class="col-sm-12 col-lg-8">
+<h1><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
+<input type="checkbox" id="collapse-section14" checked aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>General updates to fix known defects and implementation enhancements.</li>
+<li>All source files: update disclaimer to add reference to the new license agreement.</li>
+<li><strong>HAL RCC</strong>
+<ul>
+<li>Fix issue where HSI is not taken into account in HAL_RCC_OscConfig.</li>
+</ul></li>
+<li><strong>HAL FLASH</strong>
+<ul>
+<li>Update to fix error checking issue when optimization is set to high.</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Reorder EXTI configuration sequence in order to avoid unexpected level detection.</li>
+</ul></li>
+<li><strong>HAL EXTI</strong>
+<ul>
+<li>Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.</li>
+</ul></li>
+<li><strong>HAL/LL ADC</strong>
+<ul>
+<li>Fix issue where an error state is returned by the IRQ handler in case of injection conversion in IT mode with trigger timer.</li>
+<li>Add missing injected external trigger to IS_ADC_EXTTRIGINJEC() macro.</li>
+<li>Add two new APIs to simplify internal channel configuration (LL_ADC_SetCommonPathInternalChAdd and LL_ADC_SetCommonPathInternalChRem).</li>
+<li>assert_param() now checks for continuous and discontinuous mode exclusivity.</li>
+<li>Update LL ADC driver to correctly configure the ADC3 resolution on some devices.</li>
+</ul></li>
+<li><strong>HAL TIM</strong>
+<ul>
+<li>Manage the Bi-directional break input feature for the concerned part numbers.</li>
+<li>Update input capture measurement in DMA mode to avoid zero return values at high frequencies.</li>
+<li>Update HAL_TIMEx_ConfigBreakInput to use CMSIS TIM1_OR2_BKDF1BK0E_Pos definition instead of its hard coded value.</li>
+<li>Fix wrong compile switch used in TIM_LL_EC_DMABURST_BASEADDR constant definitions.</li>
+</ul></li>
+<li><strong>HAL UART</strong>
+<ul>
+<li>Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA().</li>
+<li>Correct UART ReceptionType management in case if ReceptionToIdle API being called from RxEvent callback.</li>
+<li>Handling of UART concurrent register access in case of race condition between TX and RX transfers (HAL UART and LL LPUART).</li>
+<li>Improve header description of UART_WaitOnFlagUntilTimeout() function.</li>
+<li>Add a check on the UART parity before enabling the parity error interruption.</li>
+<li>Add const qualifier for read only pointers in API prototypes.</li>
+<li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig().</li>
+</ul></li>
+<li><strong>HAL/LL USART</strong>
+<ul>
+<li>Improve header description of USART_WaitOnFlagUntilTimeout() function.</li>
+<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
+<li>Add const qualifier for read only pointers for API prototypes.</li>
+<li>Handling of UART concurrent register access in case of race condition between TX and RX transfers (HAL UART and LL LPUART).</li>
+<li>Fix compilation warnings generated with ARMV6 compiler.</li>
+</ul></li>
+<li><strong>LL LPUART</strong>
+<ul>
+<li>Remove TXFECF reference from LL LPUART driver.</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li>Add Fm+ support to SMBus to be rev3 compliant.</li>
+<li>Add the support of wake up capability.</li>
+<li>Add new APIs:
+<ul>
+<li>HAL_SMBUSEx_EnableWakeUp()</li>
+<li>HAL_SMBUSEx_DisableWakeUp()</li>
+</ul></li>
+<li>Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master.</li>
+<li>Add flush on TX register.</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Updated I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.</li>
+<li>Fix written reserved bit 28 in I2C_CR2 register</li>
+<li>Update to handle errors in polling mode.</li>
+<li>Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.</li>
+<li>Update to fix issue detected due to low system frequency execution (HSI).</li>
+<li>Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA.</li>
+</ul></li>
+<li><strong>HAL LPTIM</strong>
+<ul>
+<li>Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable().</li>
+</ul></li>
+<li><strong>HAL Generic</strong>
+<ul>
+<li>Fix HAL_Init_Tick() priority handling for alternate (non SysTick) time bases.</li>
+</ul></li>
+<li><strong>HAL IRDA</strong>
+<ul>
+<li>Improve header description of IRDA_WaitOnFlagUntilTimeout() function.</li>
+<li>Add a check on the IRDA parity before enabling the parity error interrupt.</li>
+<li>Add const qualifier for read only pointers for API prototypes.</li>
+<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li>
+</ul></li>
+<li><strong>HAL RTC_BKP</strong>
+<ul>
+<li>Add an exit condition to the RTC_EnterInitMode and HAL_RTC_DeInit functions to avoid the infinite loop when initializing and de-initializing the RTC.</li>
+<li>Add use of macros _\_RTC_<>_EXTI_ENABLE_IT() in case of DUAL_CORE configuration inside functions HAL_RTC_SetAlarm_IT(), HAL_RTCEx_SetWakeUpTimer_IT(),HAL_RTCEx_SetTimeStamp_IT(), and HAL_RTCEx_SetTamper_IT().</li>
+</ul></li>
+<li><strong>HAL DBGMCU</strong>
+<ul>
+<li>In Legacy/stm32_hal_legacy.h, exclude HAL_EnableDBG<em>Mode() HAL_DisableDBG</em>Mode() declarations as still defined in stm32h7xx_hal.c.</li>
+</ul></li>
+<li><strong>HAL NOR</strong>
+<ul>
+<li>Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.</li>
+</ul></li>
+<li><strong>HAL SDMMC</strong>
+<ul>
+<li>Fix an issue with HAL_SD_GetCardState().</li>
+<li>Fix to take into consideration if the received RCA is 0x0 or not.</li>
+</ul></li>
+<li><strong>LL RTC_BKP</strong>
+<ul>
+<li>Fix IS_LL_RTC_MONTH assert check.</li>
+</ul></li>
+<li><strong>HAL DMA</strong>
+<ul>
+<li>Update HAL_DMA_IRQHandler() API to set the DMA state before unlocking access to the DMA handle.</li>
+<li>Manage the case of an invalid value of CallbackID passed to the HAL_DMA_RegisterCallback() API.</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong>
+<ul>
+<li>Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function.</li>
+<li>Add const qualifier for read only pointers in API prototypes.</li>
+<li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().</li>
+</ul></li>
+<li><strong>LL HSEM</strong>
+<ul>
+<li>Fix an issue where LL_HSEM_1StepLock uses HSEM_R_LOCK instead of HSEM_RLR_LOCK while checking the RLR register.</li>
+</ul></li>
+<li><strong>HAL RNG</strong>
+<ul>
+<li>Add check to avoid false timeout detection in case of preemption.</li>
+</ul></li>
+<li><strong>HAL ETH</strong>
+<ul>
+<li>Correct wrong call to DMAErrorCallback() instead of MACErrorCallback().</li>
+</ul></li>
+<li><strong>HAL/LL USB</strong>
+<ul>
+<li>hal_hcd: fix added to avoid compiler otmization on count variable used for USB HAL timeout loop check.</li>
+<li>hal_pcd: added missing registered callbacks check for HAL_HCD_HC_NotifyURBChange_Callback().</li>
+<li>hal_pcd: New API HAL_PCD_SetTestMode() added to handle USB device high speed Test modes.</li>
+<li>hal_pcd: setting SNAK for EPs not required during device reset.</li>
+<li>ll_USB: change added in USB_SetCurrentMode to improve required wait timing to change core mode.</li>
+<li>ll_USB: remove non required 200ms delay during host initialization.</li>
+<li>ll_USB: fix added to USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO.</li>
+<li>ll_USB: fix added to avoid resetting host channel direction during channel halt.</li>
+</ul></li>
+<li><strong>HAL USB_OTG</strong>
+<ul>
+<li>USB LL driver fix on USB_HC_Halt() function, should not clear channel direction during halt.</li>
+<li>USB HAL: fix unexpected HAL_TIMEOUT during USB core reset due to compiler optimization.</li>
+</ul></li>
+<li><strong>HAL IWDG</strong>
+<ul>
+<li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li>
+</ul></li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li><strong>HAL/ETH</strong>
+<ul>
+<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
+</ul></li>
+</ul>
+<h2 id="backward-compatibility">Backward compatibility</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li><p>General updates to fix known defects and implementation enhancements</p></li>
<li><p>Fix minor issues related to English typo in comments</p></li>
-<li>Update stm32h7xx_hal_def.h implementation to support MDK-ARM AC6 compiler
+<li><p>Update stm32h7xx_hal_def.h implementation to support MDK-ARM AC6 compiler</p>
<ul>
<li>Notes:
<ul>
@@ -53,7 +236,7 @@
<li>Template projects updated with “Use default compiler version 6” setting and “AC5-like warning” setting</li>
</ul></li>
</ul></li>
-<li><strong>HAL</strong>:
+<li><p><strong>HAL</strong>:</p>
<ul>
<li>stm32h7xx_hal.h and stm32h7xx_hal.c:
<ul>
@@ -69,7 +252,7 @@
<li>Update USE_SD_TRANSCEIVER define default value to zero Notes: This define shall be set in the target project according to the given board: set to 1 in case of an SD transceiver is present or zero if not</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL ADC</strong>:
+<li><p><strong>HAL/LL ADC</strong>:</p>
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
@@ -80,14 +263,14 @@
<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
</ul></li>
</ul></li>
-<li><strong>HAL CEC</strong>:
+<li><p><strong>HAL CEC</strong>:</p>
<ul>
<li>stm32h7xx_hal_cec.c:
<ul>
<li>Update “HAL_CEC_IRQHandler” implementation to avoid extra byte sent with CEC command</li>
</ul></li>
</ul></li>
-<li><strong>HAL CRYP</strong>:
+<li><p><strong>HAL CRYP</strong>:</p>
<ul>
<li>stm32h7xx_hal_cryp.h:
<ul>
@@ -102,14 +285,14 @@
<li>Update the implementation of the “HAL_CRYPEx_AESGCM_GenerateAuthTAG” function to support the header width unit setting</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL EXTI</strong>:
+<li><p><strong>HAL/LL EXTI</strong>:</p>
<ul>
<li>stm32h7xx_hal_exti.h:
<ul>
<li>Update IS_EXTI_PROPERTY to IS_EXTI_CONFIG_LINE macros implementation using “<strong>EXTI_LINE</strong>” instead of “<strong>LINE</strong>” o avoid clash with compiler key word “<strong>LINE</strong>”</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL ETH</strong>:
+<li><p><strong>HAL/LL ETH</strong>:</p>
<ul>
<li>stm32h7xx_hal_eth.h:
<ul>
@@ -124,7 +307,7 @@
<li>This implementation allows to improve packet transmission performance using NetX Duo TCPIP stack, however a more elaborated implementation will be provided in next release</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL FLASH</strong>:
+<li><p><strong>HAL/LL FLASH</strong>:</p>
<ul>
<li>stm32h7xx_hal_flash_ex.h:
<ul>
@@ -137,7 +320,7 @@
<li>Update “HAL_FLASH_Program” description with details for “FlashAddress” and “DataAddress” alignment requirements</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL GPIO</strong>:
+<li><p><strong>HAL/LL GPIO</strong>:</p>
<ul>
<li>stm32h7xx_hal_gpio.c:
<ul>
@@ -148,28 +331,28 @@
<li>Update and fix LL_GPIO_TogglePin implementation to allow toggle of multiple pin</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL HRTIM</strong>:
+<li><p><strong>HAL/LL HRTIM</strong>:</p>
<ul>
<li>stm32h7xx_hal_hrtim.c:
<ul>
<li>Update HRTIM_HRTIM_ISR implementation to optimize the read flags</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL IWDG</strong>:
+<li><p><strong>HAL/LL IWDG</strong>:</p>
<ul>
<li>stm32h7xx_hal_iwdg.c:
<ul>
<li>Update timeout mechanism to avoid false timeout detection in case of preemptio</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL LPTIM</strong>
+<li><p><strong>HAL/LL LPTIM</strong></p>
<ul>
<li>stm32h7xx_hal_lptim.c:
<ul>
<li>Update “HAL_LPTIM_Init” implementation to improve behavior for external clock configuration</li>
</ul></li>
</ul></li>
-<li><strong>HAL NAND</strong>:
+<li><p><strong>HAL NAND</strong>:</p>
<ul>
<li>stm32h7xx_hal_nand.c:
<ul>
@@ -177,7 +360,7 @@
<li>Update implementation of “HAL_NAND_Write_Page_16b” and “HAL_NAND_Read_Page_16b” APIs implementation to fix an issue with the page calculation of 8 bits memories</li>
</ul></li>
</ul></li>
-<li><strong>HAL NOR</strong>:
+<li><p><strong>HAL NOR</strong>:</p>
<ul>
<li>stm32h7xx_hal_nor.c:
<ul>
@@ -185,7 +368,7 @@
<li>Update NOR APIs implementation to support some specific memories</li>
</ul></li>
</ul></li>
-<li><strong>HAL RCC</strong>:
+<li><p><strong>HAL RCC</strong>:</p>
<ul>
<li>stm32h7xx_hal_rcc.c:
<ul>
@@ -202,7 +385,7 @@
<li>Update implementation of “HAL_RCCEx_GetPLL1ClockFreq” to use HSI in default case as per the specification</li>
</ul></li>
</ul></li>
-<li><strong>HAL RNG</strong>:
+<li><p><strong>HAL RNG</strong>:</p>
<ul>
<li>stm32h7xx_hal_rng.h:
<ul>
@@ -223,7 +406,7 @@
<li>Add “HAL_RNGEx_RecoverSeedError” function</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL SDMMC</strong>:
+<li><p><strong>HAL/LL SDMMC</strong>:</p>
<ul>
<li>stm32h7xx_hal_mmc.c:
<ul>
@@ -255,7 +438,7 @@
<li>Add “SDMMC_CmdSetRelAddMmc” function to set relative address</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL SPI</strong>
+<li><p><strong>HAL/LL SPI</strong></p>
<ul>
<li>Update “HAL_SPI_TransmitReceive_IT” implementation to disable RXP and TXP interrupt when DXP is enabled</li>
<li>Update “HAL_SPI_Init” implementation with NSS Software Management</li>
@@ -264,14 +447,14 @@
<li>Update “LL_SPI_Init” implementation to set the internal SS level</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL TIM</strong>:
+<li><p><strong>HAL/LL TIM</strong>:</p>
<ul>
<li>stm32h7xx_ll_tim.h:
<ul>
<li>Fix “LL_TIM_GetCounterMode” implementation to handle all possible return combinations</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL UART</strong>:
+<li><p><strong>HAL/LL UART</strong>:</p>
<ul>
<li>stm32h7xx_hal_uart.h:
<ul>
@@ -302,14 +485,14 @@
<li>Update “LL_LPUART_SetBaudRate” implementation to avoid potential division by zero</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL USART</strong>:
+<li><p><strong>HAL/LL USART</strong>:</p>
<ul>
<li>stm32h7xx_ll_usart.h:
<ul>
<li>Update “LL_USART_SetBaudRate” implementation to avoid potential division by zero</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL USB</strong>:
+<li><p><strong>HAL/LL USB</strong>:</p>
<ul>
<li>Update to ensure to have coherency between USB APIs start and stop which should mainly control device connect and disconnect of the USB RPU</li>
<li>Fix ping with DMA OFF, fix Data toggle issue with DMA multi max packet size transfers and clean up device and core speeds</li>
@@ -318,7 +501,7 @@
<li>Update to fix USB OTG read FIFO packet in stm32h7xx_ll_usb.c file</li>
<li>Update to support USB OTG FIFO with scatter gather</li>
</ul></li>
-<li><strong>LL SYSTEM</strong>:
+<li><p><strong>LL SYSTEM</strong>:</p>
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
@@ -326,14 +509,14 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li><strong>HAL/ETH</strong>
<ul>
<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility">Backward compatibility</h2>
+<h2 id="backward-compatibility-1">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -342,7 +525,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>First official release of the STM32CubeH7 Firmware Package supporting <strong>STM32H72x/3x</strong> new devices</li>
<li>General updates to fix known defects and implementation enhancements</li>
@@ -414,7 +597,7 @@
<li>stm32h7xx_hal_eth.h:
<ul>
<li><p>Update ETH_DMADescTypeDef definition: remove useless volatile of the BackupAddr0 and BackupAddr1 fields since they are not used by ETH DMA.</p></li>
-<li>stm32h7xx_hal_eth.c:
+<li><p>stm32h7xx_hal_eth.c:</p>
<ul>
<li>HAL_ETH_Start_IT:
<ul>
@@ -936,11 +1119,11 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li>Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 families)</li>
</ul>
@@ -949,7 +1132,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -1183,7 +1366,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1193,7 +1376,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-2">Backward compatibility</h2>
+<h2 id="backward-compatibility-3">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -1202,12 +1385,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
-<li>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
-</li>
-<li>General updates to fix known defects and implementation enhancements</li>
-<li><strong>HAL</strong>: generic
+<li><p>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
+</p></li>
+<li><p>General updates to fix known defects and implementation enhancements</p></li>
+<li><p><strong>HAL</strong>: generic</p>
<ul>
<li>stm32h7xx_hal.h:
<ul>
@@ -1229,7 +1412,7 @@
<li>Fix HAL_EXTI_D1_ClearFlag and HAL_EXTI_D2_ClearFlag APIs implementation: using direct write operation (instead of read/modify/write)</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL ADC</strong>:
+<li><p><strong>HAL/LL ADC</strong>:</p>
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
@@ -1266,7 +1449,7 @@
<li>Update HAL_ADCEx_LinearCalibration_FactorLoad API implementation to consider ADC2 and ADC3 in addition to ADC1</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL COMP</strong>:
+<li><p><strong>HAL/LL COMP</strong>:</p>
<ul>
<li>stm32h7xx_hal_comp.h:
<ul>
@@ -1292,7 +1475,7 @@
<li>Add LL_COMP_SetOutputAlternateFunction and LL_COMP_GetOutputAlternateFunction allowing to Set/Get the output alternate function in the Option register</li>
</ul></li>
</ul></li>
-<li><strong>HAL CRYP</strong>:
+<li><p><strong>HAL CRYP</strong>:</p>
<ul>
<li>stm32h7xx_hal_cryp.h:
<ul>
@@ -1306,7 +1489,7 @@
<li>Update to support user input/output buffers size that is not multiple of 4 words (size of the CRYP peripheral FIFO)</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL DAC</strong>:
+<li><p><strong>HAL/LL DAC</strong>:</p>
<ul>
<li>stm32h7xx_hal_dac.h:
<ul>
@@ -1346,7 +1529,7 @@
</ul></li>
<li>stm32h7xx_ll_dac.h: Update to support STM32H7A3/B3xx/B0xx devices New DAC triggers</li>
</ul></li>
-<li><strong>HAL DCMI</strong>:
+<li><p><strong>HAL DCMI</strong>:</p>
<ul>
<li>stm32h7xx_hal_dcmi.h:
<ul>
@@ -1358,7 +1541,7 @@
<li>Add implementation HAL_DCMI_ConfigSyncUnmask API</li>
</ul></li>
</ul></li>
-<li><strong>HAL DFSDM</strong>:
+<li><p><strong>HAL DFSDM</strong>:</p>
<ul>
<li>stm32h7xx_hal_dfsdm.h:
<ul>
@@ -1377,7 +1560,7 @@
<li>New extension file with HAL_DFDSMEx_ChannelSetPulsesSkipping and HAL_DFDSMEx_ChannelGetPulsesSkipping APIs implementation</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL DMA</strong>:
+<li><p><strong>HAL/LL DMA</strong>:</p>
<ul>
<li>stm32h7xx_hal_dma.h:
<ul>
@@ -1403,7 +1586,7 @@
<li>HRTIM, SAI3, SAI4, ADC3 requests are available only when these peripherals are present on the given device (through CMSIS device mapping)</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL DMA2D</strong>:
+<li><p><strong>HAL/LL DMA2D</strong>:</p>
<ul>
<li>stm32h7xx_hal_dma2d.h:
<ul>
@@ -1434,28 +1617,28 @@
<li>Update LL_DMA2D_StructInit API implementation to support byte swap and line offset modes</li>
</ul></li>
</ul></li>
-<li><strong>HAL DTS</strong>:
+<li><p><strong>HAL DTS</strong>:</p>
<ul>
<li>Add New HAL DTS driver stm32h7xx_hal_dts.h/stm32h7xx_hal_dts.c (Digital Temperature Sensor). This peripheral is available on STM32H7A3/B3xx/B0xx devices only</li>
</ul></li>
-<li><strong>HAL/LL EXTI</strong>:
+<li><p><strong>HAL/LL EXTI</strong>:</p>
<ul>
<li>Update to consider STM32H7A3/B3xx/B0xx devices EXTI lines</li>
<li>Update EXTI Pend Clear Sources considering STM32H7A3/B3xx/B0xx devices: LPTIM2 and LPTIM3 used as SRD domain wakeup pend clear source versus LPTIM4/LPTIM5 in the legacy devices</li>
</ul></li>
-<li><strong>HAL FLASH</strong>:
+<li><p><strong>HAL FLASH</strong>:</p>
<ul>
<li>Update to consider Flash operations on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
-<li><strong>HAL GFXMMU</strong>:
+<li><p><strong>HAL GFXMMU</strong>:</p>
<ul>
<li>Add GFXMMU HAL driver stm32h7xx_hal_gfxmmu.h/stm32h7xx_hal_gfxmmu.c. This peripheral is available on STM32H7A3/B3xx/B0xx devices only</li>
</ul></li>
-<li><strong>HAL GPIO</strong>:
+<li><p><strong>HAL GPIO</strong>:</p>
<ul>
<li>Update GPIO Alternate functions definitions (in stm32h7xx_hal_gpio_ex.h file) for STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
-<li><strong>HAL HASH</strong>:
+<li><p><strong>HAL HASH</strong>:</p>
<ul>
<li>stm32h7xx_hal_hash.h:
<ul>
@@ -1477,7 +1660,7 @@
<li>Add implementation of HAL_HASHEx_SHA224_Accmlt_IT/HAL_HASHEx_SHA224_Accmlt_End_IT, HAL_HASHEx_SHA256_Accmlt_IT/HAL_HASHEx_SHA256_Accmlt_End_IT APIs</li>
</ul></li>
</ul></li>
-<li><strong>HAL I2S</strong>:
+<li><p><strong>HAL I2S</strong>:</p>
<ul>
<li>stm32h7xx_hal_i2s.h:
<ul>
@@ -1493,7 +1676,7 @@
</ul></li>
<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c : These files are empty as full duplex feature is not available in this release</li>
</ul></li>
-<li><strong>HAL/LL LPTIM</strong>:
+<li><p><strong>HAL/LL LPTIM</strong>:</p>
<ul>
<li>stm32h7xx_hal_lptim.h:
<ul>
@@ -1504,7 +1687,7 @@
<li>Add definition of LL_LPTIM_TRIG_SOURCE_LPTIM2 to LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK trigger sources</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL MDMA</strong>:
+<li><p><strong>HAL/LL MDMA</strong>:</p>
<ul>
<li>stm32h7xx_hal_mdma.h:
<ul>
@@ -1525,7 +1708,7 @@
<li>Delimit definition of LTDC, QUADSPI and JPEG requests by the peripherals availability</li>
</ul></li>
</ul></li>
-<li><strong>HAL MMC</strong>:
+<li><p><strong>HAL MMC</strong>:</p>
<ul>
<li>stm32h7xx_hal_mmc_ex.h:
<ul>
@@ -1541,7 +1724,7 @@
<li>Fix HAL_MMCEx_ConfigDMAMultiBuffer API implementation regarding DMA block size</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL OPAMP</strong>:
+<li><p><strong>HAL/LL OPAMP</strong>:</p>
<ul>
<li>stm32h7xx_hal_opamp.h:
<ul>
@@ -1563,14 +1746,14 @@
<li><p><strong>HAL OSPI</strong>: New HAL driver stm32h7xx_hal_ospi.h/stm32h7xx_hal_ospi.c to handle OctoSPI peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
<li><p><strong>HAL OTFDEC</strong>: New HAL driver stm32h7xx_hal_otfdec.h/stm32h7xx_hal_otfdec.c to handle OTFDEC peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
<li><p><strong>HAL PSSI</strong>: New HAL driver stm32h7xx_hal_pssi.h/stm32h7xx_hal_pssi.c to handle PSSI peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
-<li><strong>HAL/LL PWR</strong>: Update to handle STM32H7A3/B3xx/B0xx devices
+<li><p><strong>HAL/LL PWR</strong>: Update to handle STM32H7A3/B3xx/B0xx devices</p>
<ul>
<li>2 power domains only (versus 3 in legacy STM32H7 devices)</li>
<li>VOS0 voltage scalling management</li>
<li>Wake up flag management</li>
<li>STOP2 Low Power mode management</li>
</ul></li>
-<li><strong>HAL RAMECC</strong>:
+<li><p><strong>HAL RAMECC</strong>:</p>
<ul>
<li>stm32h7xx_hal_ramecc.h:
<ul>
@@ -1584,7 +1767,7 @@
<li>Add HAL_RAMECC_IsECCSingleErrorDetected, HAL_RAMECC_IsECCDoubleErrorDetected APIs implementation</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL RCC</strong>:
+<li><p><strong>HAL/LL RCC</strong>:</p>
<ul>
<li>stm32h7xx_hal_rcc.h: Update to support STM32H7A3/B3xx/B0xx devices</li>
<li>Add OCTOSPI1/2, OCTOSPIM, OTFDEC1/2, GFXMMU peripherals clock enabling/disabling, force reset/release reset macros</li>
@@ -1614,7 +1797,7 @@
</ul></li>
<li>Update other peripherals clock source definitions according to the number of instance on STM32H7A3/B3xx/B0xx devices and on the legacy STM32H7 devices</li>
</ul></li>
-<li><strong>HAL/LL RNG</strong>:
+<li><p><strong>HAL/LL RNG</strong>:</p>
<ul>
<li>stm32h7xx_hal_rng.h: Update to support STM32H7A3/B3xx/B0xx devices</li>
<li>Add definition of HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_SEED and HAL_RNG_ERROR_CLOCK error codes</li>
@@ -1644,7 +1827,7 @@
</ul></li>
</ul></li>
<li><p><strong>HAL/LL RTC</strong>: Update to support STM32H7A3/B3xx/B0xx devices new RTC features</p></li>
-<li><strong>HAL SAI</strong>:
+<li><p><strong>HAL SAI</strong>:</p>
<ul>
<li>Update to support STM32H7A3/B3xx/B0xx devices SAI instances:
<ul>
@@ -1653,11 +1836,11 @@
<li>Usage of a giving SAI instance is conditioned with its presence on the given device (according to the CMSIS device memory mapping)</li>
</ul></li>
</ul></li>
-<li><strong>HAL SAI</strong>:
+<li><p><strong>HAL SAI</strong>:</p>
<ul>
<li>Update to support STM32H7A3/B3xx/B0xx devices SAI instances:</li>
</ul></li>
-<li><strong>HAL SD</strong>:
+<li><p><strong>HAL SD</strong>:</p>
<ul>
<li>stm32h7xx_hal_sd_ex.h:
<ul>
@@ -1674,7 +1857,7 @@
<li>Fix HAL_SDEx_ReadBlocksDMAMultiBuffer/HAL_SDEx_WriteBlocksDMAMultiBuffer APIs implementation to avoid losing data in read and dead lock in write</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL SPI</strong>:
+<li><p><strong>HAL/LL SPI</strong>:</p>
<ul>
<li>stm32h7xx_hal_spi.c:
<ul>
@@ -1686,14 +1869,14 @@
</ul></li>
</ul></li>
</ul></li>
-<li><strong>HAL SPI</strong>:
+<li><p><strong>HAL SPI</strong>:</p>
<ul>
<li>stm32h7xx_hal_spi.c:
<ul>
<li>Fix GCC compilation war</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL TIM</strong>:
+<li><p><strong>HAL/LL TIM</strong>:</p>
<ul>
<li>stm32h7xx_hal_tim.h:
<ul>
@@ -1711,19 +1894,19 @@
<li>Update TIM_SlaveTimer_SetConfig API implementation to handle TIM_TS_ITR9 to TIM_TS_ITR13 input triggers</li>
</ul></li>
</ul></li>
-<li><strong>LL BUS</strong>:
+<li><p><strong>LL BUS</strong>:</p>
<ul>
<li>stm32h7xx_ll_bus.h: Update to support STM32H7A3/B3xx/B0xx devices peripherals</li>
</ul></li>
-<li><strong>LL CRS</strong>:
+<li><p><strong>LL CRS</strong>:</p>
<ul>
<li>stm32h7xx_ll_crs.h/stm32h7xx_ll_crs.c: New LL driver allowing to handle CRS (Clock Recovery System) module</li>
</ul></li>
-<li><strong>LL SDMMC</strong> (LL core driver for HAL SD/MMC):
+<li><p><strong>LL SDMMC</strong> (LL core driver for HAL SD/MMC):</p>
<ul>
<li>stm32h7xx_ll_sdmmc.c: Fix SDMMC_CmdStopTransfer implementation to ignore address Out Of Range error that is not relevant at end of memory</li>
</ul></li>
-<li><strong>LL SYSTEM</strong>:
+<li><p><strong>LL SYSTEM</strong>:</p>
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
@@ -1735,7 +1918,7 @@
<li>Add LL_SYSCFG_VDMMCSetNMOSCompensationCode/LL_SYSCFG_VDMMCGetNMOSCompensationCode APIs</li>
</ul></li>
</ul></li>
-<li><strong>LL UTILS</strong>:
+<li><p><strong>LL UTILS</strong>:</p>
<ul>
<li>stm32h7xx_ll_utils.h:
<ul>
@@ -1743,7 +1926,7 @@
<li>Update LL_GetPackageType API to support STM32H7A3/B3xx/B0xx devices package types</li>
</ul></li>
</ul></li>
-<li><strong>LL DELAY BLOCK</strong> (LL core driver for HAL SD):
+<li><p><strong>LL DELAY BLOCK</strong> (LL core driver for HAL SD):</p>
<ul>
<li>stm32h7xx_ll_delayblock.h:
<ul>
@@ -1757,7 +1940,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1771,7 +1954,7 @@
<li>New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-3">Backward compatibility</h2>
+<h2 id="backward-compatibility-4">Backward compatibility</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1795,10 +1978,10 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
-<li>General updates to fix known defects and implementation enhancements</li>
-<li><strong>HAL</strong>: generic
+<li><p>General updates to fix known defects and implementation enhancements</p></li>
+<li><p><strong>HAL</strong>: generic</p>
<ul>
<li>stm32h7xx_hal.h:
<ul>
@@ -1818,7 +2001,7 @@
<li>Add “USE_SPI_CRC” definition set to 1 by default and customizable by the HAL user</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL ADC</strong>:
+<li><p><strong>HAL/LL ADC</strong>:</p>
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
@@ -1854,7 +2037,7 @@
<li>Update “HAL_ADCEx_InjectedConfigChannel” implementation to set the ADC selected offset right shift</li>
</ul></li>
</ul></li>
-<li><strong>HAL CRYP</strong>:
+<li><p><strong>HAL CRYP</strong>:</p>
<ul>
<li>stm32h7xx_hal_cryp.c:
<ul>
@@ -1862,14 +2045,14 @@
<li>Update “CRYP_Workaround” to fix the implementation of the authentication tags computation phase during a GCM encryption when the size of the last payload block is inferior to 128 bits</li>
</ul></li>
</ul></li>
-<li><strong>HAL GPIO</strong>:
+<li><p><strong>HAL GPIO</strong>:</p>
<ul>
<li>stm32h7xx_hal_gpio.c:
<ul>
<li>Fix implementation of “HAL_GPIO_DeInit” API in order to clear the correct external interrupt/event in SYSCFG EXTICR register</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL HRTIM</strong>:
+<li><p><strong>HAL/LL HRTIM</strong>:</p>
<ul>
<li>stm32h7xx_hal_hrtim.h:
<ul>
@@ -1889,21 +2072,21 @@
<li>Fix definitions of the output set sources (“LL_HRTIM_CROSSBAR_NONE” to “LL_HRTIM_CROSSBAR_UPDATE” replacing “LL_HRTIM_OUTPUTSET_NONE” to LL_HRTIM_OUTPUTSET_UPDATE) according to the reference manual (<strong>compatibility break</strong>)</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL HSEM</strong>:
+<li><p><strong>HAL/LL HSEM</strong>:</p>
<ul>
<li>stm32h7xx_hal_hsem.c:
<ul>
<li>Update “HAL_HSEM_Release” implementation to support dynamic CPU ID detection useful when code is intended to be shared between the Cortex-M4 and Cortex-M7 in a dual core device</li>
</ul></li>
</ul></li>
-<li><strong>HAL IRDA</strong>:
+<li><p><strong>HAL IRDA</strong>:</p>
<ul>
<li>stm32h7xx_hal_irda.c:
<ul>
<li>Update description of “HAL_IRDA_Transmit_XXX”, “HAL_IRDA_Receive_XXX” APIs with more details about the data size management</li>
</ul></li>
</ul></li>
-<li><strong>HAL LPTIM</strong>:
+<li><p><strong>HAL LPTIM</strong>:</p>
<ul>
<li>stm32h7xx_hal_lptim.c:
<ul>
@@ -1921,7 +2104,7 @@
</ul></li>
</ul></li>
</ul></li>
-<li><strong>HAL MMC</strong>:
+<li><p><strong>HAL MMC</strong>:</p>
<ul>
<li>stm32h7xx_hal_mmc.h:
<ul>
@@ -1975,14 +2158,14 @@
<li>Update “HAL_SD_ConfigSpeedBusOperation” implementation to handle “SDMMC_SPEED_MODE_AUTO” and “SDMMC_SPEED_MODE_HIGH” SD card speed modes in case of no transceiver present</li>
</ul></li>
</ul></li>
-<li><strong>LL SDMMC</strong>:
+<li><p><strong>LL SDMMC</strong>:</p>
<ul>
<li>Update “SDMMC_InitTypeDef” structure to add “TranceiverPresent” field in case of the define “USE_SD_TRANSCEIVER” is not zero:
<ul>
<li>This parameter allows to handle 2 SD instances with different settings regarding the transceiver presence as described above</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL RCC</strong>:
+<li><p><strong>HAL/LL RCC</strong>:</p>
<ul>
<li>stm32h7xx_ll_rcc.h:
<ul>
@@ -1997,7 +2180,7 @@
<li>Update “HAL_RCCEx_GetPeriphCLKFreq” API implementation to add support of the SDMMC peripheral clock frequency calculation</li>
</ul></li>
</ul></li>
-<li><strong>HAL TIM</strong>:
+<li><p><strong>HAL TIM</strong>:</p>
<ul>
<li>stm32h7xx_hal_tim.h:
<ul>
@@ -2018,7 +2201,7 @@
<li>Update “HAL_TIMEx_ConfigBreakDeadTime” description to add details about interrupts enabling and generation</li>
</ul></li>
</ul></li>
-<li><strong>HAL UART</strong>:
+<li><p><strong>HAL UART</strong>:</p>
<ul>
<li>Update to add UART Receiver timeout management (RTOF)</li>
<li>stm32h7xx_hal_uart.h:
@@ -2036,7 +2219,7 @@
<li>Add implementation of “HAL_UART_ReceiverTimeout_Config”, “HAL_UART_EnableReceiverTimeout” and “HAL_UART_DisableReceiverTimeout” APIs</li>
</ul></li>
</ul></li>
-<li><strong>HAL USB</strong>:
+<li><p><strong>HAL USB</strong>:</p>
<ul>
<li>stm32h7xx_hal_hcd.c
<ul>
@@ -2051,7 +2234,7 @@
<li>Update “HAL_PCD_IRQHandler” to remove useless initialization of epnum variable in HAL_PCD_IRQHandler() for OTG instance</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL USART</strong>:
+<li><p><strong>HAL/LL USART</strong>:</p>
<ul>
<li>stm32h7xx_hal_usart.c:
<ul>
@@ -2062,7 +2245,7 @@
<li>Update “LL_USART_SetBaudRate” implementation to avoid overflow in “USART_PRESCALER_TAB” table</li>
</ul></li>
</ul></li>
-<li><strong>LL SYSTEM</strong>:
+<li><p><strong>LL SYSTEM</strong>:</p>
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
@@ -2070,11 +2253,11 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-4">Backward compatibility</h2>
+<h2 id="backward-compatibility-5">Backward compatibility</h2>
<ul>
<li><strong>HAL TIM</strong>:
<ul>
@@ -2092,7 +2275,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add support for VOS0 power regulator voltage scaling with 480MHz over clock</li>
@@ -2562,7 +2745,7 @@
<li>Update LL_Init1msTick and LL_SetSystemCoreClock description for <strong>DUAL CORE</strong> lines</li>
</ul></li>
</ul>
-<h2 id="known-limitations-5">Known Limitations</h2>
+<h2 id="known-limitations-6">Known Limitations</h2>
<ul>
<li><strong>HAL SD</strong>:
<ul>
@@ -2576,7 +2759,7 @@
<li>Full duplex Transmit/receive feature not available</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-5">Backward compatibility</h2>
+<h2 id="backward-compatibility-6">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -2628,7 +2811,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</li>
@@ -2897,7 +3080,7 @@
<li>Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled</li>
</ul></li>
</ul>
-<h2 id="known-limitations-6">Known Limitations</h2>
+<h2 id="known-limitations-7">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -2905,7 +3088,7 @@
<li>A new version of this driver will be available in next release with full features tested</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-6">Backward compatibility</h2>
+<h2 id="backward-compatibility-7">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -2944,8 +3127,7 @@
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
-<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers</li>
<li><strong>HAL Cortex</strong>: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15</li>
@@ -2953,22 +3135,18 @@
<li><strong>HAL SDMMC</strong>: Fix and enhancements to support high speed mode</li>
</ul>
</div>
-</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
-<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL SPI</strong>: Driver reworked to fix critical issues</li>
<li>HAL: Update HAL Tick implementation</li>
</ul>
</div>
-</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
-<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL FLASH</strong>: Add Mass Erase for both banks</li>
@@ -2979,17 +3157,14 @@
<li><strong>HAL SPDIFRX</strong>: Add symbol clock generation</li>
</ul>
</div>
-</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
-<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>First official release for STM32H743xx/753xx devices</li>
</ul>
</div>
-</div>
-</div>
+</section>
</div>
<footer class="sticky">
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
diff --git a/Src/stm32h7xx_hal.c b/Src/stm32h7xx_hal.c
index 099fb4b..bda07b4 100644
--- a/Src/stm32h7xx_hal.c
+++ b/Src/stm32h7xx_hal.c
@@ -5,6 +5,17 @@
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,17 +30,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -47,11 +47,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32H7xx HAL Driver version number V1.10.0
+ * @brief STM32H7xx HAL Driver version number V1.10.1
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x0AUL) /*!< [23:16] sub1 version */
-#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
+#define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
|(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
@@ -914,7 +914,7 @@
* @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
* @retval None
*/
-void HAL_EnableDBGSleepMode(void)
+void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
}
@@ -923,7 +923,7 @@
* @brief Disable the Debug Module during Domain1/CDomain SLEEP mode
* @retval None
*/
-void HAL_DisableDBGSleepMode(void)
+void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
}
@@ -933,7 +933,7 @@
* @brief Enable the Debug Module during Domain1/CDomain STOP mode
* @retval None
*/
-void HAL_EnableDBGStopMode(void)
+void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
}
@@ -942,7 +942,7 @@
* @brief Disable the Debug Module during Domain1/CDomain STOP mode
* @retval None
*/
-void HAL_DisableDBGStopMode(void)
+void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
}
@@ -951,7 +951,7 @@
* @brief Enable the Debug Module during Domain1/CDomain STANDBY mode
* @retval None
*/
-void HAL_EnableDBGStandbyMode(void)
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
}
@@ -960,7 +960,7 @@
* @brief Disable the Debug Module during Domain1/CDomain STANDBY mode
* @retval None
*/
-void HAL_DisableDBGStandbyMode(void)
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
}
@@ -1314,4 +1314,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_adc.c b/Src/stm32h7xx_hal_adc.c
index 7803f92..92152fe 100644
--- a/Src/stm32h7xx_hal_adc.c
+++ b/Src/stm32h7xx_hal_adc.c
@@ -5,20 +5,22 @@
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Converter (ADC)
* peripheral:
- * + Initialization and de-initialization functions
- * ++ Initialization and Configuration of ADC
- * + Operation functions
- * ++ Start, stop, get result of conversions of regular
- * group, using 3 possible modes: polling, interruption or DMA.
- * + Control functions
- * ++ Channels configuration on regular group
- * ++ Analog Watchdog configuration
- * + State functions
- * ++ ADC state machine management
- * ++ Interrupts and flags management
+ * + Peripheral Control functions
+ * + Peripheral State functions
* Other functions (extended functions) are available in file
* "stm32h7xx_hal_adc_ex.c".
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### ADC peripheral features #####
@@ -221,11 +223,11 @@
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_ADC_RegisterCallback()
+ Use Functions HAL_ADC_RegisterCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ Function HAL_ADC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
@@ -241,11 +243,11 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
@@ -261,27 +263,27 @@
(+) MspDeInitCallback : ADC Msp DeInit callback
[..]
- By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
- or @ref HAL_ADC_Init() function.
+ using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+ or HAL_ADC_Init() function.
[..]
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
@@ -290,17 +292,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2529,44 +2520,46 @@
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
- if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
- ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
{
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
{
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
{
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
}
}
}
@@ -4059,4 +4052,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_adc_ex.c b/Src/stm32h7xx_hal_adc_ex.c
index 8e44bf1..6dd4901 100644
--- a/Src/stm32h7xx_hal_adc_ex.c
+++ b/Src/stm32h7xx_hal_adc_ex.c
@@ -5,20 +5,21 @@
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Converter (ADC)
* peripheral:
- * + Operation functions
- * ++ Start, stop, get result of conversions of ADC group injected,
- * using 2 possible modes: polling, interruption.
- * ++ Calibration
- * +++ ADC automatic self-calibration
- * +++ Calibration factors get or set
- * ++ Multimode feature when available
- * + Control functions
- * ++ Channels configuration on ADC group injected
- * + State functions
- * ++ ADC group injected contexts queue management
+ * + Peripheral Control functions
* Other functions (generic functions) are available in file
* "stm32h7xx_hal_adc.c".
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
[..]
(@) Sections "ADC peripheral features" and "How to use this driver" are
@@ -26,17 +27,6 @@
[..]
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2102,7 +2092,18 @@
if (sConfigInjected->InjecOversamplingMode == ENABLE)
{
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance == ADC3)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO_ADC3(sConfigInjected->InjecOversampling.Ratio));
+ }
+ else
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+ }
+#else
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+#endif
assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
/* JOVSE must be reset in case of triggered regular mode */
@@ -2113,14 +2114,39 @@
/* - Right bit shift */
/* Enable OverSampling mode */
+#if defined(ADC_VER_V5_V90)
+ if (hadc->Instance != ADC3)
+ {
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_JOVSE |
+ ADC_CFGR2_OVSR |
+ ADC_CFGR2_OVSS,
+ ADC_CFGR2_JOVSE |
+ ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+ sConfigInjected->InjecOversampling.RightBitShift
+ );
+ }
+ else
+ {
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_JOVSE |
+ ADC3_CFGR2_OVSR |
+ ADC_CFGR2_OVSS,
+ ADC_CFGR2_JOVSE |
+ (sConfigInjected->InjecOversampling.Ratio) |
+ sConfigInjected->InjecOversampling.RightBitShift
+ );
+ }
+#else
MODIFY_REG(hadc->Instance->CFGR2,
- ADC_CFGR2_JOVSE |
- ADC_CFGR2_OVSR |
- ADC_CFGR2_OVSS,
- ADC_CFGR2_JOVSE |
- ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
- sConfigInjected->InjecOversampling.RightBitShift
- );
+ ADC_CFGR2_JOVSE |
+ ADC_CFGR2_OVSR |
+ ADC_CFGR2_OVSS,
+ ADC_CFGR2_JOVSE |
+ ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+ sConfigInjected->InjecOversampling.RightBitShift
+ );
+#endif
}
else
{
@@ -2145,7 +2171,7 @@
{
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
}
-
+
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
@@ -2590,4 +2616,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_cec.c b/Src/stm32h7xx_hal_cec.c
index d732a36..e9d04cf 100644
--- a/Src/stm32h7xx_hal_cec.c
+++ b/Src/stm32h7xx_hal_cec.c
@@ -11,6 +11,17 @@
* + Peripheral Control function
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -47,10 +58,10 @@
The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
+ Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
to register an interrupt callback.
- Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
+ Function HAL_CEC_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Transfer completed callback.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : CEC MspInit.
@@ -59,11 +70,11 @@
and a pointer to the user callback function.
For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
- @ref HAL_CEC_RegisterRxCpltCallback().
+ HAL_CEC_RegisterRxCpltCallback().
- Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Transfer completed callback.
@@ -72,15 +83,15 @@
(+) MspDeInitCallback : CEC MspDeInit.
For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
- @ref HAL_CEC_UnRegisterRxCpltCallback().
+ HAL_CEC_UnRegisterRxCpltCallback().
- By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
+ By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
all callbacks are set to the corresponding weak functions :
- examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
+ examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
+ reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
+ if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
@@ -88,25 +99,14 @@
in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
- or @ref HAL_CEC_Init() function.
+ using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
+ or HAL_CEC_Init() function.
When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -696,7 +696,7 @@
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
uint8_t *pData, uint32_t Size)
{
- /* if the IP isn't already busy and if there is no previous transmission
+ /* if the peripheral isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
if (hcec->gState == HAL_CEC_STATE_READY)
{
@@ -994,4 +994,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_comp.c b/Src/stm32h7xx_hal_comp.c
index 59a2590..e73ebb6 100644
--- a/Src/stm32h7xx_hal_comp.c
+++ b/Src/stm32h7xx_hal_comp.c
@@ -6,10 +6,19 @@
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
* + Initialization and de-initialization functions
- * + Start/Stop operation functions in polling mode
- * + Start/Stop operation functions in interrupt mode
* + Peripheral control functions
- * + Peripheral state functions
+ * + Peripheral state functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### COMP Peripheral features #####
@@ -98,11 +107,11 @@
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_COMP_RegisterCallback()
+ Use Functions HAL_COMP_RegisterCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
+ Function HAL_COMP_RegisterCallback() allows to register following callbacks:
(+) TriggerCallback : callback for COMP trigger.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
@@ -110,11 +119,11 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
+ Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TriggerCallback : callback for COMP trigger.
@@ -122,27 +131,27 @@
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
+ By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
all callbacks are set to the corresponding weak functions:
- example @ref HAL_COMP_TriggerCallback().
+ example HAL_COMP_TriggerCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
+ reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
+ in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
- or @ref HAL_COMP_Init() function.
+ using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
+ or HAL_COMP_Init() function.
[..]
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
@@ -180,17 +189,6 @@
(2) Comparators output to timers is set in timers instances.
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1247,4 +1245,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_cordic.c b/Src/stm32h7xx_hal_cordic.c
index 37f70e7..7ac929a 100644
--- a/Src/stm32h7xx_hal_cordic.c
+++ b/Src/stm32h7xx_hal_cordic.c
@@ -11,7 +11,18 @@
* + IRQ handler management
* + Peripheral State functions
*
- * @verbatim
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
================================================================================
##### How to use this driver #####
================================================================================
@@ -79,9 +90,9 @@
The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback.
+ Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback.
- Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks:
+ Function HAL_CORDIC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : Error Callback.
(+) CalculateCpltCallback : Calculate complete Callback.
(+) MspInitCallback : CORDIC MspInit.
@@ -89,9 +100,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : Error Callback.
@@ -101,11 +112,11 @@
By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback().
+ examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when
+ reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when
these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit()
+ if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
@@ -113,7 +124,7 @@
in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit()
+ using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit()
or HAL_CORDIC_Init() function.
When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
@@ -121,18 +132,6 @@
are set to the corresponding weak functions.
@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
******************************************************************************
*/
@@ -1352,5 +1351,3 @@
#endif /* HAL_CORDIC_MODULE_ENABLED */
#endif /* CORDIC */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_cortex.c b/Src/stm32h7xx_hal_cortex.c
index e45e793..05730c1 100644
--- a/Src/stm32h7xx_hal_cortex.c
+++ b/Src/stm32h7xx_hal_cortex.c
@@ -68,13 +68,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -530,4 +529,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_crc.c b/Src/stm32h7xx_hal_crc.c
index e0860ac..1deacc0 100644
--- a/Src/stm32h7xx_hal_crc.c
+++ b/Src/stm32h7xx_hal_crc.c
@@ -9,6 +9,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -29,17 +40,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -62,8 +62,8 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
+ * @{
+ */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/**
@@ -77,8 +77,8 @@
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -250,8 +250,8 @@
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions.
- *
+ * @brief management functions.
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -385,8 +385,8 @@
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -418,8 +418,8 @@
*/
/** @addtogroup CRC_Private_Functions
- * @{
- */
+ * @{
+ */
/**
* @brief Enter 8-bit input data to the CRC calculator.
@@ -514,5 +514,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_crc_ex.c b/Src/stm32h7xx_hal_crc_ex.c
index 97e70c1..d713187 100644
--- a/Src/stm32h7xx_hal_crc_ex.c
+++ b/Src/stm32h7xx_hal_crc_ex.c
@@ -6,6 +6,17 @@
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### How to use this driver #####
@@ -16,17 +27,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -221,5 +221,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_cryp.c b/Src/stm32h7xx_hal_cryp.c
index c1febda..d4684da 100644
--- a/Src/stm32h7xx_hal_cryp.c
+++ b/Src/stm32h7xx_hal_cryp.c
@@ -13,6 +13,17 @@
* + CRYP IRQ handler management
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -251,20 +262,6 @@
95 ...64 CRYP_IV1L[31:0] B0[95:64]
63 ... 32 CRYP_IV0R[31:0] B0[63:32]
31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
-
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -456,7 +453,7 @@
}
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
- /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type and Algorithm */
+ /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
#if !defined (CRYP_VER_2_2)
@@ -567,7 +564,7 @@
hcryp->Init.B0 = pConf->B0;
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
- /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type, AlgoMode and operating mode*/
+ /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
@@ -976,7 +973,7 @@
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Statrt DES/TDES encryption process */
+ /* Start DES/TDES encryption process */
status = CRYP_TDES_Process(hcryp, Timeout);
break;
@@ -5179,4 +5176,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_cryp_ex.c b/Src/stm32h7xx_hal_cryp_ex.c
index ae24733..c871552 100644
--- a/Src/stm32h7xx_hal_cryp_ex.c
+++ b/Src/stm32h7xx_hal_cryp_ex.c
@@ -7,6 +7,17 @@
* functionalities of CRYP extension peripheral:
* + Extended AES processing functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,18 +27,6 @@
Encryption/Decryption to get the authentication messages.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -158,7 +157,7 @@
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
- /*ALGODIR bit must be set to ‘0’.*/
+ /*ALGODIR bit must be set to '0'.*/
hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
/* Enable the CRYP peripheral */
@@ -315,7 +314,7 @@
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
- /* Select final phase & ALGODIR bit must be set to ‘0’. */
+ /* Select final phase & ALGODIR bit must be set to '0'. */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
@@ -455,4 +454,3 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dac.c b/Src/stm32h7xx_hal_dac.c
index db5ab8c..2425ee3 100644
--- a/Src/stm32h7xx_hal_dac.c
+++ b/Src/stm32h7xx_hal_dac.c
@@ -11,6 +11,17 @@
* + Peripheral State and Errors functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### DAC Peripheral features #####
@@ -48,6 +59,7 @@
(DAC_TRIGGER_HR1_TRGO1, DAC_TRIGGER_HR1_TRGO2)
(#) Software using DAC_TRIGGER_SOFTWARE
+
*** DAC Buffer mode feature ***
===============================
[..]
@@ -60,15 +72,6 @@
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
- *** DAC connect feature ***
- ===============================
- [..]
- Each DAC channel can be connected internally.
- To connect, use
- sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
- or
- sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;
-
*** GPIO configurations guidelines ***
=====================
[..]
@@ -219,7 +222,7 @@
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+ Use Functions HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@@ -234,7 +237,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@@ -249,12 +252,12 @@
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+ By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
- and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
+ and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -262,8 +265,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
- or @ref HAL_DAC_Init function.
+ using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
+ or HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -284,17 +287,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -542,6 +534,7 @@
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
}
}
+
else
{
/* Check if software trigger enabled */
@@ -552,6 +545,7 @@
}
}
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -595,7 +589,7 @@
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param pData The destination peripheral Buffer address.
+ * @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
@@ -653,6 +647,7 @@
break;
}
}
+
else
{
/* Set the DMA transfer complete callback for channel2 */
@@ -687,6 +682,7 @@
}
}
+
/* Enable the DMA Stream */
if (Channel == DAC_CHANNEL_1)
{
@@ -696,6 +692,7 @@
/* Enable the DMA Stream */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
+
else
{
/* Enable the DAC DMA underrun interrupt */
@@ -705,6 +702,7 @@
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
+
/* Process Unlocked */
__HAL_UNLOCK(hdac);
@@ -754,6 +752,7 @@
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
+
else /* Channel2 is used for */
{
/* Disable the DMA Stream */
@@ -763,6 +762,7 @@
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -788,7 +788,7 @@
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to chanel1 DMA underrun error */
+ /* Set DAC error code to channel1 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
/* Clear the underrun flag */
@@ -806,6 +806,7 @@
}
}
+
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
{
/* Check underrun flag of DAC channel 2 */
@@ -831,6 +832,7 @@
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
+
}
/**
@@ -851,7 +853,7 @@
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
- __IO uint32_t tmp = 0;
+ __IO uint32_t tmp = 0UL;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -863,11 +865,13 @@
{
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
+
else
{
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
+
/* Set the DAC channel selected data holding register */
*(__IO uint32_t *) tmp = Data;
@@ -970,18 +974,23 @@
*/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ uint32_t result;
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
- /* Returns the DAC channel data output register value */
if (Channel == DAC_CHANNEL_1)
{
- return hdac->Instance->DOR1;
+ result = hdac->Instance->DOR1;
}
+
else
{
- return hdac->Instance->DOR2;
+ result = hdac->Instance->DOR2;
}
+
+ /* Returns the DAC channel data output register value */
+ return result;
}
/**
@@ -1052,6 +1061,7 @@
HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
+
else /* Channel 2 */
{
/* SHSR2 can be written when BWST2 is cleared */
@@ -1073,6 +1083,7 @@
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
+
/* HoldTime */
MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
@@ -1143,7 +1154,7 @@
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
- hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
+ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -1267,6 +1278,7 @@
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = pCallback;
break;
+
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = pCallback;
break;
@@ -1279,6 +1291,7 @@
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = pCallback;
break;
+
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
@@ -1366,6 +1379,7 @@
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
break;
+
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
break;
@@ -1378,6 +1392,7 @@
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
break;
+
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
@@ -1389,10 +1404,12 @@
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
hdac->MspInitCallback = HAL_DAC_MspInit;
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
@@ -1522,4 +1539,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dac_ex.c b/Src/stm32h7xx_hal_dac_ex.c
index 50dd895..c9290be 100644
--- a/Src/stm32h7xx_hal_dac_ex.c
+++ b/Src/stm32h7xx_hal_dac_ex.c
@@ -7,13 +7,26 @@
* functionalities of the DAC peripheral.
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
+
*** Dual mode IO operation ***
==============================
+ [..]
(+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
for dual mode operation.
If software trigger is selected, using HAL_DACEx_DualStart() will start
@@ -35,6 +48,7 @@
*** Signal generation operation ***
===================================
+ [..]
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
@@ -46,17 +60,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
@@ -106,6 +109,7 @@
* @{
*/
+
/**
* @brief Enables DAC and starts conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -343,6 +347,7 @@
return status;
}
+
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -443,6 +448,7 @@
return HAL_OK;
}
+
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -552,6 +558,7 @@
*/
}
+
/**
* @brief Run the self calibration of one DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -762,6 +769,7 @@
* @{
*/
+
/**
* @brief Return the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -780,10 +788,10 @@
return tmp;
}
+
/**
* @}
*/
-
/**
* @}
*/
@@ -794,6 +802,7 @@
* @{
*/
+
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
@@ -852,6 +861,7 @@
hdac->State = HAL_DAC_STATE_READY;
}
+
/**
* @}
*/
@@ -868,4 +878,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dcmi.c b/Src/stm32h7xx_hal_dcmi.c
index f9079cf..50971e7 100644
--- a/Src/stm32h7xx_hal_dcmi.c
+++ b/Src/stm32h7xx_hal_dcmi.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -105,18 +116,6 @@
(@) You can refer to the DCMI HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1224,4 +1223,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dfsdm.c b/Src/stm32h7xx_hal_dfsdm.c
index e73cd80..f83b8a5 100644
--- a/Src/stm32h7xx_hal_dfsdm.c
+++ b/Src/stm32h7xx_hal_dfsdm.c
@@ -16,6 +16,17 @@
* + Clock absence detector feature
* + Break generation on analog watchdog or short-circuit event
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -251,17 +262,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -3795,4 +3795,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dfsdm_ex.c b/Src/stm32h7xx_hal_dfsdm_ex.c
index de2f6c6..4b48b04 100644
--- a/Src/stm32h7xx_hal_dfsdm_ex.c
+++ b/Src/stm32h7xx_hal_dfsdm_ex.c
@@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -132,4 +131,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dma.c b/Src/stm32h7xx_hal_dma.c
index 934400c..b8a17fc 100644
--- a/Src/stm32h7xx_hal_dma.c
+++ b/Src/stm32h7xx_hal_dma.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -78,18 +89,6 @@
(@) You can refer to the DMA HAL driver header file for more useful macros.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -244,12 +243,12 @@
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
}
- /* Allocate lock resource */
- __HAL_UNLOCK(hdma);
-
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hdma);
+
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
@@ -358,12 +357,12 @@
assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
}
- /* Allocate lock resource */
- __HAL_UNLOCK(hdma);
-
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hdma);
+
/* Get the CR register value */
registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
@@ -652,12 +651,12 @@
}
else
{
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
/* Return error status */
status = HAL_ERROR;
}
@@ -748,12 +747,12 @@
}
else
{
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
/* Set the error code to busy */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
/* Return error status */
status = HAL_ERROR;
}
@@ -835,12 +834,12 @@
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_ERROR;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
return HAL_ERROR;
}
}
@@ -873,11 +872,11 @@
}
}
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
}
return HAL_OK;
@@ -945,12 +944,12 @@
}
}
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
{
@@ -1173,10 +1172,10 @@
(*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
}
+ hdma->State = HAL_DMA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
- hdma->State = HAL_DMA_STATE_READY;
}
else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
{
@@ -1324,12 +1323,12 @@
/* Clear all interrupt flags at correct offset within the register */
regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
@@ -1366,11 +1365,11 @@
/* Disable the transfer complete interrupt */
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC);
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
}
if(hdma->XferCpltCallback != NULL)
@@ -1401,9 +1400,6 @@
}
while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
{
/* Change the DMA state to error if DMA disable fails */
@@ -1414,6 +1410,9 @@
/* Change the DMA state to Ready if DMA disable success */
hdma->State = HAL_DMA_STATE_READY;
}
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
}
if(hdma->XferErrorCallback != NULL)
@@ -1509,11 +1508,11 @@
/* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
}
if(hdma->XferCpltCallback != NULL)
@@ -1537,12 +1536,12 @@
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
@@ -1613,6 +1612,7 @@
break;
default:
+ status = HAL_ERROR;
break;
}
}
@@ -2054,4 +2054,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dma2d.c b/Src/stm32h7xx_hal_dma2d.c
index dcc1883..d535aa9 100644
--- a/Src/stm32h7xx_hal_dma2d.c
+++ b/Src/stm32h7xx_hal_dma2d.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -147,17 +158,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2183,5 +2183,3 @@
*/
#endif /* DMA2D */
#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dma_ex.c b/Src/stm32h7xx_hal_dma_ex.c
index e55c3d5..a134b4e 100644
--- a/Src/stm32h7xx_hal_dma_ex.c
+++ b/Src/stm32h7xx_hal_dma_ex.c
@@ -37,13 +37,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -711,4 +710,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dsi.c b/Src/stm32h7xx_hal_dsi.c
index 073c2a6..b193562 100644
--- a/Src/stm32h7xx_hal_dsi.c
+++ b/Src/stm32h7xx_hal_dsi.c
@@ -9,6 +9,17 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -140,17 +151,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -173,7 +173,7 @@
/** @addtogroup DSI_Private_Constants
* @{
*/
-#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
+#define DSI_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */
#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
@@ -200,12 +200,14 @@
uint32_t Data1);
static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
- uint32_t ChannelID,
- uint32_t Mode,
- uint32_t Param1,
- uint32_t Param2);
-
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2);
/* Private functions ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Functions DSI Private Functions
+ * @{
+ */
/**
* @brief Generic DSI packet header configuration
* @param DSIx Pointer to DSI register base
@@ -255,10 +257,10 @@
tickstart = HAL_GetTick();
/* Wait for Command FIFO Empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+ while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -271,6 +273,10 @@
return HAL_OK;
}
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DSI_Exported_Functions
* @{
@@ -365,11 +371,17 @@
/* Set the PLL division factors */
hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
- hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \
+ ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \
+ ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos));
/* Enable the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
+ /* Requires min of 400µs delay before reading the PLLLS flag */
+ /* 1ms delay is inserted that is the minimum HAL delay granularity */
+ HAL_Delay(1);
+
/* Get tick */
tickstart = HAL_GetTick();
@@ -419,7 +431,7 @@
hdsi->Instance->IER[1U] = 0U;
hdsi->ErrorMsk = 0U;
- /* Initialise the error code */
+ /* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
/* Initialize the DSI state*/
@@ -473,7 +485,7 @@
HAL_DSI_MspDeInit(hdsi);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
- /* Initialise the error code */
+ /* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
/* Initialize the DSI state*/
@@ -733,11 +745,11 @@
break;
case HAL_DSI_MSPINIT_CB_ID :
- hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
break;
case HAL_DSI_MSPDEINIT_CB_ID :
- hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
break;
default :
@@ -753,11 +765,11 @@
switch (CallbackID)
{
case HAL_DSI_MSPINIT_CB_ID :
- hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
break;
case HAL_DSI_MSPDEINIT_CB_ID :
- hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
break;
default :
@@ -808,7 +820,8 @@
*/
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
{
- uint32_t ErrorStatus0, ErrorStatus1;
+ uint32_t ErrorStatus0;
+ uint32_t ErrorStatus1;
/* Tearing Effect Interrupt management ***************************************/
if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
@@ -1365,7 +1378,8 @@
High-Speed transmission.
To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
to Low-Power and from Low-Power to High-Speed.
- This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
+ This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration
+ Register (DSI_CLTCR).
But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
@@ -1587,7 +1601,7 @@
/* Process locked */
__HAL_LOCK(hdsi);
- status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
+ status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1616,7 +1630,9 @@
uint32_t Param1,
uint8_t *ParametersTable)
{
- uint32_t uicounter, nbBytes, count;
+ uint32_t uicounter;
+ uint32_t nbBytes;
+ uint32_t count;
uint32_t tickstart;
uint32_t fifoword;
uint8_t *pparams = ParametersTable;
@@ -1721,7 +1737,7 @@
{
/* set max return packet size */
if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
- (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
+ (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1782,6 +1798,21 @@
return HAL_TIMEOUT;
}
+
+ /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */
+ /* issued to the panel and the read data is not captured by the DSI Host */
+ /* which returns Packet Size Error. */
+ /* Need to ensure that the Read command has finished before checking PSE */
+ if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)
+ {
+ if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+ }
}
/* Process unlocked */
@@ -2077,7 +2108,7 @@
/* De-assert the ULPM requests and the ULPM exit bits */
hdsi->Instance->PUCR = 0U;
- /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
+ /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PHY);
/* Restore clock lane configuration to HS */
@@ -2727,5 +2758,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_dts.c b/Src/stm32h7xx_hal_dts.c
index e2774d1..21faccd 100644
--- a/Src/stm32h7xx_hal_dts.c
+++ b/Src/stm32h7xx_hal_dts.c
@@ -11,6 +11,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### DTS Peripheral features #####
@@ -27,17 +38,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -824,4 +824,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_eth.c b/Src/stm32h7xx_hal_eth.c
index decff79..9bcc558 100644
--- a/Src/stm32h7xx_hal_eth.c
+++ b/Src/stm32h7xx_hal_eth.c
@@ -9,7 +9,17 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
+ ******************************************************************************
+ * @attention
*
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -130,17 +140,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1562,7 +1561,7 @@
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call registered MAC Error callback*/
- heth->DMAErrorCallback(heth);
+ heth->MACErrorCallback(heth);
#else
/* Ethernet MAC Error callback */
HAL_ETH_MACErrorCallback(heth);
@@ -3027,4 +3026,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_eth_ex.c b/Src/stm32h7xx_hal_eth_ex.c
index 5672dfe..46c6a5f 100644
--- a/Src/stm32h7xx_hal_eth_ex.c
+++ b/Src/stm32h7xx_hal_eth_ex.c
@@ -3,17 +3,15 @@
* @file stm32h7xx_hal_eth_ex.c
* @author MCD Application Team
* @brief ETH HAL Extended module driver.
- *
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -556,4 +554,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_exti.c b/Src/stm32h7xx_hal_exti.c
index e49dc3a..da12923 100644
--- a/Src/stm32h7xx_hal_exti.c
+++ b/Src/stm32h7xx_hal_exti.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
@@ -103,18 +114,6 @@
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -440,6 +439,10 @@
}
#endif /*DUAL_CORE*/
+ /* Get default Trigger and GPIOSel configuration */
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00U;
+
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
{
@@ -451,10 +454,6 @@
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
- else
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- }
/* Get falling configuration */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
@@ -474,27 +473,16 @@
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
}
- else
- {
- pExtiConfig->GPIOSel = 0x00U;
- }
}
- else
- {
- pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
- pExtiConfig->GPIOSel = 0x00U;
- }
+
+ /* Get default Pend Clear Source */
+ pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
/* 3] Get D3 Pend Clear source */
if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
- if(((*regaddr) & linepos) == 0UL)
- {
- /* if PMR unset, then no pend clear source is used */
- pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
- }
- else
+ if(((*regaddr) & linepos) != 0UL)
{
/* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */
if(linepos < 16UL)
@@ -511,11 +499,6 @@
pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
}
}
- else
- {
- /* if line wakeup target is not any, then no pend clear source is used */
- pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
- }
return HAL_OK;
}
@@ -874,4 +857,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_fdcan.c b/Src/stm32h7xx_hal_fdcan.c
index 0549620..7306fc4 100644
--- a/Src/stm32h7xx_hal_fdcan.c
+++ b/Src/stm32h7xx_hal_fdcan.c
@@ -11,6 +11,17 @@
* + Peripheral Configuration and Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -96,10 +107,10 @@
The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+ Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
to register an interrupt callback.
- Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+ Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
(+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
(+) RxBufferNewMessageCallback : Rx Buffer New Message Callback.
(+) HighPriorityMessageCallback : High Priority Message Callback.
@@ -114,16 +125,16 @@
For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
- respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
- @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
- @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
- @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
- @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
- @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+ respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(),
+ HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
+ HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(),
+ HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+ HAL_FDCAN_TT_RegisterTimeMarkCallback(), HAL_FDCAN_TT_RegisterStopWatchCallback() and
+ HAL_FDCAN_TT_RegisterGlobalTimeCallback().
- Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
@@ -138,20 +149,20 @@
For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
- register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
- @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
- @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
- @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
- @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
- @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+ register callbacks : respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+ HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(),
+ HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+ HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(),
+ HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+ HAL_FDCAN_TT_UnRegisterStopWatchCallback() and HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
- By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+ By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_FDCAN_ErrorCallback().
+ examples HAL_FDCAN_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
+ reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
+ if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
@@ -159,26 +170,14 @@
in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
- or @ref HAL_FDCAN_Init() function.
+ using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
+ or HAL_FDCAN_Init() function.
When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
******************************************************************************
*/
@@ -6195,4 +6194,3 @@
#endif /* FDCAN1 */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_flash.c b/Src/stm32h7xx_hal_flash.c
index a73e8ed..1df845e 100644
--- a/Src/stm32h7xx_hal_flash.c
+++ b/Src/stm32h7xx_hal_flash.c
@@ -74,14 +74,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -1001,7 +999,7 @@
flag will be set */
uint32_t bsyflag = FLASH_FLAG_QW_BANK1;
- uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+ uint32_t errorflag = 0;
uint32_t tickstart = HAL_GetTick();
assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
@@ -1010,8 +1008,6 @@
if (Bank == FLASH_BANK_2)
{
- /* Get Error Flags */
- errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
/* Select bsyflag depending on Bank */
bsyflag = FLASH_FLAG_QW_BANK2;
}
@@ -1028,6 +1024,18 @@
}
}
+ /* Get Error Flags */
+ if (Bank == FLASH_BANK_1)
+ {
+ errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+ }
+#if defined (DUAL_BANK)
+ else
+ {
+ errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
+ }
+#endif /* DUAL_BANK */
+
/* In case of error reported in Flash SR1 or SR2 register */
if((errorflag & 0x7FFFFFFFU) != 0U)
{
@@ -1184,4 +1192,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_flash_ex.c b/Src/stm32h7xx_hal_flash_ex.c
index d021924..fd4acec 100644
--- a/Src/stm32h7xx_hal_flash_ex.c
+++ b/Src/stm32h7xx_hal_flash_ex.c
@@ -62,14 +62,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -408,7 +406,7 @@
/**
* @brief Program option bytes
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
* contains the configuration information for the programming.
*
* @retval HAL Status
@@ -549,7 +547,7 @@
/**
* @brief Get the Option byte configuration
- * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
* contains the configuration information for the programming.
* @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
* as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
@@ -971,7 +969,7 @@
* @brief Enable the write protection of the desired bank1 or bank 2 sectors
* @param WRPSector specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
- * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
+ * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL
*
* @param Banks the specific bank to apply WRP sectors
* This parameter can be one of the following values:
@@ -1006,7 +1004,7 @@
* @brief Disable the write protection of the desired bank1 or bank 2 sectors
* @param WRPSector specifies the sector(s) to disable write protection.
* This parameter can be one of the following values:
- * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+ * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
*
* @param Banks the specific bank to apply WRP sectors
* This parameter can be one of the following values:
@@ -1045,7 +1043,7 @@
* @param WRPSector gives the write protected sector(s) on the given bank .
* This parameter can be one of the following values:
- * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+ * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
*
* @param Bank the specific bank to apply WRP sectors
* This parameter can be exclusively one of the following values:
@@ -1819,7 +1817,7 @@
*/
static uint32_t FLASH_OB_SharedRAM_GetConfig(void)
{
- return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);;
+ return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);
}
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
@@ -1846,7 +1844,7 @@
*/
static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
{
- return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);;
+ return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);
}
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
@@ -1860,4 +1858,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_fmac.c b/Src/stm32h7xx_hal_fmac.c
index 9159210..dd2e1ec 100644
--- a/Src/stm32h7xx_hal_fmac.c
+++ b/Src/stm32h7xx_hal_fmac.c
@@ -9,7 +9,19 @@
* + Peripheral Control functions
* + Callback functions
* + IRQ handler management
- * + Peripheral State functions
+ * + Peripheral State and Error functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
*
* @verbatim
================================================================================
@@ -26,9 +38,10 @@
(+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
(++) In case of using DMA to control data transfer (e.g. access configured
as FMAC_BUFFER_ACCESS_DMA):
- (+++) Enable the DMA1 interface clock using __HAL_RCC_DMA1_CLK_ENABLE().
+ (+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE()
+ or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
(+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
- (+++) If the initialisation of the internal buffers (coefficients, input,
+ (+++) If the initialization of the internal buffers (coefficients, input,
output) is done via DMA, configure and enable one DMA channel for
managing data transfer from memory to memory (preload channel).
(+++) If the input buffer is accessed via DMA, configure and enable one
@@ -64,7 +77,7 @@
Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
the error status will be kept, but no more interrupt will be triggered.
(++) Write the provided coefficients into the internal memory using polling
- mode (HAL_FMAC_FilterConfig()) or DMA (HAL_FMAC_FilterConfig_DMA()).
+ mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ).
In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
the handling is over.
@@ -73,7 +86,7 @@
filter. If a saturation occurs, the interruption will be triggered in loop.
In order to recover, the user will have to:
(++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
- he wishes to continue all the same.
+ the user wishes to continue all the same.
(++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
(#) Optionally, preload input (FIR, IIR) and output (IIR) data using
@@ -137,8 +150,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_FMAC_RegisterCallback() to register a user callback.
- Function @ref HAL_FMAC_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_FMAC_RegisterCallback() to register a user callback.
+ Function HAL_FMAC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : Error Callback.
(+) HalfGetDataCallback : Get Half Data Callback.
(+) GetDataCallback : Get Data Callback.
@@ -152,9 +165,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_FMAC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
+ HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : Error Callback.
@@ -168,13 +181,13 @@
(+) MspDeInitCallback : FMAC MspDeInit.
[..]
- By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
+ By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_FMAC_TxCpltCallback(), @ref HAL_FMAC_RxHalfCpltCallback().
+ examples GetDataCallback(), OutputDataReadyCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init()
- and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init()
+ and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -183,8 +196,8 @@
in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_FMAC_RegisterCallback() before calling @ref HAL_FMAC_DeInit()
- or @ref HAL_FMAC_Init() function.
+ using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit()
+ or HAL_FMAC_Init() function.
[..]
When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
@@ -194,18 +207,6 @@
@endverbatim
*
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -219,11 +220,10 @@
*/
/** @defgroup FMAC FMAC
- * @brief FMAC HAL driver modules
+ * @brief FMAC HAL driver module
* @{
*/
-/* External variables --------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup FMAC_Private_Constants FMAC Private Constants
@@ -231,12 +231,23 @@
*/
#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
+#define MAX_PRELOAD_INDEX 0xFFU
#define PRELOAD_ACCESS_DMA 0x00U
#define PRELOAD_ACCESS_POLLING 0x01U
#define POLLING_DISABLED 0U
#define POLLING_ENABLED 1U
#define POLLING_NOT_STOPPED 0U
#define POLLING_STOPPED 1U
+/* FMAC polling-based communications time-out value */
+#define HAL_FMAC_TIMEOUT_VALUE 1000U
+/* FMAC reset time-out value */
+#define HAL_FMAC_RESET_TIMEOUT_VALUE 500U
+/* DMA Read Requests Enable */
+#define FMAC_DMA_REN FMAC_CR_DMAREN
+/* DMA Write Channel Enable */
+#define FMAC_DMA_WEN FMAC_CR_DMAWEN
+/* FMAC Execution Enable */
+#define FMAC_START FMAC_PARAM_START
/**
* @}
@@ -296,40 +307,27 @@
((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
/**
- * @brief Get the threshold matching the watermak.
+ * @brief Get the threshold matching the watermark.
* @param __WM__ Watermark value.
* @retval THRESHOLD
*/
-#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) ((__WM__ == FMAC_THRESHOLD_1)? 1U: \
- (__WM__ == FMAC_THRESHOLD_2)? 2U: \
- (__WM__ == FMAC_THRESHOLD_4)? 4U:8U)
-
-/**
- * @brief Check whether the threshold is applicable.
- * @param __SIZE__ Size of the matching buffer.
- * @param __WM__ Watermark value.
- * @param __ACCESS__ Access to the buffer (polling, it, dma, none).
- * @retval THRESHOLD
- */
-#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
- ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
- ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
- ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \
- ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U)
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
-
+/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
-static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
uint8_t PreloadAccess);
static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess);
@@ -349,7 +347,7 @@
static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
-/* Private functions ---------------------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
/** @defgroup FMAC_Exported_Functions FMAC Exported Functions
* @{
@@ -367,6 +365,8 @@
(+) DeInitialize the FMAC peripheral
(+) Initialize the FMAC MSP (MCU Specific Package)
(+) De-Initialize the FMAC MSP
+ (+) Register a User FMAC Callback
+ (+) Unregister a FMAC CallBack
[..]
@@ -377,10 +377,12 @@
/**
* @brief Initialize the FMAC peripheral and the associated handle.
* @param hfmac pointer to a FMAC_HandleTypeDef structure.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
{
+ HAL_StatusTypeDef status;
+
/* Check the FMAC handle allocation */
if (hfmac == NULL)
{
@@ -392,7 +394,7 @@
if (hfmac->State == HAL_FMAC_STATE_RESET)
{
- /* Allocate lock resource and initialize it */
+ /* Initialize lock resource */
hfmac->Lock = HAL_UNLOCKED;
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
@@ -419,36 +421,36 @@
}
/* Reset pInput and pOutput */
- hfmac->FilterParam = 0UL;
+ hfmac->FilterParam = 0U;
FMAC_ResetDataPointers(hfmac);
/* Reset FMAC unit (internal pointers) */
- if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+ if (FMAC_Reset(hfmac) == HAL_ERROR)
{
/* Update FMAC error code and FMAC peripheral state */
- hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hfmac);
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Update FMAC error code and FMAC peripheral state */
+ hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+ hfmac->State = HAL_FMAC_STATE_READY;
- return HAL_TIMEOUT;
+ status = HAL_OK;
}
- /* Update FMAC error code and FMAC peripheral state */
- hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
- hfmac->State = HAL_FMAC_STATE_READY;
-
- /* Process Unlocked */
__HAL_UNLOCK(hfmac);
- return HAL_OK;
+ return status;
}
/**
* @brief De-initialize the FMAC peripheral.
* @param hfmac pointer to a FMAC structure.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
{
@@ -468,7 +470,7 @@
hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
/* Reset pInput and pOutput */
- hfmac->FilterParam = 0UL;
+ hfmac->FilterParam = 0U;
FMAC_ResetDataPointers(hfmac);
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
@@ -486,10 +488,9 @@
/* Change FMAC peripheral state */
hfmac->State = HAL_FMAC_STATE_RESET;
- /* Release Lock */
+ /* Always release Lock in case of de-initialization */
__HAL_UNLOCK(hfmac);
- /* Return function status */
return HAL_OK;
}
@@ -525,8 +526,8 @@
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/**
- * @brief Register a User FMAC Callback
- * to be used instead of the weak predefined callback.
+ * @brief Register a User FMAC Callback.
+ * @note The User FMAC Callback is to be used instead of the weak predefined callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param CallbackID ID of the callback to be registered.
@@ -541,13 +542,19 @@
* @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
* @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
* @param pCallback pointer to the Callback function.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
pFMAC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
if (pCallback == NULL)
{
/* Update the error code */
@@ -555,10 +562,9 @@
return HAL_ERROR;
}
- /* Process locked */
__HAL_LOCK(hfmac);
- if (HAL_FMAC_STATE_READY == hfmac->State)
+ if (hfmac->State == HAL_FMAC_STATE_READY)
{
switch (CallbackID)
{
@@ -607,7 +613,7 @@
break;
}
}
- else if (HAL_FMAC_STATE_RESET == hfmac->State)
+ else if (hfmac->State == HAL_FMAC_STATE_RESET)
{
switch (CallbackID)
{
@@ -637,7 +643,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
__HAL_UNLOCK(hfmac);
return status;
@@ -645,7 +650,7 @@
/**
* @brief Unregister a FMAC CallBack.
- * FMAC callback is redirected to the weak predefined callback.
+ * @note The FMAC callback is redirected to the weak predefined callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module
* @param CallbackID ID of the callback to be unregistered.
@@ -659,53 +664,61 @@
* @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
* @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
* @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
+ /* Check the FMAC handle allocation */
+ if (hfmac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
__HAL_LOCK(hfmac);
- if (HAL_FMAC_STATE_READY == hfmac->State)
+ if (hfmac->State == HAL_FMAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_FMAC_ERROR_CB_ID :
- hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */
+ hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_FMAC_HALF_GET_DATA_CB_ID :
- hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */
+ hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */
break;
case HAL_FMAC_GET_DATA_CB_ID :
- hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */
+ hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */
break;
case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
- hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak HalfOutputDataReadyCallback */
+ hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak
+ HalfOutputDataReadyCallback */
break;
case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
- hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak OutputDataReadyCallback */
+ hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak
+ OutputDataReadyCallback */
break;
case HAL_FMAC_FILTER_CONFIG_CB_ID :
- hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak FilterConfigCallback */
+ hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak
+ FilterConfigCallback */
break;
case HAL_FMAC_FILTER_PRELOAD_CB_ID :
- hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallback */
+ hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallba */
break;
case HAL_FMAC_MSPINIT_CB_ID :
- hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */
+ hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_FMAC_MSPDEINIT_CB_ID :
- hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -717,7 +730,7 @@
break;
}
}
- else if (HAL_FMAC_STATE_RESET == hfmac->State)
+ else if (hfmac->State == HAL_FMAC_STATE_RESET)
{
switch (CallbackID)
{
@@ -747,7 +760,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
__HAL_UNLOCK(hfmac);
return status;
@@ -778,38 +790,40 @@
*/
/**
- * @brief Configure the FMAC filter according to the parameters
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
* specified in the FMAC_FilterConfigTypeDef structure.
* The provided data will be loaded using polling mode.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
-HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
{
- return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_POLLING));
+ return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING));
}
/**
- * @brief Configure the FMAC filter according to the parameters
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
* specified in the FMAC_FilterConfigTypeDef structure.
* The provided data will be loaded using DMA.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
-HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
{
- return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_DMA));
+ return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA));
}
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
- * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* The provided data will be loaded using polling mode.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
@@ -821,10 +835,10 @@
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
- * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize)
@@ -834,7 +848,7 @@
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
- * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* The provided data will be loaded using DMA.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
@@ -846,10 +860,10 @@
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
- * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize)
@@ -867,21 +881,21 @@
* If it is set to NULL, the output will not be read and it will be up to
* an external IP to empty the output buffer.
* @param pOutputSize pointer to the size of the output buffer. The number of read data will be written here.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
{
- uint32_t tmpcr = 0UL;
+ uint32_t tmpcr = 0U;
HAL_StatusTypeDef status;
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check that a valid configuration was done previously */
- if (hfmac->FilterParam == 0UL)
+ if (hfmac->FilterParam == 0U)
{
return HAL_ERROR;
}
@@ -936,34 +950,27 @@
/* Reset the busy flag (do not overwrite the possible write and read flag) */
hfmac->State = HAL_FMAC_STATE_READY;
-
- /* Return function status */
- return status;
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_ERROR;
}
+
+ return status;
}
/**
- * @brief Provide a new input buffer that will be loaded into the FMAC
- * input memory area.
+ * @brief Provide a new input buffer that will be loaded into the FMAC input memory area.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput New input vector (additional input data).
* @param pInputSize Size of the input vector (if all the data can't be
* written, it will be updated with the number of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
{
- /* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef status;
/* Check the function parameters */
if ((pInput == NULL) || (pInputSize == NULL))
@@ -975,6 +982,12 @@
return HAL_ERROR;
}
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the FMAC configuration */
if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE)
{
@@ -984,40 +997,36 @@
/* Check whether the previous input vector has been handled */
if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize)))
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
/* Check that FMAC was initialized and that no writing is already ongoing */
if (hfmac->WrState == HAL_FMAC_STATE_READY)
{
/* Register the new input buffer */
- return (FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize));
+ status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize);
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_ERROR;
}
+
+ return status;
}
/**
- * @brief Provide a new output buffer to be filled with the data
- * computed by FMAC unit.
+ * @brief Provide a new output buffer to be filled with the data computed by FMAC unit.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pOutput New output vector.
* @param pOutputSize Size of the output vector (if the vector can't
* be entirely filled, pOutputSize will be updated with the number
* of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
{
- /* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef status;
/* Check the function parameters */
if ((pOutput == NULL) || (pOutputSize == NULL))
@@ -1029,6 +1038,12 @@
return HAL_ERROR;
}
+ /* Check the START bit state */
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the FMAC configuration */
if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
{
@@ -1038,25 +1053,27 @@
/* Check whether the previous output vector has been handled */
if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize)))
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
/* Check that FMAC was initialized and that not reading is already ongoing */
if (hfmac->RdState == HAL_FMAC_STATE_READY)
{
/* Register the new output buffer */
- return (FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize));
+ status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_ERROR;
}
+
+ return status;
}
/**
- * @brief Write the previously provided user's input data and
- * fill the previously provided user's output buffer,
+ * @brief Handle the input and/or output data in polling mode
+ * @note This function writes the previously provided user's input data and
+ * fills the previously provided user's output buffer,
* according to the existing FMAC configuration (polling mode only).
* The function returns when the input data has been handled or
* when the output data is filled. The possible unused data isn't
@@ -1066,7 +1083,7 @@
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param Timeout timeout value.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
{
@@ -1075,9 +1092,10 @@
uint8_t inpollingover = POLLING_NOT_STOPPED;
uint8_t outpolling;
uint8_t outpollingover = POLLING_NOT_STOPPED;
+ HAL_StatusTypeDef status;
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
+ if (FMAC_GET_START_BIT(hfmac) == 0U)
{
return HAL_ERROR;
}
@@ -1162,41 +1180,40 @@
/* Reset the busy flag (do not overwrite the possible write and read flag) */
hfmac->State = HAL_FMAC_STATE_READY;
- /* Return function status */
if ((HAL_GetTick() - tickstart) >= Timeout)
{
- return HAL_TIMEOUT;
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ status = HAL_ERROR;
}
else
{
- return HAL_OK;
+ status = HAL_OK;
}
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_ERROR;
}
+
+ return status;
}
/**
* @brief Stop the FMAC processing.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
{
-
- /* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) == 0UL)
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef status;
/* Check handle state is ready */
if (hfmac->State == HAL_FMAC_STATE_READY)
{
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
+
/* Set the START bit to 0 (stop the previously configured filter) */
CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START);
@@ -1214,25 +1231,30 @@
}
/* Reset FMAC unit (internal pointers) */
- if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+ if (FMAC_Reset(hfmac) == HAL_ERROR)
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset the data pointers */
+ FMAC_ResetDataPointers(hfmac);
+
+ status = HAL_OK;
}
- /* Reset the data pointers */
- FMAC_ResetDataPointers(hfmac);
-
- /* Return function status */
- return HAL_OK;
+ /* Reset the busy flag */
+ hfmac->State = HAL_FMAC_STATE_READY;
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_ERROR;
}
+
+ return status;
}
/**
@@ -1398,7 +1420,7 @@
/* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U))
{
/* Read some data if possible (Y size is used as a pseudo timeout in order
to not get stuck too long under IT if FMAC keeps on processing input
@@ -1425,7 +1447,7 @@
/* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U))
{
/* Write some data if possible (X1 size is used as a pseudo timeout in order
to not get stuck too long under IT if FMAC keep on processing input
@@ -1452,21 +1474,21 @@
/* Check if the overflow error interrupt is enabled and if overflow error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
}
/* Check if the underflow error interrupt is enabled and if underflow error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
}
/* Check if the saturation error interrupt is enabled and if saturation error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN);
- if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0UL))
+ if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
}
@@ -1487,29 +1509,30 @@
* @}
*/
-/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions.
+/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions
+ * @brief Peripheral State and Error functions.
*
@verbatim
==============================================================================
- ##### Peripheral State functions #####
+ ##### Peripheral State and Error functions #####
==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
+ [..] This subsection provides functions allowing to
+ (+) Check the FMAC state
+ (+) Get error code
@endverbatim
* @{
*/
/**
- * @brief Return the FMAC handle state.
+ * @brief Return the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @retval HAL state
+ * @retval HAL_FMAC_StateTypeDef FMAC state
*/
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
{
- /* Return FMAC handle state */
+ /* Return FMAC state */
return hfmac->State;
}
@@ -1518,7 +1541,7 @@
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @note The returned error is a bit-map combination of possible errors.
- * @retval Error bit-map
+ * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
*/
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
{
@@ -1546,7 +1569,7 @@
/**
* @brief Perform a reset of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
{
@@ -1559,11 +1582,12 @@
SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
/* Wait until flag is reset */
- while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0UL)
+ while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
{
if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ return HAL_ERROR;
}
}
@@ -1574,7 +1598,7 @@
/**
* @brief Reset the data pointers of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval None
*/
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
{
@@ -1585,7 +1609,7 @@
/**
* @brief Reset the input data pointers of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval None
*/
static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
@@ -1598,7 +1622,7 @@
/**
* @brief Reset the output data pointers of the FMAC unit.
* @param hfmac FMAC handle.
- * @retval FMAC status
+ * @retval None
*/
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
@@ -1609,19 +1633,17 @@
}
/**
- * @brief Configure the FMAC filter according to the parameters
- specified in the FMAC_FilterConfigTypeDef structure.
+ * @brief Configure the FMAC filter.
+ * @note The configuration is done according to the parameters
+ * specified in the FMAC_FilterConfigTypeDef structure.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
- * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+ * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
- * @param PreloadAccess buffer preload method
- * This parameter can be one of the following values:
- * @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU
- * @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA
- * @retval HAL status
+ * @param PreloadAccess access mode used for the preload (polling or DMA).
+ * @retval HAL_StatusTypeDef HAL status
*/
-static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
uint8_t PreloadAccess)
{
uint32_t tickstart;
@@ -1631,193 +1653,193 @@
#endif /* USE_FULL_ASSERT */
/* Check the parameters */
- assert_param(IS_FMAC_THRESHOLD(sConfig->InputThreshold));
- assert_param(IS_FMAC_THRESHOLD(sConfig->OutputThreshold));
- assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->InputAccess));
- assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->OutputAccess));
- assert_param(IS_FMAC_CLIP_STATE(sConfig->Clip));
- assert_param(IS_FMAC_FILTER_FUNCTION(sConfig->Filter));
- assert_param(IS_FMAC_PARAM_P(sConfig->Filter, sConfig->P));
- assert_param(IS_FMAC_PARAM_Q(sConfig->Filter, sConfig->Q));
- assert_param(IS_FMAC_PARAM_R(sConfig->Filter, sConfig->R));
+ assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold));
+ assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold));
+ assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess));
+ assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess));
+ assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip));
+ assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter));
+ assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P));
+ assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q));
+ assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R));
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check handle state is ready */
- if (hfmac->State == HAL_FMAC_STATE_READY)
+ if (hfmac->State != HAL_FMAC_STATE_READY)
{
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_BUSY;
+ return HAL_ERROR;
+ }
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
- /* Indicate that there is no valid configuration done */
- hfmac->FilterParam = 0UL;
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
- if (sConfig->InputBufferSize != 0U)
- {
- MODIFY_REG(hfmac->Instance->X1BUFCFG, \
- (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
- (((((uint32_t)(sConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
- ((((uint32_t)(sConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE)));
- }
+ /* Indicate that there is no valid configuration done */
+ hfmac->FilterParam = 0U;
- /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
- if (sConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
- {
- /* Check the parameter */
- assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), sConfig->InputThreshold, sConfig->InputAccess));
+ /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
+ if (pConfig->InputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
+ (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
+ ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \
+ FMAC_X1BUFCFG_X1_BUF_SIZE)));
+ }
- MODIFY_REG(hfmac->Instance->X1BUFCFG, \
- FMAC_X1BUFCFG_FULL_WM, \
- ((sConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
- }
+ /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
+ if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess));
- /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
- if (sConfig->CoeffBufferSize != 0U)
- {
- MODIFY_REG(hfmac->Instance->X2BUFCFG, \
- (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
- (((((uint32_t)(sConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
- ((((uint32_t)(sConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE)));
- }
+ MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+ FMAC_X1BUFCFG_FULL_WM, \
+ ((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
+ }
- /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
- if (sConfig->OutputBufferSize != 0U)
- {
- MODIFY_REG(hfmac->Instance->YBUFCFG, \
- (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \
- (((((uint32_t)(sConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \
- ((((uint32_t)(sConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
- }
+ /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
+ if (pConfig->CoeffBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->X2BUFCFG, \
+ (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
+ (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
+ ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\
+ FMAC_X2BUFCFG_X2_BUF_SIZE)));
+ }
- /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
- if (sConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
- {
- /* Check the parameter */
- assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), sConfig->OutputThreshold, sConfig->OutputAccess));
+ /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
+ if (pConfig->OutputBufferSize != 0U)
+ {
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \
+ (((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \
+ ((((uint32_t)(pConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
+ }
- MODIFY_REG(hfmac->Instance->YBUFCFG, \
- FMAC_YBUFCFG_EMPTY_WM, \
- ((sConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
- }
+ /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
+ if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
+ {
+ /* Check the parameter */
+ assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess));
- /* CR: Configure the clip feature */
- tmpcr = sConfig->Clip & FMAC_CR_CLIPEN;
+ MODIFY_REG(hfmac->Instance->YBUFCFG, \
+ FMAC_YBUFCFG_EMPTY_WM, \
+ ((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
+ }
- /* CR: If IT or DMA will be used, enable error interrupts.
- * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
- if ((sConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) ||
- (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
- {
- tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
- }
+ /* FMAC_CR: Configure the clip feature */
+ tmpcr = pConfig->Clip & FMAC_CR_CLIPEN;
- /* CR: write the value */
- WRITE_REG(hfmac->Instance->CR, tmpcr);
+ /* FMAC_CR: If IT or DMA will be used, enable error interrupts.
+ * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
+ if ((pConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) ||
+ (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
+ {
+ tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
+ }
- /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
- hfmac->InputAccess = sConfig->InputAccess;
- hfmac->OutputAccess = sConfig->OutputAccess;
+ /* FMAC_CR: write the value */
+ WRITE_REG(hfmac->Instance->CR, tmpcr);
- /* Check whether the configured X2 is big enough for the filter */
+ /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
+ hfmac->InputAccess = pConfig->InputAccess;
+ hfmac->OutputAccess = pConfig->OutputAccess;
+
+ /* Check whether the configured X2 is big enough for the filter */
#if defined(USE_FULL_ASSERT)
- x2size = FMAC_GET_X2_SIZE(hfmac);
+ x2size = FMAC_GET_X2_SIZE(hfmac);
#endif /* USE_FULL_ASSERT */
- assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= sConfig->P)) || \
- ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)sConfig->P + (uint32_t)sConfig->Q))));
+ assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \
+ ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
- /* Build the PARAM value that will be used when starting the filter */
- hfmac->FilterParam = (FMAC_PARAM_START | sConfig->Filter | \
- ((((uint32_t)(sConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
- ((((uint32_t)(sConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
- ((((uint32_t)(sConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
+ /* Build the PARAM value that will be used when starting the filter */
+ hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \
+ ((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
+ ((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
+ ((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
- /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
- if ((sConfig->pCoeffB != NULL) && (sConfig->CoeffBSize != 0U))
+ /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
+ if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U))
+ {
+ /* FIR/IIR: The provided coefficients should match X2 size */
+ assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size);
+ /* FIR/IIR: The size of pCoeffB should match the parameter P */
+ assert_param(pConfig->CoeffBSize >= pConfig->P);
+ /* pCoeffA should be provided for IIR but not for FIR */
+ /* IIR : if pCoeffB is provided, pCoeffA should also be there */
+ /* IIR: The size of pCoeffA should match the parameter Q */
+ assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
+ (pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) ||
+ ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
+ (pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) &&
+ (pConfig->CoeffASize >= pConfig->Q)));
+
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
+ ((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
+ FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
{
- /* FIR/IIR: The provided coefficients should match X2 size */
- assert_param(((uint32_t)sConfig->CoeffASize + (uint32_t)sConfig->CoeffBSize) <= x2size);
- /* FIR/IIR: The size of pCoeffB should match the parameter P */
- assert_param(sConfig->CoeffBSize >= sConfig->P);
- /* pCoeffA should be provided for IIR but not for FIR */
- /* IIR : if pCoeffB is provided, pCoeffA should also be there */
- /* IIR: The size of pCoeffA should match the parameter Q */
- assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
- (sConfig->pCoeffA == NULL) && (sConfig->CoeffASize == 0U)) ||
- ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
- (sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U) &&
- (sConfig->CoeffASize >= sConfig->Q)));
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize);
- /* Write number of values to be loaded, the data load function and start the operation */
- WRITE_REG(hfmac->Instance->PARAM, \
- (((uint32_t)(sConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
- ((uint32_t)(sConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
- FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
-
- if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ /* Load pCoeffA if needed */
+ if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U))
{
/* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffB), sConfig->CoeffBSize);
-
- /* Load pCoeffA if needed */
- if ((sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U))
- {
- /* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffA), sConfig->CoeffASize);
- }
-
- /* Wait for the end of the writing */
- if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
- {
- hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
-
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_READY;
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize);
}
- else
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
{
- hfmac->pInput = sConfig->pCoeffA;
- hfmac->InputCurrentSize = sConfig->CoeffASize;
-
- /* Set the FMAC DMA transfer complete callback */
- hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
- hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
- /* Set the DMA error callback */
- hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
- /* Enable the DMA stream managing FMAC preload data write */
- return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)sConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
- sConfig->CoeffBSize));
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_ERROR;
}
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
}
else
{
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_READY;
+ hfmac->pInput = pConfig->pCoeffA;
+ hfmac->InputCurrentSize = pConfig->CoeffASize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
+ pConfig->CoeffBSize));
}
}
else
{
- /* Return function status */
- return HAL_BUSY;
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
}
- /* Return function status */
return HAL_OK;
}
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
- * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+ * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput Preloading of the first elements of the input buffer (X1).
@@ -1828,28 +1850,26 @@
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
- * @param PreloadAccess buffer preload method
- * This parameter can be one of the following values:
- * @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU
- * @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA
- * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+ * @param PreloadAccess access mode used for the preload (polling or DMA).
+ * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
{
uint32_t tickstart;
+ HAL_StatusTypeDef status;
/* Check the START bit state */
- if (FMAC_GET_START_BIT(hfmac) != 0UL)
+ if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check that a valid configuration was done previously */
- if (hfmac->FilterParam == 0UL)
+ if (hfmac->FilterParam == 0U)
{
return HAL_ERROR;
}
@@ -1867,122 +1887,126 @@
}
/* Check handle state is ready */
- if (hfmac->State == HAL_FMAC_STATE_READY)
+ if (hfmac->State != HAL_FMAC_STATE_READY)
{
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_BUSY;
+ return HAL_ERROR;
+ }
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_BUSY;
- /* Preload the input buffer if required */
- if ((pInput != NULL) && (InputSize != 0U))
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Preload the input buffer if required */
+ if ((pInput != NULL) && (InputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
{
- /* Write number of values to be loaded, the data load function and start the operation */
- WRITE_REG(hfmac->Instance->PARAM, \
- (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
- if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
{
- /* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
-
- /* Wait for the end of the writing */
- if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
- {
- hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_ERROR;
}
- else
- {
- hfmac->pInput = pOutput;
- hfmac->InputCurrentSize = OutputSize;
-
- /* Set the FMAC DMA transfer complete callback */
- hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
- hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
- /* Set the DMA error callback */
- hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
- /* Enable the DMA stream managing FMAC preload data write */
- return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
- }
- }
-
- /* Preload the output buffer if required */
- if ((pOutput != NULL) && (OutputSize != 0U))
- {
- /* Write number of values to be loaded, the data load function and start the operation */
- WRITE_REG(hfmac->Instance->PARAM, \
- (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
-
- if (PreloadAccess == PRELOAD_ACCESS_POLLING)
- {
- /* Load the buffer into the internal memory */
- FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
-
- /* Wait for the end of the writing */
- if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
- {
- hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- else
- {
- hfmac->pInput = NULL;
- hfmac->InputCurrentSize = 0U;
-
- /* Set the FMAC DMA transfer complete callback */
- hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
- hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
- /* Set the DMA error callback */
- hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
- /* Enable the DMA stream managing FMAC preload data write */
- return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
- }
- }
-
- /* Update the error codes */
- if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
- {
- hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
- }
- if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
- {
- hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
- }
-
- /* Change the FMAC state */
- hfmac->State = HAL_FMAC_STATE_READY;
-
- /* Return function status */
- if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
- {
- return HAL_OK;
}
else
{
- return HAL_ERROR;
+ hfmac->pInput = pOutput;
+ hfmac->InputCurrentSize = OutputSize;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
}
}
+
+ /* Preload the output buffer if required */
+ if ((pOutput != NULL) && (OutputSize != 0U))
+ {
+ /* Write number of values to be loaded, the data load function and start the operation */
+ WRITE_REG(hfmac->Instance->PARAM, \
+ (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
+
+ if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+ {
+ /* Load the buffer into the internal memory */
+ FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
+
+ /* Wait for the end of the writing */
+ if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+ hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ hfmac->pInput = NULL;
+ hfmac->InputCurrentSize = 0U;
+
+ /* Set the FMAC DMA transfer complete callback */
+ hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+ hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+ /* Set the DMA error callback */
+ hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+ /* Enable the DMA stream managing FMAC preload data write */
+ return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
+ }
+ }
+
+ /* Update the error codes */
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
+ }
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
+ }
+ if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT))
+ {
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
+ }
+
+ /* Change the FMAC state */
+ hfmac->State = HAL_FMAC_STATE_READY;
+
+ /* Return function status */
+ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
+ {
+ status = HAL_OK;
+ }
else
{
- /* Return function status */
- return HAL_BUSY;
+ status = HAL_ERROR;
}
+ return status;
}
/**
* @brief Write data into FMAC internal memory through WDATA and increment input buffer pointer.
- * This function is only used with preload functions.
+ * @note This function is only used with preload functions.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param ppData pointer to pointer to the data buffer.
* @param Size size of the data buffer.
- * @retval none
+ * @retval None
*/
static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
{
@@ -2001,33 +2025,31 @@
* @param hfmac FMAC handle.
* @param Tickstart Tick start value.
* @param Timeout Timeout duration.
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag changes */
- while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
if ((HAL_GetTick() - Tickstart) > Timeout)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hfmac);
+ hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
}
/**
- * @brief Register the new input buffer, update DMA configuration
- * if needed and change the FMAC state.
+ * @brief Register the new input buffer, update DMA configuration if needed and change the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput New input vector (additional input data).
* @param pInputSize Size of the input vector (if all the data can't be
* written, it will be updated with the number of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
uint16_t *pInputSize)
@@ -2060,20 +2082,18 @@
hfmac->pInputSize = pInputSize;
}
- /* Return function status */
return HAL_OK;
}
/**
- * @brief Register the new output buffer, update DMA configuration
- * if needed and change the FMAC state.
+ * @brief Register the new output buffer, update DMA configuration if needed and change the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pOutput New output vector.
* @param pOutputSize Size of the output vector (if the vector can't
* be entirely filled, pOutputSize will be updated with the number
* of data read from FMAC).
- * @retval HAL status
+ * @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
uint16_t *pOutputSize)
@@ -2082,7 +2102,7 @@
hfmac->OutputCurrentSize = 0U;
/* Check whether a valid pointer was provided */
- if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0UL))
+ if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U))
{
/* The user will have to provide a valid configuration later */
hfmac->pOutput = NULL;
@@ -2119,7 +2139,6 @@
hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
}
- /* Return function status */
return HAL_OK;
}
@@ -2128,7 +2147,7 @@
* @param hfmac FMAC handle.
* @param MaxSizeToRead Maximum number of data to read (this serves as a timeout
* if FMAC continuously writes into the output buffer).
- * @retval HAL status
+ * @retval None
*/
static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
{
@@ -2137,7 +2156,7 @@
uint32_t tmpvalue;
/* Check if there is data to read */
- if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0UL)
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U)
{
return;
}
@@ -2166,7 +2185,7 @@
*(hfmac->pOutput) = (int16_t)tmpvalue;
hfmac->pOutput++;
hfmac->OutputCurrentSize++;
- } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0UL);
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U);
/* Y buffer empty flag has just be raised, read the threshold */
threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U;
@@ -2192,7 +2211,7 @@
* @param hfmac FMAC handle.
* @param MaxSizeToWrite Maximum number of data to write (this serves as a timeout
* if FMAC continuously empties the input buffer).
- * @retval HAL status
+ * @retval None
*/
static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
{
@@ -2200,7 +2219,7 @@
uint16_t threshold;
/* Check if there is room in FMAC */
- if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0UL)
+ if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U)
{
return;
}
@@ -2228,7 +2247,7 @@
WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
hfmac->pInput++;
hfmac->InputCurrentSize++;
- } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0UL);
+ } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U);
/* X1 buffer full flag has just be raised, read the threshold */
threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U;
@@ -2357,7 +2376,7 @@
else
{
/* Wait for the end of the writing */
- for (index = 0U; index < 0xFFU; index++)
+ for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
{
if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
{
@@ -2365,8 +2384,8 @@
}
}
- /* If 'START' is still set, there was an error: set FMAC handle state to error */
- if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ /* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
}
@@ -2409,16 +2428,16 @@
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Wait for the end of the X1 writing */
- for (index = 0U; index < 0xFFU; index++)
+ for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
{
- if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0UL)
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
{
break;
}
}
/* If 'START' is still set, there was an error: set FMAC handle state to error */
- if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+ if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
@@ -2454,7 +2473,6 @@
/* nothing to do */
}
- /* Return function status */
if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
{
/* Change the FMAC state */
@@ -2516,5 +2534,3 @@
#endif /* HAL_FMAC_MODULE_ENABLED */
#endif /* FMAC */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_gfxmmu.c b/Src/stm32h7xx_hal_gfxmmu.c
index bed9b62..14fd90a 100644
--- a/Src/stm32h7xx_hal_gfxmmu.c
+++ b/Src/stm32h7xx_hal_gfxmmu.c
@@ -10,7 +10,18 @@
* + Modify physical buffer addresses.
* + Modify cache and pre-fetch parameters.
* + Error management.
- *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -121,17 +132,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -890,4 +890,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_gpio.c b/Src/stm32h7xx_hal_gpio.c
index 8d0a5f6..3580f78 100644
--- a/Src/stm32h7xx_hal_gpio.c
+++ b/Src/stm32h7xx_hal_gpio.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
@@ -90,17 +101,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -122,14 +122,6 @@
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
-#define GPIO_MODE (0x00000003U)
-#define ANALOG_MODE (0x00000008U)
-#define EXTI_MODE (0x10000000U)
-#define GPIO_MODE_IT (0x00010000U)
-#define GPIO_MODE_EVT (0x00020000U)
-#define RISING_EDGE (0x00100000U)
-#define FALLING_EDGE (0x00200000U)
-#define GPIO_OUTPUT_TYPE (0x00000010U)
#if defined(DUAL_CORE)
#define EXTI_CPU1 (0x01000000U)
@@ -187,7 +179,6 @@
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00U)
@@ -199,11 +190,11 @@
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
- if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
@@ -213,18 +204,24 @@
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
+ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ {
+ /* Check the Pull parameter */
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
+ }
/* In case of Alternate function mode selection */
- if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
@@ -245,7 +242,7 @@
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
- if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
@@ -255,27 +252,10 @@
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
- /* Clear EXTI line configuration */
- temp = EXTI_CurrentCPU->IMR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- {
- temp |= iocurrent;
- }
- EXTI_CurrentCPU->IMR1 = temp;
-
- temp = EXTI_CurrentCPU->EMR1;
- temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- temp |= iocurrent;
- }
- EXTI_CurrentCPU->EMR1 = temp;
-
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
{
temp |= iocurrent;
}
@@ -283,11 +263,28 @@
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
- if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
+
+ temp = EXTI_CurrentCPU->EMR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+ {
+ temp |= iocurrent;
+ }
+ EXTI_CurrentCPU->EMR1 = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI_CurrentCPU->IMR1;
+ temp &= ~(iocurrent);
+ if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+ {
+ temp |= iocurrent;
+ }
+ EXTI_CurrentCPU->IMR1 = temp;
}
}
@@ -338,8 +335,8 @@
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
- EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
+ EXTI->RTSR1 &= ~(iocurrent);
tmp = 0x0FUL << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
@@ -556,4 +553,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_hash.c b/Src/stm32h7xx_hal_hash.c
index bdfea69..5f4a682 100644
--- a/Src/stm32h7xx_hal_hash.c
+++ b/Src/stm32h7xx_hal_hash.c
@@ -12,6 +12,17 @@
* + Peripheral State methods
* + HASH or HMAC processing suspension/resumption
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -71,7 +82,8 @@
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set
+ through __HAL_HASH_SET_MDMAT() macro.
From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer through the
@@ -119,34 +131,36 @@
and not extra bits.
(##) If user needs to perform a hash computation of a large input buffer that is spread around various places
- in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it
- becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
+ in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes
+ necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
It is advised to the user to
(+++) achieve the first formatting operation by software then enter the data
- (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs.
+ (+++) while the Peripheral is processing the first input set, carry out the second formatting
+ operation by software, to be ready when DINIS occurs.
(+++) repeat step 2 until the whole message is processed.
[..]
(#) HAL in DMA mode
(##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
- The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer
- to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the
- end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at
- the end of the intermediary transfers.
+ The same field described above in HASH_STR is used to specify which bits to discard at the end of the
+ DMA transfer to process only the message bits and not extra bits. Due to hardware implementation,
+ this is possible only at the end of the complete message. When several DMA transfers are needed to
+ enter the message, this is not applicable at the end of the intermediary transfers.
- (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data
- by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment
- required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode.
+ (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive
+ chunks of data by software while the DMA transfer and processing is on-going for the first parts of
+ the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the
+ software formatting operation is more complex than in the IT mode.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+ Use function HAL_HASH_RegisterCallback() to register a user callback.
- (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+ (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : callback for input completion.
(+) DgstCpltCallback : callback for digest computation completion.
(+) ErrorCallback : callback for error.
@@ -155,9 +169,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+ (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : callback for input completion.
@@ -166,13 +180,13 @@
(+) MspInitCallback : HASH MspInit.
(+) MspDeInitCallback : HASH MspDeInit.
- (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+ (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
- examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+ examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
- and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
- If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_HASH_Init
+ and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
@@ -180,8 +194,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
- or @ref HAL_HASH_Init function.
+ using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit
+ or HAL_HASH_Init function.
When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -189,17 +203,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -270,7 +273,8 @@
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASH_DMAError(DMA_HandleTypeDef *hdma);
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout);
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
@@ -284,8 +288,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization, configuration and call-back functions.
- *
+ * @brief Initialization, configuration and call-back functions.
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -324,11 +328,11 @@
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
/* Check the hash handle allocation */
- if(hhash == NULL)
+ if (hhash == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
@@ -340,9 +344,10 @@
/* Reset Callback pointers in HAL_HASH_STATE_RESET only */
hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
- hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+ completion callback */
hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
- if(hhash->MspInitCallback == NULL)
+ if (hhash->MspInitCallback == NULL)
{
hhash->MspInitCallback = HAL_HASH_MspInit;
}
@@ -351,7 +356,7 @@
hhash->MspInitCallback(hhash);
}
#else
- if(hhash->State == HAL_HASH_STATE_RESET)
+ if (hhash->State == HAL_HASH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhash->Lock = HAL_UNLOCKED;
@@ -361,7 +366,7 @@
}
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
- /* Change the HASH state */
+ /* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
@@ -379,7 +384,7 @@
/* Set the data type bit */
MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
/* Reset MDMAT bit */
-__HAL_HASH_RESET_MDMAT();
+ __HAL_HASH_RESET_MDMAT();
/* Reset HASH handle status */
hhash->Status = HAL_OK;
@@ -401,7 +406,7 @@
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
{
/* Check the HASH handle allocation */
- if(hhash == NULL)
+ if (hhash == NULL)
{
return HAL_ERROR;
}
@@ -420,13 +425,13 @@
hhash->DigestCalculationDisable = RESET;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- if(hhash->MspDeInitCallback == NULL)
- {
- hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
- }
+ if (hhash->MspDeInitCallback == NULL)
+ {
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+ }
- /* DeInit the low level hardware */
- hhash->MspDeInitCallback(hhash);
+ /* DeInit the low level hardware */
+ hhash->MspDeInitCallback(hhash);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_HASH_MspDeInit(hhash);
@@ -549,11 +554,12 @@
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+ pHASH_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
@@ -562,64 +568,64 @@
/* Process locked */
__HAL_LOCK(hhash);
- if(HAL_HASH_STATE_READY == hhash->State)
+ if (HAL_HASH_STATE_READY == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_INPUTCPLT_CB_ID :
- hhash->InCpltCallback = pCallback;
- break;
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = pCallback;
+ break;
- case HAL_HASH_DGSTCPLT_CB_ID :
- hhash->DgstCpltCallback = pCallback;
- break;
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = pCallback;
+ break;
- case HAL_HASH_ERROR_CB_ID :
- hhash->ErrorCallback = pCallback;
- break;
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = pCallback;
+ break;
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_HASH_STATE_RESET == hhash->State)
+ else if (HAL_HASH_STATE_RESET == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = pCallback;
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
/* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -642,69 +648,70 @@
*/
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
{
-HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hhash);
- if(HAL_HASH_STATE_READY == hhash->State)
+ if (HAL_HASH_STATE_READY == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_INPUTCPLT_CB_ID :
- hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
- break;
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ break;
- case HAL_HASH_DGSTCPLT_CB_ID :
- hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
- break;
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+ completion callback */
+ break;
- case HAL_HASH_ERROR_CB_ID :
- hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
- break;
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ break;
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_HASH_STATE_RESET == hhash->State)
+ else if (HAL_HASH_STATE_RESET == hhash->State)
{
switch (CallbackID)
{
- case HAL_HASH_MSPINIT_CB_ID :
- hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
- break;
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
- case HAL_HASH_MSPDEINIT_CB_ID :
- hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
- break;
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
- default :
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
{
- /* Update the error code */
- hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -718,8 +725,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
- * @brief HASH processing functions using polling mode.
- *
+ * @brief HASH processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HASH processing functions #####
@@ -757,7 +764,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
@@ -784,7 +792,7 @@
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
@@ -797,7 +805,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
@@ -813,7 +822,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
@@ -840,7 +850,7 @@
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
@@ -853,7 +863,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
@@ -863,8 +874,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
- * @brief HASH processing functions using interrupt mode.
- *
+ * @brief HASH processing functions using interrupt mode.
+ *
@verbatim
===============================================================================
##### Interruption mode HASH processing functions #####
@@ -900,9 +911,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
/**
@@ -925,7 +937,7 @@
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
@@ -937,9 +949,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
/**
@@ -952,9 +965,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
@@ -978,7 +992,7 @@
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
@@ -990,9 +1004,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
/**
@@ -1025,8 +1040,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
- * @brief HASH processing functions using DMA mode.
- *
+ * @brief HASH processing functions using DMA mode.
+ *
@verbatim
===============================================================================
##### DMA mode HASH processing functions #####
@@ -1077,9 +1092,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -1108,9 +1123,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -1118,8 +1133,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
- * @brief HMAC processing functions using polling mode.
- *
+ * @brief HMAC processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HMAC processing functions #####
@@ -1149,7 +1164,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
@@ -1167,7 +1183,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
@@ -1178,8 +1195,8 @@
/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
- * @brief HMAC processing functions using interrupt mode.
- *
+ * @brief HMAC processing functions using interrupt mode.
+ *
@verbatim
===============================================================================
##### Interrupt mode HMAC processing functions #####
@@ -1208,7 +1225,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
@@ -1225,7 +1243,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
@@ -1237,8 +1256,8 @@
/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
- * @brief HMAC processing functions using DMA modes.
- *
+ * @brief HMAC processing functions using DMA modes.
+ *
@verbatim
===============================================================================
##### DMA mode HMAC processing functions #####
@@ -1313,8 +1332,8 @@
*/
/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
===============================================================================
##### Peripheral State methods #####
@@ -1381,7 +1400,7 @@
* must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
* @retval None
*/
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1391,20 +1410,21 @@
UNUSED(hhash);
/* Save IMR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
- mem_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI);
+ mem_ptr += 4U;
/* Save STR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
- mem_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW);
+ mem_ptr += 4U;
/* Save CR register content */
- *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
- mem_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO |
+ HASH_CR_LKEY | HASH_CR_MDMAT);
+ mem_ptr += 4U;
/* By default, save all CSRs registers */
- for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
{
- *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
- mem_ptr+=4U;
- csr_ptr+=4U;
+ *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr);
+ mem_ptr += 4U;
+ csr_ptr += 4U;
}
}
@@ -1421,7 +1441,7 @@
* beforehand).
* @retval None
*/
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1431,25 +1451,25 @@
UNUSED(hhash);
/* Restore IMR register content */
- WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
+ WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
/* Restore STR register content */
- WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
+ WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
/* Restore CR register content */
- WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
+ WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
/* Reset the HASH processor before restoring the Context
Swap Registers (CSR) */
__HAL_HASH_INIT();
/* By default, restore all CSR registers */
- for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
{
- WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
- mem_ptr+=4U;
- csr_ptr+=4U;
+ WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr)));
+ mem_ptr += 4U;
+ csr_ptr += 4U;
}
}
@@ -1492,7 +1512,7 @@
else
{
- /* Make sure there is enough time to suspend the processing */
+ /* Make sure there is enough time to suspend the processing */
tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
@@ -1505,7 +1525,7 @@
/* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
}
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
@@ -1516,7 +1536,7 @@
/* Wait for BUSY flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
}
/* Disable DMA channel */
/* Note that the Abort function will
@@ -1524,13 +1544,13 @@
- Unlock
- Set the State
*/
- if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
+ if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear DMAE bit */
- CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+ CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
/* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
@@ -1564,19 +1584,22 @@
{
/* Compute how many words were supposed to be transferred by DMA */
- tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
+ tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \
+ ((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U));
- /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported
- by HASH Peripheral, correct it */
+ /* If discrepancy between the number of words reported by DMA Peripheral and
+ the numbers of words entered as reported by HASH Peripheral, correct it */
/* tmp_words_already_pushed reflects the number of words that were already pushed before
the start of DMA transfer (multi-buffer processing case) */
tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
- if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED())
+ if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - \
+ tmp_remaining_DMATransferSize_inWords) % 16U) != HASH_NBW_PUSHED())
{
tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
}
- /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */
+ /* Accordingly, update the input pointer that points at the next word to be
+ transferred to the Peripheral by DMA */
hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
/* And store in HashInCount the remaining size to transfer (in bytes) */
@@ -1596,7 +1619,7 @@
* @brief Return the HASH handle error code.
* @param hhash pointer to a HASH_HandleTypeDef structure.
* @retval HASH Error Code
-*/
+ */
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
{
/* Return HASH Error Code */
@@ -1624,10 +1647,10 @@
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t inputaddr;
uint32_t buffersize;
- HAL_StatusTypeDef status ;
+ HAL_StatusTypeDef status = HAL_OK;
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
@@ -1726,19 +1749,21 @@
}
}
- /* Configure the Number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(buffersize);
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(buffersize);
/* Set the HASH DMA transfer completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Enable the DMA In DMA stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \
+ (buffersize / 4U)));
- /* Enable DMA requests */
- SET_BIT(HASH->CR, HASH_CR_DMAE);
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
- /* Return function status */
+ /* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
@@ -1747,9 +1772,9 @@
else
{
/* Change HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ hhash->State = HAL_HASH_STATE_BUSY;
}
- }
+ }
}
return;
@@ -1764,14 +1789,14 @@
*/
static void HASH_DMAError(DMA_HandleTypeDef *hdma)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
/* Set HASH state to ready to prevent any blocking issue in user code
present in HAL_HASH_ErrorCallback() */
- hhash->State= HAL_HASH_STATE_READY;
+ hhash->State = HAL_HASH_STATE_READY;
/* Set HASH handle status to error */
hhash->Status = HAL_ERROR;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
@@ -1801,18 +1826,18 @@
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
- for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
+ for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
{
/* Write input data 4 bytes at a time */
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
{
/* wait for flag BUSY not set before Wait for DINIS = 1*/
- if (buffercounter >=64U)
+ if (buffercounter >= 64U)
{
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
@@ -1831,14 +1856,14 @@
if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
{
/* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashInCount = Size - (buffercounter + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
+ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashKeyCount = Size - (buffercounter + 4U);
}
@@ -1872,63 +1897,63 @@
{
uint32_t msgdigest = (uint32_t)pMsgDigest;
- switch(Size)
+ switch (Size)
{
/* Read the message digest */
case 16: /* MD5 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- break;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ break;
case 20: /* SHA1 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- break;
- case 28: /* SHA224 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- break;
- case 32: /* SHA256 */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
- break;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ case 28: /* SHA224 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ break;
+ case 32: /* SHA256 */
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ msgdigest += 4U;
+ *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+ break;
default:
- break;
+ break;
}
}
@@ -1942,19 +1967,20 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Wait until flag is set */
- if(Status == RESET)
+ if (Status == RESET)
{
- while(__HAL_HASH_GET_FLAG(Flag) == RESET)
+ while (__HAL_HASH_GET_FLAG(Flag) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Set State to Ready to be able to restart later on */
hhash->State = HAL_HASH_STATE_READY;
@@ -1971,12 +1997,12 @@
}
else
{
- while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+ while (__HAL_HASH_GET_FLAG(Flag) != RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Set State to Ready to be able to restart later on */
hhash->State = HAL_HASH_STATE_READY;
@@ -2009,10 +2035,10 @@
if (hhash->State == HAL_HASH_STATE_BUSY)
{
/* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
- if(hhash->HashITCounter == 0U)
+ if (hhash->HashITCounter == 0U)
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* HASH state set back to Ready to prevent any issue in user code
present in HAL_HASH_ErrorCallback() */
hhash->State = HAL_HASH_STATE_READY;
@@ -2020,9 +2046,9 @@
}
else if (hhash->HashITCounter == 1U)
{
- /* This is the first call to HASH_IT, the first input data are about to be
- entered in the Peripheral. A specific processing is carried out at this point to
- start-up the processing. */
+ /* This is the first call to HASH_IT, the first input data are about to be
+ entered in the Peripheral. A specific processing is carried out at this point to
+ start-up the processing. */
hhash->HashITCounter = 2U;
}
else
@@ -2039,7 +2065,7 @@
HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Reset HASH state machine */
@@ -2060,10 +2086,10 @@
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
+ if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Reset SuspendRequest */
hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
@@ -2092,7 +2118,7 @@
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
return HAL_TIMEOUT;
}
/* Initialization start for HMAC STEP 2 */
@@ -2100,7 +2126,8 @@
__HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */
hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */
hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */
- hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
+ of a new phase */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
@@ -2109,7 +2136,7 @@
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
- __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
return HAL_TIMEOUT;
}
/* Initialization start for HMAC STEP 3 */
@@ -2117,7 +2144,8 @@
__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */
hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */
hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */
- hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
+ of a new phase */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
}
else
@@ -2151,28 +2179,28 @@
uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
/* If there are more than 64 bytes remaining to be entered */
- if(hhash->HashInCount > 64U)
+ if (hhash->HashInCount > 64U)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register
(16 32-bit words, or 64 bytes are entered) */
- for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U)
{
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
}
/* If this is the start of input data entering, an additional word
must be entered to start up the HASH processing */
- if(hhash->HashITCounter == 2U)
+ if (hhash->HashITCounter == 2U)
{
- HASH->DIN = *(uint32_t*)inputaddr;
- if(hhash->HashInCount >= 68U)
+ HASH->DIN = *(uint32_t *)inputaddr;
+ if (hhash->HashInCount >= 68U)
{
/* There are still data waiting to be entered in the Peripheral.
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round. */
hhash->HashInCount -= 68U;
- hhash->pHashInBuffPtr+= 68U;
+ hhash->pHashInBuffPtr += 68U;
}
else
{
@@ -2186,7 +2214,7 @@
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round.*/
hhash->HashInCount -= 64U;
- hhash->pHashInBuffPtr+= 64U;
+ hhash->pHashInBuffPtr += 64U;
}
}
else
@@ -2202,10 +2230,10 @@
__HAL_HASH_DISABLE_IT(HASH_IT_DINI);
/* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
+ for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++)
{
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
}
if (hhash->Accumulation == 1U)
@@ -2219,9 +2247,9 @@
hhash->State = HAL_HASH_STATE_READY;
/* Call Input data transfer complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- hhash->InCpltCallback(hhash);
+ hhash->InCpltCallback(hhash);
#else
- HAL_HASH_InCpltCallback(hhash);
+ HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
}
else
@@ -2251,7 +2279,8 @@
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
{
/* Ensure first that Phase is correct */
- if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
+ if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2)
+ && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
@@ -2348,11 +2377,11 @@
}
- /* HMAC Step 3 processing.
- After phase check, HMAC_Processing() may
- - directly start up from this point in resumption case
- if the same Step 3 processing was suspended previously
- - or fall through from the Step 2 processing carried out hereabove */
+ /* HMAC Step 3 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 3 processing was suspended previously
+ - or fall through from the Step 2 processing carried out hereabove */
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
/************************** STEP 3 ******************************************/
@@ -2380,7 +2409,7 @@
__HAL_HASH_START_DIGEST();
/* Wait for DCIS flag to be set */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2392,14 +2421,14 @@
hhash->Phase = HAL_HASH_PHASE_READY;
}
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
- /* Process Unlock */
- __HAL_UNLOCK(hhash);
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
+ /* Return function status */
+ return HAL_OK;
}
@@ -2415,7 +2444,8 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
@@ -2423,7 +2453,7 @@
/* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (pOutBuffer == NULL))
@@ -2436,13 +2466,13 @@
__HAL_LOCK(hhash);
/* Check if initialization phase has not been already performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
@@ -2564,7 +2594,7 @@
}
/* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
@@ -2573,7 +2603,7 @@
return HAL_ERROR;
}
- /* Process Locked */
+ /* Process Locked */
__HAL_LOCK(hhash);
/* If resuming the HASH processing */
@@ -2600,10 +2630,10 @@
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
}
/* Set the phase */
@@ -2667,7 +2697,7 @@
}
/* Initiate HASH processing in case of start or resumption */
- if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
@@ -2676,7 +2706,7 @@
return HAL_ERROR;
}
- /* Process Locked */
+ /* Process Locked */
__HAL_LOCK(hhash);
/* If resuming the HASH processing */
@@ -2691,15 +2721,15 @@
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
hhash->HashITCounter = 1;
}
else
{
- hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+ hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
}
/* Set the phase */
@@ -2709,13 +2739,13 @@
fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
Therefore, first words are manually entered until DINIS raises, or until there
is not more data to enter. */
- while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
+ while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
{
/* Write input data 4 bytes at a time */
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- SizeVar-=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ SizeVar -= 4U;
}
/* If DINIS is still not set or if all the data have been fed, stop here */
@@ -2736,10 +2766,10 @@
to be fed to the Peripheral */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
the next interruption */
- /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
- the information describing where the HASH process is stopped.
- These variables are used later on to resume the HASH processing at the
- correct location. */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
}
@@ -2776,16 +2806,17 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
uint32_t polling_step = 0U;
uint32_t initialization_skipped = 0U;
uint32_t SizeVar = Size;
/* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
@@ -2804,23 +2835,23 @@
hhash->HashITCounter = 1;
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
to be fed to the Peripheral */
hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at
the next interruption */
- /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
- the information describing where the HASH process is stopped.
- These variables are used later on to resume the HASH processing at the
- correct location. */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
@@ -2832,17 +2863,17 @@
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /* If DINIS is equal to 0 (for example if an incomplete block has been previously
- fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
- Therefore, first words are manually entered until DINIS raises. */
- while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
+ /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+ fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+ Therefore, first words are manually entered until DINIS raises. */
+ while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
{
polling_step = 1U; /* note that some words are entered before enabling the interrupt */
/* Write input data 4 bytes at a time */
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- SizeVar-=4U;
+ HASH->DIN = *(uint32_t *)inputaddr;
+ inputaddr += 4U;
+ SizeVar -= 4U;
}
if (polling_step == 1U)
@@ -2854,7 +2885,7 @@
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
/* Start the Digest calculation */
- __HAL_HASH_START_DIGEST();
+ __HAL_HASH_START_DIGEST();
/* Process Unlock */
__HAL_UNLOCK(hhash);
@@ -2871,7 +2902,8 @@
Update HashInCount and pHashInBuffPtr accordingly. */
hhash->HashInCount = SizeVar;
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
- __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */
+ /* Update the configuration of the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(SizeVar);
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
if (initialization_skipped == 1U)
{
@@ -2883,11 +2915,11 @@
/* DINIS is not set but it remains a few data to enter (not enough for a full word).
Manually enter the last bytes before enabling DCIE. */
__HAL_HASH_SET_NBVALIDBITS(SizeVar);
- HASH->DIN = *(uint32_t*)inputaddr;
+ HASH->DIN = *(uint32_t *)inputaddr;
- /* Start the Digest calculation */
+ /* Start the Digest calculation */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
- __HAL_HASH_START_DIGEST();
+ __HAL_HASH_START_DIGEST();
/* Process Unlock */
__HAL_UNLOCK(hhash);
@@ -2904,7 +2936,7 @@
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Return function status */
return HAL_OK;
@@ -2944,15 +2976,15 @@
(case of multi-buffer HASH processing) */
assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
- /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ( (pInBuffer == NULL ) || (Size == 0U) ||
- /* Check phase coherency. Phase must be
- either READY (fresh start)
- or PROCESS (multi-buffer HASH management) */
- ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
+ if ((pInBuffer == NULL) || (Size == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or PROCESS (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -2972,10 +3004,10 @@
If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
API is processing a new input data message in case of multi-buffer HASH
computation. */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -3015,7 +3047,9 @@
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
/* Enable the DMA In DMA stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) : \
+ (inputSize / 4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -3046,10 +3080,10 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- if(hhash->State == HAL_HASH_STATE_READY)
+ if (hhash->State == HAL_HASH_STATE_READY)
{
/* Check parameter */
if (pOutBuffer == NULL)
@@ -3107,15 +3141,17 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Timeout, uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+ || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -3128,28 +3164,34 @@
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
- if(hhash->Init.KeySize > 64U)
+ if (hhash->Init.KeySize > 64U)
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
/* Set the phase to Step 1 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
/* Resort to hhash internal fields to feed the Peripheral.
Parameters will be updated in case of suspension to contain the proper
information at resumption time. */
- hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
- hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */
- hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */
- hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
- hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input
+ parameter for Step 2 */
+ hhash->HashInCount = Size; /* Input data size, HMAC_Processing input
+ parameter for Step 2 */
+ hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process*/
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step
+ 1 and Step 3 */
+ hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1
+ and Step 3 */
}
/* Carry out HMAC processing */
@@ -3177,15 +3219,17 @@
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
+ uint32_t Algorithm)
{
- HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+ || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -3204,13 +3248,15 @@
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
- if(hhash->Init.KeySize > 64U)
+ if (hhash->Init.KeySize > 64U)
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
- MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
/* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
@@ -3255,7 +3301,7 @@
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
- __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Return function status */
return HAL_OK;
@@ -3290,18 +3336,18 @@
uint32_t inputSize;
HAL_StatusTypeDef status ;
HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
- is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
- assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
+ is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
+ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
/* If State is ready or suspended, start or resume DMA-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
- if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
- /* Check phase coherency. Phase must be
- either READY (fresh start)
- or one of HMAC PROCESS steps (multi-buffer HASH management) */
- ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or one of HMAC PROCESS steps (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
@@ -3314,63 +3360,65 @@
/* If not a case of resumption after suspension */
if (hhash->State == HAL_HASH_STATE_READY)
{
- /* Check whether or not initialization phase has already be performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
- At the same time, ensure MDMAT bit is cleared. */
- if(hhash->Init.KeySize > 64U)
+ /* Check whether or not initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
{
- MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
+ At the same time, ensure MDMAT bit is cleared. */
+ if (hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+ Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ /* Store input aparameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
+ hhash->HashBuffSize = Size; /* input data size (in bytes) */
+
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
+ inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
+
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+
}
- else
- {
- MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- /* Store input aparameters in handle fields to manage steps transition
- or possible HMAC suspension/resumption */
- hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
- hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
- hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
- hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
- hhash->HashBuffSize = Size; /* input data size (in bytes) */
-
- /* Set DMA input parameters */
- inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
- inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
-
- /* Configure the number of valid bits in last word of the key */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Set the phase to Step 1 */
- hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
-
- }
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
- {
- /* Process a new input data message in case of multi-buffer HMAC processing
- (this is not a resumption case) */
+ {
+ /* Process a new input data message in case of multi-buffer HMAC processing
+ (this is not a resumption case) */
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Save input parameters to be able to manage possible suspension/resumption */
+ /* Save input parameters to be able to manage possible suspension/resumption */
hhash->HashInCount = Size; /* Input message address */
hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */
- /* Set DMA input parameters */
+ /* Set DMA input parameters */
inputaddr = (uint32_t)pInBuffer; /* Input message address */
inputSize = Size; /* Input message size in bytes */
- if (hhash->DigestCalculationDisable == RESET)
- {
- /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
- __HAL_HASH_RESET_MDMAT();
- __HAL_HASH_SET_NBVALIDBITS(inputSize);
+ if (hhash->DigestCalculationDisable == RESET)
+ {
+ /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+ __HAL_HASH_RESET_MDMAT();
+ __HAL_HASH_SET_NBVALIDBITS(inputSize);
+ }
}
- }
else
{
/* Phase not aligned with handle READY state */
@@ -3381,7 +3429,7 @@
}
else
{
- /* Resumption case (phase may be Step 1, 2 or 3) */
+ /* Resumption case (phase may be Step 1, 2 or 3) */
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
@@ -3404,7 +3452,10 @@
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
/* Enable the DMA In DMA stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+ (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
+ : (inputSize / 4U)));
+
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -3440,6 +3491,3 @@
* @}
*/
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_hash_ex.c b/Src/stm32h7xx_hal_hash_ex.c
index 2ddac61..86b7030 100644
--- a/Src/stm32h7xx_hal_hash_ex.c
+++ b/Src/stm32h7xx_hal_hash_ex.c
@@ -14,6 +14,17 @@
* and SHA-256.
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### HASH peripheral extended features #####
@@ -39,14 +50,15 @@
User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
well the computed digest.
- (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
+ (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
except for the last one.
User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set through
+ __HAL_HASH_SET_MDMAT() macro.
From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer through the
@@ -68,17 +80,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -107,8 +108,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
- * @brief HASH extended processing functions using polling mode.
- *
+ * @brief HASH extended processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HASH extended processing functions #####
@@ -147,7 +148,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
@@ -174,7 +176,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -187,7 +189,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
@@ -203,7 +206,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
@@ -230,7 +234,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+ return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -243,7 +247,8 @@
* @param Timeout Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
@@ -253,8 +258,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
- * @brief HASH extended processing functions using interrupt mode.
- *
+ * @brief HASH extended processing functions using interrupt mode.
+ *
@verbatim
===============================================================================
##### Interruption mode HASH extended processing functions #####
@@ -285,9 +290,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -310,7 +316,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -322,9 +328,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
@@ -337,9 +344,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -362,7 +370,7 @@
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+ return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -374,9 +382,10 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
- return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
@@ -384,8 +393,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
- * @brief HASH extended processing functions using DMA mode.
- *
+ * @brief HASH extended processing functions using DMA mode.
+ *
@verbatim
===============================================================================
##### DMA mode HASH extended processing functions #####
@@ -440,9 +449,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -470,9 +479,9 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
- return HASH_Finish(hhash, pOutBuffer, Timeout);
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
@@ -480,8 +489,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
- * @brief HMAC extended processing functions using polling mode.
- *
+ * @brief HMAC extended processing functions using polling mode.
+ *
@verbatim
===============================================================================
##### Polling mode HMAC extended processing functions #####
@@ -512,7 +521,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
@@ -530,7 +540,8 @@
* @param Timeout Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
@@ -541,8 +552,8 @@
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
- * @brief HMAC extended processing functions using interruption mode.
- *
+ * @brief HMAC extended processing functions using interruption mode.
+ *
@verbatim
===============================================================================
##### Interrupt mode HMAC extended processing functions #####
@@ -572,7 +583,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
@@ -589,7 +601,8 @@
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
+ uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
@@ -603,8 +616,8 @@
/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
- * @brief HMAC extended processing functions using DMA mode.
- *
+ * @brief HMAC extended processing functions using DMA mode.
+ *
@verbatim
===============================================================================
##### DMA mode HMAC extended processing functions #####
@@ -681,8 +694,8 @@
*/
/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
- * @brief HMAC extended processing functions in multi-buffer DMA mode.
- *
+ * @brief HMAC extended processing functions in multi-buffer DMA mode.
+ *
@verbatim
===============================================================================
##### Multi-buffer DMA mode HMAC extended processing functions #####
@@ -1025,6 +1038,3 @@
* @}
*/
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_hcd.c b/Src/stm32h7xx_hal_hcd.c
index 1e5a89a..13b6521 100644
--- a/Src/stm32h7xx_hal_hcd.c
+++ b/Src/stm32h7xx_hal_hcd.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -40,17 +51,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -61,7 +61,6 @@
*/
#ifdef HAL_HCD_MODULE_ENABLED
-
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @defgroup HCD HCD
@@ -495,7 +494,8 @@
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t i, interrupt;
+ uint32_t i;
+ uint32_t interrupt;
/* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
@@ -537,14 +537,19 @@
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
{
+ /* Flush USB Fifo */
+ (void)USB_FlushTxFifo(USBx, 0x10U);
+ (void)USB_FlushRxFifo(USBx);
+
+ /* Restore FS Clock */
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->DisconnectCallback(hhcd);
#else
HAL_HCD_Disconnect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-
- (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
}
@@ -950,7 +955,8 @@
/**
* @brief Unregister the USB HCD Host Channel Notify URB Change Callback
- * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * USB HCD Host Channel Notify URB Change Callback is redirected
+ * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
* @param hhcd HCD handle
* @retval HAL status
*/
@@ -1008,8 +1014,11 @@
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
- __HAL_HCD_ENABLE(hhcd);
+ /* Enable port power */
(void)USB_DriveVbus(hhcd->Instance, 1U);
+
+ /* Enable global interrupt */
+ __HAL_HCD_ENABLE(hhcd);
__HAL_UNLOCK(hhcd);
return HAL_OK;
@@ -1172,13 +1181,13 @@
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
hhcd->hc[ch_num].state = HC_BBLERR;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
@@ -1187,26 +1196,21 @@
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- hhcd->hc[ch_num].state = HC_STALL;
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+ hhcd->hc[ch_num].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- hhcd->hc[ch_num].state = HC_DATATGLERR;
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+ hhcd->hc[ch_num].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else
{
@@ -1215,7 +1219,6 @@
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
}
@@ -1234,7 +1237,6 @@
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
@@ -1279,8 +1281,6 @@
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
- __HAL_HCD_MASK_HALT_HC_INT(ch_num);
-
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
@@ -1329,14 +1329,18 @@
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
hhcd->hc[ch_num].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
@@ -1347,7 +1351,6 @@
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_NAK;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
@@ -1381,7 +1384,8 @@
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
@@ -1390,16 +1394,14 @@
if (hhcd->hc[ch_num].do_ping == 1U)
{
hhcd->hc[ch_num].do_ping = 0U;
- hhcd->hc[ch_num].urb_state = URB_NOTREADY;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
@@ -1411,26 +1413,23 @@
hhcd->hc[ch_num].do_ping = 1U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
hhcd->hc[ch_num].state = HC_XFRC;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
{
hhcd->hc[ch_num].state = HC_NYET;
hhcd->hc[ch_num].do_ping = 1U;
hhcd->hc[ch_num].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
hhcd->hc[ch_num].state = HC_STALL;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
@@ -1445,7 +1444,6 @@
}
}
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
@@ -1454,7 +1452,6 @@
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_XACTERR;
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else
@@ -1464,7 +1461,12 @@
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
@@ -1475,38 +1477,32 @@
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
- (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
hhcd->hc[ch_num].state = HC_DATATGLERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
- __HAL_HCD_MASK_HALT_HC_INT(ch_num);
-
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
{
- if (hhcd->Init.dma_enable == 1U)
- {
- if (hhcd->hc[ch_num].xfer_len > 0U)
- {
- num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
-
- if ((num_packets & 1U) != 0U)
- {
- hhcd->hc[ch_num].toggle_out ^= 1U;
- }
- }
- }
- else
+ if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].toggle_out ^= 1U;
}
+
+ if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U))
+ {
+ num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
+
+ if ((num_packets & 1U) != 0U)
+ {
+ hhcd->hc[ch_num].toggle_out ^= 1U;
+ }
+ }
}
}
else if (hhcd->hc[ch_num].state == HC_NAK)
@@ -1547,7 +1543,12 @@
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
@@ -1630,7 +1631,8 @@
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- __IO uint32_t hprt0, hprt0_dup;
+ __IO uint32_t hprt0;
+ __IO uint32_t hprt0_dup;
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
@@ -1650,7 +1652,7 @@
HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
- hprt0_dup |= USB_OTG_HPRT_PCDET;
+ hprt0_dup |= USB_OTG_HPRT_PCDET;
}
/* Check whether Port Enable Changed */
@@ -1723,5 +1725,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_hrtim.c b/Src/stm32h7xx_hal_hrtim.c
index 1d7efa1..56a3d49 100644
--- a/Src/stm32h7xx_hal_hrtim.c
+++ b/Src/stm32h7xx_hal_hrtim.c
@@ -49,6 +49,18 @@
* + Waveform Timer Burst Status Get
* + Waveform Timer Push-Pull Status Get
* + Peripheral State Get
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### Simple mode v.s. waveform mode #####
@@ -70,6 +82,8 @@
operates in waveform mode, all the HRTIM features are accessible without
any restriction. HRTIM waveform modes are managed through the set of
functions named HAL_HRTIM_Waveform<Function>
+
+==============================================================================
##### How to use this driver #####
==============================================================================
[..]
@@ -339,18 +353,6 @@
callbacks are set to the corresponding weak functions.
@endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
******************************************************************************
*/
@@ -1618,11 +1620,11 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ if(hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
@@ -2235,11 +2237,11 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ if(hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
@@ -5329,7 +5331,7 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMERID(Timers));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
@@ -5764,11 +5766,11 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ if(hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
{
@@ -6115,6 +6117,9 @@
/* Check parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(TimerIdx);
+
/* Set output state according to output control status and output disable status */
switch (Output)
{
@@ -9290,5 +9295,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_hsem.c b/Src/stm32h7xx_hal_hsem.c
index 78ae43b..1d17bac 100644
--- a/Src/stm32h7xx_hal_hsem.c
+++ b/Src/stm32h7xx_hal_hsem.c
@@ -14,6 +14,17 @@
* + IRQ handler management
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -71,17 +82,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -205,7 +205,7 @@
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
-#else
+#else
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
{
@@ -445,5 +445,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_i2c.c b/Src/stm32h7xx_hal_i2c.c
index 09b3e2a..9954e5a 100644
--- a/Src/stm32h7xx_hal_i2c.c
+++ b/Src/stm32h7xx_hal_i2c.c
@@ -9,6 +9,17 @@
* + IO operation functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,7 +30,7 @@
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
@@ -28,7 +39,8 @@
(+++) Configure the I2Cx interrupt priority
(+++) Enable the NVIC I2C IRQ Channel
(##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
+ (+++) Declare a DMA_HandleTypeDef handle structure for
+ the transmit or receive stream or channel depends on Instance
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx stream or channel depends on Instance
@@ -39,49 +51,49 @@
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
- (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
- (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
- (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
- (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
@@ -92,120 +104,135 @@
when a direction change during transfer
[..]
(+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
+ (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
+ no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
- (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
- and data to transfer without a final stop condition, an then permit a call the same master sequential interface
- several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
- or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
+ start condition, address and data to transfer without a final stop condition,
+ an then permit a call the same master sequential interface several times
+ (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+ or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
if no direction change and without a final stop condition in both cases
(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
- and with new data to transfer if the direction change or manage only the new data to transfer
+ and with new data to transfer if the direction change or manage only the new data to
+ transfer
if no direction change and with a final stop condition in both cases
- (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
- interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
- Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
- or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
- or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
- or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+ after several call of the same master sequential interface several times
+ (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using
+ HAL_I2C_Master_Seq_Transmit_IT
+ or HAL_I2C_Master_Seq_Receive_IT
+ or HAL_I2C_Master_Seq_Transmit_DMA
+ or HAL_I2C_Master_Seq_Receive_DMA
+ with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
+ Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
- (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+ each call of the same master sequential
interface.
- Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
- or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
- or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
- or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
- Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+ Usage can, transfer several bytes one by one with a restart with slave address between
+ each bytes using
+ HAL_I2C_Master_Seq_Transmit_IT
+ or HAL_I2C_Master_Seq_Receive_IT
+ or HAL_I2C_Master_Seq_Transmit_DMA
+ or HAL_I2C_Master_Seq_Receive_DMA
+ with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+ generation of STOP condition.
(+) Different sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
- or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
- (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
- or using @ref HAL_I2C_Master_Seq_Receive_DMA()
- (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
- or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
- (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
- or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
- (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
- (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
+ users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+ HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+ add their own code to check the Address Match Code and the transmission direction request by master
+ (Write/Read).
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
+ users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+ HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- @ref HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- @ref HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- @ref HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
- (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- @ref HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- @ref HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
@@ -213,23 +240,23 @@
[..]
Below the list of most used macros in I2C HAL driver.
- (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+ Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+ Function HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
@@ -244,11 +271,11 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
- For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+ For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
[..]
- Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+ Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
- @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
@@ -263,24 +290,24 @@
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+ For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
[..]
- By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+ examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+ reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
- or @ref HAL_I2C_Init() function.
+ using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+ or HAL_I2C_Init() function.
[..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
@@ -290,18 +317,6 @@
(@) You can refer to the I2C HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -336,28 +351,48 @@
#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
#define MAX_NBYTE_SIZE 255U
-#define SlaveAddr_SHIFT 7U
-#define SlaveAddr_MSK 0x06U
+#define SLAVE_ADDR_SHIFT 7U
+#define SLAVE_ADDR_MSK 0x06U
/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
-#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+ (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+ (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+ (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
+ @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
+ @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
+ and @ref I2C_XFER_RX_IT */
-#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
-#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
-#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
+ and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -366,6 +401,9 @@
*/
/* Private macro -------------------------------------------------------------*/
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -390,24 +428,34 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart);
/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
@@ -559,7 +607,8 @@
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
/* Configure I2Cx: Dual mode and Own Address2 */
- hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+ (hi2c->Init.OwnAddress2Masks << 8));
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
@@ -1065,8 +1114,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -1097,12 +1146,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
@@ -1132,12 +1183,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
}
@@ -1180,8 +1233,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
- uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -1212,12 +1265,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
@@ -1248,12 +1303,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
}
@@ -1294,7 +1351,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1376,22 +1434,27 @@
hi2c->XferCount--;
}
+ /* Wait until AF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
@@ -1431,7 +1494,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1455,6 +1519,7 @@
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
@@ -1497,6 +1562,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
return HAL_ERROR;
@@ -1509,6 +1575,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
/* Wait until STOP flag is set */
@@ -1606,7 +1673,8 @@
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -1627,7 +1695,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
@@ -1675,7 +1744,8 @@
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
@@ -1724,7 +1794,8 @@
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
@@ -1773,7 +1844,8 @@
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
@@ -1846,7 +1918,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -1906,7 +1979,8 @@
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1916,7 +1990,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -1990,7 +2065,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -2050,7 +2126,8 @@
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2060,7 +2137,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -2118,7 +2196,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -2221,7 +2300,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -2374,12 +2454,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
@@ -2474,12 +2556,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
}
do
@@ -2510,12 +2594,14 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+ I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
@@ -2608,7 +2694,8 @@
}
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+ != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2627,7 +2714,8 @@
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -2719,7 +2807,8 @@
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
@@ -2792,7 +2881,8 @@
}
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
+ != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2813,7 +2903,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -2957,7 +3048,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -3028,7 +3120,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -3205,9 +3298,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3291,9 +3386,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3324,7 +3421,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -3383,7 +3481,8 @@
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3393,7 +3492,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -3453,9 +3553,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3539,9 +3641,11 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame,
+ do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+ (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -3572,7 +3676,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+ hi2c->XferSize);
}
else
{
@@ -3631,7 +3736,8 @@
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+ I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3641,7 +3747,8 @@
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
- /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
@@ -3862,7 +3969,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
}
else
{
@@ -3912,15 +4020,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
return HAL_OK;
}
else
@@ -4138,7 +4246,8 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+ (uint32_t)pData, hi2c->XferSize);
}
else
{
@@ -4188,15 +4297,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
return HAL_OK;
}
else
@@ -4356,7 +4465,8 @@
uint32_t tmperror;
/* I2C Bus error interrupt occurred ------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
@@ -4365,7 +4475,8 @@
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
@@ -4374,7 +4485,8 @@
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
@@ -4628,7 +4740,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint16_t devaddress;
uint32_t tmpITFlags = ITFlags;
@@ -4636,7 +4749,8 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -4649,7 +4763,8 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
@@ -4663,7 +4778,8 @@
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
@@ -4674,7 +4790,8 @@
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
@@ -4690,11 +4807,13 @@
hi2c->XferSize = hi2c->XferCount;
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+ hi2c->XferOptions, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -4714,7 +4833,8 @@
}
}
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
@@ -4745,7 +4865,8 @@
/* Nothing to do */
}
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, tmpITFlags);
@@ -4765,7 +4886,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t tmpITFlags = ITFlags;
@@ -4774,13 +4896,15 @@
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
- if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -4788,8 +4912,9 @@
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
- /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
@@ -4828,7 +4953,8 @@
}
}
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
if (hi2c->XferCount > 0U)
{
@@ -4854,11 +4980,12 @@
{
I2C_ITAddrCplt(hi2c, tmpITFlags);
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all data have already been sent */
+ /* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
@@ -4900,7 +5027,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint16_t devaddress;
uint32_t xfermode;
@@ -4908,7 +5036,8 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -4924,7 +5053,8 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
@@ -4985,7 +5115,8 @@
}
}
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
@@ -5011,7 +5142,8 @@
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
@@ -5035,7 +5167,8 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
@@ -5045,13 +5178,15 @@
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
- if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5065,7 +5200,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
{
treatdmanack = 1U;
}
@@ -5077,7 +5212,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
{
treatdmanack = 1U;
}
@@ -5086,8 +5221,9 @@
if (treatdmanack == 1U)
{
- /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+ Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
@@ -5148,7 +5284,8 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
- else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
@@ -5175,8 +5312,9 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
@@ -5229,8 +5367,9 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
- uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+ uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+ uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
@@ -5298,7 +5437,7 @@
/* If 10bits addressing mode is selected */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+ if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
{
slaveaddrcode = ownadd1code;
hi2c->AddrEventCount++;
@@ -5684,7 +5823,7 @@
if (hi2c->hdmatx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
}
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
@@ -5694,7 +5833,7 @@
if (hi2c->hdmarx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
}
}
else
@@ -6025,7 +6164,8 @@
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -6053,7 +6193,8 @@
}
/* Enable the DMA stream or channel depends on Instance */
- if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+ if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize) != HAL_OK)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
@@ -6073,7 +6214,8 @@
*/
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
@@ -6100,7 +6242,8 @@
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -6128,7 +6271,8 @@
}
/* Enable the DMA stream or channel depends on Instance */
- if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+ if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+ hi2c->XferSize) != HAL_OK)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
@@ -6148,10 +6292,11 @@
*/
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
- if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+ if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Disable DMA Request */
@@ -6176,11 +6321,12 @@
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t treatdmaerror = 0U;
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
if (hi2c->hdmatx != NULL)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
{
treatdmaerror = 1U;
}
@@ -6188,7 +6334,7 @@
if (hi2c->hdmarx != NULL)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
{
treatdmaerror = 1U;
}
@@ -6213,7 +6359,8 @@
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Reset AbortCpltCallback */
if (hi2c->hdmatx != NULL)
@@ -6229,11 +6376,12 @@
}
/**
- * @brief This function handles I2C Communication Timeout.
+ * @brief This function handles I2C Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Flag Specifies the I2C flag to check.
- * @param Status The new Flag status (SET or RESET).
+ * @param Status The actual Flag status (SET or RESET).
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
@@ -6269,12 +6417,13 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
{
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
@@ -6306,12 +6455,13 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
@@ -6340,12 +6490,13 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
- /* Check if a NACK is detected */
- if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
@@ -6363,13 +6514,22 @@
}
else
{
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -6396,60 +6556,136 @@
}
/**
- * @brief This function handles Acknowledge failed detection during an I2C Communication.
+ * @brief This function handles errors detection during an I2C Communication.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t itflag = hi2c->Instance->ISR;
+ uint32_t error_code = 0;
+ uint32_t tickstart = Tickstart;
+ uint32_t tmp1;
+ HAL_I2C_ModeTypeDef tmp2;
+
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
{
- /* Wait until STOP Flag is reset */
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
- while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+ tmp2 = hi2c->Mode;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
+ /* In case of I2C still busy, try to regenerate a STOP manually */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+ (tmp1 != I2C_CR2_STOP) && \
+ (tmp2 != HAL_I2C_MODE_SLAVE))
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Update Tick with new reference */
+ tickstart = HAL_GetTick();
+ }
+
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ status = HAL_ERROR;
+ }
+ }
}
}
}
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* In case STOP Flag is detected, clear it */
+ if (status == HAL_OK)
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ error_code |= HAL_I2C_ERROR_AF;
+ status = HAL_ERROR;
+ }
+
+ /* Refresh Content of Status register */
+ itflag = hi2c->Instance->ISR;
+
+ /* Then verify if an additional errors occurs */
+ /* Check if a Bus error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+ {
+ error_code |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Over-Run/Under-Run error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+ {
+ error_code |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+ status = HAL_ERROR;
+ }
+
+ /* Check if an Arbitration Loss error occurred */
+ if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+ {
+ error_code |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_OK)
+ {
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ hi2c->ErrorCode |= error_code;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
}
- return HAL_OK;
+
+ return status;
}
/**
@@ -6479,12 +6715,16 @@
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
/* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2,
+ MODIFY_REG(hi2c->Instance->CR2, \
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
- (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
/**
@@ -6663,5 +6903,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_i2c_ex.c b/Src/stm32h7xx_hal_i2c_ex.c
index 26a046b..d9b8e46 100644
--- a/Src/stm32h7xx_hal_i2c_ex.c
+++ b/Src/stm32h7xx_hal_i2c_ex.c
@@ -5,8 +5,21 @@
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
- * + Extended features functions
+ * + Filter Mode Functions
+ * + WakeUp Mode Functions
+ * + FastModePlus Functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
@@ -32,18 +45,6 @@
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -71,17 +72,15 @@
* @{
*/
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
+/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+ * @brief Filter Mode Functions
*
@verbatim
===============================================================================
- ##### Extended features functions #####
+ ##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
- (+) Configure Wake Up Feature
- (+) Configure Fast Mode Plus
@endverbatim
* @{
@@ -182,6 +181,23 @@
return HAL_BUSY;
}
}
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @brief WakeUp Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Mode Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Wake Up Feature
+
+@endverbatim
+ * @{
+ */
/**
* @brief Enable I2C wakeup from Stop mode(s).
@@ -260,6 +276,23 @@
return HAL_BUSY;
}
}
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ * @brief Fast Mode Plus Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Fast Mode Plus Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
/**
* @brief Enable the I2C fast mode plus driving capability.
@@ -322,11 +355,9 @@
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
}
-
/**
* @}
*/
-
/**
* @}
*/
@@ -339,5 +370,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_i2s.c b/Src/stm32h7xx_hal_i2s.c
index fa1a7cb..eb1233c 100644
--- a/Src/stm32h7xx_hal_i2s.c
+++ b/Src/stm32h7xx_hal_i2s.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -117,6 +128,7 @@
(+) TxRxCpltCallback : I2S TxRx Completed callback
(+) TxHalfCpltCallback : I2S Tx Half Completed callback
(+) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback
(+) ErrorCallback : I2S Error callback
(+) MspInitCallback : I2S Msp Init callback
(+) MspDeInitCallback : I2S Msp DeInit callback
@@ -134,6 +146,7 @@
(+) TxRxCpltCallback : I2S TxRx Completed callback
(+) TxHalfCpltCallback : I2S Tx Half Completed callback
(+) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback
(+) ErrorCallback : I2S Error callback
(+) MspInitCallback : I2S Msp Init callback
(+) MspDeInitCallback : I2S Msp DeInit callback
@@ -161,18 +174,6 @@
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -356,12 +357,12 @@
/* Get the source clock value: based on System Clock value */
#if defined (SPI_SPI6I2S_SUPPORT)
- if (hi2s->Instance == SPI6)
- {
- /* SPI6 source clock */
+ if (hi2s->Instance == SPI6)
+ {
+ /* SPI6 source clock */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
}
- else
+ else
{
/* SPI1,SPI2 and SPI3 share the same source clock */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
@@ -369,7 +370,7 @@
#else
/* SPI1,SPI2 and SPI3 share the same source clock */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
-#endif
+#endif /* SPI_SPI6I2S_SUPPORT */
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
@@ -414,7 +415,7 @@
}
MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD),
- ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
+ ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
}
/*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
@@ -425,10 +426,10 @@
SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \
SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_WSINV | \
SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_MCKOE),
- (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
- hi2s->Init.Standard | hi2s->Init.DataFormat | \
- hi2s->Init.CPOL | hi2s->Init.WSInversion | \
- hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
+ (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
+ hi2s->Init.Standard | hi2s->Init.DataFormat | \
+ hi2s->Init.CPOL | hi2s->Init.WSInversion | \
+ hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
/*Clear status register*/
WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
@@ -538,7 +539,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -567,7 +569,7 @@
case HAL_I2S_TX_RX_COMPLETE_CB_ID :
hi2s->TxRxCpltCallback = pCallback;
break;
-
+
case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
hi2s->TxHalfCpltCallback = pCallback;
break;
@@ -580,7 +582,7 @@
case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
hi2s->TxRxHalfCpltCallback = pCallback;
break;
-
+
case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = pCallback;
break;
@@ -679,7 +681,7 @@
case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
break;
-
+
case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
break;
@@ -812,15 +814,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -851,7 +852,7 @@
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
while (hi2s->TxXferCount > 0UL)
@@ -883,7 +884,7 @@
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
/* Check if an underrun occurs */
@@ -930,15 +931,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -971,7 +971,7 @@
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
@@ -1038,17 +1038,16 @@
__IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
#endif /* __GNUC__ */
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ return HAL_BUSY;
+ }
+
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1153,7 +1152,7 @@
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
@@ -1183,15 +1182,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1260,15 +1258,14 @@
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1331,17 +1328,16 @@
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size)
{
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
-
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ return HAL_BUSY;
+ }
+
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1357,7 +1353,7 @@
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
- /* Set the function for IT treatment */
+ /* Set the function for IT treatment */
if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
{
hi2s->TxISR = I2S_Transmit_32Bit_IT;
@@ -1369,7 +1365,7 @@
hi2s->RxISR = I2S_Receive_16Bit_IT;
}
- /* Check if the I2S is already enabled */
+ /* Check if the I2S is already enabled */
if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable I2S peripheral */
@@ -1409,20 +1405,21 @@
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
if ((pData == NULL) || (Size == 0UL))
{
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1445,14 +1442,16 @@
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
/* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
+ hi2s->TxXferCount))
{
/* Update I2S error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
+ return errorcode;
}
/* Check if the I2S Tx request is already enabled */
@@ -1473,7 +1472,7 @@
SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
__HAL_UNLOCK(hi2s);
- return HAL_OK;
+ return errorcode;
}
/**
@@ -1492,20 +1491,21 @@
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
if ((pData == NULL) || (Size == 0UL))
{
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if (hi2s->State != HAL_I2S_STATE_READY)
{
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
@@ -1529,12 +1529,13 @@
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
/* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
+ hi2s->RxXferCount))
{
/* Update I2S error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
-
+ errorcode = HAL_ERROR;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
@@ -1557,7 +1558,7 @@
SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
__HAL_UNLOCK(hi2s);
- return HAL_OK;
+ return errorcode;
}
/**
@@ -1578,17 +1579,19 @@
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size)
{
- if (hi2s->State != HAL_I2S_STATE_READY)
- {
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ return HAL_BUSY;
+ }
+
/* Process Locked */
__HAL_LOCK(hi2s);
@@ -1614,16 +1617,17 @@
/* Set the I2S Rx DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
/* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
+ hi2s->TxXferCount))
{
/* Update I2S error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
+ return errorcode;
}
/* Check if the I2S Tx request is already enabled */
@@ -1633,13 +1637,14 @@
SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
}
- /* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
+ hi2s->RxXferCount))
{
/* Update I2S error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
-
+ errorcode = HAL_ERROR;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
@@ -1662,7 +1667,7 @@
SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
__HAL_UNLOCK(hi2s);
- return HAL_OK;
+ return errorcode;
}
/**
@@ -2127,7 +2132,8 @@
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* if DMA is configured in DMA_NORMAL Mode */
if (hdma->Init.Mode == DMA_NORMAL)
@@ -2154,7 +2160,8 @@
*/
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Call user Tx half complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
@@ -2172,7 +2179,8 @@
*/
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* if DMA is configured in DMA_NORMAL Mode */
if (hdma->Init.Mode == DMA_NORMAL)
@@ -2198,7 +2206,8 @@
*/
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Call user Rx half complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
@@ -2252,7 +2261,8 @@
*/
static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Derogation MISRAC2012-Rule-11.5 */
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Rx and Tx DMA Request */
CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
@@ -2295,7 +2305,7 @@
/* Disable TXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
- if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
{
hi2s->State = HAL_I2S_STATE_READY;
}
@@ -2326,7 +2336,7 @@
/* Disable TXP and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
- if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+ if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
{
hi2s->State = HAL_I2S_STATE_READY;
}
@@ -2454,7 +2464,8 @@
* @param Timeout Duration of the timeout
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -2495,4 +2506,3 @@
#endif /* HAL_I2S_MODULE_ENABLED */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_i2s_ex.c b/Src/stm32h7xx_hal_i2s_ex.c
index dad1c58..171dcf7 100644
--- a/Src/stm32h7xx_hal_i2s_ex.c
+++ b/Src/stm32h7xx_hal_i2s_ex.c
@@ -5,21 +5,20 @@
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
- * + Extension features Functions
+ * + Extension features Functions
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
-
+
/**
******************************************************************************
===== I2S FULL DUPLEX FEATURE =====
@@ -30,4 +29,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_irda.c b/Src/stm32h7xx_hal_irda.c
index 865e9c8..e3ba448 100644
--- a/Src/stm32h7xx_hal_irda.c
+++ b/Src/stm32h7xx_hal_irda.c
@@ -11,6 +11,17 @@
* + Peripheral State and Errors functions
* + Peripheral Control functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -114,8 +125,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
- Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_IRDA_RegisterCallback() to register a user callback.
+ Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -130,9 +141,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -147,13 +158,13 @@
(+) MspDeInitCallback : IRDA MspDeInit.
[..]
- By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+ examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
- and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
+ and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -162,8 +173,8 @@
in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
- or @ref HAL_IRDA_Init() function.
+ using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
+ or HAL_IRDA_Init() function.
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
@@ -172,17 +183,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -801,10 +801,10 @@
* @param Timeout Specify timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
@@ -831,7 +831,7 @@
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
pdata8bits = NULL;
- pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
}
else
{
@@ -980,7 +980,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
@@ -1052,8 +1052,16 @@
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ /* Enable the IRDA Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1077,7 +1085,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
@@ -1194,8 +1202,11 @@
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1287,7 +1298,10 @@
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the IRDA DMA Rx request */
@@ -2285,28 +2299,28 @@
{
case IRDA_CLOCKSOURCE_D2PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_D2PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_PLL2Q:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_PLL3Q:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_CSI:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_HSI:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_LSE:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
default:
ret = HAL_ERROR;
@@ -2316,7 +2330,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
- hirda->Instance->BRR = tmpreg;
+ hirda->Instance->BRR = (uint16_t)tmpreg;
}
else
{
@@ -2374,11 +2388,12 @@
}
/**
- * @brief Handle IRDA Communication Timeout.
+ * @brief Handle IRDA Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param Flag Specifies the IRDA flag to check.
- * @param Status Flag status (SET or RESET)
+ * @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
@@ -2779,7 +2794,7 @@
*/
static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
@@ -2796,7 +2811,7 @@
{
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+ tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
hirda->pTxBuffPtr += 2U;
}
@@ -2904,4 +2919,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_iwdg.c b/Src/stm32h7xx_hal_iwdg.c
index 85548ac..2ec2829 100644
--- a/Src/stm32h7xx_hal_iwdg.c
+++ b/Src/stm32h7xx_hal_iwdg.c
@@ -8,6 +8,17 @@
* + Initialization and Start functions
* + IO operation functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### IWDG Generic features #####
@@ -87,18 +98,6 @@
the reload register
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -122,11 +121,13 @@
/* Status register needs up to 5 LSI clock periods divided by the clock
prescaler to be updated. The number of LSI clock periods is upper-rounded to
6 for the timeout value calculation.
- The timeout value is also calculated using the highest prescaler (256) and
+ The timeout value is calculated using the highest prescaler (256) and
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
- The timeout value is multiplied by 1000 to be converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+ The timeout value is multiplied by 1000 to be converted in milliseconds.
+ LSI startup time is also considered here by adding LSI_STARTUP_TIME
+ converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
@@ -280,5 +281,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_jpeg.c b/Src/stm32h7xx_hal_jpeg.c
index ce873e2..d833271 100644
--- a/Src/stm32h7xx_hal_jpeg.c
+++ b/Src/stm32h7xx_hal_jpeg.c
@@ -16,6 +16,17 @@
* + IRQ handler management
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -203,17 +214,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -4197,4 +4197,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_lptim.c b/Src/stm32h7xx_hal_lptim.c
index 5c39666..16bcdfc 100644
--- a/Src/stm32h7xx_hal_lptim.c
+++ b/Src/stm32h7xx_hal_lptim.c
@@ -11,6 +11,17 @@
* + Reading operation functions.
* + Peripheral State functions.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -96,13 +107,13 @@
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
- @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ Use Function HAL_LPTIM_RegisterCallback() to register a callback.
+ HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
- Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
+ Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function.
- @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
These functions allow to register/unregister following callbacks:
@@ -120,7 +131,7 @@
[..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
- examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+ examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
@@ -134,7 +145,7 @@
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+ using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
@@ -143,17 +154,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -235,8 +235,8 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
- || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
@@ -279,8 +279,8 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
- || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
@@ -310,8 +310,8 @@
}
/* Configure LPTIM external clock polarity and digital filter */
- if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
- || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
hlptim->Init.UltraLowPowerClock.SampleTime);
@@ -545,7 +545,7 @@
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -681,7 +681,7 @@
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -768,7 +768,7 @@
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -904,7 +904,7 @@
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -991,7 +991,7 @@
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1127,7 +1127,7 @@
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the TIM state*/
+ /* Change the LPTIM state*/
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -2177,39 +2177,48 @@
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ /* Legacy weak MspInit Callback */
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ /* Legacy weak Msp DeInit Callback */
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
break;
case HAL_LPTIM_COMPARE_MATCH_CB_ID :
- hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */
+ /* Legacy weak Compare match Callback */
+ hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
break;
case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
- hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */
+ /* Legacy weak Auto-reload match Callback */
+ hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
break;
case HAL_LPTIM_TRIGGER_CB_ID :
- hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */
+ /* Legacy weak External trigger event detection Callback */
+ hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
break;
case HAL_LPTIM_COMPARE_WRITE_CB_ID :
- hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */
+ /* Legacy weak Compare register write complete Callback */
+ hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
break;
case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
- hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */
+ /* Legacy weak Auto-reload register write complete Callback */
+ hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
break;
case HAL_LPTIM_DIRECTION_UP_CB_ID :
- hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */
+ /* Legacy weak Up-counting direction change Callback */
+ hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
break;
case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
- hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */
+ /* Legacy weak Down-counting direction change Callback */
+ hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
break;
default :
@@ -2223,11 +2232,13 @@
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
- hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ /* Legacy weak MspInit Callback */
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
- hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ /* Legacy weak Msp DeInit Callback */
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
break;
default :
@@ -2302,13 +2313,13 @@
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
{
/* Reset the LPTIM callback to the legacy weak callbacks */
- lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */
- lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */
- lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */
- lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */
- lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
- lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */
- lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */
+ lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
+ lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+ lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
+ lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
+ lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+ lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
+ lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -2351,9 +2362,12 @@
uint32_t tmpCFGR;
uint32_t tmpCMP;
uint32_t tmpARR;
+ uint32_t primask_bit;
uint32_t tmpCFGR2;
- __disable_irq();
+ /* Enter critical section */
+ primask_bit = __get_PRIMASK();
+ __set_PRIMASK(1) ;
/*********** Save LPTIM Config ***********/
/* Save LPTIM source clock */
@@ -2519,7 +2533,8 @@
hlptim->Instance->CFGR = tmpCFGR;
hlptim->Instance->CFGR2 = tmpCFGR2;
- __enable_irq();
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
}
/**
* @}
@@ -2534,5 +2549,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_ltdc.c b/Src/stm32h7xx_hal_ltdc.c
index 0258304..5f2b79b 100644
--- a/Src/stm32h7xx_hal_ltdc.c
+++ b/Src/stm32h7xx_hal_ltdc.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -146,17 +157,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2159,5 +2159,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_ltdc_ex.c b/Src/stm32h7xx_hal_ltdc_ex.c
index d53d698..b299937 100644
--- a/Src/stm32h7xx_hal_ltdc_ex.c
+++ b/Src/stm32h7xx_hal_ltdc_ex.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -145,5 +144,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_mdios.c b/Src/stm32h7xx_hal_mdios.c
index 834ffeb..d80bc56 100644
--- a/Src/stm32h7xx_hal_mdios.c
+++ b/Src/stm32h7xx_hal_mdios.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -112,18 +123,6 @@
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -954,4 +953,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_mdma.c b/Src/stm32h7xx_hal_mdma.c
index 1ce7664..089d9fb 100644
--- a/Src/stm32h7xx_hal_mdma.c
+++ b/Src/stm32h7xx_hal_mdma.c
@@ -7,6 +7,17 @@
* + Initialization/de-initialization functions
* + I/O operation functions
* + Peripheral State and errors functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -132,19 +143,7 @@
[..]
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
+ @endverbatim
*/
/* Includes ------------------------------------------------------------------*/
@@ -1898,4 +1897,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_mmc.c b/Src/stm32h7xx_hal_mmc.c
index 07ec0b2..3e57148 100644
--- a/Src/stm32h7xx_hal_mmc.c
+++ b/Src/stm32h7xx_hal_mmc.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + MMC card Control functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -177,7 +188,7 @@
The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
+ Use Functions HAL_MMC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -192,7 +203,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -206,12 +217,12 @@
(+) MspDeInitCallback : MMC MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
+ By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
- and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_MMC_Init
+ and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -219,8 +230,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
- or @ref HAL_MMC_Init function.
+ using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit
+ or HAL_MMC_Init function.
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -228,17 +239,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -261,7 +261,7 @@
* @{
*/
#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
-#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE
+#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
@@ -271,7 +271,7 @@
#define MMC_EXT_CSD_PWR_CL_52_POS 0
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
#else
-#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE
+#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
@@ -280,10 +280,15 @@
#define MMC_EXT_CSD_PWR_CL_26_POS 24
#define MMC_EXT_CSD_PWR_CL_52_POS 16
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
-#endif
+#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/
+
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS 0
+#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX 217
+#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8
/* Frequencies used in the driver for clock divider calculation */
-#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
/**
* @}
@@ -378,7 +383,7 @@
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_MMC_MspInit(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
hmmc->State = HAL_MMC_STATE_BUSY;
@@ -518,7 +523,7 @@
#else
/* De-Initialize the MSP layer */
HAL_MMC_MspDeInit(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_RESET;
@@ -594,7 +599,9 @@
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count, data, dataremaining;
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
@@ -615,7 +622,8 @@
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
- if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
+ & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
@@ -787,7 +795,9 @@
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count, data, dataremaining;
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
@@ -1452,7 +1462,8 @@
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
- if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
+ & 0x000000FFU) != 0x0U)
{
if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
{
@@ -1576,7 +1587,7 @@
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
@@ -1590,7 +1601,7 @@
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
@@ -1598,7 +1609,7 @@
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else if ((context & MMC_CONTEXT_IT) != 0U)
@@ -1614,7 +1625,7 @@
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
@@ -1628,7 +1639,7 @@
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else
{
@@ -1636,7 +1647,7 @@
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else
@@ -1730,7 +1741,7 @@
hmmc->Write_DMADblBuf1CpltCallback(hmmc);
#else
HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
{
@@ -1738,7 +1749,7 @@
hmmc->Read_DMADblBuf1CpltCallback(hmmc);
#else
HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else /* MMC_DMA_BUFFER1 */
@@ -1750,7 +1761,7 @@
hmmc->Write_DMADblBuf0CpltCallback(hmmc);
#else
HAL_MMCEx_Write_DMADoubleBuf0CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
{
@@ -1758,7 +1769,7 @@
hmmc->Read_DMADblBuf0CpltCallback(hmmc);
#else
HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
}
@@ -2055,7 +2066,7 @@
__HAL_UNLOCK(hmmc);
return status;
}
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
@@ -2285,7 +2296,7 @@
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 512;
+ config.DataLength = 512U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@@ -2747,7 +2758,7 @@
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -2905,7 +2916,9 @@
*/
HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc)
{
- uint32_t errorstate, response = 0U, count;
+ uint32_t errorstate;
+ uint32_t response = 0U;
+ uint32_t count;
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
@@ -3014,7 +3027,10 @@
*/
HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode)
{
- uint32_t srt, errorstate, response = 0U, count;
+ uint32_t srt;
+ uint32_t errorstate;
+ uint32_t response = 0U;
+ uint32_t count;
/* Check the erase type value is correct */
assert_param(IS_MMC_SRT_TYPE(SRTMode));
@@ -3138,6 +3154,343 @@
}
/**
+ * @brief Switch the device from Standby State to Sleep State.
+ * @param hmmc pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate,
+ sleep_timeout,
+ timeout,
+ count,
+ response = 0U ;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+ /* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Field SLEEP_NOTIFICATION_TIME [216] */
+ sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >>
+ MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU);
+
+ /* Sleep/Awake Timeout = 10µs * 2^SLEEP_NOTIFICATION_TIME */
+ /* In HAL, the tick interrupt occurs each ms */
+ if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+ {
+ sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+ }
+ timeout = (((1UL << sleep_timeout) / 100U) + 1U);
+
+ /* Wait that the device is ready by checking the D0 line */
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if ((HAL_GetTick() - tickstart) >= timeout)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
+ (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ else
+ {
+ /* Switch the device in stand-by mode */
+ (void)SDMMC_CmdSelDesel(hmmc->Instance, 0U);
+
+ /* Field S_A_TIEMOUT [217] */
+ sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >>
+ MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU);
+
+ /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
+ /* In HAL, the tick interrupt occurs each ms */
+ if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+ {
+ sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+ }
+ timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
+
+ if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+ {
+ /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */
+ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance,
+ ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U)));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if ((HAL_GetTick() - tickstart) >= timeout)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Switch the device from Sleep State to Standby State.
+ * @param hmmc pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate;
+ uint32_t sleep_timeout;
+ uint32_t timeout;
+ uint32_t count;
+ uint32_t response = 0U;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the state of the driver */
+ if (hmmc->State == HAL_MMC_STATE_READY)
+ {
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Field S_A_TIEMOUT [217] */
+ sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) &
+ 0x000000FFU);
+
+ /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
+ /* In HAL, the tick interrupt occurs each ms */
+ if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+ {
+ sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+ }
+ timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
+
+ /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */
+ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Wait that the device is ready by checking the D0 line */
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ if ((HAL_GetTick() - tickstart) >= timeout)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear the flag corresponding to end D0 bus line */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+ {
+ /* Switch the device in transfer mode */
+ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER)
+ {
+ /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+ if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
+ (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ } while (((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else if (errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ }
+ else
+ {
+ /* NOthing to do */
+ }
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+ }
+ }
+ else
+ {
+ errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+ }
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ /* Manage errors */
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
* @}
*/
@@ -3267,7 +3620,8 @@
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
{
__IO uint32_t count = 0U;
- uint32_t response = 0U, validvoltage = 0U;
+ uint32_t response = 0U;
+ uint32_t validvoltage = 0U;
uint32_t errorstate;
/* CMD0: GO_IDLE_STATE */
@@ -3376,7 +3730,7 @@
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 512;
+ config.DataLength = 512U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@@ -3395,7 +3749,8 @@
}
/* Poll on SDMMC flags */
- while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+ SDMMC_FLAG_DATAEND))
{
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
@@ -3476,7 +3831,8 @@
*/
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count, data;
+ uint32_t count;
+ uint32_t data;
uint8_t *tmp;
tmp = hmmc->pRxBuffPtr;
@@ -3510,7 +3866,8 @@
*/
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count, data;
+ uint32_t count;
+ uint32_t data;
uint8_t *tmp;
tmp = hmmc->pTxBuffPtr;
@@ -3545,7 +3902,8 @@
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response = 0U, count;
+ uint32_t response = 0U;
+ uint32_t count;
uint32_t sdmmc_clk;
SDMMC_InitTypeDef Init;
@@ -3613,13 +3971,21 @@
{
/* High Speed Clock should be less or equal to 52MHz*/
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+
if (sdmmc_clk == 0U)
{
errorstate = SDMMC_ERROR_INVALID_PARAMETER;
}
else
{
- Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ);
+ if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = 0;
+ }
+ else
+ {
+ Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U;
+ }
(void)SDMMC_Init(hmmc->Instance, Init);
SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
@@ -3649,7 +4015,8 @@
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t response = 0U, count;
+ uint32_t response = 0U;
+ uint32_t count;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
{
@@ -3758,7 +4125,8 @@
uint32_t count;
uint32_t response = 0U;
uint32_t errorstate = HAL_MMC_ERROR_NONE;
- uint32_t power_class, supported_pwr_class;
+ uint32_t power_class;
+ uint32_t supported_pwr_class;
if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
{
@@ -3922,5 +4290,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_mmc_ex.c b/Src/stm32h7xx_hal_mmc_ex.c
index f392a54..10acaf3 100644
--- a/Src/stm32h7xx_hal_mmc_ex.c
+++ b/Src/stm32h7xx_hal_mmc_ex.c
@@ -7,6 +7,17 @@
* functionalities of the Secure Digital (MMC) peripheral:
* + Extended features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -20,17 +31,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -351,5 +351,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_msp_template.c b/Src/stm32h7xx_hal_msp_template.c
index 48d5a2b..6f7fb11 100644
--- a/Src/stm32h7xx_hal_msp_template.c
+++ b/Src/stm32h7xx_hal_msp_template.c
@@ -6,6 +6,17 @@
* This file template is located in the HAL folder and should be copied
* to the user folder.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -14,17 +25,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -98,4 +98,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_nand.c b/Src/stm32h7xx_hal_nand.c
index 1b59059..74f6c6c 100644
--- a/Src/stm32h7xx_hal_nand.c
+++ b/Src/stm32h7xx_hal_nand.c
@@ -6,6 +6,17 @@
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -58,25 +69,25 @@
The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
+ Use Functions HAL_NAND_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+ By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
- and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
+ and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -84,8 +95,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
- or @ref HAL_NAND_Init function.
+ using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
+ or HAL_NAND_Init function.
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -93,17 +104,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2239,5 +2239,3 @@
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_nor.c b/Src/stm32h7xx_hal_nor.c
index 1fab108..60a0dee 100644
--- a/Src/stm32h7xx_hal_nor.c
+++ b/Src/stm32h7xx_hal_nor.c
@@ -6,6 +6,17 @@
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -55,25 +66,25 @@
The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+ Use Functions HAL_NOR_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+ By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
- and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
+ and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -81,8 +92,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
- or @ref HAL_NOR_Init function.
+ using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
+ or HAL_NOR_Init function.
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -90,17 +101,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -229,6 +229,7 @@
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR handle parameter */
if (hnor == NULL)
@@ -301,11 +302,23 @@
deviceaddress = NOR_MEMORY_ADRESS4;
}
+ FMC_NORSRAM_WriteOperation_Enable(hnor->Instance,hnor->Init.NSBank);
+
/* Get the value of the command set */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ status = HAL_NOR_ReturnToReadMode(hnor);
- return HAL_NOR_ReturnToReadMode(hnor);
+ if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
+ {
+ FMC_NORSRAM_WriteOperation_Disable(hnor->Instance,hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+ }
+
+ return status;
}
/**
@@ -1509,5 +1522,3 @@
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_opamp.c b/Src/stm32h7xx_hal_opamp.c
index 5ebf16e..096baae 100644
--- a/Src/stm32h7xx_hal_opamp.c
+++ b/Src/stm32h7xx_hal_opamp.c
@@ -4,15 +4,23 @@
* @author MCD Application Team
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the operational amplifier(s) peripheral:
- * + OPAMP configuration
- * + OPAMP calibration
- * Thanks to
+ * functionalities of the operational amplifier(s) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
- *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
================================================================================
##### OPAMP Peripheral Features #####
@@ -112,14 +120,14 @@
(++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
+ (++) Use Functions HAL_OPAMP_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
+ (++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspDeInit.
@@ -193,18 +201,6 @@
| | | COMP1_INN7 if | |
| | | connected internally | |
|-----------------|--------|-----------------------|---------------------|
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1160,4 +1156,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_opamp_ex.c b/Src/stm32h7xx_hal_opamp_ex.c
index f53006f..8eedb67 100644
--- a/Src/stm32h7xx_hal_opamp_ex.c
+++ b/Src/stm32h7xx_hal_opamp_ex.c
@@ -4,22 +4,20 @@
* @author MCD Application Team
* @brief Extended OPAMP HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
- * peripheral:
+ * functionalities of the operational amplifier(s) peripheral:
* + Extended Initialization and de-initialization functions
* + Extended Peripheral Control functions
- *
+ *
@verbatim
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -432,4 +430,4 @@
*/
#endif /* HAL_OPAMP_MODULE_ENABLED */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_ospi.c b/Src/stm32h7xx_hal_ospi.c
index 69cb96e..62cfcbb 100644
--- a/Src/stm32h7xx_hal_ospi.c
+++ b/Src/stm32h7xx_hal_ospi.c
@@ -15,6 +15,17 @@
+ Errors management and abort functionality
+ IO manager configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -109,24 +120,24 @@
====================================
[..]
Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_OSPI_MspInit() function :
- (+) MDMA settings for write operation :
- (++) The DestinationInc should be MDMA_DEST_INC_DISABLE
+ (+) MDMA settings for write operation :
+ (++) The DestinationInc should be MDMA_DEST_INC_DISABLE
(++) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
- (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
+ (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Source_increment_mode .
- (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
- (+) MDMA settings for read operation :
- (++) The SourceInc should be MDMA_SRC_INC_DISABLE
+ (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ (+) MDMA settings for read operation :
+ (++) The SourceInc should be MDMA_SRC_INC_DISABLE
(++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
(++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
(++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Destination_increment_mode.
(+) The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi.
[..]
- In case of wrong MDMA setting
- (+) For write operation :
+ In case of wrong MDMA setting
+ (+) For write operation :
(++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA().
- (+) For read operation :
+ (+) For read operation :
(++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA().
*** Memory-mapped functional mode ***
@@ -244,17 +255,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -303,7 +303,7 @@
static void OSPI_DMACplt (MDMA_HandleTypeDef *hmdma);
static void OSPI_DMAError (MDMA_HandleTypeDef *hmdma);
static void OSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma);
-static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
+static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
@@ -366,7 +366,6 @@
assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle));
assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary));
assert_param(IS_OSPI_CKCSHT (hospi->Init.ClkChipSelectHighTime));
- assert_param(IS_OSPI_DLYBYP (hospi->Init.DelayBlockBypass));
assert_param(IS_OSPI_MAXTRAN (hospi->Init.MaxTran));
/* Initialize error code */
@@ -403,14 +402,13 @@
/* Configure the default timeout for the OSPI memory access */
(void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
- /* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
+ /* Configure memory type, device size, chip select high time, clocked chip select high time, free running clock, clock mode */
MODIFY_REG(hospi->Instance->DCR1,
- (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
- OCTOSPI_DCR1_DLYBYP | OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
+ (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
+ OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
(hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
- (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) |
- hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
+ (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) | hospi->Init.ClockMode));
/* Configure wrap size */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);
@@ -431,7 +429,7 @@
if (status == HAL_OK)
{
/* Configure clock prescaler */
- MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
+ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
@@ -611,7 +609,7 @@
hospi->FifoThresholdCallback(hospi);
#else
HAL_OSPI_FifoThresholdCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
/* OctoSPI transfer complete interrupt occurred ----------------------------*/
else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
@@ -641,7 +639,7 @@
hospi->RxCpltCallback(hospi);
#else
HAL_OSPI_RxCpltCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
@@ -666,7 +664,7 @@
hospi->TxCpltCallback(hospi);
#else
HAL_OSPI_TxCpltCallback(hospi);
-#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
{
@@ -772,7 +770,7 @@
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
/* OctoSPI timeout interrupt occurred --------------------------------------*/
@@ -853,9 +851,9 @@
/* Check the state of the driver */
state = hospi->State;
if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
- ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
+ ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
|| (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
- ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
+ ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
(cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
{
/* Wait till busy flag is reset */
@@ -1463,7 +1461,7 @@
/* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment to disable */
MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
-
+
/* Update MDMA configuration with the correct SourceInc field for Write operation */
if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
{
@@ -1477,7 +1475,7 @@
{
MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
}
- else
+ else
{
/* in case of incorrect source data size */
hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
@@ -1486,18 +1484,18 @@
/* Enable the transmit MDMA Channel */
if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
-
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+
+ /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -1528,7 +1526,6 @@
uint32_t data_size = hospi->Instance->DLR + 1U;
uint32_t addr_reg = hospi->Instance->AR;
uint32_t ir_reg = hospi->Instance->IR;
-
/* Check the data pointer allocation */
if (pData == NULL)
{
@@ -1564,60 +1561,60 @@
/* Clear the DMA abort callback */
hospi->hmdma->XferAbortCallback = NULL;
-/* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
-
- /* Update MDMA configuration with the correct DestinationInc field for read operation */
- if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
- {
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
- }
- else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
- {
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
- }
- else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
- {
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
- }
- else
- {
- /* in case of incorrect destination data size */
- hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
- status = HAL_ERROR;
- }
+ /* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
+
+ /* Update MDMA configuration with the correct DestinationInc field for read operation */
+ if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
+ {
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
+ }
+ else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
+ {
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
+ }
+ else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
+ {
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
+ }
+ else
+ {
+ /* in case of incorrect destination data size */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
+ status = HAL_ERROR;
+ }
/* Enable the transmit MDMA Channel */
if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
- /* Trig the transfer by re-writing address or instruction register */
- if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
- {
- WRITE_REG(hospi->Instance->AR, addr_reg);
- }
- else
- {
- if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
- WRITE_REG(hospi->Instance->IR, ir_reg);
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ WRITE_REG(hospi->Instance->IR, ir_reg);
+ }
}
- }
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -2332,7 +2329,7 @@
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
else
@@ -2572,9 +2569,9 @@
(cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
- if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) &&
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) &&
(cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
- (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
+ (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
/* Multiplexing should be performed */
@@ -2620,12 +2617,12 @@
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
}
else
@@ -2635,12 +2632,12 @@
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
}
else
@@ -2650,23 +2647,23 @@
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
(OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
if (cfg->DQSPort != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
(OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
}
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
@@ -2677,13 +2674,13 @@
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
}
@@ -2861,7 +2858,7 @@
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *ccr_reg;
__IO uint32_t *tcr_reg;
- __IO uint32_t *ir_reg;
+ __IO uint32_t *ir_reg;
__IO uint32_t *abr_reg;
/* Re-initialize the value of the functional mode */
@@ -3040,7 +3037,7 @@
static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t reg;
+ uint32_t reg;
uint32_t value = 0U;
uint32_t index;
@@ -3062,7 +3059,7 @@
{
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
{
- value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
+ value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
| OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
}
else
@@ -3165,5 +3162,3 @@
*/
#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_otfdec.c b/Src/stm32h7xx_hal_otfdec.c
index 2b3fd1b..f54567b 100644
--- a/Src/stm32h7xx_hal_otfdec.c
+++ b/Src/stm32h7xx_hal_otfdec.c
@@ -9,6 +9,17 @@
* + Region setting/enable functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -58,11 +69,11 @@
The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_OTFDEC_RegisterCallback()
+ Use Functions HAL_OTFDEC_RegisterCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
+ Function HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : OTFDEC error callback
(+) MspInitCallback : OTFDEC Msp Init callback
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
@@ -70,11 +81,11 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
+ Use function HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : OTFDEC error callback
@@ -82,27 +93,27 @@
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
[..]
- By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
+ By default, after the HAL_OTFDEC_Init() and when the state is HAL_OTFDEC_STATE_RESET
all callbacks are set to the corresponding weak functions:
- example @ref HAL_OTFDEC_ErrorCallback().
+ example HAL_OTFDEC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
+ reset to the legacy weak functions in the HAL_OTFDEC_Init()/ HAL_OTFDEC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/ HAL_OTFDEC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_OTFDEC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
+ in HAL_OTFDEC_STATE_READY or HAL_OTFDEC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
- or @ref HAL_OTFDEC_Init() function.
+ using HAL_OTFDEC_RegisterCallback() before calling HAL_OTFDEC_DeInit()
+ or HAL_OTFDEC_Init() function.
[..]
When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
@@ -110,18 +121,6 @@
are set to the corresponding weak functions.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32h7xx_hal_pcd.c b/Src/stm32h7xx_hal_pcd.c
index e577f40..1f9eae3 100644
--- a/Src/stm32h7xx_hal_pcd.c
+++ b/Src/stm32h7xx_hal_pcd.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -41,17 +52,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -224,7 +224,7 @@
hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY;
-
+
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
{
@@ -721,7 +721,8 @@
/**
* @brief Unregister the USB PCD Iso OUT incomplete Callback
- * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * USB PCD Iso OUT incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -795,7 +796,8 @@
/**
* @brief Unregister the USB PCD Iso IN incomplete Callback
- * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * USB PCD Iso IN incomplete Callback is redirected
+ * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -1053,9 +1055,13 @@
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t i, ep_intr, epint, epnum;
- uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
+ uint32_t i;
+ uint32_t ep_intr;
+ uint32_t epint;
+ uint32_t epnum;
+ uint32_t fifoemptymsk;
+ uint32_t temp;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -1101,6 +1107,7 @@
{
/* ... */
}
+
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
@@ -1204,6 +1211,7 @@
}
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
{
+ (void)USB_FlushTxFifo(USBx, epnum);
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
}
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
@@ -1294,7 +1302,6 @@
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
- USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
@@ -1925,6 +1932,32 @@
}
/**
+ * @brief Abort an USB EP transaction.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ HAL_StatusTypeDef ret;
+ PCD_EPTypeDef *ep;
+
+ if ((0x80U & ep_addr) == 0x80U)
+ {
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ }
+
+ /* Stop Xfer */
+ ret = USB_EPStopXfer(hpcd->Instance, ep);
+
+ return ret;
+}
+
+/**
* @brief Flush an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
@@ -1998,6 +2031,33 @@
}
/**
+ * @brief Set the USB Device high speed test mode.
+ * @param hpcd PCD handle
+ * @param address test mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ switch (testmode)
+ {
+ case TEST_J:
+ case TEST_K:
+ case TEST_SE0_NAK:
+ case TEST_PACKET:
+ case TEST_FORCE_EN:
+ USBx_DEVICE->DCTL |= testmode << 4;
+ break;
+
+ default:
+ break;
+ }
+
+ return HAL_OK;
+}
+/**
* @}
*/
@@ -2224,5 +2284,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_pcd_ex.c b/Src/stm32h7xx_hal_pcd_ex.c
index 5debbe0..34f25ff 100644
--- a/Src/stm32h7xx_hal_pcd_ex.c
+++ b/Src/stm32h7xx_hal_pcd_ex.c
@@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -164,7 +163,7 @@
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
- /* Wait Detect flag or a timeout is happen*/
+ /* Wait Detect flag or a timeout is happen */
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
{
/* Check for the Timeout */
@@ -344,5 +343,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_pssi.c b/Src/stm32h7xx_hal_pssi.c
index 19f0a69..44cd6b7 100644
--- a/Src/stm32h7xx_hal_pssi.c
+++ b/Src/stm32h7xx_hal_pssi.c
@@ -9,6 +9,17 @@
* + IO operation functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,7 +30,7 @@
(#) Declare a PSSI_HandleTypeDef handle structure, for example:
PSSI_HandleTypeDef hpssi;
- (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API:
+ (#) Initialize the PSSI low level resources by implementing the HAL_PSSI_MspInit() API:
(##) Enable the PSSIx interface clock
(##) PSSI pins configuration
(+++) Enable the clock for the PSSI GPIOs
@@ -39,8 +50,8 @@
(#) Configure the Communication Bus Width, Control Signals, Input Polarity and Output Polarity
in the hpssi Init structure.
- (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
+ (#) Initialize the PSSI registers by calling the HAL_PSSI_Init(), configure also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_PSSI_MspInit(&hpssi) API.
(#) For PSSI IO operations, two operation modes are available within this driver :
@@ -48,44 +59,44 @@
*** Polling mode IO operation ***
=================================
[..]
- (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit()
- (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive()
+ (+) Transmit an amount of data by byte in blocking mode using HAL_PSSI_Transmit()
+ (+) Receive an amount of data by byte in blocking mode using HAL_PSSI_Receive()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit an amount of data in non-blocking mode (DMA) using
- @ref HAL_PSSI_Transmit_DMA()
- (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback()
+ HAL_PSSI_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_PSSI_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_PSSI_TxCpltCallback()
(+) Receive an amount of data in non-blocking mode (DMA) using
- @ref HAL_PSSI_Receive_DMA()
- (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback()
- (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback()
- (+) Abort a PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT()
- (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback()
+ HAL_PSSI_Receive_DMA()
+ (+) At reception end of transfer, HAL_PSSI_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_PSSI_RxCpltCallback()
+ (+) In case of transfer Error, HAL_PSSI_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_PSSI_ErrorCallback()
+ (+) Abort a PSSI process communication with Interrupt using HAL_PSSI_Abort_IT()
+ (+) End of abort process, HAL_PSSI_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_PSSI_AbortCpltCallback()
*** PSSI HAL driver macros list ***
==================================
[..]
Below the list of most used macros in PSSI HAL driver.
- (+) @ref HAL_PSSI_ENABLE : Enable the PSSI peripheral
- (+) @ref HAL_PSSI_DISABLE : Disable the PSSI peripheral
- (+) @ref HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not
- (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag
- (+) @ref HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt
- (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt
+ (+) HAL_PSSI_ENABLE : Enable the PSSI peripheral
+ (+) HAL_PSSI_DISABLE : Disable the PSSI peripheral
+ (+) HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not
+ (+) HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag
+ (+) HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt
+ (+) HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt
*** Callback registration ***
=============================================
- Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback()
+ Use Functions HAL_PSSI_RegisterCallback() or HAL_PSSI_RegisterAddrCallback()
to register an interrupt callback.
- Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks:
+ Function HAL_PSSI_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : callback for transmission end of transfer.
(+) RxCpltCallback : callback for reception end of transfer.
(+) ErrorCallback : callback for error detection.
@@ -96,9 +107,9 @@
and a pointer to the user callback function.
- Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default
+ Use function HAL_PSSI_UnRegisterCallback to reset a callback to the default
weak function.
- @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : callback for transmission end of transfer.
@@ -109,22 +120,22 @@
(+) MspDeInitCallback : callback for Msp DeInit.
- By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET
+ By default, after the HAL_PSSI_Init() and when the state is HAL_PSSI_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback().
+ examples HAL_PSSI_TxCpltCallback(), HAL_PSSI_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when
+ reset to the legacy weak functions in the HAL_PSSI_Init()/ HAL_PSSI_DeInit() only when
these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_PSSI_Init()/ HAL_PSSI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
- Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_PSSI_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state,
+ in HAL_PSSI_STATE_READY or HAL_PSSI_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit()
- or @ref HAL_PSSI_Init() function.
+ using HAL_PSSI_RegisterCallback() before calling HAL_PSSI_DeInit()
+ or HAL_PSSI_Init() function.
[..]
@@ -132,17 +143,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1794,5 +1794,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_pwr.c b/Src/stm32h7xx_hal_pwr.c
index 0de6bb2..aeb9933 100644
--- a/Src/stm32h7xx_hal_pwr.c
+++ b/Src/stm32h7xx_hal_pwr.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions.
* + Peripheral Control functions.
* + Interrupt Handling functions.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### PWR peripheral overview #####
@@ -129,18 +140,6 @@
(+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -872,4 +871,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_pwr_ex.c b/Src/stm32h7xx_hal_pwr_ex.c
index aaa5809..5d51ceb 100644
--- a/Src/stm32h7xx_hal_pwr_ex.c
+++ b/Src/stm32h7xx_hal_pwr_ex.c
@@ -6,6 +6,17 @@
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
* + Peripheral Extended features functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -136,18 +147,6 @@
AVD interrupt request.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2141,4 +2140,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_qspi.c b/Src/stm32h7xx_hal_qspi.c
index 1221496..0a7dfa4 100644
--- a/Src/stm32h7xx_hal_qspi.c
+++ b/Src/stm32h7xx_hal_qspi.c
@@ -14,6 +14,17 @@
* + Errors management and abort functionality
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -93,16 +104,16 @@
(#) Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_QSPI_MspInit() function :
(++) MDMA settings for write operation :
(+) The DestinationInc should be MDMA_DEST_INC_DISABLE
- (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
- (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
- aligned with @ref MDMA_Source_increment_mode .
- (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ (+) The SourceInc must be a value of MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
+ (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
+ aligned with MDMA_Source_increment_mode .
+ (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
(++) MDMA settings for read operation :
(+) The SourceInc should be MDMA_SRC_INC_DISABLE
- (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
- (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
- (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
- aligned with @ref MDMA_Destination_increment_mode.
+ (+) The DestinationInc must be a value of MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
+ (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
+ (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ aligned with MDMA_Destination_increment_mode.
(++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
(#)In case of wrong MDMA setting
(++) For write operation :
@@ -132,7 +143,7 @@
=================================================
[..]
(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
+ (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
flushes the fifo :
(++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
@@ -154,7 +165,7 @@
The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
+ Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
@@ -169,7 +180,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
@@ -183,12 +194,12 @@
(+) MspDeInitCallback : QSPI MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
+ By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
- and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
+ and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -196,8 +207,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
- or @ref HAL_QSPI_Init function.
+ using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
+ or HAL_QSPI_Init function.
When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -211,17 +222,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -300,7 +300,7 @@
/**
* @brief Initialize the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and initialize the associated handle.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@@ -394,7 +394,7 @@
/**
* @brief De-Initialize the QSPI peripheral.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -432,7 +432,7 @@
/**
* @brief Initialize the QSPI MSP.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@@ -447,7 +447,7 @@
/**
* @brief DeInitialize the QSPI MSP.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@@ -486,7 +486,7 @@
/**
* @brief Handle QSPI interrupt request.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@@ -775,9 +775,9 @@
/**
* @brief Set the command configuration.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @param cmd : structure that contains the command configuration information
- * @param Timeout : Timeout duration
+ * @param Timeout Timeout duration
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -865,8 +865,8 @@
/**
* @brief Set the command configuration in interrupt mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -964,11 +964,10 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @param Timeout : Timeout duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Timeout duration
* @note This function is used only in Indirect Write Mode
-
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
@@ -1048,9 +1047,9 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
- * @param Timeout : Timeout duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1134,8 +1133,8 @@
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1194,8 +1193,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1258,8 +1257,8 @@
/**
* @brief Send an amount of data in non-blocking mode with DMA.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1371,8 +1370,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hqspi : QSPI handle
- * @param pData : pointer to data buffer.
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1486,10 +1485,10 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the polling configuration information.
- * @param Timeout : Timeout duration
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
+ * @param Timeout Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1587,9 +1586,9 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the polling configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1691,9 +1690,9 @@
/**
* @brief Configure the Memory Mapped mode.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information.
- * @param cfg : structure that contains the memory mapped configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@@ -1780,7 +1779,7 @@
/**
* @brief Transfer Error callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@@ -1795,7 +1794,7 @@
/**
* @brief Abort completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1810,7 +1809,7 @@
/**
* @brief Command completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1825,7 +1824,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1840,7 +1839,7 @@
/**
* @brief Tx Transfer completed callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1856,7 +1855,7 @@
/**
* @brief FIFO Threshold callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@@ -1871,7 +1870,7 @@
/**
* @brief Status Match callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@@ -1886,7 +1885,7 @@
/**
* @brief Timeout callback.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@@ -1902,8 +1901,8 @@
/**
* @brief Register a User QSPI Callback
* To be used instead of the weak (surcharged) predefined callback
- * @param hqspi : QSPI handle
- * @param CallbackId : ID of the callback to be registered
+ * @param hqspi QSPI handle
+ * @param CallbackId ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
* @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
@@ -1915,7 +1914,7 @@
* @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
* @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
* @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
- * @param pCallback : pointer to the Callback function
+ * @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
@@ -2008,8 +2007,8 @@
/**
* @brief Unregister a User QSPI Callback
* QSPI Callback is redirected to the weak (surcharged) predefined callback
- * @param hqspi : QSPI handle
- * @param CallbackId : ID of the callback to be unregistered
+ * @param hqspi QSPI handle
+ * @param CallbackId ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
* @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
@@ -2128,7 +2127,7 @@
/**
* @brief Return the QSPI handle state.
- * @param hqspi : QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -2139,7 +2138,7 @@
/**
* @brief Return the QSPI error code.
-* @param hqspi : QSPI handle
+* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -2149,7 +2148,7 @@
/**
* @brief Abort the current transmission.
-* @param hqspi : QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@@ -2206,7 +2205,7 @@
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi : QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@@ -2262,8 +2261,8 @@
}
/** @brief Set QSPI timeout.
- * @param hqspi : QSPI handle.
- * @param Timeout : Timeout for the QSPI memory access.
+ * @param hqspi QSPI handle.
+ * @param Timeout Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2272,8 +2271,8 @@
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi : QSPI handle.
- * @param Threshold : Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi QSPI handle.
+ * @param Threshold Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2305,7 +2304,7 @@
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi : QSPI handle.
+ * @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@@ -2314,8 +2313,8 @@
}
/** @brief Set FlashID.
- * @param hqspi : QSPI handle.
- * @param FlashID : Index of the flash memory to be accessed.
+ * @param hqspi QSPI handle.
+ * @param FlashID Index of the flash memory to be accessed.
* This parameter can be a value of @ref QSPI_Flash_Select.
* @note The FlashID is ignored when dual flash mode is enabled.
* @retval HAL status
@@ -2364,7 +2363,7 @@
/**
* @brief DMA QSPI receive process complete callback.
- * @param hmdma : MDMA handle
+ * @param hmdma MDMA handle
* @retval None
*/
static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
@@ -2378,7 +2377,7 @@
/**
* @brief DMA QSPI transmit process complete callback.
- * @param hmdma : MDMA handle
+ * @param hmdma MDMA handle
* @retval None
*/
static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
@@ -2392,7 +2391,7 @@
/**
* @brief DMA QSPI communication error callback.
- * @param hmdma : MDMA handle
+ * @param hmdma MDMA handle
* @retval None
*/
static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
@@ -2414,7 +2413,7 @@
/**
* @brief MDMA QSPI abort complete callback.
- * @param hmdma : MDMA handle
+ * @param hmdma MDMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
@@ -2453,11 +2452,11 @@
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi : QSPI handle
- * @param Flag : Flag checked
- * @param State : Value of the flag expected
- * @param Tickstart : Tick start value
- * @param Timeout : Duration of the timeout
+ * @param hqspi QSPI handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Tickstart Tick start value
+ * @param Timeout Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@@ -2483,9 +2482,9 @@
/**
* @brief Configure the communication registers.
- * @param hqspi : QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @param FunctionalMode : functional mode to configured
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param FunctionalMode functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@@ -2649,5 +2648,3 @@
*/
#endif /* defined(QUADSPI) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_ramecc.c b/Src/stm32h7xx_hal_ramecc.c
index 54491f9..628f8f0 100644
--- a/Src/stm32h7xx_hal_ramecc.c
+++ b/Src/stm32h7xx_hal_ramecc.c
@@ -9,6 +9,17 @@
* + Monitoring operation functions
* + Error information functions
* + State and error functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -17,7 +28,7 @@
(#) Enable and latch error information through HAL_RAMECC_Init().
(#) For a given Monitor, enable and disable interrupt through
- HAL_RAMECC_EnableNotifiaction().
+ HAL_RAMECC_EnableNotification().
To enable a notification for a given RAMECC instance, use global
interrupts.
To enable a notification for only RAMECC monitor, use monitor interrupts.
@@ -33,11 +44,12 @@
*** Interrupt mode ***
======================
[..]
- (+) Use HAL_RAMECC_EnableNotifiaction() to enable interrupts for a
+ (+) Use HAL_RAMECC_EnableNotification() to enable interrupts for a
given error.
(+) Configure the RAMECC interrupt priority using
HAL_NVIC_SetPriority().
(+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ().
+ (+) Start RAMECC latch failing information using HAL_RAMECC_StartMonitor().
*** Failing information ***
======================
@@ -69,18 +81,6 @@
(+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected
flag.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -689,4 +689,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_rcc.c b/Src/stm32h7xx_hal_rcc.c
index b5e93c7..c95945d 100644
--- a/Src/stm32h7xx_hal_rcc.c
+++ b/Src/stm32h7xx_hal_rcc.c
@@ -54,14 +54,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -486,9 +484,23 @@
{
return HAL_ERROR;
}
- /* Otherwise, just the calibration is allowed */
+ /* Otherwise, only HSI division and calibration are allowed */
else
{
+ /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
+ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ {
+ if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
@@ -1779,4 +1791,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_rcc_ex.c b/Src/stm32h7xx_hal_rcc_ex.c
index afde46b..2b8800e 100644
--- a/Src/stm32h7xx_hal_rcc_ex.c
+++ b/Src/stm32h7xx_hal_rcc_ex.c
@@ -10,14 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -3757,4 +3755,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_rng.c b/Src/stm32h7xx_hal_rng.c
index ff1cf10..2ec0554 100644
--- a/Src/stm32h7xx_hal_rng.c
+++ b/Src/stm32h7xx_hal_rng.c
@@ -9,6 +9,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -31,8 +42,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
- Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_RNG_RegisterCallback() to register a user callback.
+ Function HAL_RNG_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : RNG Error Callback.
(+) MspInitCallback : RNG MspInit.
(+) MspDeInitCallback : RNG MspDeInit.
@@ -40,9 +51,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : RNG Error Callback.
@@ -51,16 +62,16 @@
[..]
For specific callback ReadyDataCallback, use dedicated register callbacks:
- respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+ respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
[..]
- By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+ By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- example @ref HAL_RNG_ErrorCallback().
+ example HAL_RNG_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
- and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
+ and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -69,8 +80,8 @@
in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
- or @ref HAL_RNG_Init() function.
+ using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
+ or HAL_RNG_Init() function.
[..]
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
@@ -79,17 +90,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -232,9 +232,13 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
#else
@@ -258,9 +262,13 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_ERROR;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
@@ -307,11 +315,15 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+ return HAL_ERROR;
+ }
}
}
@@ -683,11 +695,15 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+ return HAL_ERROR;
+ }
}
}
@@ -1004,8 +1020,7 @@
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
+ } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
@@ -1033,8 +1048,7 @@
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
return HAL_ERROR;
}
- }
- while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
+ } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
}
/* Update the error code */
hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED;
@@ -1058,4 +1072,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_rng_ex.c b/Src/stm32h7xx_hal_rng_ex.c
index 4377a04..a063df7 100644
--- a/Src/stm32h7xx_hal_rng_ex.c
+++ b/Src/stm32h7xx_hal_rng_ex.c
@@ -11,13 +11,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -31,7 +30,7 @@
#if defined(RNG)
-/** @addtogroup RNGEx
+/** @addtogroup RNG_Ex
* @brief RNG Extended HAL module driver.
* @{
*/
@@ -40,7 +39,7 @@
#if defined(RNG_CR_CONDRST)
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Defines RNGEx Private Defines
+/** @defgroup RNG_Ex_Private_Defines RNGEx Private Defines
* @{
*/
/* Health test control register information to use in CCM algorithm */
@@ -55,7 +54,7 @@
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+/** @defgroup RNG_Ex_Private_Constants RNGEx Private Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
@@ -67,11 +66,11 @@
/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RNGEx_Exported_Functions
+/** @addtogroup RNG_Ex_Exported_Functions
* @{
*/
-/** @addtogroup RNGEx_Exported_Functions_Group1
+/** @addtogroup RNG_Ex_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
@@ -156,9 +155,13 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of prememption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
@@ -280,7 +283,7 @@
* @}
*/
-/** @addtogroup RNGEx_Exported_Functions_Group2
+/** @addtogroup RNG_Ex_Exported_Functions_Group2
* @brief Recover from seed error function
*
@verbatim
@@ -348,4 +351,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_rtc.c b/Src/stm32h7xx_hal_rtc.c
index b158d38..4673873 100644
--- a/Src/stm32h7xx_hal_rtc.c
+++ b/Src/stm32h7xx_hal_rtc.c
@@ -15,6 +15,17 @@
* + RTC Tamper and TimeStamp Pins Selection
* + Interrupts and flags management
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### RTC Operating Condition #####
@@ -93,9 +104,9 @@
The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+ Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
- Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+ Function HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback.
(+) TimeStampEventCallback : RTC TimeStamp Event callback.
@@ -108,9 +119,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
@@ -123,13 +134,13 @@
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
- By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+ By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions :
- examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
+ examples AlarmAEventCallback(), WakeUpTimerEventCallback().
Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
- in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+ in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
(not registered beforehand).
- If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+ If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
@@ -137,26 +148,14 @@
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
- or @ref HAL_RTC_Init() function.
+ using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
+ or HAL_RTC_Init() function.
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -393,10 +392,10 @@
/* Wait till WUTWF flag is set and if Time out is reached exit */
#if defined(RTC_ICSR_WUTWF)
- while (((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U)
+ while ((((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) && (status != HAL_TIMEOUT))
#endif /* RTC_ICSR_WUTWF */
#if defined(RTC_ISR_WUTWF)
- while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U)
+ while ((((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U) && (status != HAL_TIMEOUT))
#endif /* RTC_ISR_WUTWF */
{
if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
@@ -406,6 +405,7 @@
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
}
}
@@ -1495,8 +1495,17 @@
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
}
-#if !defined(DUAL_CORE)
/* RTC Alarm Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)
+ {
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+ }
+ else
+ {
+ __HAL_RTC_ALARM_EXTID2_ENABLE_IT();
+ }
+#else /* SINGLE_CORE */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
#endif
@@ -1950,7 +1959,7 @@
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
- while ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
+ while (((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
{
if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -1968,7 +1977,7 @@
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
- while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
+ while (((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
{
if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -2072,4 +2081,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_rtc_ex.c b/Src/stm32h7xx_hal_rtc_ex.c
index e1a0d3a..ba820c6 100644
--- a/Src/stm32h7xx_hal_rtc_ex.c
+++ b/Src/stm32h7xx_hal_rtc_ex.c
@@ -11,6 +11,17 @@
* + Extended Control functions
* + Extended RTC features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -86,18 +97,6 @@
function.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -251,10 +250,19 @@
/* Enable IT timestamp */
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
-#if !defined(DUAL_CORE)
/* RTC timestamp Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)
+ {
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+ }
+ else
+ {
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT();
+ }
+#else /* SINGLE_CORE */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-#endif
+#endif /* DUAL_CORE */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -912,10 +920,19 @@
/* Copy desired configuration into configuration register */
hrtc->Instance->TAMPCR = tmpreg;
-#if !defined(DUAL_CORE)
/* RTC Tamper Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)
+ {
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+ }
+ else
+ {
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT();
+ }
+#else /* SINGLE_CORE */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-#endif
+#endif /* DUAL_CORE */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@@ -1315,7 +1332,7 @@
hrtc->TimeStampEventCallback(hrtc);
#else
HAL_RTCEx_TimeStampEventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Not immediately clear flags because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/
hrtc->Instance->SCR = RTC_SCR_CTSF;
}
@@ -1336,7 +1353,7 @@
#else
/* Tamper1 callback */
HAL_RTCEx_Tamper1EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_TAMP1E */
@@ -1350,7 +1367,7 @@
#else
/* Tamper2 callback */
HAL_RTCEx_Tamper2EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_TAMP2E */
@@ -1364,7 +1381,7 @@
#else
/* Tamper3 callback */
HAL_RTCEx_Tamper3EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_TAMP3E */
@@ -1378,7 +1395,7 @@
#else
/* Call Internal Tamper Event by-default callback */
HAL_RTCEx_InternalTamper1EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_ITAMP1E */
@@ -1392,7 +1409,7 @@
#else
/* Call Internal Tamper Event by-default callback */
HAL_RTCEx_InternalTamper2EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_ITAMP2E */
@@ -1406,7 +1423,7 @@
#else
/* Call Internal Tamper Event by-default callback */
HAL_RTCEx_InternalTamper3EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_ITAMP3E */
@@ -1420,7 +1437,7 @@
#else
/* Call Internal Tamper Event by-default callback */
HAL_RTCEx_InternalTamper4EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_ITAMP4E */
@@ -1434,7 +1451,7 @@
#else
/* Call Internal Tamper Event by-default callback */
HAL_RTCEx_InternalTamper5EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_ITAMP5E */
@@ -1448,7 +1465,7 @@
#else
/* Call Internal Tamper Event by-default callback */
HAL_RTCEx_InternalTamper6EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_ITAMP6E */
@@ -1462,7 +1479,7 @@
#else
/* Call Internal Tamper Event by-default callback */
HAL_RTCEx_InternalTamper8EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
#endif /* TAMP_CR1_ITAMP8E */
@@ -1483,7 +1500,7 @@
{
__HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG();
}
-#else /* SINGLE_CORE */
+#else /* SINGLE_CORE */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
#endif /* DUAL_CORE */
@@ -2118,10 +2135,19 @@
hrtc->Instance->CR = CR_tmp;
}
-#if !defined(DUAL_CORE)
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)
+ {
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+ }
+ else
+ {
+ __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_IT();
+ }
+#else /* SINGLE_CORE */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-#endif
+#endif /* DUAL_CORE */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
@@ -2227,7 +2253,7 @@
{
__HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG();
}
-#else /* SINGLE_CORE */
+#else /* SINGLE_CORE */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
#endif /* DUAL_CORE */
@@ -2959,4 +2985,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_sai.c b/Src/stm32h7xx_hal_sai.c
index fefb011..42d7dd4 100644
--- a/Src/stm32h7xx_hal_sai.c
+++ b/Src/stm32h7xx_hal_sai.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -199,18 +210,6 @@
and weak (surcharged) callbacks are used.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -2943,4 +2942,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_sai_ex.c b/Src/stm32h7xx_hal_sai_ex.c
index 2af598f..0567c04 100644
--- a/Src/stm32h7xx_hal_sai_ex.c
+++ b/Src/stm32h7xx_hal_sai_ex.c
@@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -132,4 +131,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_sd.c b/Src/stm32h7xx_hal_sd.c
index 6bf4dcc..fc13c07 100644
--- a/Src/stm32h7xx_hal_sd.c
+++ b/Src/stm32h7xx_hal_sd.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -182,7 +193,7 @@
The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
+ Use Functions HAL_SD_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -197,9 +208,9 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
For specific callbacks TransceiverCallback use dedicated register callbacks:
- respectively @ref HAL_SD_RegisterTransceiverCallback().
+ respectively HAL_SD_RegisterTransceiverCallback().
- Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
@@ -213,14 +224,14 @@
(+) MspDeInitCallback : SD MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
For specific callbacks TransceiverCallback use dedicated unregister callbacks:
- respectively @ref HAL_SD_UnRegisterTransceiverCallback().
+ respectively HAL_SD_UnRegisterTransceiverCallback().
- By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+ By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
- and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+ and HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -228,8 +239,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
- or @ref HAL_SD_Init function.
+ using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+ or HAL_SD_Init function.
When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -237,17 +248,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -269,7 +269,7 @@
* @{
*/
/* Frequencies used in the driver for clock divider calculation */
-#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define SD_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */
#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */
/* Private macro -------------------------------------------------------------*/
@@ -398,7 +398,7 @@
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
- hsd->State = HAL_SD_STATE_BUSY;
+ hsd->State = HAL_SD_STATE_PROGRAMMING;
/* Initialize the Card parameters */
if (HAL_SD_InitCard(hsd) != HAL_OK)
@@ -470,7 +470,7 @@
{
uint32_t errorstate;
SD_InitTypeDef Init;
- uint32_t sdmmc_clk;
+ uint32_t sdmmc_clk = 0U;
/* Default SDMMC peripheral configuration for SD card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
@@ -2295,7 +2295,7 @@
}
/**
- * @brief Gets the SD status info.
+ * @brief Gets the SD status info.( shall be called if there is no SD transaction ongoing )
* @param hsd: Pointer to SD handle
* @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
* will contain the SD card status information
@@ -2307,6 +2307,11 @@
uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
+ if (hsd->State == HAL_SD_STATE_BUSY)
+ {
+ return HAL_ERROR;
+ }
+
errorstate = SD_SendSDStatus(hsd, sd_status);
if (errorstate != HAL_SD_ERROR_NONE)
{
@@ -2355,6 +2360,7 @@
status = HAL_ERROR;
}
+
return status;
}
@@ -2394,7 +2400,7 @@
{
SDMMC_InitTypeDef Init;
uint32_t errorstate;
- uint32_t sdmmc_clk;
+ uint32_t sdmmc_clk = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@@ -2476,7 +2482,7 @@
}
else
{
- if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+ if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
{
Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
}
@@ -2502,7 +2508,7 @@
}
else
{
- if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+ if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
{
Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
}
@@ -2926,7 +2932,8 @@
{
HAL_SD_CardCSDTypeDef CSD;
uint32_t errorstate;
- uint16_t sd_rca = 1U;
+ uint16_t sd_rca = 0U;
+ uint32_t tickstart = HAL_GetTick();
/* Check the power State */
if (SDMMC_GetPowerState(hsd->Instance) == 0U)
@@ -2957,10 +2964,17 @@
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
- errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
- if (errorstate != HAL_SD_ERROR_NONE)
+ while (sd_rca == 0U)
{
- return errorstate;
+ errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+ if (errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ if ((HAL_GetTick() - tickstart) >= SDMMC_CMDTIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
}
}
if (hsd->SdCard.CardType != CARD_SECURED)
@@ -3030,7 +3044,7 @@
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
- if (errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */
{
hsd->SdCard.CardVersion = CARD_V1_X;
/* CMD0: GO_IDLE_STATE */
@@ -3088,7 +3102,10 @@
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
- if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ /* Set default card type */
+ hsd->SdCard.CardType = CARD_SDSC;
+
+ if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY)
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
#if (USE_SD_TRANSCEIVER != 0U)
@@ -4028,5 +4045,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_sd_ex.c b/Src/stm32h7xx_hal_sd_ex.c
index 67124cb..1cc19e3 100644
--- a/Src/stm32h7xx_hal_sd_ex.c
+++ b/Src/stm32h7xx_hal_sd_ex.c
@@ -7,6 +7,17 @@
* functionalities of the Secure Digital (SD) peripheral:
* + Extended features functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,17 +30,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -311,9 +311,3 @@
/**
* @}
*/
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_sdram.c b/Src/stm32h7xx_hal_sdram.c
index 47c34a5..34c5cfb 100644
--- a/Src/stm32h7xx_hal_sdram.c
+++ b/Src/stm32h7xx_hal_sdram.c
@@ -6,6 +6,17 @@
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -63,25 +74,25 @@
The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback,
+ Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : SDRAM MspInit.
(+) MspDeInitCallback : SDRAM MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : SDRAM MspInit.
(+) MspDeInitCallback : SDRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
+ By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init
- and @ref HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
+ and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -89,8 +100,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit
- or @ref HAL_SDRAM_Init function.
+ using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
+ or HAL_SDRAM_Init function.
When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -98,17 +109,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1307,5 +1307,3 @@
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_smartcard.c b/Src/stm32h7xx_hal_smartcard.c
index 9004803..8d5e999 100644
--- a/Src/stm32h7xx_hal_smartcard.c
+++ b/Src/stm32h7xx_hal_smartcard.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -167,17 +178,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -809,11 +809,11 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
- uint8_t *ptmpdata = pData;
+ const uint8_t *ptmpdata = pData;
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -983,7 +983,7 @@
* @param Size amount of data to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -1141,7 +1141,7 @@
* @param Size amount of data to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -2422,43 +2422,43 @@
{
case SMARTCARD_CLOCKSOURCE_D2PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_D2PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PLL2Q:
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
- tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ tmpreg = (uint32_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PLL3Q:
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
- tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ tmpreg = (uint32_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
- tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) /
+ tmpreg = (uint32_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) /
SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
}
else
{
- tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
}
break;
case SMARTCARD_CLOCKSOURCE_CSI:
- tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ tmpreg = (uint32_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
- tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
(hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
default:
@@ -2469,7 +2469,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
- hsmartcard->Instance->BRR = tmpreg;
+ hsmartcard->Instance->BRR = (uint16_t)tmpreg;
}
else
{
@@ -2600,11 +2600,12 @@
}
/**
- * @brief Handle SMARTCARD Communication Timeout.
+ * @brief Handle SMARTCARD Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @param Flag Specifies the SMARTCARD flag to check.
- * @param Status The new Flag status (SET or RESET).
+ * @param Status The actual Flag status (SET or RESET).
* @param Tickstart Tick start value
* @param Timeout Timeout duration.
* @retval HAL status
@@ -3204,4 +3205,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_smartcard_ex.c b/Src/stm32h7xx_hal_smartcard_ex.c
index 35505d8..5c76a67 100644
--- a/Src/stm32h7xx_hal_smartcard_ex.c
+++ b/Src/stm32h7xx_hal_smartcard_ex.c
@@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
=============================================================================
##### SMARTCARD peripheral extended features #####
@@ -27,17 +38,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -493,4 +493,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_smbus.c b/Src/stm32h7xx_hal_smbus.c
index 3d0c843..0504c2a 100644
--- a/Src/stm32h7xx_hal_smbus.c
+++ b/Src/stm32h7xx_hal_smbus.c
@@ -10,6 +10,17 @@
* + IO operation functions
* + Peripheral State and Errors functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -20,7 +31,7 @@
(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
SMBUS_HandleTypeDef hsmbus;
- (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
+ (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
(##) Enable the SMBUSx interface clock
(##) SMBUS pins configuration
(+++) Enable the clock for the SMBUS GPIOs
@@ -33,69 +44,75 @@
Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
- (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
+ (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
(++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
+ by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
- (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
(#) For SMBUS IO operations, only one mode of operations is available within this driver
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
- (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
- (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
- (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
- (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
(++) The associated previous transfer callback is called at the end of abort process
- (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
- (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
(+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
- using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
- (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
- add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
- (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
- (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
- (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
- (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
- (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
- (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
- (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
- to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
- (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
- (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
- to check the Error Code using function @ref HAL_SMBUS_GetError()
+ using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
+ add their own code to check the Address Match Code and the transmission direction
+ request by master/host (Write/Read).
+ (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
+ using HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using
+ HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+ (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
+ add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function HAL_SMBUS_GetError()
*** SMBUS HAL driver macros list ***
==================================
[..]
Below the list of most used macros in SMBUS HAL driver.
- (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
- (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
- (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
- (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
- (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
- (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+ (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
+ Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+ Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
@@ -107,11 +124,11 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
- For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
+ For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
[..]
- Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+ Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function.
- @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
@@ -123,24 +140,24 @@
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
+ For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
[..]
- By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
+ examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
+ reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
these callbacks are null (not registered beforehand).
- If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
- or @ref HAL_SMBUS_Init() function.
+ using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
+ or HAL_SMBUS_Init() function.
[..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
@@ -150,18 +167,6 @@
(@) You can refer to the SMBUS HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -203,20 +208,28 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
- uint32_t Timeout);
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout);
-static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+/* Private functions for SMBUS transfer IRQ handler */
static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-
static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
- uint32_t Request);
+/* Private functions to centralize the enable/disable of Interrupts */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+
+/* Private function to flush TXDR register */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private function to handle start, restart or stop a transfer */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
+ uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
@@ -364,15 +377,20 @@
/*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
/* Configure SMBUSx: Dual mode and Own Address2 */
- hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
+ (hsmbus->Init.OwnAddress2Masks << 8U));
/*---------------------------- SMBUSx CR1 Configuration ------------------------*/
/* Configure SMBUSx: Generalcall and NoStretch mode */
- hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
+ hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
+ hsmbus->Init.AnalogFilter);
- /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
- if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
- && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled
+ and SMBUS Peripheral is set in Slave mode */
+ if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
+ ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
{
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
}
@@ -581,7 +599,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID,
pSMBUS_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -695,7 +714,8 @@
* @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+ HAL_SMBUS_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -790,7 +810,8 @@
* @param pCallback pointer to the Address Match Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+ pSMBUS_AddrCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -914,8 +935,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
@@ -955,7 +976,8 @@
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
- SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_GENERATE_START_WRITE);
}
else
{
@@ -965,9 +987,11 @@
/* Store current volatile XferOptions, misra rule */
tmp = hsmbus->XferOptions;
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -976,7 +1000,9 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ hsmbus->XferOptions,
+ SMBUS_GENERATE_START_WRITE);
}
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
@@ -1057,7 +1083,8 @@
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
- SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_GENERATE_START_READ);
}
else
{
@@ -1067,9 +1094,11 @@
/* Store current volatile XferOptions, Misra rule */
tmp = hsmbus->XferOptions;
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
+ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -1078,7 +1107,9 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ hsmbus->XferOptions,
+ SMBUS_GENERATE_START_READ);
}
}
@@ -1222,12 +1253,14 @@
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
- SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
@@ -1313,7 +1346,8 @@
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
{
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
}
else
{
@@ -1576,7 +1610,8 @@
uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+ SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
@@ -1600,7 +1635,8 @@
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+ SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
(SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
@@ -1720,7 +1756,8 @@
* @param AddrMatchCode Address Match Code
* @retval None
*/
-__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+ uint16_t AddrMatchCode)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
@@ -1842,6 +1879,9 @@
/* No need to generate STOP, it is automatically done */
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -1967,13 +2007,15 @@
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
- (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
@@ -2130,6 +2172,9 @@
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
}
@@ -2151,6 +2196,9 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -2225,7 +2273,9 @@
else
{
/* Set Reload for next Bytes */
- SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+ SMBUS_NO_STARTSTOP);
/* Ack last Byte Read */
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -2237,14 +2287,16 @@
{
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+ SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
@@ -2489,7 +2541,8 @@
uint32_t tmperror;
/* SMBUS Bus error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
@@ -2498,7 +2551,8 @@
}
/* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
@@ -2507,7 +2561,8 @@
}
/* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
@@ -2516,7 +2571,8 @@
}
/* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
@@ -2525,7 +2581,8 @@
}
/* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
@@ -2534,7 +2591,8 @@
}
/* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+ if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
+ ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
@@ -2542,7 +2600,10 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Store current volatile hsmbus->State, misra rule */
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+
+ /* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
/* Call the Error Callback in case of Error detected */
@@ -2582,8 +2643,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
- uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2613,6 +2674,27 @@
}
/**
+ * @brief SMBUS Tx data register flush process.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ hsmbus->Instance->TXDR = 0x00U;
+ }
+
+ /* Flush TX register if not empty */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET)
+ {
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE);
+ }
+}
+
+/**
* @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
* @param hsmbus SMBUS handle.
* @param DevAddress specifies the slave address to be programmed.
@@ -2632,8 +2714,8 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
- uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size,
+ uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2644,9 +2726,10 @@
MODIFY_REG(hsmbus->Instance->CR2,
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
- I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -2703,5 +2786,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_spdifrx.c b/Src/stm32h7xx_hal_spdifrx.c
index e0536b6..68f8ae2 100644
--- a/Src/stm32h7xx_hal_spdifrx.c
+++ b/Src/stm32h7xx_hal_spdifrx.c
@@ -8,6 +8,18 @@
* + Data transfers functions
* + DMA transfers management
* + Interrupts and flags management
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -142,18 +154,6 @@
are set to the corresponding weak functions.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1631,5 +1631,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_spi.c b/Src/stm32h7xx_hal_spi.c
index 95f6c25..55ff09b 100644
--- a/Src/stm32h7xx_hal_spi.c
+++ b/Src/stm32h7xx_hal_spi.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -34,7 +45,8 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+ or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -113,18 +125,6 @@
Those functions are maintained for backward compatibility reasons.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -190,8 +190,8 @@
*/
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -234,11 +234,7 @@
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
-#if (USE_SPI_CRC != 0UL)
uint32_t crc_length;
-#else
- uint32_t crc_length = 0UL;
-#endif
uint32_t packet_length;
/* Check the SPI handle allocation */
@@ -267,8 +263,8 @@
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
}
@@ -355,13 +351,20 @@
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
+#if (USE_SPI_CRC == 0)
+ /* Keep the default value of CRCSIZE in case of CRC is not used */
+ crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE;
+#endif /* USE_SPI_CRC */
+
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit, CRC calculation state, CRC Length */
/* SPIx NSS Software Management Configuration */
- if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
- ((hspi->Init.Mode == SPI_MODE_SLAVE) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
+ if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \
+ (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
+ ((hspi->Init.Mode == SPI_MODE_SLAVE) && \
+ (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
}
@@ -371,10 +374,12 @@
hspi->Init.FifoThreshold | hspi->Init.DataSize));
/* SPIx CFG2 Configuration */
- WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | hspi->Init.NSSPolarity |
- hspi->Init.NSS | hspi->Init.CLKPolarity | hspi->Init.CLKPhase |
- hspi->Init.FirstBit | hspi->Init.Mode | hspi->Init.MasterInterDataIdleness |
- hspi->Init.Direction | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
+ WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode |
+ hspi->Init.NSSPolarity | hspi->Init.NSS |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase |
+ hspi->Init.FirstBit | hspi->Init.Mode |
+ hspi->Init.MasterInterDataIdleness | hspi->Init.Direction |
+ hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
#if (USE_SPI_CRC != 0UL)
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
@@ -423,7 +428,7 @@
/* Set Default Underrun configuration */
#if (USE_SPI_CRC != 0UL)
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE)
-#endif
+#endif /* USE_SPI_CRC */
{
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
}
@@ -534,7 +539,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -545,7 +551,7 @@
return HAL_ERROR;
}
- /* Process locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
if (HAL_SPI_STATE_READY == hspi->State)
@@ -648,7 +654,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
if (HAL_SPI_STATE_READY == hspi->State)
@@ -744,8 +750,8 @@
*/
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -797,7 +803,7 @@
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
- /* Process Locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
/* Init tickstart for timeout management*/
@@ -870,12 +876,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -914,12 +920,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -963,12 +969,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -983,7 +989,7 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
hspi->State = HAL_SPI_STATE_READY;
@@ -1022,7 +1028,7 @@
return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
- /* Process Locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
/* Init tickstart for timeout management*/
@@ -1095,12 +1101,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -1139,12 +1145,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -1189,12 +1195,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -1214,7 +1220,7 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
hspi->State = HAL_SPI_STATE_READY;
@@ -1254,7 +1260,7 @@
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process Locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
/* Init tickstart for timeout management*/
@@ -1266,7 +1272,9 @@
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && \
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
__HAL_UNLOCK(hspi);
@@ -1339,12 +1347,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -1405,12 +1413,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -1485,12 +1493,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
}
}
@@ -1504,7 +1512,7 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
hspi->State = HAL_SPI_STATE_READY;
@@ -1531,7 +1539,7 @@
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
- /* Process Locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
if ((pData == NULL) || (Size == 0UL))
@@ -1622,7 +1630,7 @@
return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
}
- /* Process Locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
if (hspi->State != HAL_SPI_STATE_READY)
@@ -1691,7 +1699,7 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1711,15 +1719,17 @@
HAL_StatusTypeDef errorcode = HAL_OK;
uint32_t max_fifo_length = 0UL;
uint32_t tmp_TxXferCount;
- #if defined (__GNUC__)
+
+#if defined (__GNUC__)
__IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
- #endif /* __GNUC__ */
+#endif /* __GNUC__ */
+
uint32_t tmp_mode;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
/* Init temporary variables */
@@ -1727,7 +1737,9 @@
tmp_mode = hspi->Init.Mode;
if (!((tmp_state == HAL_SPI_STATE_READY) || \
- ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ ((tmp_mode == SPI_MODE_MASTER) && \
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
__HAL_UNLOCK(hspi);
@@ -1755,7 +1767,7 @@
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- tmp_TxXferCount = hspi->TxXferCount;
+ tmp_TxXferCount = hspi->TxXferCount;
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
@@ -1856,15 +1868,16 @@
}
/* Enable EOT, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR |
+ SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
if (hspi->Init.Mode == SPI_MODE_MASTER)
{
- /* Master transfer start */
+ /* Start Master transfer */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1933,7 +1946,7 @@
__HAL_UNLOCK(hspi);
return errorcode;
}
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
#if defined(USE_SPI_RELOAD_TRANSFER)
/**
@@ -1999,7 +2012,7 @@
__HAL_UNLOCK(hspi);
return errorcode;
}
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
#if defined(USE_SPI_RELOAD_TRANSFER)
/**
@@ -2068,7 +2081,7 @@
__HAL_UNLOCK(hspi);
return errorcode;
}
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
@@ -2085,7 +2098,7 @@
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
- /* Process Locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
if (hspi->State != HAL_SPI_STATE_READY)
@@ -2173,12 +2186,17 @@
CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
/* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+ hspi->TxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
return errorcode;
}
@@ -2207,7 +2225,7 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -2235,7 +2253,7 @@
return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
- /* Process Locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
if (hspi->State != HAL_SPI_STATE_READY)
@@ -2322,12 +2340,17 @@
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
return errorcode;
}
@@ -2356,7 +2379,7 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -2382,14 +2405,17 @@
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Process locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
/* Init temporary variables */
tmp_state = hspi->State;
tmp_mode = hspi->Init.Mode;
- if (!(((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)) || (tmp_state == HAL_SPI_STATE_READY)))
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && \
+ (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \
+ (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
__HAL_UNLOCK(hspi);
@@ -2432,7 +2458,7 @@
{
/* Restriction the DMA data received is not allowed in this mode */
errorcode = HAL_ERROR;
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -2494,12 +2520,17 @@
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
return errorcode;
}
@@ -2514,12 +2545,17 @@
hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */
- if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+ hspi->TxXferCount))
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- errorcode = HAL_ERROR;
+
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
hspi->State = HAL_SPI_STATE_READY;
+ errorcode = HAL_ERROR;
return errorcode;
}
@@ -2547,7 +2583,7 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -2564,14 +2600,14 @@
* + Set handle State to READY.
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
__IO uint32_t count;
- /* Process locked */
+ /* Lock the process */
__HAL_LOCK(hspi);
/* Set hspi->state to aborting to avoid any interaction */
@@ -2593,8 +2629,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
/* Disable the SPI DMA Tx request if enabled */
@@ -2650,7 +2685,7 @@
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
}
- /* Process Unlocked */
+ /* Unlock the process */
__HAL_UNLOCK(hspi);
/* Restore hspi->state to ready */
@@ -2673,12 +2708,13 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
__IO uint32_t count;
- uint32_t dma_tx_abort_done = 1UL, dma_rx_abort_done = 1UL;
+ uint32_t dma_tx_abort_done = 1UL;
+ uint32_t dma_rx_abort_done = 1UL;
/* Set hspi->state to aborting to avoid any interaction */
hspi->State = HAL_SPI_STATE_ABORT;
@@ -2699,14 +2735,13 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
before any call to DMA Abort functions */
- if(hspi->hdmatx != NULL)
+ if (hspi->hdmatx != NULL)
{
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
{
@@ -2731,7 +2766,7 @@
}
}
- if(hspi->hdmarx != NULL)
+ if (hspi->hdmarx != NULL)
{
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
{
@@ -2854,7 +2889,8 @@
/* SPI in mode Transmitter and Receiver ------------------------------------*/
- if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
+ HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
{
hspi->TxISR(hspi);
hspi->RxISR(hspi);
@@ -2862,14 +2898,16 @@
}
/* SPI in mode Receiver ----------------------------------------------------*/
- if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \
+ HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
{
hspi->RxISR(hspi);
handled = 1UL;
}
/* SPI in mode Transmitter -------------------------------------------------*/
- if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \
+ HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
{
hspi->TxISR(hspi);
handled = 1UL;
@@ -2882,7 +2920,7 @@
hspi->Reload.Requested = 0UL;
__HAL_SPI_CLEAR_TSERFFLAG(hspi);
}
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
if (handled != 0UL)
{
@@ -2901,9 +2939,9 @@
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
/* DMA Normal Mode */
- if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || // IT based transfer is done
- ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode
- ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) // DMA is used in normal mode
+ if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) ||
+ ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) ||
+ ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL)))
{
/* For the IT based receive extra polling maybe required for last packet */
if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
@@ -2982,7 +3020,7 @@
HAL_SPI_TxCpltCallback(hspi);
}
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- else
+ else
{
/* End of the appropriate call */
}
@@ -3035,7 +3073,8 @@
__HAL_SPI_DISABLE(hspi);
/* Disable all interrupts */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR);
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF |
+ SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR));
/* Disable the SPI DMA requests if enabled */
if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
@@ -3558,7 +3597,7 @@
#else
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
}
}
@@ -3601,7 +3640,7 @@
#else
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
}
}
@@ -3638,7 +3677,7 @@
#else
/* Disable RXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
}
}
@@ -3675,7 +3714,7 @@
#else
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
}
}
@@ -3717,7 +3756,7 @@
#else
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
}
}
@@ -3753,7 +3792,7 @@
#else
/* Disable TXP interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
}
}
@@ -3769,7 +3808,8 @@
__HAL_SPI_DISABLE(hspi);
/* Disable ITs */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+ SPI_IT_FRE | SPI_IT_MODF));
/* Clear the Status flags in the SR register */
__HAL_SPI_CLEAR_EOTFLAG(hspi);
@@ -3799,7 +3839,7 @@
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL_ERROR: if any error detected
-* HAL_OK: if nothing detected
+ * HAL_OK: if nothing detected
*/
static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
{
@@ -3812,7 +3852,8 @@
__HAL_SPI_DISABLE(hspi);
/* Disable ITs */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+ SPI_IT_FRE | SPI_IT_MODF));
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
@@ -3909,7 +3950,6 @@
return data_size * fifo_threashold;
}
-
/**
* @}
*/
@@ -3923,5 +3963,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_spi_ex.c b/Src/stm32h7xx_hal_spi_ex.c
index ade9c64..963b85b 100644
--- a/Src/stm32h7xx_hal_spi_ex.c
+++ b/Src/stm32h7xx_hal_spi_ex.c
@@ -11,13 +11,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -160,7 +159,8 @@
* This parameter can be a value of @ref SPI_Underrun_Behaviour.
* @retval None
*/
-HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+ uint32_t UnderrunBehaviour)
{
HAL_StatusTypeDef errorcode = HAL_OK;
@@ -225,5 +225,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_sram.c b/Src/stm32h7xx_hal_sram.c
index daf8e3f..8e1bbdd 100644
--- a/Src/stm32h7xx_hal_sram.c
+++ b/Src/stm32h7xx_hal_sram.c
@@ -6,6 +6,17 @@
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -64,25 +75,25 @@
The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
+ Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+ By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
- and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
+ and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
@@ -90,8 +101,8 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
- or @ref HAL_SRAM_Init function.
+ using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
+ or HAL_SRAM_Init function.
When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
@@ -99,17 +110,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1109,5 +1109,3 @@
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_swpmi.c b/Src/stm32h7xx_hal_swpmi.c
index 839af3b..0cf0c1c 100644
--- a/Src/stm32h7xx_hal_swpmi.c
+++ b/Src/stm32h7xx_hal_swpmi.c
@@ -9,6 +9,17 @@
* + Data transfers functions
* + DMA transfers management
* + Interrupts and flags management
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -146,7 +157,7 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit
+ using HAL_SWPMI_RegisterCallback before calling HAL_SWPMI_DeInit
or HAL_SWPMI_Init function.
[..]
When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or
@@ -154,18 +165,6 @@
and weak (surcharged) callbacks are used.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -243,7 +242,7 @@
uint32_t tickstart = HAL_GetTick();
/* Check the SWPMI handle allocation */
- if(hswpmi == NULL)
+ if (hswpmi == NULL)
{
status = HAL_ERROR;
}
@@ -255,7 +254,7 @@
assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
- if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+ if (hswpmi->State == HAL_SWPMI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hswpmi->Lock = HAL_UNLOCKED;
@@ -269,7 +268,7 @@
hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- if(hswpmi->MspInitCallback == NULL)
+ if (hswpmi->MspInitCallback == NULL)
{
hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
}
@@ -303,12 +302,12 @@
/* Enable the SWPMI transceiver */
SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN);
/* Wait on RDYF flag to activate SWPMI */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK)
+ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK)
{
status = HAL_TIMEOUT;
}
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
hswpmi->State = HAL_SWPMI_STATE_READY;
@@ -336,7 +335,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the SWPMI handle allocation */
- if(hswpmi == NULL)
+ if (hswpmi == NULL)
{
status = HAL_ERROR;
}
@@ -359,7 +358,7 @@
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
- if(hswpmi->MspDeInitCallback == NULL)
+ if (hswpmi->MspDeInitCallback == NULL)
{
hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
}
@@ -426,12 +425,12 @@
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi,
- HAL_SWPMI_CallbackIDTypeDef CallbackID,
- pSWPMI_CallbackTypeDef pCallback)
+ HAL_SWPMI_CallbackIDTypeDef CallbackID,
+ pSWPMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* update the error code */
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
@@ -440,55 +439,55 @@
}
else
{
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
+ if (hswpmi->State == HAL_SWPMI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SWPMI_RX_COMPLETE_CB_ID :
- hswpmi->RxCpltCallback = pCallback;
- break;
- case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
- hswpmi->RxHalfCpltCallback = pCallback;
- break;
- case HAL_SWPMI_TX_COMPLETE_CB_ID :
- hswpmi->TxCpltCallback = pCallback;
- break;
- case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
- hswpmi->TxHalfCpltCallback = pCallback;
- break;
- case HAL_SWPMI_ERROR_CB_ID :
- hswpmi->ErrorCallback = pCallback;
- break;
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = pCallback;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = pCallback;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_RX_COMPLETE_CB_ID :
+ hswpmi->RxCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
+ hswpmi->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_TX_COMPLETE_CB_ID :
+ hswpmi->TxCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
+ hswpmi->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SWPMI_ERROR_CB_ID :
+ hswpmi->ErrorCallback = pCallback;
+ break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = pCallback;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+ else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = pCallback;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = pCallback;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = pCallback;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -518,59 +517,59 @@
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi,
- HAL_SWPMI_CallbackIDTypeDef CallbackID)
+ HAL_SWPMI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- if(hswpmi->State == HAL_SWPMI_STATE_READY)
+ if (hswpmi->State == HAL_SWPMI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SWPMI_RX_COMPLETE_CB_ID :
- hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
- break;
- case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
- hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
- break;
- case HAL_SWPMI_TX_COMPLETE_CB_ID :
- hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
- break;
- case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
- hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
- break;
- case HAL_SWPMI_ERROR_CB_ID :
- hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
- break;
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_RX_COMPLETE_CB_ID :
+ hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
+ break;
+ case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
+ hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
+ break;
+ case HAL_SWPMI_TX_COMPLETE_CB_ID :
+ hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
+ break;
+ case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
+ hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
+ break;
+ case HAL_SWPMI_ERROR_CB_ID :
+ hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
+ break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+ else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SWPMI_MSPINIT_CB_ID :
- hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
- break;
- case HAL_SWPMI_MSPDEINIT_CB_ID :
- hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
- break;
- default :
- /* update the error code */
- hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SWPMI_MSPINIT_CB_ID :
+ hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
+ break;
+ case HAL_SWPMI_MSPDEINIT_CB_ID :
+ hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -652,7 +651,7 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
HAL_StatusTypeDef status = HAL_OK;
@@ -660,7 +659,7 @@
uint32_t *ptmp_data;
uint32_t tmp_size;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -670,10 +669,10 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
{
/* Check if a non-blocking receive process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
@@ -696,7 +695,7 @@
do
{
/* Wait the TXE to write data */
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
{
hswpmi->Instance->TDR = *ptmp_data;
ptmp_data++;
@@ -705,19 +704,20 @@
else
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
break;
}
}
}
- } while(tmp_size != 0U);
+ }
+ while (tmp_size != 0U);
/* Wait on TXBEF flag to be able to start a second transfer */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
+ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
{
/* Timeout occurred */
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
@@ -725,10 +725,10 @@
status = HAL_TIMEOUT;
}
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
/* Check if a non-blocking receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
@@ -744,7 +744,7 @@
}
}
- if((status != HAL_OK) && (status != HAL_BUSY))
+ if ((status != HAL_OK) && (status != HAL_BUSY))
{
hswpmi->State = HAL_SWPMI_STATE_READY;
}
@@ -771,7 +771,7 @@
uint32_t *ptmp_data;
uint32_t tmp_size;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -781,10 +781,10 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
{
/* Check if a non-blocking transmit process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
@@ -804,7 +804,7 @@
do
{
/* Wait the RXNE to read data */
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
{
*ptmp_data = hswpmi->Instance->RDR;
ptmp_data++;
@@ -813,27 +813,28 @@
else
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
break;
}
}
}
- } while(tmp_size != 0U);
+ }
+ while (tmp_size != 0U);
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
- if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
{
/* Clear RXBFF at end of reception */
WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
}
/* Check if a non-blocking transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
}
@@ -849,7 +850,7 @@
}
}
- if((status != HAL_OK) && (status != HAL_BUSY))
+ if ((status != HAL_OK) && (status != HAL_BUSY))
{
hswpmi->State = HAL_SWPMI_STATE_READY;
}
@@ -872,7 +873,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -882,7 +883,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
{
/* Update handle */
hswpmi->pTxBuffPtr = pData;
@@ -891,7 +892,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a receive process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
@@ -939,7 +940,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -949,7 +950,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
{
/* Update handle */
hswpmi->pRxBuffPtr = pData;
@@ -958,7 +959,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
@@ -1002,7 +1003,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -1012,7 +1013,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
{
/* Update handle */
hswpmi->pTxBuffPtr = pData;
@@ -1021,7 +1022,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a receive process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
@@ -1043,7 +1044,7 @@
hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
/* Enable the SWPMI transmit DMA stream */
- if(HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
{
hswpmi->State = tmp_state; /* Back to previous state */
hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
@@ -1089,7 +1090,7 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SWPMI_StateTypeDef tmp_state;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
status = HAL_ERROR;
}
@@ -1099,7 +1100,7 @@
__HAL_LOCK(hswpmi);
tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+ if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
{
/* Update handle */
hswpmi->pRxBuffPtr = pData;
@@ -1107,7 +1108,7 @@
hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
- if(tmp_state == HAL_SWPMI_STATE_READY)
+ if (tmp_state == HAL_SWPMI_STATE_READY)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
@@ -1129,7 +1130,7 @@
hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
/* Enable the DMA request */
- if(HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
{
hswpmi->State = tmp_state; /* Back to previous state */
hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
@@ -1179,18 +1180,18 @@
CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
/* Abort the SWPMI DMA tx stream */
- if(hswpmi->hdmatx != NULL)
+ if (hswpmi->hdmatx != NULL)
{
- if(HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
{
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
status = HAL_ERROR;
}
}
/* Abort the SWPMI DMA rx stream */
- if(hswpmi->hdmarx != NULL)
+ if (hswpmi->hdmarx != NULL)
{
- if(HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
{
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
status = HAL_ERROR;
@@ -1295,7 +1296,7 @@
uint32_t errcode = HAL_SWPMI_ERROR_NONE;
/* SWPMI CRC error interrupt occurred --------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
{
/* Disable Receive CRC interrupt */
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
@@ -1306,7 +1307,7 @@
}
/* SWPMI Over-Run interrupt occurred -----------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
{
/* Disable Receive overrun interrupt */
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
@@ -1317,7 +1318,7 @@
}
/* SWPMI Under-Run interrupt occurred -----------------------------------------*/
- if(((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
{
/* Disable Transmit under run interrupt */
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
@@ -1327,27 +1328,27 @@
errcode |= HAL_SWPMI_ERROR_UDR;
}
- /* Call SWPMI Error Call back function if needed --------------------------*/
- if(errcode != HAL_SWPMI_ERROR_NONE)
+ /* Call SWPMI Error Call back function if needed --------------------------*/
+ if (errcode != HAL_SWPMI_ERROR_NONE)
{
hswpmi->ErrorCode |= errcode;
- if((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
+ if ((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
{
/* Check TXDMA transfer to abort */
- if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
{
/* Disable DMA TX at SWPMI level */
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
/* Abort the USART DMA Tx stream */
- if(hswpmi->hdmatx != NULL)
+ if (hswpmi->hdmatx != NULL)
{
/* Set the SWPMI Tx DMA Abort callback :
will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
{
/* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */
hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
@@ -1380,19 +1381,19 @@
else
{
/* Check RXDMA transfer to abort */
- if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
+ if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
{
/* Disable DMA RX at SWPMI level */
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
/* Abort the USART DMA Rx stream */
- if(hswpmi->hdmarx != NULL)
+ if (hswpmi->hdmarx != NULL)
{
/* Set the SWPMI Rx DMA Abort callback :
will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
{
/* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */
hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
@@ -1425,31 +1426,31 @@
}
/* SWPMI in mode Receiver ---------------------------------------------------*/
- if(((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U))
{
SWPMI_Receive_IT(hswpmi);
}
/* SWPMI in mode Transmitter ------------------------------------------------*/
- if(((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
{
SWPMI_Transmit_IT(hswpmi);
}
/* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
- if(((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
{
SWPMI_EndTransmit_IT(hswpmi);
}
/* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
- if(((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
+ if (((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
{
SWPMI_EndReceive_IT(hswpmi);
}
/* Both Transmission and reception complete ---------------------------------*/
- if(((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
+ if (((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
{
SWPMI_EndTransmitReceive_IT(hswpmi);
}
@@ -1597,14 +1598,14 @@
if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
{
- if(hswpmi->TxXferCount == 0U)
+ if (hswpmi->TxXferCount == 0U)
{
/* Disable the SWPMI TXE and Underrun Interrupts */
CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
}
else
{
- hswpmi->Instance->TDR = (uint32_t)*hswpmi->pTxBuffPtr;
+ hswpmi->Instance->TDR = (uint32_t) * hswpmi->pTxBuffPtr;
hswpmi->pTxBuffPtr++;
hswpmi->TxXferCount--;
}
@@ -1628,7 +1629,7 @@
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
/* Check if a receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
@@ -1654,13 +1655,13 @@
{
HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State;
- if((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
+ if ((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
{
*hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR);
hswpmi->pRxBuffPtr++;
--hswpmi->RxXferCount;
- if(hswpmi->RxXferCount == 0U)
+ if (hswpmi->RxXferCount == 0U)
{
/* Wait for RXBFF flag to update state */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
@@ -1689,7 +1690,7 @@
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
/* Check if a transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
}
@@ -1712,11 +1713,11 @@
CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
/* Check if a receive Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
- else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
+ else if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
{
hswpmi->State = HAL_SWPMI_STATE_READY;
}
@@ -1733,11 +1734,11 @@
*/
static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t tickstart;
/* DMA Normal mode*/
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
+ if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
{
hswpmi->TxXferCount = 0U;
@@ -1749,7 +1750,7 @@
tickstart = HAL_GetTick();
/* Wait the TXBEF */
- if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
+ if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout occurred */
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
@@ -1764,7 +1765,7 @@
{
/* No Timeout */
/* Check if a receive process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
}
@@ -1798,7 +1799,7 @@
*/
static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
hswpmi->TxHalfCpltCallback(hswpmi);
@@ -1815,10 +1816,10 @@
*/
static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode*/
- if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
+ if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
{
hswpmi->RxXferCount = 0U;
@@ -1827,7 +1828,7 @@
CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
/* Check if a transmit Process is ongoing or not */
- if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+ if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
{
hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
}
@@ -1850,7 +1851,7 @@
*/
static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
hswpmi->RxHalfCpltCallback(hswpmi);
@@ -1866,12 +1867,12 @@
*/
static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update handle */
hswpmi->RxXferCount = 0U;
hswpmi->TxXferCount = 0U;
- hswpmi->State= HAL_SWPMI_STATE_READY;
+ hswpmi->State = HAL_SWPMI_STATE_READY;
hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
@@ -1888,12 +1889,12 @@
*/
static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update handle */
hswpmi->RxXferCount = 0U;
hswpmi->TxXferCount = 0U;
- hswpmi->State= HAL_SWPMI_STATE_READY;
+ hswpmi->State = HAL_SWPMI_STATE_READY;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
hswpmi->ErrorCallback(hswpmi);
@@ -1905,7 +1906,7 @@
/**
* @brief Handle SWPMI Communication Timeout.
* @param hswpmi SWPMI handle
- * @param Flag: specifies the SWPMI flag to check.
+ * @param Flag specifies the SWPMI flag to check.
* @param Tickstart Tick start value
* @param Timeout timeout duration.
* @retval HAL status
@@ -1915,7 +1916,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Wait until flag is set */
- while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
+ while (!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
{
/* Check for the Timeout */
if ((((HAL_GetTick() - Tickstart) > Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
@@ -1945,5 +1946,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_tim.c b/Src/stm32h7xx_hal_tim.c
index 5dc8d35..8114f55 100644
--- a/Src/stm32h7xx_hal_tim.c
+++ b/Src/stm32h7xx_hal_tim.c
@@ -29,6 +29,17 @@
* + Commutation Event configuration with Interruption and DMA
* + TIM OCRef clear configuration
* + TIM External Clock configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### TIMER Generic features #####
@@ -103,14 +114,14 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
- @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ Use Function HAL_TIM_RegisterCallback() to register a callback.
+ HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
- Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
@@ -147,7 +158,7 @@
[..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
- examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+ examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
@@ -161,7 +172,7 @@
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+ using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
@@ -170,17 +181,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -561,7 +561,8 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -881,6 +882,7 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -926,34 +928,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -969,6 +975,8 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1003,26 +1011,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1040,6 +1052,7 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1078,7 +1091,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1099,7 +1113,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1120,7 +1135,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1140,7 +1156,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1151,34 +1168,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1194,6 +1215,8 @@
*/
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1232,26 +1255,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1522,7 +1549,9 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1566,34 +1595,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1609,6 +1642,8 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1643,26 +1678,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1680,6 +1719,7 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1718,7 +1758,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1739,7 +1780,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1759,7 +1801,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1779,7 +1822,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1790,34 +1834,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Enable the main output */
- __HAL_TIM_MOE_ENABLE(htim);
- }
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1833,6 +1881,8 @@
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1871,26 +1921,30 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (status == HAL_OK)
{
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2150,7 +2204,9 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
+
HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
@@ -2199,27 +2255,32 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2235,6 +2296,8 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -2269,21 +2332,25 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+ if (status == HAL_OK)
+ {
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2301,7 +2368,9 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
+
HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
@@ -2333,6 +2402,9 @@
return HAL_ERROR;
}
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2345,7 +2417,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2365,7 +2438,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2385,7 +2459,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2405,7 +2480,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -2416,12 +2492,10 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
@@ -2437,7 +2511,7 @@
}
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -2453,6 +2527,8 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
@@ -2495,18 +2571,22 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ if (status == HAL_OK)
+ {
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM channel state */
- TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM channel state */
+ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
* @}
@@ -2692,8 +2772,8 @@
* @brief Starts the TIM One Pulse signal generation.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -2749,8 +2829,8 @@
* @brief Stops the TIM One Pulse signal generation.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -2792,8 +2872,8 @@
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -2855,8 +2935,8 @@
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
* @note Though OutputChannel parameter is deprecated and ignored by the function
* it has been kept to avoid HAL_TIM API compatibility break.
- * @note The pulse output channel is determined when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel See note above
* @retval HAL status
@@ -3559,7 +3639,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -3567,11 +3648,12 @@
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
break;
}
@@ -3584,7 +3666,8 @@
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -3592,15 +3675,16 @@
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
}
- case TIM_CHANNEL_ALL:
+ default:
{
/* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
@@ -3610,7 +3694,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -3624,27 +3709,27 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
- /* Enable the Capture compare channel */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
break;
}
-
- default:
- break;
}
/* Return function status */
@@ -3972,6 +4057,8 @@
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
@@ -4043,12 +4130,13 @@
}
default:
+ status = HAL_ERROR;
break;
}
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -4066,6 +4154,8 @@
*/
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
@@ -4122,7 +4212,7 @@
/* Set the IC3PSC value */
htim->Instance->CCMR2 |= sConfig->ICPrescaler;
}
- else
+ else if (Channel == TIM_CHANNEL_4)
{
/* TI4 Configuration */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
@@ -4138,10 +4228,14 @@
/* Set the IC4PSC value */
htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
+ else
+ {
+ status = HAL_ERROR;
+ }
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -4163,6 +4257,8 @@
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
@@ -4277,12 +4373,13 @@
}
default:
+ status = HAL_ERROR;
break;
}
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -4307,6 +4404,7 @@
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel)
{
+ HAL_StatusTypeDef status = HAL_OK;
TIM_OC_InitTypeDef temp1;
/* Check the parameters */
@@ -4337,6 +4435,7 @@
TIM_OC1_SetConfig(htim->Instance, &temp1);
break;
}
+
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -4344,60 +4443,67 @@
TIM_OC2_SetConfig(htim->Instance, &temp1);
break;
}
+
default:
+ status = HAL_ERROR;
break;
}
- switch (InputChannel)
+ if (status == HAL_OK)
{
- case TIM_CHANNEL_1:
+ switch (InputChannel)
{
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ default:
+ status = HAL_ERROR;
+ break;
}
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
-
- /* Reset the IC2PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
- /* Select the Trigger source */
- htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- break;
- }
-
- default:
- break;
}
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
else
{
@@ -4428,13 +4534,13 @@
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
- *
+ *
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4453,8 +4559,14 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
- return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
+
+
+ return status;
}
/**
@@ -4480,13 +4592,13 @@
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
- *
+ *
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4507,6 +4619,8 @@
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
@@ -4533,6 +4647,7 @@
{
/* nothing to do */
}
+
switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
@@ -4546,7 +4661,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4564,7 +4679,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4582,7 +4697,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4600,7 +4715,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4618,7 +4733,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4636,7 +4751,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4654,7 +4769,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4662,16 +4777,20 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -4682,6 +4801,8 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4724,17 +4845,21 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -4760,13 +4885,13 @@
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
- *
+ *
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4785,8 +4910,13 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
- return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
+ HAL_StatusTypeDef status;
+
+ status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
+
+ return status;
}
/**
@@ -4812,13 +4942,13 @@
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_CCMR3
- * @arg TIM_DMABASE_CCR5
- * @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
- *
+ *
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4839,6 +4969,8 @@
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
@@ -4878,7 +5010,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4896,7 +5028,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4914,7 +5046,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4932,7 +5064,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4950,7 +5082,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4968,7 +5100,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4986,7 +5118,7 @@
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -4994,17 +5126,21 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ if (status == HAL_OK)
+ {
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -5015,6 +5151,8 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -5057,17 +5195,21 @@
break;
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (status == HAL_OK)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- /* Change the DMA burst operation state */
- htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -5134,6 +5276,8 @@
TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
@@ -5175,104 +5319,108 @@
}
default:
+ status = HAL_ERROR;
break;
}
- switch (Channel)
+ if (status == HAL_OK)
{
- case TIM_CHANNEL_1:
+ switch (Channel)
{
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ case TIM_CHANNEL_1:
{
- /* Enable the OCREF clear feature for Channel 1 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ break;
}
- else
+ case TIM_CHANNEL_2:
{
- /* Disable the OCREF clear feature for Channel 1 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ break;
}
- break;
+ case TIM_CHANNEL_3:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_4:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_5:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 5 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 5 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_6:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 6 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 6 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ break;
+ }
+ default:
+ break;
}
- case TIM_CHANNEL_2:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 2 */
- SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 2 */
- CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
- }
- break;
- }
- case TIM_CHANNEL_3:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 3 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 3 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
- }
- break;
- }
- case TIM_CHANNEL_4:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 4 */
- SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 4 */
- CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
- }
- break;
- }
- case TIM_CHANNEL_5:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 5 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 5 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
- }
- break;
- }
- case TIM_CHANNEL_6:
- {
- if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
- {
- /* Enable the OCREF clear feature for Channel 6 */
- SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- }
- else
- {
- /* Disable the OCREF clear feature for Channel 6 */
- CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
- }
- break;
- }
- default:
- break;
}
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -5284,6 +5432,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Process Locked */
@@ -5409,22 +5558,23 @@
case TIM_CLOCKSOURCE_ITR6:
case TIM_CLOCKSOURCE_ITR7:
case TIM_CLOCKSOURCE_ITR8:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
default:
+ status = HAL_ERROR;
break;
}
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
/**
@@ -5950,7 +6100,7 @@
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
@@ -6016,14 +6166,14 @@
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -6080,120 +6230,148 @@
switch (CallbackID)
{
case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
break;
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
break;
case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
break;
case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
break;
case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
break;
case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
break;
case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
break;
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
break;
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
break;
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
break;
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
break;
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
break;
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
break;
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
break;
case HAL_TIM_PERIOD_ELAPSED_CB_ID :
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ /* Legacy weak Period Elapsed Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
break;
case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
+ /* Legacy weak Period Elapsed half complete Callback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
break;
case HAL_TIM_TRIGGER_CB_ID :
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ /* Legacy weak Trigger Callback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
break;
case HAL_TIM_TRIGGER_HALF_CB_ID :
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
+ /* Legacy weak Trigger half complete Callback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
break;
case HAL_TIM_IC_CAPTURE_CB_ID :
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ /* Legacy weak IC Capture Callback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
break;
case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
+ /* Legacy weak IC Capture half complete Callback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
break;
case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ /* Legacy weak OC Delay Elapsed Callback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
break;
case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ /* Legacy weak PWM Pulse Finished Callback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
break;
case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+ /* Legacy weak PWM Pulse Finished half complete Callback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
break;
case HAL_TIM_ERROR_CB_ID :
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ /* Legacy weak Error Callback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
break;
case HAL_TIM_COMMUTATION_CB_ID :
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
+ /* Legacy weak Commutation Callback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
break;
case HAL_TIM_COMMUTATION_HALF_CB_ID :
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
+ /* Legacy weak Commutation half complete Callback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
break;
case HAL_TIM_BREAK_CB_ID :
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ /* Legacy weak Break Callback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
break;
case HAL_TIM_BREAK2_CB_ID :
- htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
+ /* Legacy weak Break2 Callback */
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
break;
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
@@ -6202,71 +6380,85 @@
switch (CallbackID)
{
case HAL_TIM_BASE_MSPINIT_CB_ID :
- htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ /* Legacy weak Base MspInit Callback */
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
break;
case HAL_TIM_BASE_MSPDEINIT_CB_ID :
- htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ /* Legacy weak Base Msp DeInit Callback */
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
break;
case HAL_TIM_IC_MSPINIT_CB_ID :
- htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ /* Legacy weak IC Msp Init Callback */
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
break;
case HAL_TIM_IC_MSPDEINIT_CB_ID :
- htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ /* Legacy weak IC Msp DeInit Callback */
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
break;
case HAL_TIM_OC_MSPINIT_CB_ID :
- htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ /* Legacy weak OC Msp Init Callback */
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
break;
case HAL_TIM_OC_MSPDEINIT_CB_ID :
- htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ /* Legacy weak OC Msp DeInit Callback */
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
break;
case HAL_TIM_PWM_MSPINIT_CB_ID :
- htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ /* Legacy weak PWM Msp Init Callback */
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
break;
case HAL_TIM_PWM_MSPDEINIT_CB_ID :
- htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ /* Legacy weak PWM Msp DeInit Callback */
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
break;
case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
- htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ /* Legacy weak One Pulse Msp Init Callback */
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
break;
case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
- htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ /* Legacy weak One Pulse Msp DeInit Callback */
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
break;
case HAL_TIM_ENCODER_MSPINIT_CB_ID :
- htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ /* Legacy weak Encoder Msp Init Callback */
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
break;
case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
- htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ /* Legacy weak Encoder Msp DeInit Callback */
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
break;
case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
- htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ /* Legacy weak Hall Sensor Msp Init Callback */
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
break;
case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
- htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ /* Legacy weak Hall Sensor Msp DeInit Callback */
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
break;
default :
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
/* Release Lock */
@@ -7181,6 +7373,7 @@
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
@@ -7287,16 +7480,18 @@
case TIM_TS_ITR11:
case TIM_TS_ITR12:
case TIM_TS_ITR13:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
default:
+ status = HAL_ERROR;
break;
}
- return HAL_OK;
+
+ return status;
}
/**
@@ -7685,20 +7880,20 @@
void TIM_ResetCallback(TIM_HandleTypeDef *htim)
{
/* Reset the TIM callback to the legacy weak callbacks */
- htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
- htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
- htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
- htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
- htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
- htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
- htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
- htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
- htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
- htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
- htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
- htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
- htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
- htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
+ htim->TriggerCallback = HAL_TIM_TriggerCallback;
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+ htim->ErrorCallback = HAL_TIM_ErrorCallback;
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback;
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
+ htim->BreakCallback = HAL_TIMEx_BreakCallback;
+ htim->Break2Callback = HAL_TIMEx_Break2Callback;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -7714,4 +7909,3 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_tim_ex.c b/Src/stm32h7xx_hal_tim_ex.c
index d929a23..a1aeeb4 100644
--- a/Src/stm32h7xx_hal_tim_ex.c
+++ b/Src/stm32h7xx_hal_tim_ex.c
@@ -11,6 +11,17 @@
* + Time Master and Slave synchronization configuration
* + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
* + Timer remapping capabilities configuration
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### TIMER Extended features #####
@@ -55,24 +66,16 @@
the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
- (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+ HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+ HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
- (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+ HAL_TIMEx_HallSensor_Start_IT().
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -91,6 +94,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+#if defined(TIM_BDTR_BKBID)
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+ * @{
+ */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+#endif /* TIM_BDTR_BKBID */
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -336,7 +352,8 @@
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -368,7 +385,8 @@
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the Peripheral */
@@ -419,7 +437,8 @@
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -451,7 +470,8 @@
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts event */
@@ -511,7 +531,8 @@
}
/* Enable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Set the DMA Input Capture 1 Callbacks */
@@ -558,7 +579,8 @@
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
- (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+ TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
@@ -698,6 +720,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -737,34 +760,38 @@
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -780,7 +807,9 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpccer;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -808,30 +837,34 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if (status == HAL_OK)
{
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -849,6 +882,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -887,7 +921,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -907,7 +942,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -927,7 +963,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -938,31 +975,35 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -978,6 +1019,8 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1008,23 +1051,27 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ if (status == HAL_OK)
+ {
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1155,6 +1202,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1193,34 +1241,38 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the TIM Break interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1236,6 +1288,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpccer;
/* Check the parameters */
@@ -1265,30 +1318,34 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
- /* Disable the TIM Break interrupt (only if no more channel is active) */
- tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if (status == HAL_OK)
{
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
-
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1306,6 +1363,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpsmcr;
/* Check the parameters */
@@ -1344,7 +1402,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1364,7 +1423,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1384,7 +1444,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA stream */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+ Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
@@ -1395,31 +1456,35 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
- /* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ if (status == HAL_OK)
{
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
}
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1435,6 +1500,8 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1465,23 +1532,27 @@
}
default:
+ status = HAL_ERROR;
break;
}
- /* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ if (status == HAL_OK)
+ {
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
- /* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
- /* Set the TIM complementary channel state */
- TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ /* Set the TIM complementary channel state */
+ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1509,8 +1580,8 @@
/**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
@@ -1530,7 +1601,7 @@
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
@@ -1558,8 +1629,8 @@
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
@@ -1597,8 +1668,8 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
@@ -1618,7 +1689,7 @@
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
@@ -1652,8 +1723,8 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @note OutputChannel must match the pulse output channel chosen when calling
- * @ref HAL_TIM_OnePulse_ConfigChannel().
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
@@ -2022,6 +2093,17 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+#if defined(TIM_BDTR_BKBID)
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+
+ /* Set BREAK AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+ }
+
+#endif /* TIM_BDTR_BKBID */
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
{
/* Check the parameters */
@@ -2033,6 +2115,17 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+#if defined(TIM_BDTR_BKBID)
+
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+
+ /* Set BREAK2 AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+ }
+#endif /* TIM_BDTR_BKBID */
}
/* Set TIMx_BDTR */
@@ -2059,6 +2152,7 @@
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmporx;
uint32_t bkin_enable_mask;
uint32_t bkin_polarity_mask;
@@ -2107,7 +2201,7 @@
case TIM_BREAKINPUTSOURCE_DFSDM1:
{
bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
- bkin_enable_bitpos = 8U;
+ bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos;
bkin_polarity_mask = 0U;
bkin_polarity_bitpos = 0U;
break;
@@ -2136,10 +2230,10 @@
/* Set the break input polarity */
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_AF1 */
htim->Instance->AF1 = tmporx;
@@ -2156,22 +2250,23 @@
/* Set the break input polarity */
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_AF2 */
htim->Instance->AF2 = tmporx;
break;
}
default:
+ status = HAL_ERROR;
break;
}
__HAL_UNLOCK(htim);
- return HAL_OK;
+ return status;
}
#endif /*TIM_BREAK_INPUT_SUPPORT */
@@ -2399,6 +2494,140 @@
return HAL_OK;
}
+#if defined(TIM_BDTR_BKBID)
+
+/**
+ * @brief Disarm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to disarm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmpbdtr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Arm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to arm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note Arming is possible at anytime, even if fault is present.
+ * @note Break input is automatically armed as soon as MOE bit is set.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+ {
+ /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+ {
+ /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ break;
+ }
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+#endif /* TIM_BDTR_BKBID */
/**
* @}
@@ -2537,7 +2766,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
@@ -2713,5 +2942,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c b/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
index 39d8881..6f82268 100644
--- a/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c
@@ -10,6 +10,19 @@
* + The alarm is configured to assert an interrupt when the RTC reaches 1ms
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
* + HSE (default), LSE or LSI can be selected as RTC clock source
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
@verbatim
==============================================================================
##### How to use this driver #####
@@ -30,17 +43,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -92,12 +94,13 @@
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
__IO uint32_t counter = 0U;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+ HAL_StatusTypeDef status;
#ifdef RTC_CLOCK_SOURCE_LSE
/* Configure LSE as RTC clock source */
@@ -122,11 +125,14 @@
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ if (status == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
- {
+ status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ }
+ if (status == HAL_OK)
+ {
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
@@ -148,99 +154,103 @@
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ status = HAL_RTC_Init(&hRTC_Handle);
+ }
+ if (status == HAL_OK)
+ {
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
- if(HAL_RTC_Init(&hRTC_Handle) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
-
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
-
- counter = 0U;
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ counter = 0U;
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
#if defined(RTC_ICSR_ALRAWF)
- while( READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_ALRAWF) == 0U)
+ while ( READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_ALRAWF) == (uint32_t)RESET)
#else
- while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == (uint32_t)RESET)
+ while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == (uint32_t)RESET)
#endif /* RTC_ICSR_ALRAWF */
- {
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
- }
+ {
+ if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+ if (status == HAL_OK)
+ {
+ hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U;
- hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
- /* Check if the Initialization mode is set */
+ /* Check if the Initialization mode is set */
#if defined(RTC_ISR_INITF)
- if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ if ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
#else
- if((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET)
+ if ((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET)
#endif /* RTC_ISR_INITF */
- {
- /* Set the Initialization mode */
+ {
+ /* Set the Initialization mode */
#if defined(RTC_ISR_INITF)
- hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
+ hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
#else
- hRTC_Handle.Instance->ICSR = (uint32_t)RTC_INIT_MASK;
+ hRTC_Handle.Instance->ICSR = (uint32_t)RTC_INIT_MASK;
#endif /* RTC_ISR_INITF */
- counter = 0U;
+ counter = 0U;
#if defined(RTC_ISR_INITF)
- while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ while ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
#else
- while((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET)
+ while ((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET)
#endif /* RTC_ISR_INITF */
- {
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
- {
- return HAL_ERROR;
- }
- }
- }
- hRTC_Handle.Instance->DR = 0U;
- hRTC_Handle.Instance->TR = 0U;
+ {
+ if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
+ {
+ status = HAL_ERROR;
+ }
+ }
+ }
+ }
+ if (status == HAL_OK)
+ {
+ hRTC_Handle.Instance->DR = 0U;
+ hRTC_Handle.Instance->TR = 0U;
#if defined(RTC_ISR_INIT)
- hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
#else
- hRTC_Handle.Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
+ hRTC_Handle.Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT;
#endif /* RTC_ISR_INIT */
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- {
+ /* Enable the RTC Alarm Interrupt */
+ HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
-
- uwTickPrio = TickPriority;
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
+ uwTickPrio = TickPriority;
}
+ else
+ {
+ status = HAL_ERROR;
+ }
+
}
- return HAL_ERROR;
+ return status;
}
/**
@@ -334,4 +344,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
index 0f0f0ab..31f7f04 100644
--- a/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c
@@ -11,6 +11,18 @@
* + The wakeup feature is configured to assert an interrupt each 1ms
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
* + HSE (default), LSE or LSI can be selected as RTC clock source
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -31,17 +43,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -105,6 +106,7 @@
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+ HAL_StatusTypeDef status;
#ifdef RTC_CLOCK_SOURCE_LSE
/* Configure LSE as RTC clock source */
@@ -129,11 +131,14 @@
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ if (status == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
- {
+ status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ }
+ if (status == HAL_OK)
+ {
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
@@ -155,12 +160,10 @@
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
-
- if(HAL_RTC_Init(&hRTC_Handle) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
+ status = HAL_RTC_Init(&hRTC_Handle);
+ }
+ if (status == HAL_OK)
+ {
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
@@ -168,66 +171,67 @@
__HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
/* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
/* Wait till RTC WUTWF flag is set */
#if defined(RTC_ICSR_WUTWF)
- while(READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
+ while (READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_WUTWF) == (uint32_t)RESET)
#else
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == (uint32_t)RESET)
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == (uint32_t)RESET)
#endif /* RTC_ICSR_WUTWF */
{
- if(counter++ == (SystemCoreClock /48U))
- {
- return HAL_ERROR;
- }
- }
-
- /* Clear PWR wake up Flag */
- __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
-
- /* Clear RTC Wake Up timer Flag */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
-
- /* Configure the Wake-up Timer counter */
- hRTC_Handle.Instance->WUTR = (uint32_t)0U;
-
- /* Clear the Wake-up Timer clock source bits in CR register */
- hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
-
- /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
- /* Configure the Interrupt in the RTC_CR register */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
-
- /* Enable the Wake-up Timer */
- __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-
- /* Configure the HAL Tick IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ if (counter++ == (SystemCoreClock / 48U))
{
- HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
-
- uwTickPrio = TickPriority;
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
+ status = HAL_ERROR;
}
}
}
- return HAL_ERROR;
+ if (status == HAL_OK)
+ {
+ /* Clear PWR wake up Flag */
+ __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
+
+ /* Clear RTC Wake Up timer Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
+
+ /* Configure the Wake-up Timer counter */
+ hRTC_Handle.Instance->WUTR = (uint32_t)0U;
+
+ /* Clear the Wake-up Timer clock source bits in CR register */
+ hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
+
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+ /* Configure the Interrupt in the RTC_CR register */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+
+ /* Enable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+ /* Enable the RTC global Interrupt */
+ HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ return status;
}
/**
@@ -293,4 +297,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_timebase_tim_template.c b/Src/stm32h7xx_hal_timebase_tim_template.c
index ec97a3e..9353743 100644
--- a/Src/stm32h7xx_hal_timebase_tim_template.c
+++ b/Src/stm32h7xx_hal_timebase_tim_template.c
@@ -9,6 +9,17 @@
* + Initializes the TIM peripheral generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -21,17 +32,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -61,20 +61,7 @@
uint32_t uwTimclock, uwAPB1Prescaler;
uint32_t uwPrescalerValue;
uint32_t pFLatency;
-
- /*Configure the TIM6 IRQ priority */
- if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- {
- HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
-
- /* Enable the TIM6 global Interrupt */
- HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
- uwTickPrio = TickPriority;
- }
- else
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef status;
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
@@ -109,16 +96,33 @@
*/
TimHandle.Init.Period = (1000000U / 1000U) - 1U;
TimHandle.Init.Prescaler = uwPrescalerValue;
- TimHandle.Init.ClockDivision = 0;
+ TimHandle.Init.ClockDivision = 0U;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
- if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ status = HAL_TIM_Base_Init(&TimHandle);
+ if (status == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
- return HAL_TIM_Base_Start_IT(&TimHandle);
- }
+ status = HAL_TIM_Base_Start_IT(&TimHandle);
+ if (status == HAL_OK)
+ {
+ /* Enable the TIM6 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
+
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ /* Enable the TIM6 global Interrupt */
+ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+}
/* Return function status */
- return HAL_ERROR;
+ return status;
}
/**
@@ -171,4 +175,4 @@
HAL_TIM_IRQHandler(&TimHandle);
}
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Src/stm32h7xx_hal_uart.c b/Src/stm32h7xx_hal_uart.c
index 218b9b5..6816123 100644
--- a/Src/stm32h7xx_hal_uart.c
+++ b/Src/stm32h7xx_hal_uart.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -76,8 +87,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
- Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_UART_RegisterCallback() to register a user callback.
+ Function HAL_UART_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -95,9 +106,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -116,16 +127,16 @@
[..]
For specific callback RxEventCallback, use dedicated registration/reset functions:
- respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+ respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
[..]
- By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
- and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+ and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -134,8 +145,8 @@
in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
- or @ref HAL_UART_Init() function.
+ using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+ or HAL_UART_Init() function.
[..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
@@ -145,17 +156,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -193,7 +193,6 @@
*/
/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -223,8 +222,8 @@
* @}
*/
-/* Exported Constants --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Constants
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
* @{
*/
const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
@@ -232,6 +231,7 @@
* @}
*/
+/* Exported Constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
@@ -1118,10 +1118,10 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *pdata8bits;
- uint16_t *pdata16bits;
+ const uint8_t *pdata8bits;
+ const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
@@ -1147,7 +1147,7 @@
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
- pdata16bits = (uint16_t *) pData;
+ pdata16bits = (const uint16_t *) pData;
}
else
{
@@ -1293,7 +1293,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
@@ -1329,7 +1329,7 @@
__HAL_UNLOCK(huart);
/* Enable the TX FIFO threshold interrupt */
- SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
}
else
{
@@ -1346,7 +1346,7 @@
__HAL_UNLOCK(huart);
/* Enable the Transmit Data Register Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
}
return HAL_OK;
@@ -1388,7 +1388,7 @@
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
@@ -1410,7 +1410,7 @@
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
@@ -1464,7 +1464,7 @@
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -1507,7 +1507,7 @@
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
@@ -1535,17 +1535,17 @@
(gstate == HAL_UART_STATE_BUSY_TX))
{
/* Disable the UART DMA Tx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
(rxstate == HAL_UART_STATE_BUSY_RX))
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Rx request */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
__HAL_UNLOCK(huart);
@@ -1565,7 +1565,7 @@
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
@@ -1573,11 +1573,14 @@
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Enable the UART DMA Rx request */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
__HAL_UNLOCK(huart);
@@ -1606,7 +1609,7 @@
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel */
if (huart->hdmatx != NULL)
@@ -1630,7 +1633,7 @@
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
(rxstate == HAL_UART_STATE_BUSY_RX))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
@@ -1668,20 +1671,21 @@
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
{
/* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
- USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
@@ -1703,10 +1707,11 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
@@ -1769,13 +1774,14 @@
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
{
/* Disable TCIE, TXEIE and TXFTIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
@@ -1827,19 +1833,20 @@
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
{
/* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
@@ -1896,14 +1903,14 @@
uint32_t abortcplt = 1U;
/* Disable interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
- USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
@@ -1937,11 +1944,11 @@
}
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
@@ -1961,10 +1968,11 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
@@ -2046,13 +2054,14 @@
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ /* Disable the UART DMA Tx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
@@ -2136,19 +2145,20 @@
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
@@ -2326,10 +2336,11 @@
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the UART DMA Rx request if enabled */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
@@ -2414,18 +2425,18 @@
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
@@ -2450,10 +2461,10 @@
&& (nb_rx_data > 0U))
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -2462,7 +2473,7 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
@@ -2812,7 +2823,7 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Enable USART mute mode by setting the MME bit in the CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
huart->gState = HAL_UART_STATE_READY;
@@ -2832,7 +2843,7 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Disable USART mute mode by clearing the MME bit in the CR1 register */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
huart->gState = HAL_UART_STATE_READY;
@@ -2861,10 +2872,10 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
huart->gState = HAL_UART_STATE_READY;
@@ -2884,10 +2895,10 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
- SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
huart->gState = HAL_UART_STATE_READY;
@@ -3189,7 +3200,7 @@
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
{
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
@@ -3245,10 +3256,10 @@
if (pclk != 0U)
{
/* USARTDIV must be greater than or equal to 0d16 */
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
- huart->Instance->BRR = usartdiv;
+ huart->Instance->BRR = (uint16_t)usartdiv;
}
else
{
@@ -3390,10 +3401,11 @@
}
/**
- * @brief Handle UART Communication Timeout.
+ * @brief This function handles UART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param huart UART handle.
* @param Flag Specifies the UART flag to check
- * @param Status Flag status (SET or RESET)
+ * @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
@@ -3411,8 +3423,9 @@
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
@@ -3431,8 +3444,9 @@
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+ USART_CR1_TXEIE_TXFNFIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
@@ -3474,7 +3488,7 @@
huart->RxState = HAL_UART_STATE_BUSY_RX;
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Configure Rx interrupt processing */
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
@@ -3492,8 +3506,11 @@
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
}
else
{
@@ -3510,7 +3527,14 @@
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
}
return HAL_OK;
}
@@ -3556,8 +3580,8 @@
__HAL_UNLOCK(huart);
- /* Restore huart->gState to ready */
- huart->gState = HAL_UART_STATE_READY;
+ /* Restore huart->RxState to ready */
+ huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR;
}
@@ -3565,14 +3589,17 @@
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ if (huart->Init.Parity != UART_PARITY_NONE)
+ {
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
@@ -3586,8 +3613,8 @@
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
{
/* Disable TXEIE, TCIE, TXFT interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
@@ -3602,13 +3629,13 @@
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
/* At end of Rx process, restore huart->RxState to Ready */
@@ -3636,10 +3663,10 @@
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
/* DMA Circular mode */
else
@@ -3687,12 +3714,12 @@
huart->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -3700,7 +3727,7 @@
/* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
}
@@ -4012,10 +4039,10 @@
if (huart->TxXferCount == 0U)
{
/* Disable the UART Transmit Data Register Empty Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
else
{
@@ -4035,7 +4062,7 @@
*/
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@@ -4043,14 +4070,14 @@
if (huart->TxXferCount == 0U)
{
/* Disable the UART Transmit Data Register Empty Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
else
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4077,10 +4104,10 @@
if (huart->TxXferCount == 0U)
{
/* Disable the TX FIFO threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
break; /* force exit loop */
}
@@ -4107,7 +4134,7 @@
*/
static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
uint16_t nb_tx_data;
/* Check that a Tx process is ongoing */
@@ -4118,16 +4145,16 @@
if (huart->TxXferCount == 0U)
{
/* Disable the TX FIFO threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
break; /* force exit loop */
}
else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4149,7 +4176,7 @@
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
@@ -4187,10 +4214,10 @@
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4202,9 +4229,17 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4224,7 +4259,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -4259,10 +4293,10 @@
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4274,9 +4308,17 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4296,7 +4338,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -4381,11 +4422,11 @@
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4397,9 +4438,17 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4419,7 +4468,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
@@ -4431,13 +4479,13 @@
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
{
/* Disable the UART RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_8BIT;
/* Enable the UART Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
}
else
@@ -4524,11 +4572,11 @@
if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -4540,9 +4588,17 @@
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- /* Disable IDLE interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ /* Set reception type to Standard */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ /* Disable IDLE interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ {
+ /* Clear IDLE Flag */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ }
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
@@ -4562,7 +4618,6 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
- huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
@@ -4574,13 +4629,13 @@
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
{
/* Disable the UART RXFT interrupt*/
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_16BIT;
/* Enable the UART Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
}
else
@@ -4603,4 +4658,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_uart_ex.c b/Src/stm32h7xx_hal_uart_ex.c
index bd57fec..e2ca48d 100644
--- a/Src/stm32h7xx_hal_uart_ex.c
+++ b/Src/stm32h7xx_hal_uart_ex.c
@@ -9,6 +9,17 @@
* + Peripheral Control functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### UART peripheral extended features #####
@@ -27,17 +38,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -483,7 +483,7 @@
__HAL_LOCK(huart);
/* Set UESM bit */
- SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -502,7 +502,7 @@
__HAL_LOCK(huart);
/* Clear UESM bit */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -858,7 +858,7 @@
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
@@ -920,7 +920,7 @@
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
@@ -1016,4 +1016,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_usart.c b/Src/stm32h7xx_hal_usart.c
index f27e32f..2f3331e 100644
--- a/Src/stm32h7xx_hal_usart.c
+++ b/Src/stm32h7xx_hal_usart.c
@@ -11,6 +11,17 @@
* + Peripheral Control functions
* + Peripheral State and Error functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
@@ -62,8 +73,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
- Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_USART_RegisterCallback() to register a user callback.
+ Function HAL_USART_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -79,9 +90,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -97,13 +108,13 @@
(+) MspDeInitCallback : USART MspDeInit.
[..]
- By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+ By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+ examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
- and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
+ and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -112,8 +123,8 @@
in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
- or @ref HAL_USART_Init() function.
+ using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
+ or HAL_USART_Init() function.
[..]
When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
@@ -123,17 +134,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -748,10 +748,10 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint8_t *ptxdata8bits;
- uint16_t *ptxdata16bits;
+ const uint8_t *ptxdata8bits;
+ const uint16_t *ptxdata16bits;
uint32_t tickstart;
if (husart->State == HAL_USART_STATE_READY)
@@ -777,7 +777,7 @@
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
ptxdata8bits = NULL;
- ptxdata16bits = (uint16_t *) pTxData;
+ ptxdata16bits = (const uint16_t *) pTxData;
}
else
{
@@ -957,13 +957,13 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
uint8_t *prxdata8bits;
uint16_t *prxdata16bits;
- uint8_t *ptxdata8bits;
- uint16_t *ptxdata16bits;
+ const uint8_t *ptxdata8bits;
+ const uint16_t *ptxdata16bits;
uint16_t uhMask;
uint16_t rxdatacount;
uint32_t tickstart;
@@ -998,7 +998,7 @@
{
prxdata8bits = NULL;
ptxdata8bits = NULL;
- ptxdata16bits = (uint16_t *) pTxData;
+ ptxdata16bits = (const uint16_t *) pTxData;
prxdata16bits = (uint16_t *) pRxData;
}
else
@@ -1104,7 +1104,7 @@
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
{
if (husart->State == HAL_USART_STATE_READY)
{
@@ -1231,7 +1231,10 @@
__HAL_UNLOCK(husart);
/* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
}
else
@@ -1250,7 +1253,14 @@
__HAL_UNLOCK(husart);
/* Enable the USART Parity Error and Data Register not empty Interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
}
if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
@@ -1291,7 +1301,7 @@
* @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
@@ -1339,8 +1349,11 @@
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Enable the USART Parity Error interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the TX and RX FIFO Threshold interrupts */
SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
@@ -1365,7 +1378,14 @@
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Enable the USART Parity Error and USART Data Register not empty Interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ else
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
/* Enable the USART Transmit Data Register Empty Interrupt */
SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
@@ -1389,10 +1409,10 @@
* @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t *tmp;
+ const uint32_t *tmp;
if (husart->State == HAL_USART_STATE_READY)
{
@@ -1423,8 +1443,8 @@
husart->hdmatx->XferErrorCallback = USART_DMAError;
/* Enable the USART transmit DMA channel */
- tmp = (uint32_t *)&pTxData;
- status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ tmp = (const uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
}
if (status == HAL_OK)
@@ -1535,8 +1555,11 @@
/* Process Unlocked */
__HAL_UNLOCK(husart);
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1591,11 +1614,11 @@
* @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
HAL_StatusTypeDef status;
- uint32_t *tmp;
+ const uint32_t *tmp;
if (husart->State == HAL_USART_STATE_READY)
{
@@ -1637,13 +1660,13 @@
/* Enable the USART receive DMA channel */
tmp = (uint32_t *)&pRxData;
- status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size);
/* Enable the USART transmit DMA channel */
if (status == HAL_OK)
{
- tmp = (uint32_t *)&pTxData;
- status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ tmp = (const uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
}
}
else
@@ -1656,8 +1679,11 @@
/* Process Unlocked */
__HAL_UNLOCK(husart);
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1774,7 +1800,10 @@
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (husart->Init.Parity != USART_PARITY_NONE)
+ {
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ }
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Enable the USART DMA Rx request before the DMA Tx request */
@@ -1866,9 +1895,10 @@
USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the USART DMA Tx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1891,9 +1921,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1995,7 +2026,7 @@
}
}
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
@@ -2019,9 +2050,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2201,9 +2233,10 @@
Disable Interrupts, and disable DMA requests, if ongoing */
USART_EndTransfer(husart);
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
/* Abort the USART DMA Tx channel */
@@ -2810,10 +2843,11 @@
/**
- * @brief Handle USART Communication Timeout.
+ * @brief Handle USART Communication Timeout. It waits
+ * until a flag is no longer in the specified status.
* @param husart USART handle.
* @param Flag Specifies the USART flag to check.
- * @param Status the Flag status (SET or RESET).
+ * @param Status the actual Flag status (SET or RESET).
* @param Tickstart Tick start value
* @param Timeout timeout duration.
* @retval HAL status
@@ -3056,7 +3090,7 @@
static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
{
const HAL_USART_StateTypeDef state = husart->State;
- uint16_t *tmp;
+ const uint16_t *tmp;
if ((state == HAL_USART_STATE_BUSY_TX) ||
(state == HAL_USART_STATE_BUSY_TX_RX))
@@ -3071,7 +3105,7 @@
}
else
{
- tmp = (uint16_t *) husart->pTxBuffPtr;
+ tmp = (const uint16_t *) husart->pTxBuffPtr;
husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
husart->pTxBuffPtr += 2U;
husart->TxXferCount--;
@@ -3137,7 +3171,7 @@
static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
{
const HAL_USART_StateTypeDef state = husart->State;
- uint16_t *tmp;
+ const uint16_t *tmp;
uint16_t nb_tx_data;
/* Check that a Tx process is ongoing */
@@ -3158,7 +3192,7 @@
}
else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
{
- tmp = (uint16_t *) husart->pTxBuffPtr;
+ tmp = (const uint16_t *) husart->pTxBuffPtr;
husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
husart->pTxBuffPtr += 2U;
husart->TxXferCount--;
@@ -3690,4 +3724,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_usart_ex.c b/Src/stm32h7xx_hal_usart_ex.c
index 2bdc87e..b1a916d 100644
--- a/Src/stm32h7xx_hal_usart_ex.c
+++ b/Src/stm32h7xx_hal_usart_ex.c
@@ -8,6 +8,17 @@
* + Peripheral Control functions
*
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### USART peripheral extended features #####
@@ -26,17 +37,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -539,4 +539,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_hal_wwdg.c b/Src/stm32h7xx_hal_wwdg.c
index 43b55b2..4eed817 100644
--- a/Src/stm32h7xx_hal_wwdg.c
+++ b/Src/stm32h7xx_hal_wwdg.c
@@ -7,6 +7,17 @@
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and Configuration functions
* + IO operation functions
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### WWDG Specific features #####
@@ -40,17 +51,17 @@
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values (case of STM32H74x/5x devices):
(++) Counter min (T[5;0] = 0x00) @100MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 40.96µs
+ max timeout before reset: approximately 40.96us
(++) Counter max (T[5;0] = 0x3F) @100MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: approximately 335.54ms
(+) Typical values (case of STM32H7Ax/Bx devices):
(++) Counter min (T[5;0] = 0x00) @140MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 29.25µs
+ max timeout before reset: approximately 29.25us
(++) Counter max (T[5;0] = 0x3F) @140MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: approximately 239.67ms
(+) Typical values (case of STM32H72x/3x devices):
(++) Counter min (T[5;0] = 0x00) @125MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 32.76µs
+ max timeout before reset: approximately 32.76us
(++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: approximately 268.43ms
@@ -64,7 +75,7 @@
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Configure the WWDG prescaler, refresh window value, counter value and early
interrupt status using HAL_WWDG_Init() function. This will automatically
- enable WWDG and start its downcounter. Time reference can be taken from
+ enable WWDG and start its downcounter. Time reference can be taken from
function exit. Care must be taken to provide a counter value
greater than 0x40 to prevent generation of immediate reset.
(+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
@@ -121,17 +132,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -427,5 +427,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_adc.c b/Src/stm32h7xx_ll_adc.c
index 1ce67c4..6c96f9d 100644
--- a/Src/stm32h7xx_ll_adc.c
+++ b/Src/stm32h7xx_ll_adc.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -823,6 +822,19 @@
/* - Set ADC data resolution */
/* - Set ADC conversion data alignment */
/* - Set ADC low power mode */
+#if defined(ADC_VER_V5_V90)
+ if(ADCx==ADC3)
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC3_CFGR_RES
+ | ADC_CFGR_AUTDLY
+ ,
+ ((__LL_ADC12_RESOLUTION_TO_ADC3(ADC_InitStruct->Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL)
+ | ADC_InitStruct->LowPowerMode
+ );
+ }
+ else
+ {
MODIFY_REG(ADCx->CFGR,
ADC_CFGR_RES
| ADC_CFGR_AUTDLY
@@ -830,6 +842,16 @@
ADC_InitStruct->Resolution
| ADC_InitStruct->LowPowerMode
);
+ }
+#else
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_RES
+ | ADC_CFGR_AUTDLY
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->LowPowerMode
+ );
+#endif
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift);
}
@@ -900,6 +922,11 @@
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
@@ -1121,4 +1148,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_bdma.c b/Src/stm32h7xx_ll_bdma.c
index d9dfcb7..4abaed3 100644
--- a/Src/stm32h7xx_ll_bdma.c
+++ b/Src/stm32h7xx_ll_bdma.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -343,4 +342,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_comp.c b/Src/stm32h7xx_ll_comp.c
index ad5d4d5..f14b2e7 100644
--- a/Src/stm32h7xx_ll_comp.c
+++ b/Src/stm32h7xx_ll_comp.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -293,4 +292,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_cordic.c b/Src/stm32h7xx_ll_cordic.c
index 7166551..3854c63 100644
--- a/Src/stm32h7xx_ll_cordic.c
+++ b/Src/stm32h7xx_ll_cordic.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -101,5 +100,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_crc.c b/Src/stm32h7xx_ll_crc.c
index 17cdb64..e1f29c0 100644
--- a/Src/stm32h7xx_ll_crc.c
+++ b/Src/stm32h7xx_ll_crc.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -26,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
@@ -81,7 +80,7 @@
/* Release CRC reset */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
-#endif/*LL_AHB4_GRP1_PERIPH_CRC)*/
+#endif /*LL_AHB4_GRP1_PERIPH_CRC)*/
}
else
{
@@ -110,6 +109,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32h7xx_ll_crs.c b/Src/stm32h7xx_ll_crs.c
index e6553d6..e2977e4 100644
--- a/Src/stm32h7xx_ll_crs.c
+++ b/Src/stm32h7xx_ll_crs.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -82,5 +81,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_dac.c b/Src/stm32h7xx_ll_dac.c
index c27d64b..29c3ca9 100644
--- a/Src/stm32h7xx_ll_dac.c
+++ b/Src/stm32h7xx_ll_dac.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -345,4 +344,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_delayblock.c b/Src/stm32h7xx_ll_delayblock.c
index 5021dde..ccb4f4f 100644
--- a/Src/stm32h7xx_ll_delayblock.c
+++ b/Src/stm32h7xx_ll_delayblock.c
@@ -8,7 +8,18 @@
* functionalities of the Delay Block peripheral:
* + input clock frequency range 25MHz to 208MHz
* + up to 12 oversampling phases
- *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### DelayBlock peripheral features #####
@@ -34,19 +45,7 @@
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
@@ -207,4 +206,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_dma.c b/Src/stm32h7xx_ll_dma.c
index 9db91e9..b7e32d2 100644
--- a/Src/stm32h7xx_ll_dma.c
+++ b/Src/stm32h7xx_ll_dma.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -422,4 +421,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_dma2d.c b/Src/stm32h7xx_ll_dma2d.c
index 0805f00..e79d451 100644
--- a/Src/stm32h7xx_ll_dma2d.c
+++ b/Src/stm32h7xx_ll_dma2d.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -633,6 +632,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32h7xx_ll_exti.c b/Src/stm32h7xx_ll_exti.c
index b9ecde5..5e3a198 100644
--- a/Src/stm32h7xx_ll_exti.c
+++ b/Src/stm32h7xx_ll_exti.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -455,4 +454,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_fmac.c b/Src/stm32h7xx_ll_fmac.c
index 337d4f7..74be426 100644
--- a/Src/stm32h7xx_ll_fmac.c
+++ b/Src/stm32h7xx_ll_fmac.c
@@ -2,17 +2,16 @@
******************************************************************************
* @file stm32h7xx_ll_fmac.c
* @author MCD Application Team
- * @brief FMAC LL module driver.
+ * @brief Header for stm32h7xx_ll_fmac.c module
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -37,41 +36,13 @@
* @{
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup FMAC_LL_Private_Macros
- * @{
- */
-
-/** @brief Check if the watermark value is a valid one.
- * @param __VALUE__ Watermak value.
- * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
- */
-#define IS_LL_FMAC_WM(__VALUE__) (((__VALUE__) == LL_FMAC_WM_0_THRESHOLD_1) \
- || ((__VALUE__) == LL_FMAC_WM_1_THRESHOLD_2) \
- || ((__VALUE__) == LL_FMAC_WM_2_THRESHOLD_4) \
- || ((__VALUE__) == LL_FMAC_WM_3_THRESHOLD_8))
-
-/** @brief Check if the function ID is a valid one.
- * @param __VALUE__ Function ID.
- * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
- */
-#define IS_LL_FMAC_FUNC(__VALUE__) (((__VALUE__) == LL_FMAC_FUNC_LOAD_X1) \
- || ((__VALUE__) == LL_FMAC_FUNC_LOAD_X2) \
- || ((__VALUE__) == LL_FMAC_FUNC_LOAD_Y) \
- || ((__VALUE__) == LL_FMAC_FUNC_CONVO_FIR) \
- || ((__VALUE__) == LL_FMAC_FUNC_IIR_DIRECT_FORM_1))
-
-
-/**
- * @}
- */
-
+/* Private variables ---------------------------------------------------------*/
+/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
/** @addtogroup FMAC_LL_Exported_Functions
* @{
*/
@@ -83,7 +54,7 @@
/**
* @brief Initialize FMAC peripheral registers to their default reset values.
* @param FMACx FMAC Instance
- * @retval An ErrorStatus enumeration value:
+ * @retval ErrorStatus enumeration value:
* - SUCCESS: FMAC registers are initialized
* - ERROR: FMAC registers are not initialized
*/
@@ -163,5 +134,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_fmc.c b/Src/stm32h7xx_ll_fmc.c
index 452d5e9..eb53261 100644
--- a/Src/stm32h7xx_ll_fmc.c
+++ b/Src/stm32h7xx_ll_fmc.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### FMC peripheral features #####
@@ -41,17 +52,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -988,10 +988,10 @@
assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
/* Set command register */
- MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 |
- FMC_SDCMR_NRFS | FMC_SDCMR_MRD), ((Command->CommandMode) |
- (Command->CommandTarget) | (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
- ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
+ MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
+ ((Command->CommandMode) | (Command->CommandTarget) |
+ (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
+ ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
/* Prevent unused argument(s) compilation warning */
UNUSED(Timeout);
return HAL_OK;
@@ -1089,5 +1089,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_gpio.c b/Src/stm32h7xx_ll_gpio.c
index 5a809db..f48c346 100644
--- a/Src/stm32h7xx_ll_gpio.c
+++ b/Src/stm32h7xx_ll_gpio.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -303,5 +302,4 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_hrtim.c b/Src/stm32h7xx_ll_hrtim.c
index 47adce6..1ee8c0a 100644
--- a/Src/stm32h7xx_ll_hrtim.c
+++ b/Src/stm32h7xx_ll_hrtim.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -79,5 +78,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_i2c.c b/Src/stm32h7xx_ll_i2c.c
index 09e20cb..34ae9d8 100644
--- a/Src/stm32h7xx_ll_i2c.c
+++ b/Src/stm32h7xx_ll_i2c.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -25,7 +24,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
@@ -133,7 +132,7 @@
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C5);
}
-#endif
+#endif /* I2C5 */
else
{
status = ERROR;
@@ -249,5 +248,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_lptim.c b/Src/stm32h7xx_ll_lptim.c
index bf08c46..a2a870d 100644
--- a/Src/stm32h7xx_ll_lptim.c
+++ b/Src/stm32h7xx_ll_lptim.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -28,7 +27,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
@@ -215,12 +214,15 @@
uint32_t tmpCFGR;
uint32_t tmpCMP;
uint32_t tmpARR;
+ uint32_t primask_bit;
uint32_t tmpCFGR2;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
- __disable_irq();
+ /* Enter critical section */
+ primask_bit = __get_PRIMASK();
+ __set_PRIMASK(1) ;
/********** Save LPTIM Config *********/
/* Save LPTIM source clock */
@@ -328,7 +330,8 @@
LPTIMx->CFGR = tmpCFGR;
LPTIMx->CFGR2 = tmpCFGR2;
- __enable_irq();
+ /* Exit critical section: restore previous priority mask */
+ __set_PRIMASK(primask_bit);
}
/**
@@ -350,5 +353,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_lpuart.c b/Src/stm32h7xx_ll_lpuart.c
index 7ff5441..335dc18 100644
--- a/Src/stm32h7xx_ll_lpuart.c
+++ b/Src/stm32h7xx_ll_lpuart.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -281,6 +280,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32h7xx_ll_mdma.c b/Src/stm32h7xx_ll_mdma.c
index 1c33f82..c57e98d 100644
--- a/Src/stm32h7xx_ll_mdma.c
+++ b/Src/stm32h7xx_ll_mdma.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -806,4 +805,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_opamp.c b/Src/stm32h7xx_ll_opamp.c
index 5b8937b..ffbb548 100644
--- a/Src/stm32h7xx_ll_opamp.c
+++ b/Src/stm32h7xx_ll_opamp.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -227,4 +226,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_pwr.c b/Src/stm32h7xx_ll_pwr.c
index 28ce161..86b029a 100644
--- a/Src/stm32h7xx_ll_pwr.c
+++ b/Src/stm32h7xx_ll_pwr.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -83,4 +82,3 @@
#endif /* defined (USE_FULL_LL_DRIVER) */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_rcc.c b/Src/stm32h7xx_ll_rcc.c
index 68ed42a..b838723 100644
--- a/Src/stm32h7xx_ll_rcc.c
+++ b/Src/stm32h7xx_ll_rcc.c
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
@@ -1786,4 +1784,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_rng.c b/Src/stm32h7xx_ll_rng.c
index a98addf..d69312b 100644
--- a/Src/stm32h7xx_ll_rng.c
+++ b/Src/stm32h7xx_ll_rng.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -42,7 +41,7 @@
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RNG_LL_Private_Macros
+/** @defgroup RNG_LL_Private_Macros RNG Private Macros
* @{
*/
#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
@@ -84,14 +83,24 @@
*/
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
{
+ ErrorStatus status = SUCCESS;
+
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
- /* Enable RNG reset state */
- LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
+ if (RNGx == RNG)
+ {
+ /* Enable RNG reset state */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
- /* Release RNG from reset state */
- LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
- return (SUCCESS);
+ /* Release RNG from reset state */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
}
/**
@@ -154,5 +163,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Src/stm32h7xx_ll_rtc.c b/Src/stm32h7xx_ll_rtc.c
index 613cd55..515fe42 100644
--- a/Src/stm32h7xx_ll_rtc.c
+++ b/Src/stm32h7xx_ll_rtc.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -87,18 +86,7 @@
#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
-#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
- || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
- || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
- || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
- || ((__VALUE__) == LL_RTC_MONTH_MAY) \
- || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
- || ((__VALUE__) == LL_RTC_MONTH_JULY) \
- || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
- || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
- || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
- || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
- || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
@@ -343,7 +331,7 @@
}
/* Exit Initialization mode */
- LL_RTC_DisableInitMode(RTC);
+ LL_RTC_DisableInitMode(RTCx);
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
@@ -431,7 +419,7 @@
}
/* Exit Initialization mode */
- LL_RTC_DisableInitMode(RTC);
+ LL_RTC_DisableInitMode(RTCx);
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
@@ -891,4 +879,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_sdmmc.c b/Src/stm32h7xx_ll_sdmmc.c
index 36c52c3..bd2cd5f 100644
--- a/Src/stm32h7xx_ll_sdmmc.c
+++ b/Src/stm32h7xx_ll_sdmmc.c
@@ -11,6 +11,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### SDMMC peripheral features #####
@@ -137,17 +148,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1060,6 +1060,31 @@
}
/**
+ * @brief Send the Sleep command to MMC card (not SD card).
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param Argument Argument of the command (RCA and Sleep/Awake)
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_MMC_SLEEP_AWAKE;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
* @brief Send the Status command and check the response.
* @param SDMMCx: Pointer to SDMMC register base
* @param Argument: Command Argument
@@ -1542,7 +1567,7 @@
if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
- /* Card is SD V2.0 compliant */
+ /* Card is not SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
@@ -1550,7 +1575,7 @@
else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
- /* Card is SD V2.0 compliant */
+ /* Card is not SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
return SDMMC_ERROR_CMD_CRC_FAIL;
@@ -1617,5 +1642,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_spi.c b/Src/stm32h7xx_ll_spi.c
index 57f63a7..879ed23 100644
--- a/Src/stm32h7xx_ll_spi.c
+++ b/Src/stm32h7xx_ll_spi.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -29,7 +28,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32H7xx_LL_Driver
* @{
@@ -49,172 +48,172 @@
* @{
*/
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
- || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \
+ ((__VALUE__) == LL_SPI_MODE_SLAVE))
-#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) \
- || ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
+#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
+ ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
-#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) \
- || ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
+#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
+ ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
-#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) \
- || ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
+#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
+ ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
-#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) \
- || ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
+#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
+ ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
-#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) \
- || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) \
- || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
+#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
+ ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \
+ ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
-#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) \
- || ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) \
- || ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
+#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
+ ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \
+ ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
-#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) \
- || ((__VALUE__) == LL_SPI_PROTOCOL_TI))
+#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \
+ ((__VALUE__) == LL_SPI_PROTOCOL_TI))
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
- || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \
+ ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
- || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \
+ ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \
+ ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
- || ((__VALUE__) == LL_SPI_MSB_FIRST))
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \
+ ((__VALUE__) == LL_SPI_MSB_FIRST))
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_TX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \
+ ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \
+ ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \
+ ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \
+ ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \
+ ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
-#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) \
- || ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
+#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \
+ ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
-#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) \
- || ((__VALUE__) == LL_SPI_CRC_5BIT) \
- || ((__VALUE__) == LL_SPI_CRC_6BIT) \
- || ((__VALUE__) == LL_SPI_CRC_7BIT) \
- || ((__VALUE__) == LL_SPI_CRC_8BIT) \
- || ((__VALUE__) == LL_SPI_CRC_9BIT) \
- || ((__VALUE__) == LL_SPI_CRC_10BIT) \
- || ((__VALUE__) == LL_SPI_CRC_11BIT) \
- || ((__VALUE__) == LL_SPI_CRC_12BIT) \
- || ((__VALUE__) == LL_SPI_CRC_13BIT) \
- || ((__VALUE__) == LL_SPI_CRC_14BIT) \
- || ((__VALUE__) == LL_SPI_CRC_15BIT) \
- || ((__VALUE__) == LL_SPI_CRC_16BIT) \
- || ((__VALUE__) == LL_SPI_CRC_17BIT) \
- || ((__VALUE__) == LL_SPI_CRC_18BIT) \
- || ((__VALUE__) == LL_SPI_CRC_19BIT) \
- || ((__VALUE__) == LL_SPI_CRC_20BIT) \
- || ((__VALUE__) == LL_SPI_CRC_21BIT) \
- || ((__VALUE__) == LL_SPI_CRC_22BIT) \
- || ((__VALUE__) == LL_SPI_CRC_23BIT) \
- || ((__VALUE__) == LL_SPI_CRC_24BIT) \
- || ((__VALUE__) == LL_SPI_CRC_25BIT) \
- || ((__VALUE__) == LL_SPI_CRC_26BIT) \
- || ((__VALUE__) == LL_SPI_CRC_27BIT) \
- || ((__VALUE__) == LL_SPI_CRC_28BIT) \
- || ((__VALUE__) == LL_SPI_CRC_29BIT) \
- || ((__VALUE__) == LL_SPI_CRC_30BIT) \
- || ((__VALUE__) == LL_SPI_CRC_31BIT) \
- || ((__VALUE__) == LL_SPI_CRC_32BIT))
+#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_5BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_6BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_7BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_8BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_9BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_10BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_11BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_12BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_13BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_14BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_15BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_16BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_17BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_18BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_19BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_20BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_21BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_22BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_23BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_24BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_25BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_26BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_27BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_28BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_29BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_30BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_31BIT) || \
+ ((__VALUE__) == LL_SPI_CRC_32BIT))
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \
+ ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \
+ ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) \
- || ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) \
- || ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) \
- || ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
+#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \
+ ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \
+ ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \
+ ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
- || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \
+ ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
@@ -256,6 +255,7 @@
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+ /* Update the return status */
status = SUCCESS;
}
#endif /* SPI1 */
@@ -268,6 +268,7 @@
/* Release reset of SPI clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+ /* Update the return status */
status = SUCCESS;
}
#endif /* SPI2 */
@@ -280,6 +281,7 @@
/* Release reset of SPI clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+ /* Update the return status */
status = SUCCESS;
}
#endif /* SPI3 */
@@ -292,6 +294,7 @@
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+ /* Update the return status */
status = SUCCESS;
}
#endif /* SPI4 */
@@ -304,6 +307,7 @@
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
+ /* Update the return status */
status = SUCCESS;
}
#endif /* SPI5 */
@@ -316,6 +320,7 @@
/* Release reset of SPI clock */
LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
+ /* Update the return status */
status = SUCCESS;
}
#endif /* SPI6 */
@@ -325,8 +330,9 @@
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled
+ * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
+ * Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
@@ -351,6 +357,7 @@
assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+ /* Check the SPI instance is not enabled */
if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
{
/*---------------------------- SPIx CFG1 Configuration ------------------------
@@ -359,20 +366,17 @@
* - CRC Computation Enable : SPI_CFG1_CRCEN bit
* - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
*/
- MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
+ MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
tmp_nss = SPI_InitStruct->NSS;
tmp_mode = SPI_InitStruct->Mode;
/* Checks to setup Internal SS signal level and avoid a MODF Error */
- if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_MASTER))
- {
- LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
- }
-
- /* Checks to setup Internal SS signal to the active level in Slave Mode */
- if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_SLAVE))
+ if ((tmp_nss == LL_SPI_NSS_SOFT) && (((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && \
+ (tmp_mode == LL_SPI_MODE_MASTER)) || \
+ ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \
+ (tmp_mode == LL_SPI_MODE_SLAVE))))
{
LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
}
@@ -389,8 +393,8 @@
MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
SPI_CFG2_CPOL | SPI_CFG2_CPHA |
SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
- SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
- SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
+ SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
+ SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
/*---------------------------- SPIx CR1 Configuration ------------------------
@@ -442,15 +446,14 @@
/**
* @}
*/
-
-/**
- * @}
- */
-
+
/**
* @}
*/
+/**
+ * @}
+ */
/** @addtogroup I2S_LL
* @{
*/
@@ -475,54 +478,54 @@
* @{
*/
-#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \
+ ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \
+ ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \
+ ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) \
- || ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
+#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \
+ ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
-#define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
- || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+#define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \
+ ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
- || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \
+ ((__VALUE__) == LL_I2S_STANDARD_MSB) || \
+ ((__VALUE__) == LL_I2S_STANDARD_LSB) || \
+ ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \
+ ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_RX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \
+ ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \
+ ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \
+ ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \
+ ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \
+ ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
- || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \
+ ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
- && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
- || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \
+ ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \
+ ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
- || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \
+ ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-#define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) \
- || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) \
- || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) \
- || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) \
- || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) \
- || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) \
- || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) \
- || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
+#define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \
+ ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \
+ ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \
+ ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \
+ ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \
+ ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \
+ ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \
+ ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
-#define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) \
- || ((__VALUE__) == LL_I2S_MSB_FIRST))
+#define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \
+ ((__VALUE__) == LL_I2S_MSB_FIRST))
/**
* @}
*/
@@ -552,9 +555,11 @@
/**
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
- * @note As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming.
+ * @note As some bits in I2S configuration registers can only be written when the SPI is disabled
+ * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
+ * Otherwise, ERROR result will be returned.
+ * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results
+ * in wrong programming.
* @param SPIx SPI Instance
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -563,9 +568,13 @@
*/
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
{
- uint32_t i2sdiv = 0UL, i2sodd = 0UL, packetlength = 1UL, ispcm = 0UL;
+ uint32_t i2sdiv = 0UL;
+ uint32_t i2sodd = 0UL;
+ uint32_t packetlength = 1UL;
+ uint32_t ispcm = 0UL;
uint32_t tmp;
- uint32_t sourceclock;
+ uint32_t sourceclock = 0UL;
+
ErrorStatus status = ERROR;
/* Check the I2S parameters */
@@ -638,7 +647,7 @@
}
#else
sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
-#endif
+#endif /* SPI_SPI6I2S_SUPPORT */
/* Compute the Real divider depending on the MCLK output state with a fixed point */
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
@@ -740,5 +749,3 @@
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_swpmi.c b/Src/stm32h7xx_ll_swpmi.c
index e2b38b5..20c2c5e 100644
--- a/Src/stm32h7xx_ll_swpmi.c
+++ b/Src/stm32h7xx_ll_swpmi.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -99,8 +98,9 @@
/**
* @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
- * @note As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0),
- * SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated
+ * (SWPMI_CR_SWPACT bit = 0), the SWPMI peripheral should be in deactivated state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @param SWPMIx SWPMI Instance
* @param SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
* the configuration information for the SWPMI peripheral.
@@ -130,8 +130,8 @@
/* Set the new configuration of the SWPMI peripheral */
MODIFY_REG(SWPMIx->CR,
- (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
- (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
+ (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
+ (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
}
/* Else (SWPMI not in deactivated state => return ERROR) */
else
@@ -175,5 +175,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_tim.c b/Src/stm32h7xx_ll_tim.c
index 688f0c1..0d7e018 100644
--- a/Src/stm32h7xx_ll_tim.c
+++ b/Src/stm32h7xx_ll_tim.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -149,6 +148,11 @@
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+#if defined(TIM_BDTR_BKBID)
+
+#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
+ || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
+#endif /* TIM_BDTR_BKBID */
#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
|| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
@@ -172,6 +176,11 @@
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
|| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+#if defined(TIM_BDTR_BKBID)
+
+#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
+ || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+#endif /*TIM_BDTR_BKBID */
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
|| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
@@ -232,91 +241,91 @@
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
}
-#endif
+#endif /* TIM2 */
#if defined(TIM3)
else if (TIMx == TIM3)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
}
-#endif
+#endif /* TIM3 */
#if defined(TIM4)
else if (TIMx == TIM4)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
}
-#endif
+#endif /* TIM4 */
#if defined(TIM5)
else if (TIMx == TIM5)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
}
-#endif
+#endif /* TIM5 */
#if defined(TIM6)
else if (TIMx == TIM6)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
}
-#endif
+#endif /* TIM6 */
#if defined (TIM7)
else if (TIMx == TIM7)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
}
-#endif
+#endif /* TIM7 */
#if defined(TIM8)
else if (TIMx == TIM8)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
}
-#endif
+#endif /* TIM8 */
#if defined(TIM12)
else if (TIMx == TIM12)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
}
-#endif
+#endif /* TIM12 */
#if defined(TIM13)
else if (TIMx == TIM13)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
}
-#endif
+#endif /* TIM13 */
#if defined(TIM14)
else if (TIMx == TIM14)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
}
-#endif
+#endif /* TIM14 */
#if defined(TIM15)
else if (TIMx == TIM15)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
}
-#endif
+#endif /* TIM15 */
#if defined(TIM16)
else if (TIMx == TIM16)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
}
-#endif
+#endif /* TIM16 */
#if defined(TIM17)
else if (TIMx == TIM17)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
}
-#endif
+#endif /* TIM17 */
else
{
result = ERROR;
@@ -344,7 +353,8 @@
/**
* @brief Configure the TIMx time base unit.
* @param TIMx Timer Instance
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+ * (TIMx time base unit configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
@@ -397,7 +407,8 @@
/**
* @brief Set the fields of the TIMx output channel configuration data
* structure to their default values.
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+ * (the output channel configuration data structure)
* @retval None
*/
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
@@ -423,7 +434,8 @@
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+ * data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx output channel is initialized
* - ERROR: TIMx output channel is not initialized
@@ -462,7 +474,8 @@
/**
* @brief Set the fields of the TIMx input channel configuration data
* structure to their default values.
- * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+ * data structure)
* @retval None
*/
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
@@ -482,7 +495,8 @@
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+ * structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx output channel is initialized
* - ERROR: TIMx output channel is not initialized
@@ -514,7 +528,8 @@
/**
* @brief Fills each TIM_EncoderInitStruct field with its default value
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+ * configuration data structure)
* @retval None
*/
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
@@ -534,7 +549,8 @@
/**
* @brief Configure the encoder interface of the timer instance.
* @param TIMx Timer Instance
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+ * configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
@@ -598,7 +614,8 @@
/**
* @brief Set the fields of the TIMx Hall sensor interface configuration data
* structure to their default values.
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+ * configuration data structure)
* @retval None
*/
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
@@ -625,7 +642,8 @@
* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
* when TIMx operates in Hall sensor interface mode.
* @param TIMx Timer Instance
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+ * interface configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: not applicable
@@ -705,7 +723,8 @@
/**
* @brief Set the fields of the Break and Dead Time configuration data structure
* to their default values.
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
* @retval None
*/
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
@@ -718,9 +737,15 @@
TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
+#if defined(TIM_BDTR_BKBID)
+ TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
+#endif /*TIM_BDTR_BKBID */
TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
+#if defined(TIM_BDTR_BKBID)
+ TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
+#endif /*TIM_BDTR_BKBID */
TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
}
@@ -735,7 +760,8 @@
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+ * data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Break and Dead Time is initialized
* - ERROR: not applicable
@@ -765,22 +791,38 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+#if defined(TIM_BDTR_BKBID)
+ if (IS_TIM_ADVANCED_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
+ }
+#else
if (IS_TIM_ADVANCED_INSTANCE(TIMx))
{
assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
}
+#endif /*TIM_BDTR_BKBID */
if (IS_TIM_BKIN2_INSTANCE(TIMx))
{
assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+#if defined(TIM_BDTR_BKBID)
+ assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
+#endif /*TIM_BDTR_BKBID */
/* Set the BREAK2 input related BDTR bit-fields */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+#if defined(TIM_BDTR_BKBID)
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
+#endif /*TIM_BDTR_BKBID */
}
/* Set TIMx_BDTR */
@@ -1377,4 +1419,3 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_usart.c b/Src/stm32h7xx_ll_usart.c
index 2dc28f0..da9dfa8 100644
--- a/Src/stm32h7xx_ll_usart.c
+++ b/Src/stm32h7xx_ll_usart.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -481,5 +480,4 @@
#endif /* USE_FULL_LL_DRIVER */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_usb.c b/Src/stm32h7xx_ll_usb.c
index 4894066..5f7412b 100644
--- a/Src/stm32h7xx_ll_usb.c
+++ b/Src/stm32h7xx_ll_usb.c
@@ -11,6 +11,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -23,17 +34,7 @@
(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+
******************************************************************************
*/
@@ -82,7 +83,6 @@
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
HAL_StatusTypeDef ret;
-
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
@@ -252,21 +252,39 @@
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
{
+ uint32_t ms = 0U;
+
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
if (mode == USB_HOST_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
}
else if (mode == USB_DEVICE_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+ do
+ {
+ HAL_Delay(1U);
+ ms++;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
}
else
{
return HAL_ERROR;
}
- HAL_Delay(50U);
+
+ if (ms == 50U)
+ {
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -427,7 +445,7 @@
}
/**
- * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
+ * @brief USB_FlushTxFifo Flush a Tx FIFO
* @param USBx Selected device
* @param num FIFO number
* This parameter can be a value from 1 to 15
@@ -436,8 +454,19 @@
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
+ /* Wait for AHB master IDLE state. */
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+ /* Flush TX Fifo */
+ count = 0U;
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
do
@@ -452,14 +481,25 @@
}
/**
- * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
- uint32_t count = 0;
+ __IO uint32_t count = 0U;
+ /* Wait for AHB master IDLE state. */
+ do
+ {
+ if (++count > 200000U)
+ {
+ return HAL_TIMEOUT;
+ }
+ } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+ /* Flush RX Fifo */
+ count = 0U;
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
do
@@ -720,7 +760,9 @@
*/
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
+ (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
if (ep->type == EP_TYPE_ISOC)
@@ -924,6 +966,60 @@
return HAL_OK;
}
+
+/**
+ * @brief USB_EPStoptXfer Stop transfer on an EP
+ * @param USBx usb device instance
+ * @param ep pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+ __IO uint32_t count = 0U;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /* EP enable, IN data in FIFO */
+ if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+ {
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
+
+ do
+ {
+ if (++count > 10000U)
+ {
+ ret = HAL_ERROR;
+ break;
+ }
+ } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
+ }
+ }
+ else /* OUT endpoint */
+ {
+ if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
+
+ do
+ {
+ if (++count > 10000U)
+ {
+ ret = HAL_ERROR;
+ break;
+ }
+ } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
+ }
+ }
+
+ return ret;
+}
+
+
/**
* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
* with the EP/channel
@@ -942,7 +1038,8 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t *pSrc = src;
- uint32_t count32b, i;
+ uint32_t count32b;
+ uint32_t i;
if (dma == 0U)
{
@@ -990,7 +1087,7 @@
{
i = 0U;
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
-
+
do
{
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
@@ -1229,7 +1326,9 @@
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t tmpreg, msk, emp;
+ uint32_t tmpreg;
+ uint32_t msk;
+ uint32_t emp;
msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK;
@@ -1325,7 +1424,7 @@
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
/* Wait for AHB master IDLE state. */
do
@@ -1361,6 +1460,7 @@
*/
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
+ HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
@@ -1394,8 +1494,15 @@
}
/* Make sure the FIFOs are flushed. */
- (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
- (void)USB_FlushRxFifo(USBx);
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+ {
+ ret = HAL_ERROR;
+ }
+
+ if (USB_FlushRxFifo(USBx) != HAL_OK)
+ {
+ ret = HAL_ERROR;
+ }
/* Clear all pending HC Interrupts */
for (i = 0U; i < cfg.Host_channels; i++)
@@ -1404,11 +1511,6 @@
USBx_HC(i)->HCINTMSK = 0U;
}
- /* Enable VBUS driving */
- (void)USB_DriveVbus(USBx, 1U);
-
- HAL_Delay(200U);
-
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
@@ -1441,7 +1543,7 @@
USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
- return HAL_OK;
+ return ret;
}
/**
@@ -1592,7 +1694,8 @@
{
HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t HCcharEpDir, HCcharLowSpeed;
+ uint32_t HCcharEpDir;
+ uint32_t HCcharLowSpeed;
uint32_t HostCoreSpeed;
/* Clear old interrupt conditions for this host channel. */
@@ -1657,6 +1760,9 @@
break;
}
+ /* Enable host channel Halt interrupt */
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
+
/* Enable the top level host channel interrupt. */
USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
@@ -1865,7 +1971,7 @@
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t hcnum = (uint32_t)hc_num;
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
@@ -1886,7 +1992,6 @@
{
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{
if (++count > 1000U)
@@ -1909,7 +2014,6 @@
{
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{
if (++count > 1000U)
@@ -1960,16 +2064,24 @@
*/
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
{
+ HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t count = 0U;
+ __IO uint32_t count = 0U;
uint32_t value;
uint32_t i;
(void)USB_DisableGlobalInt(USBx);
- /* Flush FIFO */
- (void)USB_FlushTxFifo(USBx, 0x10U);
- (void)USB_FlushRxFifo(USBx);
+ /* Flush USB FIFO */
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+ {
+ ret = HAL_ERROR;
+ }
+
+ if (USB_FlushRxFifo(USBx) != HAL_OK)
+ {
+ ret = HAL_ERROR;
+ }
/* Flush out any leftover queued requests. */
for (i = 0U; i <= 15U; i++)
@@ -2005,7 +2117,7 @@
(void)USB_EnableGlobalInt(USBx);
- return HAL_OK;
+ return ret;
}
/**
@@ -2056,5 +2168,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32h7xx_ll_utils.c b/Src/stm32h7xx_ll_utils.c
index 00c3975..865129e 100644
--- a/Src/stm32h7xx_ll_utils.c
+++ b/Src/stm32h7xx_ll_utils.c
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1071,4 +1070,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
