Release v1.0.4
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index e57e823..5ade8e1 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -383,7 +382,6 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
-
/**
* @}
*/
@@ -604,16 +602,16 @@
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@@ -774,49 +772,6 @@
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-/** @brief Constants defining the events that can be selected to configure the
- * set/reset crossbar of a timer output
- */
-#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
-#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
-#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
-#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
-#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
-#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
-#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
-#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
-#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
-
-#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
-#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
-#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
-#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
-#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
-#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
-#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
-#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
-#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
-
-/** @brief Constants defining the event filtering applied to external events
- * by a timer
- */
-#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
@@ -896,7 +851,6 @@
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
/**
* @}
*/
@@ -969,6 +923,11 @@
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
/**
* @}
@@ -980,15 +939,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
- #define I2S_IT_TXE I2S_IT_TXP
- #define I2S_IT_RXNE I2S_IT_RXP
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
- #define I2S_FLAG_TXE I2S_FLAG_TXP
- #define I2S_FLAG_RXNE I2S_FLAG_RXP
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
@@ -1023,7 +982,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1123,16 +1082,16 @@
#if defined(STM32H7)
- #define SPI_FLAG_TXE SPI_FLAG_TXP
- #define SPI_FLAG_RXNE SPI_FLAG_RXP
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
- #define SPI_IT_TXE SPI_IT_TXP
- #define SPI_IT_RXNE SPI_IT_RXP
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
- #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
- #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
- #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
- #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
@@ -1459,7 +1418,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@@ -1481,7 +1440,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1495,7 +1454,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1503,7 +1463,8 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
@@ -1526,9 +1487,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
@@ -1538,7 +1499,8 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
@@ -1563,9 +1525,9 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
@@ -1620,9 +1582,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@@ -1871,15 +1833,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@@ -2090,8 +2052,8 @@
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
@@ -2147,7 +2109,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
- #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
@@ -2284,7 +2246,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -3252,7 +3215,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3381,7 +3344,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3401,19 +3364,19 @@
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
@@ -3597,6 +3560,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index 6793b0e..15c12f1 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -24,7 +24,7 @@
#define STM32_ASSERT_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
diff --git a/Inc/stm32l5xx_hal.h b/Inc/stm32l5xx_hal.h
index a587772..b80a298 100644
--- a/Inc/stm32l5xx_hal.h
+++ b/Inc/stm32l5xx_hal.h
@@ -23,7 +23,7 @@
#define STM32L5xx_HAL_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -204,8 +204,8 @@
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
/**
- * @}
- */
+ * @}
+ */
/** @defgroup SYSCFG_Lock_items SYSCFG Lock items
* @brief SYSCFG items to set lock on
@@ -395,7 +395,7 @@
*/
#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
- }while(0)
+ }while(0)
/** @brief SRAM2 page 32 to 63 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
@@ -403,7 +403,7 @@
*/
#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
- }while(0)
+ }while(0)
/** @brief SRAM2 page write protection unlock prior to erase
* @note Writing a wrong key reactivates the write protection
@@ -422,11 +422,11 @@
*/
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
- }while(0)
+ }while(0)
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
- }while(0)
+ }while(0)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
@@ -459,7 +459,8 @@
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
+ & (__FLAG__))!= 0U) ? 1U : 0U)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
@@ -587,7 +588,7 @@
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
diff --git a/Inc/stm32l5xx_hal_conf_template.h b/Inc/stm32l5xx_hal_conf_template.h
index cd47676..104ab9d 100644
--- a/Inc/stm32l5xx_hal_conf_template.h
+++ b/Inc/stm32l5xx_hal_conf_template.h
@@ -24,7 +24,7 @@
#define STM32L5xx_HAL_CONF_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
@@ -86,11 +86,11 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
- #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */
+#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
+#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -98,7 +98,7 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
- #define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
+#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
@@ -107,7 +107,7 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/
+#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@@ -118,7 +118,7 @@
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
- #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
@@ -126,20 +126,20 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
- #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
+#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature.*/
+The real value may vary depending on the variations
+in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
+#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
+#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -148,7 +148,7 @@
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
- #define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/**
@@ -157,7 +157,7 @@
* frequency.
*/
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
- #define EXTERNAL_SAI2_CLOCK_VALUE 48000UL /*!< Value of the SAI2 External clock source in Hz*/
+#define EXTERNAL_SAI2_CLOCK_VALUE 48000UL /*!< Value of the SAI2 External clock source in Hz*/
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -245,171 +245,171 @@
*/
#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32l5xx_hal_rcc.h"
+#include "stm32l5xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32l5xx_hal_gpio.h"
+#include "stm32l5xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32l5xx_hal_dma.h"
+#include "stm32l5xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32l5xx_hal_dfsdm.h"
+#include "stm32l5xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32l5xx_hal_cortex.h"
+#include "stm32l5xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32l5xx_hal_adc.h"
+#include "stm32l5xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32l5xx_hal_comp.h"
+#include "stm32l5xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32l5xx_hal_crc.h"
+#include "stm32l5xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32l5xx_hal_cryp.h"
+#include "stm32l5xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32l5xx_hal_dac.h"
+#include "stm32l5xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
- #include "stm32l5xx_hal_exti.h"
+#include "stm32l5xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
- #include "stm32l5xx_hal_fdcan.h"
+#include "stm32l5xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32l5xx_hal_flash.h"
+#include "stm32l5xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_GTZC_MODULE_ENABLED
- #include "stm32l5xx_hal_gtzc.h"
+#include "stm32l5xx_hal_gtzc.h"
#endif /* HAL_GTZC_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32l5xx_hal_hash.h"
+#include "stm32l5xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l5xx_hal_i2c.h"
+#include "stm32l5xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_ICACHE_MODULE_ENABLED
- #include "stm32l5xx_hal_icache.h"
+#include "stm32l5xx_hal_icache.h"
#endif /* HAL_ICACHE_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l5xx_hal_irda.h"
+#include "stm32l5xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l5xx_hal_iwdg.h"
+#include "stm32l5xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32l5xx_hal_lptim.h"
+#include "stm32l5xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32l5xx_hal_mmc.h"
+#include "stm32l5xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32l5xx_hal_nand.h"
+#include "stm32l5xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32l5xx_hal_nor.h"
+#include "stm32l5xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32l5xx_hal_opamp.h"
+#include "stm32l5xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
- #include "stm32l5xx_hal_ospi.h"
+#include "stm32l5xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_OTFDEC_MODULE_ENABLED
- #include "stm32l5xx_hal_otfdec.h"
+#include "stm32l5xx_hal_otfdec.h"
#endif /* HAL_OTFDEC_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l5xx_hal_pcd.h"
+#include "stm32l5xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PKA_MODULE_ENABLED
- #include "stm32l5xx_hal_pka.h"
+#include "stm32l5xx_hal_pka.h"
#endif /* HAL_PKA_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l5xx_hal_pwr.h"
+#include "stm32l5xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l5xx_hal_rng.h"
+#include "stm32l5xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l5xx_hal_rtc.h"
+#include "stm32l5xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32l5xx_hal_sai.h"
+#include "stm32l5xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l5xx_hal_sd.h"
+#include "stm32l5xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l5xx_hal_smartcard.h"
+#include "stm32l5xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l5xx_hal_smbus.h"
+#include "stm32l5xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l5xx_hal_spi.h"
+#include "stm32l5xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32l5xx_hal_sram.h"
+#include "stm32l5xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l5xx_hal_tim.h"
+#include "stm32l5xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32l5xx_hal_tsc.h"
+#include "stm32l5xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l5xx_hal_uart.h"
+#include "stm32l5xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l5xx_hal_usart.h"
+#include "stm32l5xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l5xx_hal_wwdg.h"
+#include "stm32l5xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
@@ -422,11 +422,11 @@
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t *file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
#else
- #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
diff --git a/Inc/stm32l5xx_hal_cortex.h b/Inc/stm32l5xx_hal_cortex.h
index 2f32f53..568fd18 100644
--- a/Inc/stm32l5xx_hal_cortex.h
+++ b/Inc/stm32l5xx_hal_cortex.h
@@ -37,6 +37,57 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */
+ uint8_t AttributesIndex; /*!< Specifies the memory attributes index.
+ This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+} MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition
+ * @{
+ */
+typedef struct
+{
+ uint8_t Number; /*!< Specifies the number of the memory attributes to configure.
+ This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
+
+ uint8_t Attributes; /*!< Specifies the memory attributes vue.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+
+} MPU_Attributes_InitTypeDef;
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
@@ -67,6 +118,115 @@
* @}
*/
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE 0U
+#define MPU_HARDFAULT_NMI 2U
+#define MPU_PRIVILEGED_DEFAULT 4U
+#define MPU_HFNMI_PRIVDEF 6U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE 1U
+#define MPU_REGION_DISABLE 0U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE 0U
+#define MPU_INSTRUCTION_ACCESS_DISABLE 1U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_NOT_SHAREABLE 0U
+#define MPU_ACCESS_OUTER_SHAREABLE 1U
+#define MPU_ACCESS_INNER_SHAREABLE 3U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_PRIV_RW 0U
+#define MPU_REGION_ALL_RW 1U
+#define MPU_REGION_PRIV_RO 2U
+#define MPU_REGION_ALL_RO 3U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 0U
+#define MPU_REGION_NUMBER1 1U
+#define MPU_REGION_NUMBER2 2U
+#define MPU_REGION_NUMBER3 3U
+#define MPU_REGION_NUMBER4 4U
+#define MPU_REGION_NUMBER5 5U
+#define MPU_REGION_NUMBER6 6U
+#define MPU_REGION_NUMBER7 7U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number
+ * @{
+ */
+#define MPU_ATTRIBUTES_NUMBER0 0U
+#define MPU_ATTRIBUTES_NUMBER1 1U
+#define MPU_ATTRIBUTES_NUMBER2 2U
+#define MPU_ATTRIBUTES_NUMBER3 3U
+#define MPU_ATTRIBUTES_NUMBER4 4U
+#define MPU_ATTRIBUTES_NUMBER5 5U
+#define MPU_ATTRIBUTES_NUMBER6 6U
+#define MPU_ATTRIBUTES_NUMBER7 7U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
+ * @{
+ */
+#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
+#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
+#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
+#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
+
+#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
+#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
+#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
+
+#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */
+#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
+
+#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
+#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
+#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
+#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
+
+#define OUTER(__ATTR__) ((__ATTR__) << 4U)
+#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U))
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+
/**
* @}
*/
@@ -96,7 +256,6 @@
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-
/**
* @}
*/
@@ -115,6 +274,19 @@
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit);
+void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit);
+#ifdef MPU_NS
+void HAL_MPU_Enable_NS(uint32_t MPU_Control);
+void HAL_MPU_Disable_NS(void);
+void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit);
+void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit);
+#endif /* MPU_NS */
+#endif /* __MPU_PRESENT */
/**
* @}
*/
@@ -144,6 +316,42 @@
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_ALL_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_ALL_RO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \
+ ((NUMBER) == MPU_ATTRIBUTES_NUMBER7))
+
+#endif /* __MPU_PRESENT */
+
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_cryp.h b/Inc/stm32l5xx_hal_cryp.h
index 24db3c7..f024357 100644
--- a/Inc/stm32l5xx_hal_cryp.h
+++ b/Inc/stm32l5xx_hal_cryp.h
@@ -109,7 +109,7 @@
typedef struct
#endif
{
- AES_TypeDef *Instance; /*!< AES Register base address */
+ AES_TypeDef *Instance; /*!< AES Register base address */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
@@ -120,13 +120,13 @@
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
- __IO uint16_t CrypInCount; /*!< Counter of input data */
+ __IO uint16_t CrypInCount; /*!< Counter of input data in words */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data in words */
- uint16_t Size; /*!< length of input data in words */
+ uint16_t Size; /*!< Length of input data */
uint32_t Phase; /*!< CRYP peripheral phase */
diff --git a/Inc/stm32l5xx_hal_def.h b/Inc/stm32l5xx_hal_def.h
index a008233..227247a 100644
--- a/Inc/stm32l5xx_hal_def.h
+++ b/Inc/stm32l5xx_hal_def.h
@@ -23,7 +23,7 @@
#define STM32L5xx_HAL_DEF_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -67,10 +67,10 @@
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
- do{ \
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
- (__DMA_HANDLE__).Parent = (__HANDLE__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0)
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
@@ -90,68 +90,68 @@
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
- /* Reserved for future use */
- #error " USE_RTOS should be 0 in the current HAL release "
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
#else
- #define __HAL_LOCK(__HANDLE__) \
- do{ \
- if((__HANDLE__)->Lock == HAL_LOCKED) \
- { \
- return HAL_BUSY; \
- } \
- else \
- { \
- (__HANDLE__)->Lock = HAL_LOCKED; \
- } \
- }while (0)
+#define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
- #define __HAL_UNLOCK(__HANDLE__) \
- do{ \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0)
+#define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif
- #ifndef __packed
- #define __packed __attribute__((packed))
- #endif
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
#elif defined (__GNUC__) /* GNU Compiler */
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif /* __weak */
- #ifndef __packed
- #define __packed __attribute__((__packed__))
- #endif /* __packed */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
- #ifndef __ALIGN_BEGIN
- #define __ALIGN_BEGIN
- #endif
- #ifndef __ALIGN_END
- #define __ALIGN_END __attribute__((aligned (4)))
- #endif
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned (4)))
+#endif
#elif defined (__GNUC__) /* GNU Compiler */
- #ifndef __ALIGN_END
- #define __ALIGN_END __attribute__((aligned (4)))
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #define __ALIGN_BEGIN
- #endif /* __ALIGN_BEGIN */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__((aligned (4)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
#else
- #ifndef __ALIGN_END
- #define __ALIGN_END
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #if defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #endif /* __ICCARM__ */
- #endif /* __ALIGN_BEGIN */
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined (__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __ICCARM__ */
+#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
diff --git a/Inc/stm32l5xx_hal_exti.h b/Inc/stm32l5xx_hal_exti.h
index 9e6f6fc..12228c3 100644
--- a/Inc/stm32l5xx_hal_exti.h
+++ b/Inc/stm32l5xx_hal_exti.h
@@ -252,22 +252,22 @@
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
- ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))))
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \
- (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
-#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \
- ((__LINE__) == EXTI_TRIGGER_FALLING))
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
+ ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))
-#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U)
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
diff --git a/Inc/stm32l5xx_hal_gtzc.h b/Inc/stm32l5xx_hal_gtzc.h
index cb20b3a..3e1b2ce 100644
--- a/Inc/stm32l5xx_hal_gtzc.h
+++ b/Inc/stm32l5xx_hal_gtzc.h
@@ -348,8 +348,8 @@
/* Private macros ------------------------------------------------------------*/
/** @defgroup GTZC_Private_Macros GTZC Private Macros
- * @{
- */
+ * @{
+ */
/* retrieve information to access register for a specific PeriphId */
#define GTZC_GET_REG_INDEX(periph_id)\
@@ -376,15 +376,15 @@
/* Exported macros -----------------------------------------------------------*/
/** @defgroup GTZC_Exported_Macros GTZC Exported Macros
- * @{
- */
+ * @{
+ */
/* user-oriented macro to get array index of a specific PeriphId
- * in case of GTZC_PERIPH_ALL usage in the two following functions:
- * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
- */
+ * in case of GTZC_PERIPH_ALL usage in the two following functions:
+ * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes()
+ */
#define HAL_GTZC_GET_ARRAY_INDEX(periph_id)\
-( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) )
+ ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) )
/**
* @}
@@ -417,12 +417,10 @@
* @{
*/
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
- uint32_t MemBaseAddress,
- MPCWM_ConfigTypeDef *pMPCWM_Desc);
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
- uint32_t MemBaseAddress,
- MPCWM_ConfigTypeDef *pMPCWM_Desc);
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc);
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_icache.h b/Inc/stm32l5xx_hal_icache.h
index fffefd4..90bb947 100644
--- a/Inc/stm32l5xx_hal_icache.h
+++ b/Inc/stm32l5xx_hal_icache.h
@@ -187,7 +187,7 @@
* @retval The state of __INTERRUPT__ (0 or 1).
*/
#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \
- ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
+ ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
/** @brief Check whether the selected ICACHE flag is set or not.
* @param __FLAG__ specifies the flag to check.
diff --git a/Inc/stm32l5xx_hal_irda.h b/Inc/stm32l5xx_hal_irda.h
index 84194c1..d2aef0d 100644
--- a/Inc/stm32l5xx_hal_irda.h
+++ b/Inc/stm32l5xx_hal_irda.h
@@ -90,7 +90,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -107,7 +107,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
diff --git a/Inc/stm32l5xx_hal_iwdg.h b/Inc/stm32l5xx_hal_iwdg.h
index d1a84d2..e37423e 100644
--- a/Inc/stm32l5xx_hal_iwdg.h
+++ b/Inc/stm32l5xx_hal_iwdg.h
@@ -87,7 +87,6 @@
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-
/**
* @}
*/
@@ -100,7 +99,6 @@
* @}
*/
-
/**
* @}
*/
@@ -138,7 +136,7 @@
* @{
*/
/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
@@ -147,7 +145,7 @@
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_lptim.h b/Inc/stm32l5xx_hal_lptim.h
index c1a2b83..6ab891b 100644
--- a/Inc/stm32l5xx_hal_lptim.h
+++ b/Inc/stm32l5xx_hal_lptim.h
@@ -394,10 +394,10 @@
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -573,7 +573,8 @@
* @retval Interrupt status.
*/
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Enable the LPTIM1 EXTI line in interrupt mode.
@@ -585,7 +586,8 @@
* @brief Disable the LPTIM1 EXTI line in interrupt mode.
* @retval None
*/
-#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_LPTIM1))
+#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR2\
+ &= ~(LPTIM_EXTI_LINE_LPTIM1))
/**
@@ -598,7 +600,8 @@
* @brief Disable the LPTIM1 EXTI line in event mode.
* @retval None
*/
-#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_LPTIM1))
+#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR2\
+ &= ~(LPTIM_EXTI_LINE_LPTIM1))
/**
* @brief Enable the LPTIM2 EXTI line in interrupt mode.
@@ -610,7 +613,8 @@
* @brief Disable the LPTIM2 EXTI line in interrupt mode.
* @retval None
*/
-#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_LPTIM2))
+#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR2\
+ &= ~(LPTIM_EXTI_LINE_LPTIM2))
/**
@@ -623,7 +627,8 @@
* @brief Disable the LPTIM2 EXTI line in event mode.
* @retval None
*/
-#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_LPTIM2))
+#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR2\
+ &= ~(LPTIM_EXTI_LINE_LPTIM2))
/**
* @brief Enable the LPTIM3 EXTI line in interrupt mode.
@@ -635,7 +640,8 @@
* @brief Disable the LPTIM3 EXTI line in interrupt mode.
* @retval None
*/
-#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_LPTIM3))
+#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR2\
+ &= ~(LPTIM_EXTI_LINE_LPTIM3))
/**
@@ -648,7 +654,8 @@
* @brief Disable the LPTIM3 EXTI line in event mode.
* @retval None
*/
-#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_LPTIM3))
+#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_EVENT() (EXTI->EMR2\
+ &= ~(LPTIM_EXTI_LINE_LPTIM3))
/**
* @}
@@ -660,9 +667,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group1
- * @brief Initialization and Configuration functions.
- * @{
- */
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -675,9 +682,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group2
- * @brief Start-Stop operation functions.
- * @{
- */
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -731,9 +738,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group3
- * @brief Read operation functions.
- * @{
- */
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
@@ -743,9 +750,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group4
- * @brief LPTIM IRQ handler and callback functions.
- * @{
- */
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -762,7 +769,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
@@ -770,9 +778,9 @@
*/
/** @addtogroup LPTIM_Group5
- * @brief Peripheral State functions.
- * @{
- */
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
@@ -878,26 +886,26 @@
#define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL)
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
- ((((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
- || \
- (((__INSTANCE__) == LPTIM2) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
- || \
- (((__INSTANCE__) == LPTIM3) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
+ ((((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
+ || \
+ (((__INSTANCE__) == LPTIM2) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
+ || \
+ (((__INSTANCE__) == LPTIM3) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
- (((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
+ (((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
/**
* @}
diff --git a/Inc/stm32l5xx_hal_mmc.h b/Inc/stm32l5xx_hal_mmc.h
index 0acdd14..cc9c9fb 100644
--- a/Inc/stm32l5xx_hal_mmc.h
+++ b/Inc/stm32l5xx_hal_mmc.h
@@ -15,14 +15,14 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L5xx_HAL_MMC_H
#define STM32L5xx_HAL_MMC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -54,7 +54,7 @@
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
-}HAL_MMC_StateTypeDef;
+} HAL_MMC_StateTypeDef;
/**
* @}
*/
@@ -102,7 +102,7 @@
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-}HAL_MMC_CardInfoTypeDef;
+} HAL_MMC_CardInfoTypeDef;
/**
* @brief MMC handle Structure definition
@@ -142,19 +142,19 @@
uint32_t Ext_CSD[128];
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Read_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Read_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Write_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* Write_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc);
- void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
-#endif
-}MMC_HandleTypeDef;
+ void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+ void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc);
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
+} MMC_HandleTypeDef;
/**
@@ -204,7 +204,7 @@
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-}HAL_MMC_CardCSDTypeDef;
+} HAL_MMC_CardCSDTypeDef;
/**
* @}
*/
@@ -225,7 +225,7 @@
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
-}HAL_MMC_CardCIDTypeDef;
+} HAL_MMC_CardCIDTypeDef;
/**
* @}
*/
@@ -247,7 +247,7 @@
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
-}HAL_MMC_CallbackIDTypeDef;
+} HAL_MMC_CallbackIDTypeDef;
/**
* @}
*/
@@ -255,11 +255,11 @@
/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
* @{
*/
-typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
+typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -282,13 +282,13 @@
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
+/*!< number of transferred bytes does not match the block length */
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
+/*!< command or if there was an attempt to access a locked card */
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
@@ -299,8 +299,8 @@
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
+#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
+/*!< of erase sequence command was received */
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
@@ -313,7 +313,7 @@
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -403,22 +403,22 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup MMC_Exported_macros MMC Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/** @brief Reset MMC handle state.
* @param __HANDLE__ MMC Handle.
* @retval None
*/
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @brief Enable the MMC device interrupt.
@@ -632,7 +632,7 @@
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
@@ -644,15 +644,21 @@
* @{
*/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
@@ -664,9 +670,10 @@
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/* MMC callback registering/unregistering */
-HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+ pMMC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -713,7 +720,8 @@
/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management
* @{
*/
-HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd,
+ uint32_t BlockEndAdd);
HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode);
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT);
@@ -734,7 +742,8 @@
/** @defgroup MMC_Private_Defines MMC Private Defines
* @{
*/
-
+#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61
+#define MMC_EXT_CSD_DATA_SEC_SIZE_POS 8
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_mmc_ex.h b/Inc/stm32l5xx_hal_mmc_ex.h
index 91d0990..bc007e3 100644
--- a/Inc/stm32l5xx_hal_mmc_ex.h
+++ b/Inc/stm32l5xx_hal_mmc_ex.h
@@ -22,7 +22,7 @@
#define STM32L5xx_HAL_MMC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -50,7 +50,7 @@
MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */
MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */
-}HAL_MMCEx_DMABuffer_MemoryTypeDef;
+} HAL_MMCEx_DMABuffer_MemoryTypeDef;
/**
@@ -60,8 +60,6 @@
/**
* @}
*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
* @{
@@ -70,10 +68,14 @@
/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
-HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
+HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0,
+ uint32_t *pDataBuffer1, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer);
void HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);
diff --git a/Inc/stm32l5xx_hal_nand.h b/Inc/stm32l5xx_hal_nand.h
index 947f9c6..d462900 100644
--- a/Inc/stm32l5xx_hal_nand.h
+++ b/Inc/stm32l5xx_hal_nand.h
@@ -133,7 +133,7 @@
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
@@ -151,7 +151,7 @@
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -175,7 +175,7 @@
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -242,7 +242,7 @@
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -287,19 +287,19 @@
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
-#define NAND_CMD_AREA_A 0x00U
-#define NAND_CMD_AREA_B 0x01U
-#define NAND_CMD_AREA_C 0x50U
-#define NAND_CMD_AREA_TRUE1 0x30U
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-#define NAND_CMD_WRITE0 0x80U
-#define NAND_CMD_WRITE_TRUE1 0x10U
-#define NAND_CMD_ERASE0 0x60U
-#define NAND_CMD_ERASE1 0xD0U
-#define NAND_CMD_READID 0x90U
-#define NAND_CMD_STATUS 0x70U
-#define NAND_CMD_LOCK_STATUS 0x7AU
-#define NAND_CMD_RESET 0xFFU
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS 0x00000100UL
@@ -324,7 +324,8 @@
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
diff --git a/Inc/stm32l5xx_hal_nor.h b/Inc/stm32l5xx_hal_nor.h
index 60f4651..421ddba 100644
--- a/Inc/stm32l5xx_hal_nor.h
+++ b/Inc/stm32l5xx_hal_nor.h
@@ -125,7 +125,7 @@
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
} NOR_HandleTypeDef;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
@@ -142,7 +142,7 @@
* @brief HAL NOR Callback pointer definition
*/
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -164,7 +164,7 @@
} while(0)
#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -213,7 +213,7 @@
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -257,23 +257,23 @@
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x61)
-#define CFI2_ADDRESS ((uint16_t)0x62)
-#define CFI3_ADDRESS ((uint16_t)0x63)
-#define CFI4_ADDRESS ((uint16_t)0x64)
+#define CFI1_ADDRESS ((uint16_t)0x0061)
+#define CFI2_ADDRESS ((uint16_t)0x0062)
+#define CFI3_ADDRESS ((uint16_t)0x0063)
+#define CFI4_ADDRESS ((uint16_t)0x0064)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0)
-#define NOR_MEMORY_16B ((uint8_t)0x1)
+#define NOR_MEMORY_8B ((uint8_t)0x00)
+#define NOR_MEMORY_16B ((uint8_t)0x01)
/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
-#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
-#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
-#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
+#define NOR_MEMORY_ADRESS1 (0x60000000U)
+#define NOR_MEMORY_ADRESS2 (0x64000000U)
+#define NOR_MEMORY_ADRESS3 (0x68000000U)
+#define NOR_MEMORY_ADRESS4 (0x6C000000U)
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_opamp.h b/Inc/stm32l5xx_hal_opamp.h
index 86cd223..32238ca 100644
--- a/Inc/stm32l5xx_hal_opamp.h
+++ b/Inc/stm32l5xx_hal_opamp.h
@@ -145,10 +145,6 @@
typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
-/**
- * @}
- */
-
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL OPAMP Callback ID enumeration definition
@@ -166,6 +162,10 @@
typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
@@ -223,8 +223,8 @@
/** @defgroup OPAMP_PowerMode OPAMP PowerMode
* @{
*/
-#define OPAMP_POWERMODE_NORMAL 0x00000000U
-#define OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM
+#define OPAMP_POWERMODE_NORMALPOWER 0x00000000U /*!< OPAMP power mode normal */
+#define OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM /*!< OPAMP power mode low-power */
/**
* @}
diff --git a/Inc/stm32l5xx_hal_opamp_ex.h b/Inc/stm32l5xx_hal_opamp_ex.h
index 524b9fd..83615b6 100644
--- a/Inc/stm32l5xx_hal_opamp_ex.h
+++ b/Inc/stm32l5xx_hal_opamp_ex.h
@@ -39,12 +39,12 @@
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
+/** @addtogroup OPAMPEx_Exported_Functions
* @{
*/
/* I/O operation functions *****************************************************/
-/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+/** @addtogroup OPAMPEx_Exported_Functions_Group1
* @{
*/
diff --git a/Inc/stm32l5xx_hal_pcd.h b/Inc/stm32l5xx_hal_pcd.h
index 119848f..80cc2e6 100644
--- a/Inc/stm32l5xx_hal_pcd.h
+++ b/Inc/stm32l5xx_hal_pcd.h
@@ -260,25 +260,41 @@
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_BcdCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_LpmCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -317,16 +333,24 @@
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type);
+
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -412,10 +436,10 @@
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
/* ENDPOINT transfer */
-#define USB_EP0StartXfer USB_EPStartXfer
+#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -424,8 +448,7 @@
* @param wType Endpoint Type.
* @retval None
*/
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -442,18 +465,19 @@
* @param bEpNum, bDir
* @retval None
*/
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
- if ((bDir) == 0U) \
- { \
- /* OUT double buffered endpoint */ \
- PCD_TX_DTOG((USBx), (bEpNum)); \
- } \
- else if ((bDir) == 1U) \
- { \
- /* IN double buffered endpoint */ \
- PCD_RX_DTOG((USBx), (bEpNum)); \
- } \
-} while(0)
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
+ do { \
+ if ((bDir) == 0U) \
+ { \
+ /* OUT double buffered endpoint */ \
+ PCD_TX_DTOG((USBx), (bEpNum)); \
+ } \
+ else if ((bDir) == 1U) \
+ { \
+ /* IN double buffered endpoint */ \
+ PCD_RX_DTOG((USBx), (bEpNum)); \
+ } \
+ } while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
@@ -462,21 +486,22 @@
* @param wState new state
* @retval None
*/
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
- uint16_t _wRegVal; \
- \
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
+ do { \
+ uint16_t _wRegVal; \
+ \
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
- /* toggle first bit ? */ \
- if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
- { \
+ /* toggle first bit ? */ \
+ if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
+ { \
_wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
- { \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
+ { \
_wRegVal ^= USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
/**
@@ -486,19 +511,20 @@
* @param wState new state
* @retval None
*/
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
- _wRegVal ^= USB_EPRX_DTOG1; \
+ _wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
- _wRegVal ^= USB_EPRX_DTOG2; \
+ _wRegVal ^= USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
@@ -511,7 +537,8 @@
* @param wStatetx new state.
* @retval None
*/
-#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
+#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
@@ -573,7 +600,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
+#define PCD_SET_EP_KIND(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@@ -581,7 +609,8 @@
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
@@ -613,7 +642,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
@@ -621,7 +651,8 @@
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
@@ -635,7 +666,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_RX_DTOG(USBx, bEpNum) do { \
+#define PCD_RX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@@ -643,7 +675,8 @@
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
-#define PCD_TX_DTOG(USBx, bEpNum) do { \
+#define PCD_TX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@@ -656,7 +689,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
@@ -667,7 +701,8 @@
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
@@ -685,7 +720,8 @@
* @param bAddr Address.
* @retval None
*/
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
@@ -711,23 +747,25 @@
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
- __IO uint16_t *_wRegVal; \
- uint32_t _wRegBase = (uint32_t)USBx; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
- *_wRegVal = ((wAddr) >> 1) << 1; \
-} while(0) /* PCD_SET_EP_TX_ADDRESS */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
+ do { \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+ } while(0) /* PCD_SET_EP_TX_ADDRESS */
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
- __IO uint16_t *_wRegVal; \
- uint32_t _wRegBase = (uint32_t)USBx; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
- *_wRegVal = ((wAddr) >> 1) << 1; \
-} while(0) /* PCD_SET_EP_RX_ADDRESS */
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
+ do { \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+ } while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
@@ -745,7 +783,8 @@
* @param wNBlocks no. of Blocks.
* @retval None
*/
-#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
+#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
+ do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
@@ -754,7 +793,8 @@
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
-#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
+#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
+ do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
@@ -763,7 +803,8 @@
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
-#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
+#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
+ do { \
uint32_t wNBlocks; \
if ((wCount) == 0U) \
{ \
@@ -780,10 +821,11 @@
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
- uint32_t _wRegBase = (uint32_t)(USBx); \
- __IO uint16_t *pdwReg; \
- \
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
+ do { \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *pdwReg; \
+ \
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
@@ -796,23 +838,25 @@
* @param wCount Counter value.
* @retval None
*/
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
+ do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
-} while(0)
+ } while(0)
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
+ do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
-} while(0)
+ } while(0)
/**
* @brief gets counter of the tx buffer.
@@ -830,10 +874,13 @@
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
+ do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
+
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
+ do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
@@ -845,7 +892,8 @@
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
+ do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
@@ -868,7 +916,8 @@
* @param wCount: Counter value
* @retval None
*/
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
@@ -884,7 +933,8 @@
} \
} while(0) /* SetEPDblBuf0Count*/
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
@@ -905,7 +955,8 @@
} \
} while(0) /* SetEPDblBuf1Count */
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */
diff --git a/Inc/stm32l5xx_hal_pcd_ex.h b/Inc/stm32l5xx_hal_pcd_ex.h
index 0dbfc94..11ddb2e 100644
--- a/Inc/stm32l5xx_hal_pcd_ex.h
+++ b/Inc/stm32l5xx_hal_pcd_ex.h
@@ -49,10 +49,8 @@
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress);
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+ uint16_t ep_kind, uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
diff --git a/Inc/stm32l5xx_hal_rcc.h b/Inc/stm32l5xx_hal_rcc.h
index b92ec92..3c36765 100644
--- a/Inc/stm32l5xx_hal_rcc.h
+++ b/Inc/stm32l5xx_hal_rcc.h
@@ -652,59 +652,59 @@
*/
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TSC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GTZC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
@@ -734,128 +734,128 @@
*/
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_ADC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#if defined(AES)
#define __HAL_RCC_AES_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#endif /* AES */
#if defined(HASH)
#define __HAL_RCC_HASH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#endif /* HASH */
#define __HAL_RCC_RNG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_PKA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
@@ -905,20 +905,20 @@
*/
#define __HAL_RCC_FMC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
@@ -937,238 +937,238 @@
*/
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_CRS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#if defined(USB)
#define __HAL_RCC_USB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#endif /* USB */
#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
@@ -1242,93 +1242,93 @@
*/
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
- UNUSED(tmpreg); \
- } while(0)
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
+ UNUSED(tmpreg); \
+ } while(0)
#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
@@ -1814,9 +1814,9 @@
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() do { \
- WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \
- WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \
- } while(0)
+ WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \
+ WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \
+ } while(0)
#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
@@ -1876,9 +1876,9 @@
#define __HAL_RCC_APB1_RELEASE_RESET() do { \
- WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \
- WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \
- } while(0)
+ WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \
+ WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \
+ } while(0)
#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
@@ -2740,7 +2740,7 @@
* @retval None
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
/**
* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
@@ -2798,7 +2798,7 @@
* @retval None
*/
#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
/**
* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
@@ -2827,10 +2827,10 @@
* @retval None
*/
#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
- do { \
- SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
- MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
- } while(0)
+ do { \
+ SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
+ MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
+ } while(0)
/**
* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
@@ -2844,7 +2844,7 @@
* @retval None
*/
#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
- MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
+ MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
* @retval MSI clock range.
@@ -2863,9 +2863,9 @@
* @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
*/
#define __HAL_RCC_GET_MSI_RANGE() \
- ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \
- (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
- (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
+ ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \
+ (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
+ (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
@@ -2904,22 +2904,22 @@
* @retval None
*/
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do { \
- if((__STATE__) == RCC_HSE_ON) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else if((__STATE__) == RCC_HSE_BYPASS) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- } while(0)
+ do { \
+ if((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ } while(0)
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
@@ -2942,22 +2942,22 @@
* @retval None
*/
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- do { \
- if((__STATE__) == RCC_LSE_ON) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else if((__STATE__) == RCC_LSE_BYPASS) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- } while(0)
+ do { \
+ if((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else if((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ } while(0)
/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
@@ -2995,7 +2995,7 @@
* @retval None
*/
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
- MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+ MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
/** @brief Macro to get the RTC clock source.
@@ -3031,7 +3031,7 @@
*
*/
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
/** @brief Macro to configure the PLL source division factor M.
* @note This function must be used only when the main PLL is disabled.
@@ -3044,7 +3044,7 @@
*
*/
#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
/**
* @brief Macro to configure the main PLL clock source, multiplication and division factors.
@@ -3085,15 +3085,15 @@
* @retval None
*/
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
- MODIFY_REG(RCC->PLLCFGR, \
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
- RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
- ((__PLLSOURCE__) | \
- (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
- ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
- ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
- ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
- ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
+ MODIFY_REG(RCC->PLLCFGR, \
+ (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
+ RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
+ ((__PLLSOURCE__) | \
+ (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
+ ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
+ ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
/** @brief Macro to get the oscillator used as PLL clock source.
* @retval The oscillator used as PLL clock source. The returned value can be one
@@ -3147,7 +3147,7 @@
* @retval None
*/
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
@@ -3174,7 +3174,7 @@
* @retval None
*/
#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
/**
* @brief Macro to configure the wake up from stop clock.
@@ -3185,7 +3185,7 @@
* @retval None
*/
#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
/** @brief Macro to configure the MCO clock.
@@ -3209,7 +3209,7 @@
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
*/
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
@@ -3312,11 +3312,11 @@
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
- ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \
- ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
- ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \
- (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
- ? 1U : 0U)
+ ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \
+ ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
+ ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \
+ (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
+ ? 1U : 0U)
/**
* @}
@@ -3371,7 +3371,8 @@
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \
+ <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
diff --git a/Inc/stm32l5xx_hal_rcc_ex.h b/Inc/stm32l5xx_hal_rcc_ex.h
index 7984b13..fd01191 100644
--- a/Inc/stm32l5xx_hal_rcc_ex.h
+++ b/Inc/stm32l5xx_hal_rcc_ex.h
@@ -271,7 +271,7 @@
#define RCC_PERIPHCLK_SAI2 0x00001000U
#if defined(USB)
#define RCC_PERIPHCLK_USB 0x00002000U
-#endif
+#endif /* USB */
#define RCC_PERIPHCLK_ADC 0x00004000U
#define RCC_PERIPHCLK_DFSDM1 0x00010000U
#define RCC_PERIPHCLK_RTC 0x00020000U
@@ -683,8 +683,8 @@
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
+ * @{
+ */
/**
@@ -724,16 +724,16 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1SOURCE__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, \
- (RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | \
- RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | \
- RCC_PLLSAI1CFGR_PLLSAI1PDIV), \
- ((__PLLSAI1SOURCE__) | \
- (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \
- ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
- ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
- ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
- ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))
+ MODIFY_REG(RCC->PLLSAI1CFGR, \
+ (RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | \
+ RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | \
+ RCC_PLLSAI1CFGR_PLLSAI1PDIV), \
+ ((__PLLSAI1SOURCE__) | \
+ (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \
+ ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
+ ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
+ ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
+ ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)))
/**
* @brief Macro to configure the PLLSAI1 clock multiplication factor N.
@@ -751,7 +751,7 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
/** @brief Macro to configure the PLLSAI1 input clock division factor M.
*
@@ -765,7 +765,7 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)
/** @brief Macro to configure the PLLSAI1 clock division factor P.
*
@@ -780,7 +780,7 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
/** @brief Macro to configure the PLLSAI1 clock division factor Q.
*
@@ -795,7 +795,7 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
/** @brief Macro to configure the PLLSAI1 clock division factor R.
*
@@ -810,7 +810,7 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
/**
* @brief Macros to enable or disable the PLLSAI1.
@@ -881,13 +881,13 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2SOURCE__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, \
- (RCC_PLLSAI2CFGR_PLLSAI2SRC | RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | \
- RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
- ((__PLLSAI2SOURCE__) | \
- (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
- ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
- ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
+ MODIFY_REG(RCC->PLLSAI2CFGR, \
+ (RCC_PLLSAI2CFGR_PLLSAI2SRC | RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | \
+ RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \
+ ((__PLLSAI2SOURCE__) | \
+ (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \
+ ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
+ ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)))
/**
* @brief Macro to configure the PLLSAI2 clock multiplication factor N.
@@ -905,7 +905,7 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
/** @brief Macro to configure the PLLSAI2 input clock division factor M.
*
@@ -920,7 +920,7 @@
*/
#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)
/** @brief Macro to configure the PLLSAI2 clock division factor P.
*
@@ -935,7 +935,7 @@
* @retval None
*/
#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
/**
* @brief Macros to enable or disable the PLLSAI2.
@@ -988,7 +988,7 @@
* @retval None
*/
#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
/** @brief Macro to get the SAI1 clock source.
* @retval The clock source can be one of the following values:
@@ -1018,7 +1018,7 @@
* @retval None
*/
#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
/** @brief Macro to get the SAI2 clock source.
* @retval The clock source can be one of the following values:
@@ -1040,7 +1040,7 @@
* @retval None
*/
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
/** @brief Macro to get the I2C1 clock source.
* @retval The clock source can be one of the following values:
@@ -1060,7 +1060,7 @@
* @retval None
*/
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
/** @brief Macro to get the I2C2 clock source.
* @retval The clock source can be one of the following values:
@@ -1080,7 +1080,7 @@
* @retval None
*/
#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
/** @brief Macro to get the I2C3 clock source.
* @retval The clock source can be one of the following values:
@@ -1100,7 +1100,7 @@
* @retval None
*/
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
/** @brief Macro to get the I2C4 clock source.
* @retval The clock source can be one of the following values:
@@ -1122,7 +1122,7 @@
* @retval None
*/
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
/** @brief Macro to get the USART1 clock source.
* @retval The clock source can be one of the following values:
@@ -1144,7 +1144,7 @@
* @retval None
*/
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
/** @brief Macro to get the USART2 clock source.
* @retval The clock source can be one of the following values:
@@ -1166,7 +1166,7 @@
* @retval None
*/
#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
/** @brief Macro to get the USART3 clock source.
* @retval The clock source can be one of the following values:
@@ -1188,7 +1188,7 @@
* @retval None
*/
#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
/** @brief Macro to get the UART4 clock source.
* @retval The clock source can be one of the following values:
@@ -1210,7 +1210,7 @@
* @retval None
*/
#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
/** @brief Macro to get the UART5 clock source.
* @retval The clock source can be one of the following values:
@@ -1232,7 +1232,7 @@
* @retval None
*/
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
/** @brief Macro to get the LPUART1 clock source.
* @retval The clock source can be one of the following values:
@@ -1254,7 +1254,7 @@
* @retval None
*/
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
/** @brief Macro to get the LPTIM1 clock source.
* @retval The clock source can be one of the following values:
@@ -1276,7 +1276,7 @@
* @retval None
*/
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
/** @brief Macro to get the LPTIM2 clock source.
* @retval The clock source can be one of the following values:
@@ -1298,7 +1298,7 @@
* @retval None
*/
#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__))
/** @brief Macro to get the LPTIM3 clock source.
* @retval The clock source can be one of the following values:
@@ -1319,7 +1319,7 @@
* @retval None
*/
#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
/** @brief Macro to get the FDCAN clock source.
* @retval The clock source can be one of the following values:
@@ -1341,18 +1341,18 @@
* @retval None
*/
#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
- do \
- { \
- if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \
- { \
- SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
- } \
- else \
- { \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \
- CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
- } \
- } while(0)
+ do \
+ { \
+ if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \
+ { \
+ SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
+ } \
+ else \
+ { \
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \
+ CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
+ } \
+ } while(0)
/** @brief Macro to get the SDMMC1 clock.
* @retval The clock source can be one of the following values:
@@ -1363,7 +1363,7 @@
* @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 clock
*/
#define __HAL_RCC_GET_SDMMC1_SOURCE() \
- ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))))
+ ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL))))
/** @brief Macro to configure the RNG clock.
*
@@ -1378,7 +1378,7 @@
* @retval None
*/
#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__RNG_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__RNG_CLKSOURCE__))
/** @brief Macro to get the RNG clock.
* @retval The clock source can be one of the following values:
@@ -1404,7 +1404,7 @@
* @retval None
*/
#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__USB_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__USB_CLKSOURCE__))
/** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values:
@@ -1426,7 +1426,7 @@
* @retval None
*/
#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
/** @brief Macro to get the ADC clock source.
* @retval The clock source can be one of the following values:
@@ -1444,7 +1444,7 @@
* @retval None
*/
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
/** @brief Macro to get the DFSDM1 clock source.
* @retval The clock source can be one of the following values:
@@ -1462,7 +1462,7 @@
* @retval None
*/
#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
/** @brief Macro to get the DFSDM1 audio clock source.
* @retval The clock source can be one of the following values:
@@ -1481,7 +1481,7 @@
* @retval None
*/
#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \
- MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__))
+ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__))
/** @brief Macro to get the OctoSPI clock source.
* @retval The clock source can be one of the following values:
@@ -1771,18 +1771,19 @@
* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
*/
/* CRS IT Error Mask */
-#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF\
+ | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
- if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
- { \
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
- } \
- else \
- { \
- WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
- } \
- } while(0)
+ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
+ { \
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+ } \
+ else \
+ { \
+ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+ } \
+ } while(0)
/**
* @brief Check whether the specified CRS flag is set or not.
@@ -1815,18 +1816,19 @@
*/
/* CRS Flag Error Mask */
-#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF\
+ | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
- if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
- { \
- WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
- } \
- else \
- { \
- WRITE_REG(CRS->ICR, (__FLAG__)); \
- } \
- } while(0)
+ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
+ { \
+ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+ } \
+ else \
+ { \
+ WRITE_REG(CRS->ICR, (__FLAG__)); \
+ } \
+ } while(0)
/**
* @brief Enable the oscillator clock for frequency error counter.
@@ -1952,165 +1954,165 @@
((__SOURCE__) == RCC_LSCOSOURCE_LSE))
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
- (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \
- (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN))
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN))
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
- ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
+ ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
#define IS_RCC_SAI1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
#define IS_RCC_SAI2CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
- ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
+ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
#define IS_RCC_LPTIM1CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
+ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
#define IS_RCC_LPTIM2CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
+ (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
#define IS_RCC_LPTIM3CLK(__SOURCE__) \
- (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \
- ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE))
+ (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE))
#define IS_RCC_FDCANCLK(__SOURCE__) \
- (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLLSAI1))
+ (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLLSAI1))
#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI) || \
- ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP))
+ (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI) || \
+ ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP))
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
+ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
#if defined(USB)
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
+ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
+ ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
#endif /* USB */
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
+ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
- ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
+ (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
- ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI))
+ (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
+ ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI))
#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
- (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
- ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \
- ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL))
+ (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \
+ ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL))
#define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
diff --git a/Inc/stm32l5xx_hal_rng.h b/Inc/stm32l5xx_hal_rng.h
index 8de7190..101d112 100644
--- a/Inc/stm32l5xx_hal_rng.h
+++ b/Inc/stm32l5xx_hal_rng.h
@@ -363,6 +363,14 @@
* @}
*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Functions RNG Private functions
+ * @{
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
+/**
+ * @}
+ */
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_rtc.h b/Inc/stm32l5xx_hal_rtc.h
index 0e35129..c4651fc 100644
--- a/Inc/stm32l5xx_hal_rtc.h
+++ b/Inc/stm32l5xx_hal_rtc.h
@@ -112,12 +112,9 @@
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
- uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
- This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+ uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
- uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit
- in CR register to store the operation.
- This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+ uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
} RTC_TimeTypeDef;
/**
@@ -557,6 +554,8 @@
/**
* @brief Add 1 hour (summer time change).
+ * @note This interface is deprecated.
+ * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
* @param __HANDLE__ specifies the RTC handle.
* @param __BKP__ Backup
* This parameter can be:
@@ -574,6 +573,8 @@
/**
* @brief Subtract 1 hour (winter time change).
+ * @note This interface is deprecated.
+ * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
* @param __HANDLE__ specifies the RTC handle.
* @param __BKP__ Backup
* This parameter can be:
@@ -747,6 +748,11 @@
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_rtc_ex.h b/Inc/stm32l5xx_hal_rtc_ex.h
index 41c6d99..1ff163a 100644
--- a/Inc/stm32l5xx_hal_rtc_ex.h
+++ b/Inc/stm32l5xx_hal_rtc_ex.h
@@ -383,6 +383,16 @@
* @}
*/
+
+/** @defgroup RTCEx_Tamper_Maskable_nb RTCEx Tampers maskable number
+ * @{
+ */
+#define RTC_TAMPER_MASKABLE_NB 3u
+
+/**
+ * @}
+ */
+
/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp
* @{
*/
@@ -1395,6 +1405,12 @@
void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_sd.h b/Inc/stm32l5xx_hal_sd.h
index ae45839..5fb82a8 100644
--- a/Inc/stm32l5xx_hal_sd.h
+++ b/Inc/stm32l5xx_hal_sd.h
@@ -22,7 +22,7 @@
#define STM32L5xx_HAL_SD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -58,7 +58,7 @@
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */
HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
-}HAL_SD_StateTypeDef;
+} HAL_SD_StateTypeDef;
/**
* @}
*/
@@ -110,7 +110,7 @@
uint32_t CardSpeed; /*!< Specifies the card Speed */
-}HAL_SD_CardInfoTypeDef;
+} HAL_SD_CardInfoTypeDef;
/**
* @brief SD handle Structure definition
@@ -148,22 +148,22 @@
uint32_t CID[4]; /*!< SD card identification number table */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
- void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Read_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Read_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Read_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Write_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* Write_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
- void (* DriveTransceiver_1_8V_Callback) (FlagStatus status);
+ void (* DriveTransceiver_1_8V_Callback)(FlagStatus status);
#endif /* USE_SD_TRANSCEIVER */
- void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
- void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd);
+ void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-}SD_HandleTypeDef;
+} SD_HandleTypeDef;
/**
* @}
@@ -211,7 +211,7 @@
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-}HAL_SD_CardCSDTypeDef;
+} HAL_SD_CardCSDTypeDef;
/**
* @}
*/
@@ -232,7 +232,7 @@
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
-}HAL_SD_CardCIDTypeDef;
+} HAL_SD_CardCIDTypeDef;
/**
* @}
*/
@@ -255,7 +255,7 @@
__IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */
__IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */
__IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */
-}HAL_SD_CardStatusTypeDef;
+} HAL_SD_CardStatusTypeDef;
/**
* @}
*/
@@ -277,7 +277,7 @@
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
-}HAL_SD_CallbackIDTypeDef;
+} HAL_SD_CallbackIDTypeDef;
/**
* @}
*/
@@ -285,7 +285,7 @@
/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
* @{
*/
-typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
+typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
#endif /* USE_SD_TRANSCEIVER */
@@ -298,7 +298,7 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
+/** @defgroup SD_Exported_Constants SD Exported Constants
* @{
*/
@@ -315,13 +315,13 @@
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */
+ /*!< number of transferred bytes does not match the block length */
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */
+ /*!< command or if there was an attempt to access a locked card */
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
@@ -332,8 +332,8 @@
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
+#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */
+ /*!< of erase sequence command was received */
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
@@ -342,7 +342,7 @@
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
@@ -397,9 +397,9 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros SD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/** @brief Reset SD handle state.
* @param __HANDLE__ SD Handle.
* @retval None
@@ -620,10 +620,10 @@
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_SD_Init (SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/**
* @}
@@ -633,23 +633,29 @@
* @{
*/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks);
-void HAL_SD_IRQHandler (SD_HandleTypeDef *hsd);
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
/* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd);
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
/* Callback to switch in 1.8V mode */
@@ -658,11 +664,12 @@
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* SD callback registering/unregistering */
-HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+ pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);
#if (USE_SD_TRANSCEIVER != 0U)
-HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);
#endif /* USE_SD_TRANSCEIVER */
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
@@ -684,10 +691,10 @@
* @{
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
-HAL_StatusTypeDef HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
@@ -704,7 +711,7 @@
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
-HAL_StatusTypeDef HAL_SD_Abort (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
/**
* @}
diff --git a/Inc/stm32l5xx_hal_sd_ex.h b/Inc/stm32l5xx_hal_sd_ex.h
index c45ff20..952093a 100644
--- a/Inc/stm32l5xx_hal_sd_ex.h
+++ b/Inc/stm32l5xx_hal_sd_ex.h
@@ -22,7 +22,7 @@
#define STM32L5xx_HAL_SD_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -50,17 +50,15 @@
SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */
SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */
-}HAL_SDEx_DMABuffer_MemoryTypeDef;
+} HAL_SDEx_DMABuffer_MemoryTypeDef;
/**
* @}
*/
-
/**
* @}
*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
* @{
@@ -70,10 +68,12 @@
* @{
*/
-HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1,
+ uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
+HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer);
void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);
void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
diff --git a/Inc/stm32l5xx_hal_smartcard.h b/Inc/stm32l5xx_hal_smartcard.h
index 7fb3afb..9aa89ff 100644
--- a/Inc/stm32l5xx_hal_smartcard.h
+++ b/Inc/stm32l5xx_hal_smartcard.h
@@ -163,7 +163,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -180,7 +180,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
diff --git a/Inc/stm32l5xx_hal_smbus.h b/Inc/stm32l5xx_hal_smbus.h
index 3b4248a..6655ba4 100644
--- a/Inc/stm32l5xx_hal_smbus.h
+++ b/Inc/stm32l5xx_hal_smbus.h
@@ -27,6 +27,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l5xx_hal_def.h"
+#include "stm32l5xx_hal_smbus_ex.h"
/** @addtogroup STM32L5xx_HAL_Driver
* @{
diff --git a/Inc/stm32l5xx_hal_smbus_ex.h b/Inc/stm32l5xx_hal_smbus_ex.h
new file mode 100644
index 0000000..ba2350c
--- /dev/null
+++ b/Inc/stm32l5xx_hal_smbus_ex.h
@@ -0,0 +1,140 @@
+/**
+ ******************************************************************************
+ * @file stm32l5xx_hal_smbus_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SMBUS HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_SMBUS_EX_H
+#define STM32L5xx_HAL_SMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUSEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
+ * @{
+ */
+#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
+#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
+ * @{
+ */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
+ * @{
+ */
+#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32l5xx_hal_smbus_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_SMBUS_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l5xx_hal_sram.h b/Inc/stm32l5xx_hal_sram.h
index 5d4820c..69c470e 100644
--- a/Inc/stm32l5xx_hal_sram.h
+++ b/Inc/stm32l5xx_hal_sram.h
@@ -78,9 +78,9 @@
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
- void (* DmaXferCpltCallback)(DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
- void (* DmaXferErrorCallback)(DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
-#endif
+ void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
} SRAM_HandleTypeDef;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
@@ -100,7 +100,7 @@
*/
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -124,7 +124,7 @@
} while(0)
#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
@@ -182,7 +182,7 @@
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
diff --git a/Inc/stm32l5xx_hal_tim.h b/Inc/stm32l5xx_hal_tim.h
index 515cfd7..ca8d26c 100644
--- a/Inc/stm32l5xx_hal_tim.h
+++ b/Inc/stm32l5xx_hal_tim.h
@@ -1071,24 +1071,24 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
@@ -2060,7 +2060,7 @@
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
-
+
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
@@ -2083,7 +2083,7 @@
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
-
+
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
diff --git a/Inc/stm32l5xx_hal_tsc.h b/Inc/stm32l5xx_hal_tsc.h
index 04afcb0..dafdc78 100644
--- a/Inc/stm32l5xx_hal_tsc.h
+++ b/Inc/stm32l5xx_hal_tsc.h
@@ -634,6 +634,10 @@
((__VALUE__) == TSC_PG_PRESC_DIV64) || \
((__VALUE__) == TSC_PG_PRESC_DIV128))
+#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
+ (((__PGPSC__) == TSC_PG_PRESC_DIV2) && ((__CTPL__) > TSC_CTPL_1CYCLE)) || \
+ (((__PGPSC__) > TSC_PG_PRESC_DIV2) && (((__CTPL__) == TSC_CTPL_1CYCLE) || ((__CTPL__) > TSC_CTPL_1CYCLE))))
+
#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
((__VALUE__) == TSC_MCV_511) || \
((__VALUE__) == TSC_MCV_1023) || \
diff --git a/Inc/stm32l5xx_hal_uart.h b/Inc/stm32l5xx_hal_uart.h
index f6906e4..aac174a 100644
--- a/Inc/stm32l5xx_hal_uart.h
+++ b/Inc/stm32l5xx_hal_uart.h
@@ -146,7 +146,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -163,7 +163,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
diff --git a/Inc/stm32l5xx_ll_adc.h b/Inc/stm32l5xx_ll_adc.h
index 2cbb89c..5cfcf80 100644
--- a/Inc/stm32l5xx_ll_adc.h
+++ b/Inc/stm32l5xx_ll_adc.h
@@ -1285,7 +1285,7 @@
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tADCVREG_STUP"). */
/* Unit: us */
-#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
/* Delay for internal voltage reference stabilization time. */
/* Delay set to maximum value (refer to device datasheet, */
diff --git a/Inc/stm32l5xx_ll_bus.h b/Inc/stm32l5xx_ll_bus.h
index e702642..79cfe53 100644
--- a/Inc/stm32l5xx_ll_bus.h
+++ b/Inc/stm32l5xx_ll_bus.h
@@ -219,7 +219,7 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -247,7 +247,7 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
* @retval State of Periphs (1 or 0).
-*/
+ */
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
@@ -272,7 +272,7 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1ENR, Periphs);
@@ -295,7 +295,7 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB1RSTR, Periphs);
@@ -318,7 +318,7 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1RSTR, Periphs);
@@ -347,7 +347,7 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
* @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -380,7 +380,7 @@
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC
* @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1SMENR, Periphs);
@@ -431,7 +431,7 @@
*
* (*) value not defined in all devices.
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -477,7 +477,7 @@
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
-*/
+ */
__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
@@ -520,7 +520,7 @@
*
* (*) value not defined in all devices.
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2ENR, Periphs);
@@ -563,7 +563,7 @@
*
* (*) value not defined in all devices.
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB2RSTR, Periphs);
@@ -606,7 +606,7 @@
*
* (*) value not defined in all devices.
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2RSTR, Periphs);
@@ -651,7 +651,7 @@
*
* (*) value not defined in all devices.
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -700,7 +700,7 @@
*
* (*) value not defined in all devices.
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2SMENR, Periphs);
@@ -723,7 +723,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -741,7 +741,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
* @retval State of Periphs (1 or 0).
-*/
+ */
__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
@@ -756,7 +756,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3ENR, Periphs);
@@ -771,7 +771,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB3RSTR, Periphs);
@@ -786,7 +786,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3RSTR, Periphs);
@@ -801,7 +801,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -820,7 +820,7 @@
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3SMENR, Periphs);
@@ -883,7 +883,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -912,7 +912,7 @@
* @arg @ref LL_APB1_GRP2_PERIPH_USB
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -970,7 +970,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @retval State of Periphs (1 or 0).
-*/
+ */
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
@@ -994,7 +994,7 @@
* @arg @ref LL_APB1_GRP2_PERIPH_USB
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval State of Periphs (1 or 0).
-*/
+ */
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
@@ -1049,7 +1049,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR1, Periphs);
@@ -1074,7 +1074,7 @@
* @arg @ref LL_APB1_GRP2_PERIPH_USB
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR2, Periphs);
@@ -1127,7 +1127,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR1, Periphs);
@@ -1152,7 +1152,7 @@
* @arg @ref LL_APB1_GRP2_PERIPH_USB
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR2, Periphs);
@@ -1205,7 +1205,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR1, Periphs);
@@ -1230,7 +1230,7 @@
* @arg @ref LL_APB1_GRP2_PERIPH_USB
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR2, Periphs);
@@ -1285,7 +1285,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1314,7 +1314,7 @@
* @arg @ref LL_APB1_GRP2_PERIPH_USB
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1373,7 +1373,7 @@
* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR1, Periphs);
@@ -1398,7 +1398,7 @@
* @arg @ref LL_APB1_GRP2_PERIPH_USB
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR2, Periphs);
@@ -1439,7 +1439,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1475,7 +1475,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @retval State of Periphs (1 or 0).
-*/
+ */
__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
@@ -1508,7 +1508,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2ENR, Periphs);
@@ -1541,7 +1541,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB2RSTR, Periphs);
@@ -1574,7 +1574,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2RSTR, Periphs);
@@ -1607,7 +1607,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
@@ -1644,7 +1644,7 @@
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
* @retval None
-*/
+ */
__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2SMENR, Periphs);
diff --git a/Inc/stm32l5xx_ll_cortex.h b/Inc/stm32l5xx_ll_cortex.h
index dfcf623..2eeeac9 100644
--- a/Inc/stm32l5xx_ll_cortex.h
+++ b/Inc/stm32l5xx_ll_cortex.h
@@ -83,6 +83,112 @@
* @}
*/
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
+#define LL_MPU_CTRL_HARDFAULT_NMI 2U
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
+#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Attributes MPU Attributes
+ * @{
+ */
+#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
+#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
+#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
+#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
+
+#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
+#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
+#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
+
+#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
+#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
+
+#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
+#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
+#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
+#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Region_Enable MPU Region Enable
+ * @{
+ */
+#define LL_MPU_REGION_ENABLE 1U
+#define LL_MPU_REGION_DISABLE 0U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Instruction_Access MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Access_Shareable MPU Instruction Access Shareable
+ * @{
+ */
+#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
+#define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos)
+#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes MPU Region Permission Attributes
+ * @{
+ */
+#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
+#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Region_Number MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0U
+#define LL_MPU_REGION_NUMBER1 1U
+#define LL_MPU_REGION_NUMBER2 2U
+#define LL_MPU_REGION_NUMBER3 3U
+#define LL_MPU_REGION_NUMBER4 4U
+#define LL_MPU_REGION_NUMBER5 5U
+#define LL_MPU_REGION_NUMBER6 6U
+#define LL_MPU_REGION_NUMBER7 7U
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_MPU_Attributes_Number MPU Memory Attributes Number
+ * @{
+ */
+#define LL_MPU_ATTRIBUTES_NUMBER0 0U
+#define LL_MPU_ATTRIBUTES_NUMBER1 1U
+#define LL_MPU_ATTRIBUTES_NUMBER2 2U
+#define LL_MPU_ATTRIBUTES_NUMBER3 3U
+#define LL_MPU_ATTRIBUTES_NUMBER4 4U
+#define LL_MPU_ATTRIBUTES_NUMBER5 5U
+#define LL_MPU_ATTRIBUTES_NUMBER6 6U
+#define LL_MPU_ATTRIBUTES_NUMBER7 7U
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+
/**
* @}
*/
@@ -361,6 +467,795 @@
* @}
*/
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable\n
+ * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable\n
+ * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable
+ * @param MPU_Control This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU*/
+ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
+
+ /* Ensure MPU settings take effects */
+ __DSB();
+
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable\n
+ * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable\n
+ * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion\n
+ * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+
+ /* Enable the MPU region */
+ SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Check if MPU region is enabled or not
+ * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion\n
+ * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region)
+{
+ return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Disable a MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Configure and enable a MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RBAR XN LL_MPU_ConfigRegion\n
+ * MPU_RBAR AP LL_MPU_ConfigRegion\n
+ * MPU_RBAR SH LL_MPU_ConfigRegion\n
+ * MPU_RLAR EN LL_MPU_ConfigRegion\n
+ * MPU_RLAR AttrIndx LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param AttrIndx This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+
+ /* Set base address */
+ MPU->RBAR |= Attributes;
+ /* Set base address */
+ MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+
+ /* Set limit address */
+ MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+ /* Configure MPU */
+ MPU->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
+}
+
+/**
+ * @brief Configure a MPU region address range
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+
+ /* Set base address */
+ MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U) ;
+
+ /* Set limit address */
+ MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Configure a MPU attributes index
+ * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes\n
+ * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes\n
+ * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes\n
+ * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes\n
+ * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes\n
+ * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes\n
+ * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes\n
+ * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes
+ * @param AttIndex This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
+{
+ if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
+ {
+ /* Program MPU_MAIR0 */
+ WRITE_REG(MPU->MAIR0, (Attributes << (AttIndex * 8U)));
+ }
+ else
+ {
+ /* Program MPU_MAIR1 */
+ WRITE_REG(MPU->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
+ }
+}
+
+/**
+ * @brief Configure a MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
+ * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
+ * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
+}
+
+/**
+ * @brief Configure a MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
+ * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set limit address */
+ MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
+ * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+ * @brief Configure a MPU region access attributes and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
+ * MPU_RBAR XN LL_MPU_SetRegionAccess\n
+ * MPU_RBAR AP LL_MPU_SetRegionAccess\n
+ * MPU_RBAR SH LL_MPU_SetRegionAccess
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ MPU->RBAR |= Attributes;
+}
+
+/**
+ * @brief Get a MPU region access attributes
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
+ * MPU_RBAR XN LL_MPU_GetRegionAccess\n
+ * MPU_RBAR AP LL_MPU_GetRegionAccess\n
+ * MPU_RBAR SH LL_MPU_GetRegionAccess
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ * @brief Enable non-secure MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable_NS\n
+ * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable_NS\n
+ * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable_NS
+ * @param MPU_Control This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ /* Enable the MPU*/
+ MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
+
+ /* Ensure MPU settings take effects */
+ __DSB();
+
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable non-secure MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS\n
+ * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable_NS\n
+ * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable_NS
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable_NS(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU_NS->CTRL, 0U);
+}
+
+/**
+ * @brief Check if non-secure MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
+{
+ return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable a non-secure MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion_NS\n
+ * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+
+ /* Enable the MPU region */
+ SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Disable a non-secure MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
+ * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
+}
+
+/**
+ * @brief Check if non-secure MPU region is enabled or not
+ * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion_NS\n
+ * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region)
+{
+ return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Configure and enable a non-secure MPU region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
+ * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
+ * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
+ * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param AttrIndx This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+
+ /* Set base address */
+ MPU_NS->RBAR |= Attributes;
+
+ /* Set base address */
+ MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+
+ /* Set limit address */
+ MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+ /* Configure MPU */
+ MPU_NS->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
+}
+
+/**
+ * @brief Configure a non-secure MPU region address range
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
+ * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+
+ /* Set base address */
+ MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+
+ /* Set limit address */
+ MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Configure a non-secure MPU attributes index
+ * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes_NS\n
+ * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes_NS
+ * @param AttIndex This parameter can be one of the following values:
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
+ * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
+ * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
+{
+ if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
+ {
+ /* Program MPU_MAIR0 */
+ WRITE_REG(MPU_NS->MAIR0, (Attributes << (AttIndex * 8U)));
+ }
+ else
+ {
+ /* Program MPU_MAIR1 */
+ WRITE_REG(MPU_NS->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
+ }
+}
+
+/**
+ * @brief Configure a non-secure MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
+ * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param BaseAddress Value of region base address
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ /* Set base address */
+ MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a non-secure MPU region base address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
+ * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
+}
+
+/**
+ * @brief Configure a non-secure MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
+ * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param LimitAddress Value of region limit address
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ /* Set limit address */
+ MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
+}
+
+/**
+ * @brief Get a non-secure MPU region limit address
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
+ * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
+}
+
+/**
+ * @brief Configure a non-secure MPU region access attributes and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
+ * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
+ * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
+ * MPU_RBAR SH LL_MPU_SetRegionAccess_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
+ * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
+ * @note cortex-M33 support 8 secure and 8 non secure regions.
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ /* Set base address Attributes */
+ MPU_NS->RBAR |= Attributes;
+}
+
+/**
+ * @brief Get a non-secure MPU region access attributes
+ * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
+ * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
+ * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
+ * MPU_RBAR SH LL_MPU_GetRegionAccess_NS
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU_NS->RNR, Region);
+ return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
+}
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_fmc.h b/Inc/stm32l5xx_ll_fmc.h
index 585bba8..80a4680 100644
--- a/Inc/stm32l5xx_ll_fmc.h
+++ b/Inc/stm32l5xx_ll_fmc.h
@@ -41,51 +41,51 @@
*/
#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
- ((__BANK__) == FMC_NORSRAM_BANK2) || \
- ((__BANK__) == FMC_NORSRAM_BANK3) || \
- ((__BANK__) == FMC_NORSRAM_BANK4))
+ ((__BANK__) == FMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FMC_NORSRAM_BANK4))
#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
- ((__SIZE__) == FMC_PAGE_SIZE_128) || \
- ((__SIZE__) == FMC_PAGE_SIZE_256) || \
- ((__SIZE__) == FMC_PAGE_SIZE_512) || \
- ((__SIZE__) == FMC_PAGE_SIZE_1024))
+ ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_512) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_1024))
#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
- ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
+ ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
- ((__MODE__) == FMC_ACCESS_MODE_B) || \
- ((__MODE__) == FMC_ACCESS_MODE_C) || \
- ((__MODE__) == FMC_ACCESS_MODE_D))
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
- ((__NBL__) == FMC_NBL_SETUPTIME_1) || \
- ((__NBL__) == FMC_NBL_SETUPTIME_2) || \
- ((__NBL__) == FMC_NBL_SETUPTIME_3))
+ ((__NBL__) == FMC_NBL_SETUPTIME_1) || \
+ ((__NBL__) == FMC_NBL_SETUPTIME_2) || \
+ ((__NBL__) == FMC_NBL_SETUPTIME_3))
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+ ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
@@ -99,18 +99,18 @@
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
+ ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
+ ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FMC_NAND_ECC_ENABLE))
+ ((__STATE__) == FMC_NAND_ECC_ENABLE))
#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
@@ -144,75 +144,75 @@
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
- This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
- This parameter can be a value of @ref FMC_Memory_Type */
+ This parameter can be a value of @ref FMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FMC_Burst_Access_Mode */
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FMC_Wait_Timing */
+ This parameter can be a value of @ref FMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
- This parameter can be a value of @ref FMC_Write_Operation */
+ This parameter can be a value of @ref FMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal */
+ This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FMC_Extended_Mode */
+ This parameter can be a value of @ref FMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FMC_AsynchronousWait */
+ This parameter can be a value of @ref FMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
+ This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Continous_Clock */
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Write_FIFO */
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO */
uint32_t PageSize; /*!< Specifies the memory page size.
- This parameter can be a value of @ref FMC_Page_Size */
+ This parameter can be a value of @ref FMC_Page_Size */
uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
- This parameter can be a value of @ref FMC_Byte_Lane */
+ This parameter can be a value of @ref FMC_Byte_Lane */
- FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank
- for PSRAM refresh.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this
+ NSBank for PSRAM refresh.
+ This parameter can be set to ENABLE or DISABLE */
- uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous
- accesses and in HCLK cycles for asynchronous accesses,
+ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for
+ synchronous accesses and in HCLK cycles for asynchronous accesses,
valid only if MaxChipSelectPulse is ENABLE.
This parameter can be a value between Min_Data = 1 and Max_Data = 65535.
- @note: This parameter is common to all NSBank. */
-}FMC_NORSRAM_InitTypeDef;
+ @note: This parameter is common to all NSBank. */
+} FMC_NORSRAM_InitTypeDef;
/**
* @brief FMC NORSRAM Timing parameters structure definition
@@ -222,45 +222,46 @@
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
+ @note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
+ @note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
- NOR Flash memories. */
+ NOR Flash memories. */
uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data hold time.
This parameter can be a value between Min_Data = 0 and Max_Data = 3.
- @note This parameter is used for used in asynchronous accesses. */
+ @note This parameter is used for used in asynchronous accesses. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
+ @note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
- HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and
+ Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
- accesses. */
+ accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
- with synchronous burst mode enable */
+ - It may assume a value between Min_Data = 2 and Max_Data = 17
+ in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FMC_Access_Mode */
-}FMC_NORSRAM_TimingTypeDef;
+ This parameter can be a value of @ref FMC_Access_Mode */
+} FMC_NORSRAM_TimingTypeDef;
/**
* @brief FMC NAND Configuration Structure definition
@@ -268,19 +269,19 @@
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
+ This parameter can be a value of @ref FMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FMC_Wait_feature */
+ This parameter can be any value of @ref FMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FMC_NAND_Data_Width */
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FMC_ECC */
+ This parameter can be any value of @ref FMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FMC_ECC_Page_Size */
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
@@ -289,7 +290,7 @@
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FMC_NAND_InitTypeDef;
+} FMC_NAND_InitTypeDef;
/**
* @brief FMC NAND Timing parameters structure definition
@@ -320,7 +321,7 @@
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-}FMC_NAND_PCC_TimingTypeDef;
+} FMC_NAND_PCC_TimingTypeDef;
/**
@@ -339,10 +340,10 @@
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
-#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
-#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
-#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+#define FMC_NORSRAM_BANK1 (0x00000000U)
+#define FMC_NORSRAM_BANK2 (0x00000002U)
+#define FMC_NORSRAM_BANK3 (0x00000004U)
+#define FMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
@@ -350,8 +351,8 @@
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
+#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
+#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
@@ -359,9 +360,9 @@
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
+#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
+#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
+#define FMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
@@ -369,9 +370,9 @@
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
@@ -379,8 +380,8 @@
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
@@ -388,8 +389,8 @@
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
+#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
+#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
@@ -397,8 +398,8 @@
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
+#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
@@ -406,8 +407,8 @@
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
+#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
@@ -415,8 +416,8 @@
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
+#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
+#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
@@ -424,8 +425,8 @@
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
+#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
@@ -433,8 +434,8 @@
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
+#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
@@ -442,8 +443,8 @@
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
@@ -451,12 +452,12 @@
/** @defgroup FMC_Page_Size FMC Page Size
* @{
*/
-#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
-#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
-#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
-#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0\
- | FMC_BCRx_CPSIZE_1))
-#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
+#define FMC_PAGE_SIZE_NONE (0x00000000U)
+#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
+#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
+#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
+ | FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
/**
* @}
*/
@@ -464,8 +465,8 @@
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
+#define FMC_WRITE_BURST_DISABLE (0x00000000U)
+#define FMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
@@ -473,8 +474,8 @@
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
@@ -482,19 +483,19 @@
/** @defgroup FMC_Write_FIFO FMC Write FIFO
* @{
*/
-#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
-#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
+#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
/**
* @}
*/
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
-*/
-#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
-#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
-#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+ */
+#define FMC_ACCESS_MODE_A (0x00000000U)
+#define FMC_ACCESS_MODE_B (0x10000000U)
+#define FMC_ACCESS_MODE_C (0x20000000U)
+#define FMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
@@ -502,10 +503,10 @@
/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
* @{
*/
-#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000)
-#define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000)
-#define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000)
-#define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000)
+#define FMC_NBL_SETUPTIME_0 (0x00000000U)
+#define FMC_NBL_SETUPTIME_1 (0x00400000U)
+#define FMC_NBL_SETUPTIME_2 (0x00800000U)
+#define FMC_NBL_SETUPTIME_3 (0x00C00000U)
/**
* @}
*/
@@ -521,7 +522,7 @@
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+#define FMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
@@ -529,8 +530,8 @@
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
-#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
+#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
@@ -538,7 +539,7 @@
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
@@ -546,8 +547,8 @@
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
-#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
@@ -555,8 +556,8 @@
/** @defgroup FMC_ECC FMC ECC
* @{
*/
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
+#define FMC_NAND_ECC_DISABLE (0x00000000U)
+#define FMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
@@ -564,12 +565,12 @@
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
@@ -582,9 +583,9 @@
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{
*/
-#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
-#define FMC_IT_LEVEL ((uint32_t)0x00000010)
-#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
+#define FMC_IT_RISING_EDGE (0x00000008U)
+#define FMC_IT_LEVEL (0x00000010U)
+#define FMC_IT_FALLING_EDGE (0x00000020U)
/**
* @}
*/
@@ -592,10 +593,10 @@
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @{
*/
-#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
-#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define FMC_FLAG_RISING_EDGE (0x00000001U)
+#define FMC_FLAG_LEVEL (0x00000002U)
+#define FMC_FLAG_FALLING_EDGE (0x00000004U)
+#define FMC_FLAG_FEMPT (0x00000040U)
/**
* @}
*/
@@ -624,7 +625,7 @@
* @retval None
*/
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- |= FMC_BCRx_MBKEN)
+ |= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
@@ -633,7 +634,7 @@
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- &= ~FMC_BCRx_MBKEN)
+ &= ~FMC_BCRx_MBKEN)
/**
* @}
@@ -744,13 +745,14 @@
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_InitTypeDef *Init);
+ FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
- FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
@@ -775,9 +777,9 @@
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
- FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
- FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
@@ -789,7 +791,7 @@
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
- uint32_t Timeout);
+ uint32_t Timeout);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_icache.h b/Inc/stm32l5xx_ll_icache.h
new file mode 100644
index 0000000..6cfebd4
--- /dev/null
+++ b/Inc/stm32l5xx_ll_icache.h
@@ -0,0 +1,782 @@
+/**
+ ******************************************************************************
+ * @file stm32l5xx_ll_icache.h
+ * @author MCD Application Team
+ * @brief Header file of ICACHE LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion ------------------------------------*/
+#ifndef STM32L5xx_LL_ICACHE_H
+#define STM32L5xx_LL_ICACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes -----------------------------------------------------------------*/
+#include "stm32l5xx.h"
+
+/** @addtogroup STM32L5xx_LL_Driver
+ * @{
+ */
+
+#if defined(ICACHE)
+
+/** @defgroup ICACHE_LL ICACHE
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure
+ * @{
+ */
+
+/**
+ * @brief LL ICACHE region configuration structure definition
+ */
+typedef struct
+{
+ uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */
+
+ uint32_t RemapAddress; /*!< Configures the remap address to be remapped */
+
+ uint32_t Size; /*!< Configures the region size.
+ This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */
+
+ uint32_t TrafficRoute; /*!< Selects the traffic route.
+ This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */
+
+ uint32_t OutputBurstType; /*!< Selects the output burst type.
+ This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */
+} LL_ICACHE_RegionTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants -------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
+ * @{
+ */
+
+/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
+ * @{
+ */
+#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
+#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
+ * @{
+ */
+#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
+#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
+#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_ICACHE_ReadReg function
+ * @{
+ */
+#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
+#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
+#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_ICACHE_WriteReg function
+ * @{
+ */
+#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
+#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
+ * @{
+ */
+#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
+#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Region Remapped Region number
+ * @{
+ */
+#define LL_ICACHE_REGION_0 0U /*!< Region 0 */
+#define LL_ICACHE_REGION_1 1U /*!< Region 1 */
+#define LL_ICACHE_REGION_2 2U /*!< Region 2 */
+#define LL_ICACHE_REGION_3 3U /*!< Region 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size
+ * @{
+ */
+#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
+#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
+#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
+#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
+#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
+#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
+#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route
+ * @{
+ */
+#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */
+#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type
+ * @{
+ */
+#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
+#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ----------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
+ * @{
+ */
+
+/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ICACHE register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ICACHE register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
+ * @{
+ */
+
+/** @defgroup ICACHE_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable the ICACHE.
+ * @rmtoll CR EN LL_ICACHE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_Enable(void)
+{
+ SET_BIT(ICACHE->CR, ICACHE_CR_EN);
+}
+
+/**
+ * @brief Disable the ICACHE.
+ * @rmtoll CR EN LL_ICACHE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_Disable(void)
+{
+ CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
+}
+
+/**
+ * @brief Return if ICACHE is enabled or not.
+ * @rmtoll CR EN LL_ICACHE_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
+{
+ return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select the ICACHE operating mode.
+ * @rmtoll CR WAYSEL LL_ICACHE_SetMode
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_1WAY
+ * @arg @ref LL_ICACHE_2WAYS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
+{
+ MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
+}
+
+/**
+ * @brief Get the selected ICACHE operating mode.
+ * @rmtoll CR WAYSEL LL_ICACHE_GetMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_1WAY
+ * @arg @ref LL_ICACHE_2WAYS
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
+{
+ return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
+}
+
+/**
+ * @brief Invalidate the ICACHE.
+ * @note Until the BSYEND flag is set, the cache is bypassed.
+ * @rmtoll CR CACHEINV LL_ICACHE_Invalidate
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_Invalidate(void)
+{
+ SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_Monitors Monitors
+ * @{
+ */
+
+/**
+ * @brief Enable the hit/miss monitor(s).
+ * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors\n
+ * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
+{
+ SET_BIT(ICACHE->CR, Monitors);
+}
+
+/**
+ * @brief Disable the hit/miss monitor(s).
+ * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors\n
+ * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
+{
+ CLEAR_BIT(ICACHE->CR, Monitors);
+}
+
+/**
+ * @brief Check if the monitor(s) is(are) enabled or disabled.
+ * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors\n
+ * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval State of parameter value (1 or 0).
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
+{
+ return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Reset the hit/miss monitor(s).
+ * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors\n
+ * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
+ * @param Monitors This parameter can be one or a combination of the following values:
+ * @arg @ref LL_ICACHE_MONITOR_HIT
+ * @arg @ref LL_ICACHE_MONITOR_MISS
+ * @arg @ref LL_ICACHE_MONITOR_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
+{
+ /* Reset */
+ SET_BIT(ICACHE->CR, (Monitors << 2U));
+ /* Release reset */
+ CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
+}
+
+/**
+ * @brief Get the Hit monitor.
+ * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
+ * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
+{
+ return (ICACHE->HMONR);
+}
+
+/**
+ * @brief Get the Miss monitor.
+ * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
+ * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
+{
+ return (ICACHE->MMONR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable BSYEND interrupt.
+ * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
+{
+ SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+}
+
+/**
+ * @brief Disable BSYEND interrupt.
+ * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
+{
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
+}
+
+/**
+ * @brief Check if the BSYEND Interrupt is enabled or disabled.
+ * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
+{
+ return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable ERR interrupt.
+ * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
+{
+ SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+}
+
+/**
+ * @brief Disable ERR interrupt.
+ * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
+{
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
+}
+
+/**
+ * @brief Check if the ERR Interrupt is enabled or disabled.
+ * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
+{
+ return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of an ongoing operation flag.
+ * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
+{
+ return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of an operation end flag.
+ * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
+{
+ return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Indicate the status of an error flag.
+ * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
+{
+ return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear busy end of operation flag.
+ * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
+{
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+}
+
+/**
+ * @brief Clear error flag.
+ * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
+{
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the remapped memory region.
+ * @note The region must have been already configured.
+ * @rmtoll CRRx REN LL_ICACHE_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region)
+{
+ SET_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REN);
+}
+
+/**
+ * @brief Disable the remapped memory region.
+ * @rmtoll CRRx REN LL_ICACHE_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region)
+{
+ CLEAR_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REN);
+}
+
+/**
+ * @brief Return if remapped memory region is enabled or not.
+ * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
+{
+ return ((READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Select the memory remapped region base address.
+ * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Address Alias address in the Code region
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
+{
+ MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR));
+}
+
+/**
+ * @brief Get the memory remapped region base address.
+ * @note The base address is the alias in the Code region.
+ * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Address Alias address in the Code region
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
+{
+ return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_BASEADDR));
+}
+
+/**
+ * @brief Select the memory remapped region remap address.
+ * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Address External memory address
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
+{
+ MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos));
+}
+
+/**
+ * @brief Get the memory remapped region base address.
+ * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Address External memory address
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
+{
+ return ((READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U);
+}
+
+/**
+ * @brief Select the memory remapped region size.
+ * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Size This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGIONSIZE_2MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_4MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_8MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_16MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_32MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_64MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_128MB
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size)
+{
+ MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos));
+}
+
+/**
+ * @brief Get the selected the memory remapped region size.
+ * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_REGIONSIZE_2MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_4MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_8MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_16MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_32MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_64MB
+ * @arg @ref LL_ICACHE_REGIONSIZE_128MB
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region)
+{
+ return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos);
+}
+
+/**
+ * @brief Select the memory remapped region output burst type.
+ * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type)
+{
+ MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_HBURST, Type);
+}
+
+/**
+ * @brief Get the selected the memory remapped region output burst type.
+ * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
+ * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)
+{
+ return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_HBURST));
+}
+
+/**
+ * @brief Select the memory remapped region cache master port.
+ * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_MASTER1_PORT
+ * @arg @ref LL_ICACHE_MASTER2_PORT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port)
+{
+ MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_MSTSEL, Port);
+}
+
+/**
+ * @brief Get the selected the memory remapped region cache master port.
+ * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ICACHE_MASTER1_PORT
+ * @arg @ref LL_ICACHE_MASTER2_PORT
+ */
+__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region)
+{
+ return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
+ ICACHE_CRRx_MSTSEL));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions
+ * @{
+ */
+
+void LL_ICACHE_ConfigRegion(uint32_t Region, LL_ICACHE_RegionTypeDef *ICACHE_RegionStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ICACHE */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_LL_ICACHE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l5xx_ll_iwdg.h b/Inc/stm32l5xx_ll_iwdg.h
index fa62fbf..13baa96 100644
--- a/Inc/stm32l5xx_ll_iwdg.h
+++ b/Inc/stm32l5xx_ll_iwdg.h
@@ -304,8 +304,8 @@
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
- * SR WVU LL_IWDG_IsReady\n
- * SR RVU LL_IWDG_IsReady
+ * SR RVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
@@ -318,7 +318,6 @@
* @}
*/
-
/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_opamp.h b/Inc/stm32l5xx_ll_opamp.h
index 5545388..9b70a49 100644
--- a/Inc/stm32l5xx_ll_opamp.h
+++ b/Inc/stm32l5xx_ll_opamp.h
@@ -153,8 +153,11 @@
/** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode
* @{
*/
-#define LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET) /*!< OPAMP power mode normal */
+#define LL_OPAMP_POWERMODE_NORMALPOWER (OPAMP_POWERMODE_OTR_REGOFFSET) /*!< OPAMP power mode normal */
#define LL_OPAMP_POWERMODE_LOWPOWER (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPALPM) /*!< OPAMP power mode low-power */
+
+#define LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALPOWER /*!< OPAMP power mode normal - Old Naming for compatibility */
+
/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_rcc.h b/Inc/stm32l5xx_ll_rcc.h
index 2963597..c9ccc63 100644
--- a/Inc/stm32l5xx_ll_rcc.h
+++ b/Inc/stm32l5xx_ll_rcc.h
@@ -1056,8 +1056,9 @@
* @arg @ref LL_RCC_PLLR_DIV_8
* @retval PLL clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
- ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+ ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
/**
* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
@@ -1115,8 +1116,9 @@
* @arg @ref LL_RCC_PLLP_DIV_31
* @retval PLL clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
- ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+ ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
/**
* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
@@ -1148,8 +1150,9 @@
* @arg @ref LL_RCC_PLLQ_DIV_8
* @retval PLL clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
- ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
+ ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
+ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
/**
* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
@@ -1208,8 +1211,8 @@
* @retval PLLSAI1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
- ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
- ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
/**
* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
@@ -1242,8 +1245,8 @@
* @retval PLLSAI1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
- ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
- ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
/**
* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
@@ -1276,8 +1279,8 @@
* @retval PLLSAI1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
- ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
- ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
+ ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
+ ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
/**
* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
@@ -1336,8 +1339,8 @@
* @retval PLLSAI2 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
- ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
- ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
+ ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
+ ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
/**
* @brief Helper macro to calculate the HCLK frequency
@@ -1354,7 +1357,8 @@
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval HCLK clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \
+ ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
/**
* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
@@ -1414,9 +1418,10 @@
* @arg @ref LL_RCC_MSISRANGE_7
* @retval MSI clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
- MSIRangeTable[((__MSIRANGE__) >> RCC_CSR_MSISRANGE_Pos) & 0x0FU] : \
- MSIRangeTable[((__MSIRANGE__) >> RCC_CR_MSIRANGE_Pos) & 0x0FU])
+#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) \
+ (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
+ MSIRangeTable[((__MSIRANGE__) >> RCC_CSR_MSISRANGE_Pos) & 0x0FU] : \
+ MSIRangeTable[((__MSIRANGE__) >> RCC_CR_MSIRANGE_Pos) & 0x0FU])
/**
* @}
diff --git a/Inc/stm32l5xx_ll_rtc.h b/Inc/stm32l5xx_ll_rtc.h
index 4557e30..affb447 100644
--- a/Inc/stm32l5xx_ll_rtc.h
+++ b/Inc/stm32l5xx_ll_rtc.h
@@ -5328,6 +5328,79 @@
}
/**
+ * @brief Enable Temperature Monitoring.
+ * @rmtoll TAMP_CFGR TMONEN LL_RTC_EnableTemperatureMonitoring
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableTemperatureMonitoring(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN);
+}
+
+/**
+ * @brief Disable Temperature Monitoring.
+ * @rmtoll TAMP_CFGR TMONEN LL_RTC_DisableTemperatureMonitoring
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableTemperatureMonitoring(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN);
+}
+
+/**
+ * @brief Enable Voltage Monitoring.
+ * @rmtoll TAMP_CFGR VMONEN LL_RTC_EnableVoltageMonitoring
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableVoltageMonitoring(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN);
+}
+
+/**
+ * @brief Disable Voltage Monitoring.
+ * @rmtoll TAMP_CFGR VMONEN LL_RTC_DisableVoltageMonitoring
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableVoltageMonitoring(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN);
+}
+
+/**
+ * @brief Enable WUT Monitoring.
+ * @rmtoll TAMP_CFGR WUTMONEN LL_RTC_EnableWUTMonitoring
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableWUTMonitoring(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ SET_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN);
+}
+
+/**
+ * @brief Disable WUT Monitoring.
+ * @rmtoll TAMP_CFGR WUTMONEN LL_RTC_DisableWUTMonitoring
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableWUTMonitoring(RTC_TypeDef *RTCx)
+{
+ UNUSED(RTCx);
+ CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN);
+}
+
+
+/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_sdmmc.h b/Inc/stm32l5xx_ll_sdmmc.h
index f2b50bf..f9c246f 100644
--- a/Inc/stm32l5xx_ll_sdmmc.h
+++ b/Inc/stm32l5xx_ll_sdmmc.h
@@ -22,7 +22,7 @@
#define STM32L5xx_LL_SDMMC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -66,7 +66,7 @@
uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher.
This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */
#endif /* USE_SD_TRANSCEIVER */
-}SDMMC_InitTypeDef;
+} SDMMC_InitTypeDef;
/**
@@ -92,7 +92,7 @@
uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_CPSM_State */
-}SDMMC_CmdInitTypeDef;
+} SDMMC_CmdInitTypeDef;
/**
@@ -117,7 +117,7 @@
uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_DPSM_State */
-}SDMMC_DataInitTypeDef;
+} SDMMC_DataInitTypeDef;
/**
* @}
@@ -135,13 +135,13 @@
#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the */
+ /*!< number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock */
+ /*!< command or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
@@ -152,8 +152,8 @@
#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
+#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out */
+ /*!< of erase sequence command was received */
#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
@@ -172,12 +172,12 @@
#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its */
+ /*!< operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information */
+ /*!< and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
@@ -185,18 +185,18 @@
#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
- (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
- for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
- STOP_TRANSMISSION command. */
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands */
+ /*!< (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
+/*!< for SDHS and SDXC. */
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */
+ /*!< fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by */
+ /*!< STOP_TRANSMISSION command. */
#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */
+ /*!< fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
@@ -205,32 +205,32 @@
#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
- system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
- Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command */
+ /*!< system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. */
+ /*!< Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
- the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
- than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
- for general purpose/application specific commands. */
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by */
+ /*!< the SET_BLOCK_LEN command. */
+#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather */
+ /*!< than a standard command. */
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card */
+ /*!< for general purpose/application specific commands. */
#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
- widths are given in SCR register. */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus */
+ /*!< widths are given in SCR register. */
#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
- 32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
- send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with */
+ /*!< 32bit+CRC data block. */
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to */
+ /*!< send its operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
@@ -503,14 +503,18 @@
#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
-#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
-#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \
+ SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \
+ SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
@@ -642,21 +646,21 @@
#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
-#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
- SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
- SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
- SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
- SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
- SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
- SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
+#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
+ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
+ SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
+ SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
+ SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
-#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
- SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
+#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
+ SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
-#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
- SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
- SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
- SDMMC_FLAG_IDMABTC))
+#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
+ SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
+ SDMMC_FLAG_IDMABTC))
/**
* @}
*/
@@ -707,9 +711,9 @@
*/
/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/**
* @brief Enable the SDMMC device interrupt.
@@ -1034,7 +1038,7 @@
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
@@ -1059,7 +1063,7 @@
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
-uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
@@ -1106,7 +1110,7 @@
* @}
*/
- /**
+/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_system.h b/Inc/stm32l5xx_ll_system.h
index 0cfec05..18f9456 100644
--- a/Inc/stm32l5xx_ll_system.h
+++ b/Inc/stm32l5xx_ll_system.h
@@ -59,16 +59,16 @@
* @{
*/
/**
- * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
- */
+ * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
+ */
#define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x0BFA0579UL)) /*!< Address of VREFBUF trimming value for VRS=0,
VREF_SC0 in STM32L5 datasheet */
#define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x0BFA0530UL)) /*!< Address of VREFBUF trimming value for VRS=1,
VREF_SC1 in STM32L5 datasheet */
/**
- * @brief Power-down in Run mode Flash key
- */
+ * @brief Power-down in Run mode Flash key
+ */
#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
diff --git a/Inc/stm32l5xx_ll_tim.h b/Inc/stm32l5xx_ll_tim.h
index d6b3466..f3e3a7a 100644
--- a/Inc/stm32l5xx_ll_tim.h
+++ b/Inc/stm32l5xx_ll_tim.h
@@ -601,8 +601,8 @@
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
* @{
*/
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
@@ -1545,7 +1545,16 @@
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+ uint32_t counter_mode;
+
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+ if (counter_mode == 0U)
+ {
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+ }
+
+ return counter_mode;
}
/**
@@ -2000,8 +2009,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -2045,8 +2054,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -2084,8 +2093,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -2118,7 +2127,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2150,7 +2159,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@@ -2187,7 +2196,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@@ -2219,7 +2228,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@@ -2244,8 +2253,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2270,8 +2279,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2296,9 +2305,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2322,8 +2331,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2347,8 +2356,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2372,9 +2381,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2401,8 +2410,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2428,8 +2437,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2457,9 +2466,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2728,8 +2737,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2756,8 +2765,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2780,8 +2789,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2806,8 +2815,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2831,8 +2840,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2869,8 +2878,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2906,8 +2915,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2935,7 +2944,7 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2963,7 +2972,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
@@ -3356,7 +3365,6 @@
*/
__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
{
-
MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
}
@@ -3696,7 +3704,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
SET_BIT(*pReg, Source);
}
@@ -3725,7 +3733,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@@ -3755,7 +3763,7 @@
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
/**
diff --git a/Inc/stm32l5xx_ll_usb.h b/Inc/stm32l5xx_ll_usb.h
index 208ec14..5da5131 100644
--- a/Inc/stm32l5xx_ll_usb.h
+++ b/Inc/stm32l5xx_ll_usb.h
@@ -135,10 +135,10 @@
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
-#define EP_MPS_64 0U
-#define EP_MPS_32 1U
-#define EP_MPS_16 2U
-#define EP_MPS_8 3U
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
/**
* @}
*/
@@ -163,10 +163,10 @@
* @}
*/
-#define BTABLE_ADDRESS 0x000U
+#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
-#define EP_ADDR_MSK 0x7U
+#define EP_ADDR_MSK 0x7U
/**
* @}
*/
@@ -187,32 +187,28 @@
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
+
+#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
-void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+#endif
+
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
-void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
-
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes);
+
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes);
/**
* @}
diff --git a/README.md b/README.md
index f74c7c8..1b2c3e5 100644
--- a/README.md
+++ b/README.md
@@ -38,9 +38,10 @@
HAL Driver L5 | CMSIS Device L5 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
-Tag v1.0.0 | Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0 (and following, if any, till next tag)
-Tag v1.0.2 | Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0 (and following, if any, till next tag)
-Tag v1.0.3 | Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0 (and following, if any, till next tag)
+Tag v1.0.0 | Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0
+Tag v1.0.2 | Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0
+Tag v1.0.3 | Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0
+Tag v1.0.4 | Tag v1.0.4 | Tag v5.6.0_cm33 | Tag v1.4.0 (and following, if any, till next tag)
The full **STM32CubeL5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL5).
diff --git a/Release_Notes.html b/Release_Notes.html
index 0feee71..2bc0a4f 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -11,24 +11,22 @@
span.underline{text-decoration: underline;}
div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
- <link rel="stylesheet" href="_htmresc/mini-st.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
+ <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
</head>
<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
<center>
-<h1 id="release-notes-for-stm32l5xx-hal-drivers"><small>Release Notes for</small> <strong>STM32L5xx HAL Drivers</strong></h1>
+<h1 id="release-notes-for">Release Notes for</h1>
+<h1 id="stm32l5xx-hal-drivers"><mark>STM32L5xx HAL Drivers</mark></h1>
<p>Copyright © 2019 STMicroelectronics<br />
</p>
-<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
-</div>
-</div>
<h1 id="license">License</h1>
<p>This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
@@ -46,15 +44,177 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
+<input type="checkbox" id="collapse-section5" checked aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.0.4 / 10-February-2021</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
-<p><strong>Fourth release</strong></p>
+<p><strong>Maintenance release</strong></p>
<h2 id="contents">Contents</h2>
-<p>Fourth release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
+<p>Maintenance release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
<ul>
+<li><strong>HAL ADC</strong> driver
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+<li><strong>HAL CORTEX</strong> driver
+<ul>
+<li>Add APIs for MPU control:
+<ul>
+<li>HAL_MPU_Enable(), HAL_MPU_Disable(), HAL_MPU_ConfigRegion() and HAL_MPU_ConfigMemoryAttributes()</li>
+<li>HAL_MPU_Enable_NS(), HAL_MPU_Disable_NS(), HAL_MPU_ConfigRegion_NS() and HAL_MPU_ConfigMemoryAttributes_NS() for non-secure MPU control</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL CRYP</strong> driver
+<ul>
+<li>Add capability to manage GCM/GMAC/CCM header feed in DMA mode</li>
+</ul></li>
+<li><strong>HAL DAC</strong> driver
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+<li><strong>HAL ICACHE</strong> driver
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+<li><strong>HAL IWDG</strong> driver
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+<li><strong>HAL LPTIM</strong> driver
+<ul>
+<li>Update external clock configuration for some ClockSource/CounterSource combinations</li>
+</ul></li>
+<li><strong>HAL MMC</strong> driver
+<ul>
+<li>High speed mode frequency computed based on real clock value</li>
+</ul></li>
+<li><strong>HAL NAND</strong> driver
+<ul>
+<li>Fix read and write in spare area (16-bits addressing)</li>
+</ul></li>
+<li><strong>HAL OPAMP</strong> driver
+<ul>
+<li>Rename definition OPAMP_POWERMODE_NORMAL to OPAMP_POWERMODE_NORMALPOWER</li>
+</ul></li>
+<li><strong>HAL PCD</strong> driver
+<ul>
+<li>Fix device ISO IN double buffer mode</li>
+<li>Fix PMA rx count descriptor update</li>
+</ul></li>
+<li><strong>HAL RCC</strong> driver
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+<li><strong>HAL RNG</strong> driver
+<ul>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+<li><strong>HAL RTC</strong> driver
+<ul>
+<li>Add APIs for daylight saving time:
+<ul>
+<li>HAL_RTC_DST_Add1Hour(), HAL_RTC_DST_Sub1Hour(), HAL_RTC_DST_SetStoreOperation(), HAL_RTC_DST_ClearStoreOperation() and HAL_RTC_DST_ReadStoreOperation()</li>
+</ul></li>
+<li>Add APIs for monitoring functions:
+<ul>
+<li>HAL_RTCEx_EnableTemperatureMonitoring() and HAL_RTCEx_DisableTemperatureMonitoring()</li>
+<li>HAL_RTCEx_EnableVoltageMonitoring() and HAL_RTCEx_DisableVoltageMonitoring()</li>
+<li>HAL_RTCEx_EnableWUTMonitoring() and HAL_RTCEx_DisableWUTMonitoring()</li>
+</ul></li>
+<li>Fix clear of registers synchronization flag (RSF) in HAL_RTC_WaitForSynchro()</li>
+</ul></li>
+<li><strong>HAL SDMMC</strong> driver
+<ul>
+<li>High speed mode frequency computed based on real clock value</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> driver
+<ul>
+<li><strong>Add extension files stm32l5xx_hal_smbus_ex.h/.c</strong> for new APIs:
+<ul>
+<li>HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus()</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SPI</strong> driver
+<ul>
+<li>Fix code optimization problem in SPI_WaitFifoStateUntilTimeout()</li>
+</ul></li>
+<li><strong>HAL TIM</strong> driver
+<ul>
+<li>Fix HAL_TIM_OnePulse_Start() not to ignore OutputChannel parameter</li>
+<li>Fix counter value latch delay at high frequency in HAL_TIM_IC_Start_DMA()</li>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
+</ul></li>
+<li><strong>HAL TSC</strong> driver
+<ul>
+<li>Add assert macro to avoid wrong CPLT/PGPSC configuration</li>
+</ul></li>
+</ul>
+<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<ul>
+<li><strong>New LL ICACHE driver: new stm32l5xx_ll_icache.h/.c files</strong>
+<ul>
+<li>Add APIs for ICACHE control:
+<ul>
+<li>LL_ICACHE_Enable(), LL_ICACHE_Disable(), LL_ICACHE_IsEnabled(), LL_ICACHE_SetMode(), LL_ICACHE_GetMode(), LL_ICACHE_Invalidate(), LL_ICACHE_EnableMonitors(), LL_ICACHE_DisableMonitors(), LL_ICACHE_IsEnabledMonitors(), LL_ICACHE_ResetMonitors(), LL_ICACHE_GetHitMonitor() and LL_ICACHE_GetMissMonitor()</li>
+<li>LL_ICACHE_ConfigRegion()</li>
+</ul></li>
+</ul></li>
+<li><strong>LL ADC</strong> driver
+<ul>
+<li>Increase internal regulator stabilization time from 10us to 20us (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US)</li>
+</ul></li>
+<li><strong>LL CORTEX</strong> driver
+<ul>
+<li>Add APIs for MPU control:
+<ul>
+<li>LL_MPU_Enable(), LL_MPU_Disable(), LL_MPU_IsEnabled(), LL_MPU_EnableRegion(), LL_MPU_DisableRegion(), LL_MPU_IsEnabledRegion(), LL_MPU_ConfigRegion(), LL_MPU_ConfigRegionAddress(), LL_MPU_ConfigAttributes(), LL_MPU_SetRegionBaseAddress(), LL_MPU_GetRegionBaseAddress(), LL_MPU_SetRegionLimitAddress(), LL_MPU_GetRegionLimitAddress(), LL_MPU_SetRegionAccess() and LL_MPU_GetRegionAccess()</li>
+<li>LL_MPU_Enable_NS(), LL_MPU_Disable_NS(), LL_MPU_IsEnabled_NS(), LL_MPU_EnableRegion_NS(), LL_MPU_DisableRegion_NS(), LL_MPU_IsEnabledRegion_NS(), LL_MPU_ConfigRegion_NS(), LL_MPU_ConfigRegionAddress_NS(), LL_MPU_ConfigAttributes_NS(), LL_MPU_SetRegionBaseAddress_NS(), LL_MPU_GetRegionBaseAddress_NS(), LL_MPU_SetRegionLimitAddress_NS(), LL_MPU_GetRegionLimitAddress_NS(), LL_MPU_SetRegionAccess_NS() and LL_MPU_GetRegionAccess_NS() for non-secure MPU</li>
+</ul></li>
+</ul></li>
+<li><strong>LL OPAMP</strong> driver
+<ul>
+<li>Rename definition LL_OPAMP_POWERMODE_NORMAL to LL_OPAMP_POWERMODE_NORMALPOWER</li>
+</ul></li>
+<li><strong>LL RTC</strong> driver
+<ul>
+<li>Add APIs for monitoring functions:
+<ul>
+<li>LL_RTC_EnableTemperatureMonitoring() and LL_RTC_DisableTemperatureMonitoring()</li>
+<li>LL_RTC_EnableVoltageMonitoring() and LL_RTC_DisableVoltageMonitoring()</li>
+<li>LL_RTC_EnableWUTMonitoring() and LL_RTC_DisableWUTMonitoring()</li>
+</ul></li>
+</ul></li>
+<li><strong>LL SPI</strong> driver
+<ul>
+<li>Fix LL_SPI_Init() for Rx FIFO threshold if 8-bits mode</li>
+</ul></li>
+<li><strong>LL TIM</strong> driver
+<ul>
+<li>Fix LL_TIM_GetCounterMode()</li>
+<li>Fix inverted comment for One Pulse Mode definitions</li>
+</ul></li>
+<li><strong>LL USART</strong> driver
+<ul>
+<li>Fix LL_USART_ClockInit() to configure clock phase and clock polarity when CR2_CLKEN is cleared</li>
+<li>Remove useless IS_LL_USART_BRR_MAX() macro</li>
+</ul></li>
+</ul>
+<h2 id="notes">Notes</h2>
+<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
+<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<p><strong>Fourth release</strong></p>
+<h2 id="contents-1">Contents</h2>
+<p>Fourth release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
+<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<ul>
<li>Global removal of ‘register’ storage class qualifier deprecated since C++ 11</li>
<li><strong>HAL</strong> generic driver
<ul>
@@ -142,7 +302,7 @@
<li>Rework BRR register value computation in HAL_UART_Init() for ROM size gain</li>
</ul></li>
</ul>
-<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
<ul>
<li>Global removal of ‘register’ storage class qualifier deprecated since C++ 11</li>
<li><strong>LL GPIO</strong> driver
@@ -167,7 +327,7 @@
<li>Change default CFGR1 register values in LL_UCPD_StructInit()</li>
</ul></li>
</ul>
-<h2 id="notes">Notes</h2>
+<h2 id="notes-1">Notes</h2>
<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
</div>
@@ -175,12 +335,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<p><strong>Third release</strong></p>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<p>Third official release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL FLASH</strong> driver
<ul>
@@ -203,7 +363,7 @@
<li>Fix HAL_SPI_Receive_DMA() and HAL_SPI_TransmitReceive_DMA() to only disable TX DMA interrupt at end of DMA reception in Master RX 2 lines mode</li>
</ul></li>
</ul>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL UTILS</strong> driver
<ul>
@@ -213,7 +373,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="notes-1">Notes</h2>
+<h2 id="notes-2">Notes</h2>
<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
<h2 id="known-limitations">Known Limitations</h2>
@@ -228,12 +388,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<p><strong>Second release</strong></p>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<p>Second official release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
-<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
+<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL FLASH</strong> driver
<ul>
@@ -277,7 +437,7 @@
<li>Add receiver timeout interrupt management with new HAL_USART_ERROR_RTO error code in HAL_USART_IRQHandler()</li>
</ul></li>
</ul>
-<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL GPIO</strong> driver
<ul>
@@ -292,7 +452,7 @@
<li>Add LL_SetFlashLatency() API</li>
</ul></li>
</ul>
-<h2 id="notes-2">Notes</h2>
+<h2 id="notes-3">Notes</h2>
<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
</div>
@@ -300,9 +460,9 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<p><strong>First release</strong></p>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-4">Contents</h2>
<p>First official release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
<h3 id="hal-drivers">HAL Drivers</h3>
@@ -314,7 +474,7 @@
<ul>
<li>ADC, BUS, COMP, CORTEX, CRC, CRS, CRYP, DAC, DMA, DMAMUX, EXTI, GPIO, I2C, IWDG, LPTIM, LPUART, OPAMP, PKA, PWR, RCC, RNG, RTC, SDMMC, SPI, SYSTEM, TIM, UCPD, USART, UTILS, WWDG</li>
</ul>
-<h2 id="notes-3">Notes</h2>
+<h2 id="notes-4">Notes</h2>
<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
</div>
diff --git a/Src/stm32l5xx_hal.c b/Src/stm32l5xx_hal.c
index 605fdaf..702a47b 100644
--- a/Src/stm32l5xx_hal.c
+++ b/Src/stm32l5xx_hal.c
@@ -49,11 +49,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32L5xx HAL Driver version number
- */
+ * @brief STM32L5xx HAL Driver version number
+ */
#define STM32L5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L5XX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
-#define STM32L5XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
+#define STM32L5XX_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define STM32L5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L5XX_HAL_VERSION ((STM32L5XX_HAL_VERSION_MAIN << 24U)\
|(STM32L5XX_HAL_VERSION_SUB1 << 16U)\
@@ -89,8 +89,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
- *
+ * @brief Initialization and de-initialization functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -269,8 +269,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- *
+ * @brief HAL Control functions
+ *
@verbatim
===============================================================================
##### HAL Control functions #####
@@ -293,7 +293,7 @@
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
@@ -435,7 +435,7 @@
*/
uint32_t HAL_GetREVID(void)
{
- return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+ return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
@@ -444,7 +444,7 @@
*/
uint32_t HAL_GetDEVID(void)
{
- return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+ return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
@@ -453,7 +453,7 @@
*/
uint32_t HAL_GetUIDw0(void)
{
- return(READ_REG(*((uint32_t *)UID_BASE)));
+ return (READ_REG(*((uint32_t *)UID_BASE)));
}
/**
@@ -462,7 +462,7 @@
*/
uint32_t HAL_GetUIDw1(void)
{
- return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+ return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
@@ -471,7 +471,7 @@
*/
uint32_t HAL_GetUIDw2(void)
{
- return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+ return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
@@ -479,8 +479,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
- * @brief HAL Debug functions
- *
+ * @brief HAL Debug functions
+ *
@verbatim
===============================================================================
##### HAL Debug functions #####
@@ -534,8 +534,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
- * @brief HAL SYSCFG configuration functions
- *
+ * @brief HAL SYSCFG configuration functions
+ *
@verbatim
===============================================================================
##### HAL SYSCFG configuration functions #####
@@ -644,9 +644,9 @@
tickstart = HAL_GetTick();
/* Wait for VRR bit */
- while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
+ while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
{
- if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -710,8 +710,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions
- * @brief SYSCFG lock management functions.
- *
+ * @brief SYSCFG lock management functions.
+ *
@verbatim
===============================================================================
##### SYSCFG lock functions #####
@@ -755,7 +755,7 @@
uint32_t tmp_lock;
/* Check null pointer */
- if(pItem == NULL)
+ if (pItem == NULL)
{
return HAL_ERROR;
}
@@ -782,8 +782,8 @@
/** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions
- * @brief SYSCFG attributes management functions.
- *
+ * @brief SYSCFG attributes management functions.
+ *
@verbatim
===============================================================================
##### SYSCFG attributes functions #####
@@ -813,7 +813,7 @@
tmp = SYSCFG_S->SECCFGR;
/* Set or reset Item */
- if((Attributes & SYSCFG_SEC) != 0x00U)
+ if ((Attributes & SYSCFG_SEC) != 0x00U)
{
tmp |= Item;
}
@@ -837,7 +837,7 @@
HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
{
/* Check null pointer */
- if(pAttributes == NULL)
+ if (pAttributes == NULL)
{
return HAL_ERROR;
}
@@ -846,7 +846,7 @@
assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item));
/* Get the secure attribute state */
- if((SYSCFG_S->SECCFGR & Item) != 0U)
+ if ((SYSCFG_S->SECCFGR & Item) != 0U)
{
*pAttributes = SYSCFG_SEC;
}
diff --git a/Src/stm32l5xx_hal_adc.c b/Src/stm32l5xx_hal_adc.c
index 4519941..7e3065b 100644
--- a/Src/stm32l5xx_hal_adc.c
+++ b/Src/stm32l5xx_hal_adc.c
@@ -499,7 +499,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -857,31 +857,28 @@
HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
*/
ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
- }
- /* DeInit the low level hardware.
-
- For example:
- __HAL_RCC_ADC_FORCE_RESET();
- __HAL_RCC_ADC_RELEASE_RESET();
- __HAL_RCC_ADC_CLK_DISABLE();
-
- Keep in mind that all ADCs use the same clock: disabling
- the clock will reset all ADCs.
-
- */
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripherals instances */
+ /* sharing the same common ADC instance: ADC state is forced to */
+ /* a similar state as after device power-on. */
+ /* Note: A possible implementation is to add RCC bus reset of ADC */
+ /* (for example, using macro */
+ /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+ /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- if (hadc->MspDeInitCallback == NULL)
- {
- hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
- }
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
- /* DeInit the low level hardware */
- hadc->MspDeInitCallback(hadc);
+ /* DeInit the low level hardware */
+ hadc->MspDeInitCallback(hadc);
#else
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
@@ -1483,13 +1480,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -1599,13 +1600,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -2400,44 +2405,46 @@
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
- if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
- ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
{
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
{
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
{
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
}
}
}
@@ -2857,7 +2864,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -3334,13 +3341,17 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
@@ -3403,13 +3414,17 @@
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
}
@@ -3463,13 +3478,17 @@
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
}
diff --git a/Src/stm32l5xx_hal_adc_ex.c b/Src/stm32l5xx_hal_adc_ex.c
index f0aefc1..279638c 100644
--- a/Src/stm32l5xx_hal_adc_ex.c
+++ b/Src/stm32l5xx_hal_adc_ex.c
@@ -516,13 +516,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -878,6 +882,10 @@
/* Process locked */
__HAL_LOCK(hadc);
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -993,6 +1001,10 @@
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1020,13 +1032,20 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
@@ -1477,6 +1496,10 @@
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1504,13 +1527,20 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
@@ -2015,7 +2045,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -2083,7 +2113,7 @@
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSlave;
+ ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
/* Check the parameters */
@@ -2098,6 +2128,10 @@
/* Process locked */
__HAL_LOCK(hadc);
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
if (tmphadcSlave.Instance == NULL)
diff --git a/Src/stm32l5xx_hal_cortex.c b/Src/stm32l5xx_hal_cortex.c
index 9fc53eb..a8260cd 100644
--- a/Src/stm32l5xx_hal_cortex.c
+++ b/Src/stm32l5xx_hal_cortex.c
@@ -115,7 +115,18 @@
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @{
+ */
+#if (__MPU_PRESENT == 1)
+static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionInit);
+static void MPU_ConfigMemoryAttributes(MPU_Type* MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit);
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
@@ -142,15 +153,15 @@
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
- * @param PriorityGroup: The priority grouping bits length.
+ * @param PriorityGroup The priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
* 0 bit for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
@@ -167,13 +178,13 @@
/**
* @brief Set the priority of an interrupt.
- * @param IRQn: External interrupt number.
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l5xxxx.h))
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * @param PreemptPriority The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 7
* A lower priority value indicates a higher priority
- * @param SubPriority: the subpriority level for the IRQ channel.
+ * @param SubPriority The subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 7
* A lower priority value indicates a higher priority.
* @retval None
@@ -238,7 +249,7 @@
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
@@ -259,7 +270,7 @@
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
- (NVIC, SYSTICK) functionalities.
+ (NVIC, SYSTICK, MPU) functionalities.
@endverbatim
@@ -278,21 +289,21 @@
/**
* @brief Get the priority of an interrupt.
- * @param IRQn: External interrupt number.
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l5xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+ * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
* 0 bit for subpriority
- * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
@@ -345,8 +356,8 @@
}
/**
- * @brief Get active interrupt (read the active register in NVIC and return the active bit).
- * @param IRQn External interrupt number
+ * @brief Get active interrupt (read the active register in NVIC and return the active bit).
+ * @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l5xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
@@ -360,8 +371,8 @@
/**
* @brief Configure the SysTick clock source.
- * @param CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
+ * @param CLKSource specifies the SysTick clock source.
+ * This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
@@ -400,6 +411,130 @@
*/
}
+#if (__MPU_PRESENT == 1)
+
+/**
+ * @brief Enable the MPU.
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged accessto the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Follow ARM recommendation with */
+ /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
+ __DMB(); /* Force memory writes before continuing */
+ __ISB(); /* Flush and refill pipeline with updated permissions */
+}
+
+/**
+ * @brief Disable the MPU.
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+ /* Disable the MPU */
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Initialize and configure the Region and the memory to be protected.
+ * @param MPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit)
+{
+ MPU_ConfigRegion(MPU, MPU_RegionInit);
+}
+
+/**
+ * @brief Initialize and configure the memory attributes.
+ * @param MPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit)
+{
+ MPU_ConfigMemoryAttributes(MPU, MPU_AttributesInit);
+}
+
+#ifdef MPU_NS
+/**
+ * @brief Enable the non-secure MPU.
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged accessto the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Follow ARM recommendation with */
+ /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
+ __DMB(); /* Force memory writes before continuing */
+ __ISB(); /* Flush and refill pipeline with updated permissions */
+}
+
+/**
+ * @brief Disable the non-secure MPU.
+ * @retval None
+ */
+void HAL_MPU_Disable_NS(void)
+{
+ __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
+
+ /* Disable the MPU */
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
+ * @param MPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit)
+{
+ MPU_ConfigRegion(MPU_NS, MPU_RegionInit);
+}
+
+/**
+ * @brief Initialize and configure the memory attributes for non-secure MPU.
+ * @param MPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit)
+{
+ MPU_ConfigMemoryAttributes(MPU_NS, MPU_AttributesInit);
+}
+#endif /* MPU_NS */
+
+#endif /* __MPU_PRESENT */
+
/**
* @}
*/
@@ -408,7 +543,87 @@
* @}
*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CORTEX_Private_Functions
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+
+static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionInit)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_RegionInit->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_RegionInit->Enable));
+
+ /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
+ __DMB();
+
+ /* Set the Region number */
+ MPUx->RNR = MPU_RegionInit->Number;
+
+ if (MPU_RegionInit->Enable != MPU_REGION_DISABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable));
+
+ MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) |
+ ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
+ ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
+ ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
+
+ MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) |
+ ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
+ ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
+ }
+ else
+ {
+ MPUx->RBAR = 0U;
+ MPUx->RLAR = 0U;
+ }
+}
+
+static void MPU_ConfigMemoryAttributes(MPU_Type* MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit)
+{
+ __IO uint32_t *mair;
+ uint32_t attr_values;
+ uint32_t attr_number;
+
+ /* Check the parameters */
+ assert_param(IS_MPU_ATTRIBUTES_NUMBER(MPU_AttributesInit->Number));
+ /* No need to check Attributes value as all 0x0..0xFF possible */
+
+ /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
+ __DMB();
+
+ if(MPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
+ {
+ /* Program MPU_MAIR0 */
+ mair = &(MPUx->MAIR0);
+ attr_number = MPU_AttributesInit->Number;
+ }
+ else
+ {
+ /* Program MPU_MAIR1 */
+ mair = &(MPUx->MAIR1);
+ attr_number = (uint32_t)MPU_AttributesInit->Number - 4U;
+ }
+
+ attr_values = *(mair);
+ attr_values &= ~(0xFFU << (attr_number * 8U));
+ *(mair) = attr_values | ((uint32_t)MPU_AttributesInit->Attributes << (attr_number * 8U));
+}
+
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
#endif /* HAL_CORTEX_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_cryp.c b/Src/stm32l5xx_hal_cryp.c
index a41da89..50186bf 100644
--- a/Src/stm32l5xx_hal_cryp.c
+++ b/Src/stm32l5xx_hal_cryp.c
@@ -6,7 +6,7 @@
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
* + Initialization, de-initialization, set config and get config functions
- * + DES/TDES, AES processing functions
+ * + AES processing functions
* + DMA callback functions
* + CRYP IRQ handler management
* + Peripheral State functions
@@ -32,8 +32,8 @@
(+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+ interrupt on the two DMA channels. The output channel should have higher
+ priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#)Initialize the CRYP according to the specified parameters :
(##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
@@ -44,9 +44,13 @@
(+++) In some specific configurations, the key is written by the application
code out of the HAL scope. In that case, user can still resort to the
HAL APIs as usual but must make sure that pKey pointer is set to NULL.
+ (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
+ algorithms) is in words or bytes.
(##) The Header used only in AES GCM and CCM Algorithm for authentication.
- (##) The HeaderSize The size of header buffer in word.
- (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
+ (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
+ (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
@@ -194,11 +198,11 @@
[..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
+ Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
+ Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
(+) ErrorCallback : callback for error detection.
@@ -208,9 +212,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
@@ -220,13 +224,13 @@
(+) MspDeInitCallback : CRYP MspDeInit.
[..]
- By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
+ By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions :
- examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
+ examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
+ reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
+ if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
[..]
@@ -235,8 +239,8 @@
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
- or @ref HAL_CRYP_Init() function.
+ using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
+ or HAL_CRYP_Init() function.
[..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
@@ -321,6 +325,7 @@
#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
@@ -345,9 +350,7 @@
* @{
*/
-#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
- (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
- }while(0U)
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
/**
* @}
@@ -361,6 +364,7 @@
*/
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
@@ -370,6 +374,7 @@
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
@@ -383,6 +388,7 @@
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
@@ -418,13 +424,13 @@
(+) DeInitialize the CRYP MSP
(+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
Parameters which are configured in This section are :
- (+) Key size
- (+) Data Type : 32,16, 8 or 1bit
- (+) AlgoMode :
- - for CRYP1 peripheral :
+ (++) Key size
+ (++) Data Type : 32,16, 8 or 1bit
+ (++) AlgoMode :
+ (+++) for CRYP1 peripheral :
ECB and CBC in DES/TDES Standard
ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
- - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
+ (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
@endverbatim
@@ -581,15 +587,17 @@
__HAL_LOCK(hcryp);
/* Set CRYP parameters */
- hcryp->Init.DataType = pConf->DataType;
- hcryp->Init.pKey = pConf->pKey;
- hcryp->Init.Algorithm = pConf->Algorithm;
- hcryp->Init.KeySize = pConf->KeySize;
- hcryp->Init.pInitVect = pConf->pInitVect;
- hcryp->Init.Header = pConf->Header;
- hcryp->Init.HeaderSize = pConf->HeaderSize;
- hcryp->Init.B0 = pConf->B0;
- hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
+ hcryp->Init.DataType = pConf->DataType;
+ hcryp->Init.pKey = pConf->pKey;
+ hcryp->Init.Algorithm = pConf->Algorithm;
+ hcryp->Init.KeySize = pConf->KeySize;
+ hcryp->Init.pInitVect = pConf->pInitVect;
+ hcryp->Init.Header = pConf->Header;
+ hcryp->Init.HeaderSize = pConf->HeaderSize;
+ hcryp->Init.B0 = pConf->B0;
+ hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
+ hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
+ hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
/* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
@@ -655,7 +663,9 @@
pConf->Header = hcryp->Init.Header ;
pConf->HeaderSize = hcryp->Init.HeaderSize;
pConf->B0 = hcryp->Init.B0;
- pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
+ pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
+ pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
+ pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
@@ -687,8 +697,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspInit could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_MspInit can be implemented in the user file
*/
}
@@ -703,8 +713,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspDeInit could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_MspDeInit can be implemented in the user file
*/
}
@@ -1185,7 +1195,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1285,7 +1295,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1385,7 +1395,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1495,7 +1505,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1604,7 +1614,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1731,7 +1741,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1869,7 +1879,7 @@
/* Clear computation complete flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
{
/* if header phase */
@@ -1882,18 +1892,6 @@
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
- else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
- {
- /* if header phase */
- if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
- {
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
- {
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
- }
- }
else /* AES Algorithm ECB,CBC or CTR*/
{
CRYP_AES_IT(hcryp);
@@ -1935,8 +1933,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_InCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_InCpltCallback can be implemented in the user file
*/
}
@@ -1951,8 +1949,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_OutCpltCallback can be implemented in the user file
*/
}
@@ -1967,8 +1965,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_ErrorCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_ErrorCallback can be implemented in the user file
*/
}
/**
@@ -2502,18 +2500,105 @@
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
{
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
- /* Call input data transfer complete callback */
+ if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
+ {
+ /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if ((headersize_in_bytes % 16U) != 0U)
+ {
+ /* Write last words that couldn't be fed by DMA */
+ hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+
+ /* Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+ } /* if ((headersize_in_bytes % 16U) != 0U) */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
+ }
+ else
+ {
+ uint32_t algo;
+ /* ECB, CBC or CTR end of input data feeding
+ or
+ end of GCM/CCM payload data feeding through DMA */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ /* Don't call input data transfer complete callback only if
+ it remains some input data to write to the peripheral.
+ This case can only occur for GCM and CCM with a payload length
+ not a multiple of 16 bytes */
+ if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \
+ (((hcryp->Size) % 16U) != 0U)))
+ {
+ /* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */
}
/**
@@ -2526,7 +2611,7 @@
uint32_t count;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t mode;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -2577,46 +2662,31 @@
hcryp->Instance->DINR = 0x0U;
count++;
}
+ /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
/*Read the output block from the output FIFO */
for (count = 0U; count < 4U; count++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
+ temp[count] = hcryp->Instance->DOUTR;
+ }
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ count = 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
hcryp->CrypOutCount++;
+ count++;
}
}
@@ -2675,7 +2745,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr address of the input buffer
- * @param Size size of the input buffer, must be a multiple of 16.
+ * @param Size size of the input and output buffers in words, must be a multiple of 4
* @param outputaddr address of the output buffer
* @retval None
*/
@@ -2734,6 +2804,43 @@
}
/**
+ * @brief Set the DMA configuration and start the header DMA transfer
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr address of the input buffer
+ * @param Size size of the input buffer in words, must be a multiple of 4
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Mark that header is fed to the peripheral in DMA mode */
+ hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
+ /* Enable the DMA input stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ /* Call error callback */
+ }
+
+ /* Enable IN DMA requests */
+ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ return HAL_OK;
+}
+
+/**
* @brief Process Data: Write Input data in polling mode and used in AES functions.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
@@ -3162,6 +3269,12 @@
uint32_t lastwordsize;
uint32_t npblb;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@@ -3171,6 +3284,17 @@
}
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ /* Manage header size given in bytes to handle cases where
+ header size is not a multiple of 4 bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
@@ -3284,7 +3408,7 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3335,42 +3459,58 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- else if ((hcryp->Init.HeaderSize) < 4U)
+ /* Enter header data */
+ /* Cher first whether header length is small enough to enter the full header in one shot */
+ else if (headersize_in_bytes <= 16U)
{
- for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ /* Write header data, padded with zeros if need be */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++ ;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
{
- /* Write the input block in the IN FIFO */
+ /* Write the first input header block in the Input FIFO,
+ the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -3415,7 +3555,7 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3466,6 +3606,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -3482,12 +3630,7 @@
*/
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -3566,122 +3709,16 @@
return HAL_ERROR;
}
- /************************ Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
} /* if (DoKeyIVConfig == 1U) */
- if (hcryp->Size == 0U)
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- else if (hcryp->Size >= 16U)
- {
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else /* length of input data is < 16 */
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
-
- /* Set Npblb in case of AES GCM payload encryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
-
- /* Enable CRYP to start the final phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
- {
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -4075,6 +4112,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */
@@ -4180,6 +4225,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -4196,12 +4249,7 @@
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -4282,119 +4330,16 @@
return HAL_ERROR;
}
- /******************** Payload phase *****************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
} /* if (DoKeyIVConfig == 1U) */
- if (hcryp->Size == 0U)
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- else if (hcryp->Size >= 16U)
- {
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else /* length of input data is < 16 */
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
-
- /* Set Npblb in case of AES CCM payload decryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
- {
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -4493,9 +4438,9 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
- /* Call output transfer complete callback */
+ /* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
@@ -4541,11 +4486,152 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
/**
+ * @brief Sets the payload phase in DMA mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval state
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint16_t wordsize = hcryp->Size / 4U ;
+ uint32_t index;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
+ uint32_t reg;
+
+ /************************ Payload phase ************************************/
+ if (hcryp->Size == 0U)
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ /*DMA transfer must not include the last block in case of Size is not %16 */
+ wordsize = wordsize - (wordsize % 4U);
+
+ /*DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /* length of input data is < 16 */
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)hcryp->Size;
+
+ /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
+ reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE);
+ if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\
+ (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /*Read the output block from the output FIFO */
+ for (index = 0U; index < 4U; index++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+ hcryp->CrypOutCount++;
+ }
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
* @brief Sets the header phase in polling mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
@@ -4557,7 +4643,9 @@
uint32_t loopcounter;
uint32_t size_in_bytes;
uint32_t tmp;
- uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -4659,9 +4747,9 @@
}
else
{
- /* Enter last bytes, padded with zeroes */
+ /* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- tmp &= mask[size_in_bytes % 4U];
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
@@ -4691,17 +4779,14 @@
}
else
{
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
- /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+ /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
}
/* Return function status */
return HAL_OK;
@@ -4715,143 +4800,112 @@
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
- if ((hcryp->Init.HeaderSize != 0U))
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* If header size is at least equal to 16 bytes, feed the header through DMA.
+ If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
+ last bytes feeding and padding will be done in CRYP_DMAInCplt() */
+ if (headersize_in_bytes >= 16U)
+ {
+ /* Initiate header DMA transfer */
+ if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
{
- /* HeaderSize %4, no padding */
- for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
- {
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while (loopcounter < 4U)
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ return HAL_ERROR;
}
}
else
{
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ if (headersize_in_bytes != 0U)
+ {
+ /* Header length is larger than 0 and strictly less than 16 bytes */
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ } /* if (headersize_in_bytes != 0U) */
+
+ /* Move to payload phase if header length is null or
+ if the header length was less than 16 and header written by software instead of DMA */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ } /* if (headersize_in_bytes >= 16U) */
+
/* Return function status */
return HAL_OK;
}
@@ -4868,9 +4922,25 @@
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
/***************************** Header phase *********************************/
- if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ /* Test whether or not the header phase is over.
+ If the test below is true, move to payload phase */
+ if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -4953,11 +5023,19 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
+ else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
{
-
+ /* Can enter full 4 header words */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/* If suspension flag has been raised, suspend processing
only if not already at the end of the header */
@@ -4992,19 +5070,40 @@
hcryp->CrypHeaderCount++;
}
}
- else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
+ else /* Write last header block (4 words), padded with zeros if needed */
{
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
}
}
@@ -5014,6 +5113,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Timeout Timeout duration.
+ * @note This function can only be used in thread mode.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
@@ -5037,6 +5137,47 @@
return HAL_OK;
}
+/**
+ * @brief Wait for Computation Complete Flag (CCF) to raise then clear it.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @note This function can be used in thread or handler mode.
+ * @retval HAL status
+ */
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t count = Timeout;
+
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+}
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
@@ -5341,9 +5482,9 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
- if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
- /* Call output transfer complete callback */
+ /* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
diff --git a/Src/stm32l5xx_hal_dac.c b/Src/stm32l5xx_hal_dac.c
index 200c86b..512af62 100644
--- a/Src/stm32l5xx_hal_dac.c
+++ b/Src/stm32l5xx_hal_dac.c
@@ -1052,13 +1052,17 @@
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
- /* Update error code */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+ {
+ /* Update error code */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
- /* Change the DMA state */
- hdac->State = HAL_DAC_STATE_TIMEOUT;
+ /* Change the DMA state */
+ hdac->State = HAL_DAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
HAL_Delay(1);
@@ -1072,13 +1076,17 @@
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
- /* Update error code */
- SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+ {
+ /* Update error code */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
- /* Change the DMA state */
- hdac->State = HAL_DAC_STATE_TIMEOUT;
+ /* Change the DMA state */
+ hdac->State = HAL_DAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
HAL_Delay(1U);
diff --git a/Src/stm32l5xx_hal_exti.c b/Src/stm32l5xx_hal_exti.c
index 77902b8..549b7b5 100644
--- a/Src/stm32l5xx_hal_exti.c
+++ b/Src/stm32l5xx_hal_exti.c
@@ -4,7 +4,8 @@
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the General Purpose Input/Output (EXTI) peripheral:
+ * functionalities of the Extended Interrupts and event controller
+ * (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@@ -25,7 +26,7 @@
(++) Falling
(++) Both of them
- (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+ (+) When set in interrupt mode, configurable Exti lines have two different
interrupt pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
diff --git a/Src/stm32l5xx_hal_gtzc.c b/Src/stm32l5xx_hal_gtzc.c
index 54c00d6..bfa6c73 100644
--- a/Src/stm32l5xx_hal_gtzc.c
+++ b/Src/stm32l5xx_hal_gtzc.c
@@ -110,8 +110,8 @@
/* Private constants ---------------------------------------------------------*/
/** @defgroup GTZC_Private_Constants GTZC Private Constants
- * @{
- */
+ * @{
+ */
/* Definitions for GTZC_TZSC_MPCWM */
#define GTZC_TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
@@ -153,25 +153,25 @@
/* Private macros ------------------------------------------------------------*/
/** @defgroup GTZC_Private_Macros GTZC Private Macros
- * @{
- */
+ * @{
+ */
#define IS_ADDRESS_IN(mem, address)\
-( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
- && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
- || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
- && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
+ ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
+ || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
#define IS_ADDRESS_IN_S(mem, address)\
-( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
- && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
+ ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
#define IS_ADDRESS_IN_NS(mem, address)\
-( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
- && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
+ ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
+ && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
#define GTZC_BASE_ADDRESS(mem)\
-( mem ## _BASE )
+ ( mem ## _BASE )
/**
* @}
@@ -219,10 +219,9 @@
uint32_t register_address;
/* check entry parameters */
- if ( (PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
- || ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
- || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U)
- && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
+ || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
@@ -271,8 +270,7 @@
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* secure configuration */
- register_address = (uint32_t)&(GTZC_TZSC->SECCFGR1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
{
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
@@ -288,8 +286,7 @@
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* privilege configuration */
- register_address = (uint32_t)&(GTZC_TZSC->PRIVCFGR1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
{
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
@@ -326,10 +323,9 @@
uint32_t register_address;
/* check entry parameters */
- if ( (PeriphAttributes == NULL)
- || ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
- || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U)
- && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ if ((PeriphAttributes == NULL)
+ || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
@@ -342,7 +338,7 @@
reg_value = READ_REG(GTZC_TZSC->SECCFGR1);
for (i = 0U; i < 32U; i++)
{
- if(((reg_value & (1UL << i)) >> i) != 0U)
+ if (((reg_value & (1UL << i)) >> i) != 0U)
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
}
@@ -355,7 +351,7 @@
reg_value = READ_REG(GTZC_TZSC->SECCFGR2);
for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++)
{
- if(((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
+ if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
}
@@ -371,7 +367,7 @@
reg_value = READ_REG(GTZC_TZSC->PRIVCFGR1);
for (i = 0U; i < 32U; i++)
{
- if(((reg_value & (1UL << i)) >> i) != 0U)
+ if (((reg_value & (1UL << i)) >> i) != 0U)
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
}
@@ -384,7 +380,7 @@
reg_value = READ_REG(GTZC_TZSC->PRIVCFGR2);
for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++)
{
- if(((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
+ if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
}
@@ -400,11 +396,10 @@
/* common case where only one peripheral is configured */
/* secure configuration */
- register_address = (uint32_t)&(GTZC_TZSC->SECCFGR1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
- if(((READ_BIT(*(__IO uint32_t *)register_address,
- 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
+ if (((READ_BIT(*(__IO uint32_t *)register_address,
+ 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
!= 0U)
{
*PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
@@ -415,11 +410,10 @@
}
/* privilege configuration */
- register_address = (uint32_t)&(GTZC_TZSC->PRIVCFGR1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
- if(((READ_BIT(*(__IO uint32_t *)register_address,
- 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
+ if (((READ_BIT(*(__IO uint32_t *)register_address,
+ 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
!= 0U)
{
*PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
@@ -459,9 +453,8 @@
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(
- uint32_t MemBaseAddress,
- MPCWM_ConfigTypeDef *pMPCWM_Desc)
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
uint32_t register_address;
uint32_t reg_value;
@@ -470,11 +463,10 @@
uint32_t length_pos, length_msk;
/* check entry parameters */
- if ( (pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
- || ( (MemBaseAddress == FMC_BANK3)
- && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
- || (( pMPCWM_Desc->Offset % GTZC_TZSC_MPCWM_GRANULARITY) != 0U)
- || (( pMPCWM_Desc->Length % GTZC_TZSC_MPCWM_GRANULARITY) != 0U))
+ if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
+ || ((MemBaseAddress == FMC_BANK3) && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
+ || ((pMPCWM_Desc->Offset % GTZC_TZSC_MPCWM_GRANULARITY) != 0U)
+ || ((pMPCWM_Desc->Length % GTZC_TZSC_MPCWM_GRANULARITY) != 0U))
{
return HAL_ERROR;
}
@@ -486,44 +478,44 @@
size = GTZC_TZSC_MPCWM1_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
{
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR1);
- start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos;
- start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk;
- length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos;
- length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk;
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1);
+ start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos;
+ start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk;
+ length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos;
+ length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk;
}
else
{
- /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
- * (Parameter already checked)
- */
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR2);
- start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos;
- start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk;
- length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos;
- length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk;
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
+ * (Parameter already checked)
+ */
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2);
+ start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos;
+ start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk;
+ length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos;
+ length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk;
}
break;
case FMC_BANK1:
size = GTZC_TZSC_MPCWM1_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
{
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR1);
- start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos;
- start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk;
- length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos;
- length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk;
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1);
+ start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos;
+ start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk;
+ length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos;
+ length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk;
}
else
{
- /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
- * (Parameter already checked)
- */
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR2);
- start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos;
- start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk;
- length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos;
- length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk;
+ /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
+ * (Parameter already checked)
+ */
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2);
+ start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos;
+ start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk;
+ length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos;
+ length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk;
}
break;
case FMC_BANK3:
@@ -531,7 +523,7 @@
* (Parameter already checked)
*/
size = GTZC_TZSC_MPCWM3_MEM_SIZE;
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM3_NSWMR1);
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1);
start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos;
start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk;
length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos;
@@ -542,10 +534,8 @@
break;
}
- if ( (pMPCWM_Desc->Offset > size)
- || ( ( pMPCWM_Desc->Offset
- + pMPCWM_Desc->Length)
- > size))
+ if ((pMPCWM_Desc->Offset > size)
+ || ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size))
{
return HAL_ERROR;
}
@@ -565,9 +555,8 @@
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(
- uint32_t MemBaseAddress,
- MPCWM_ConfigTypeDef *pMPCWM_Desc)
+HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
+ MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
uint32_t register_address;
uint32_t reg_value;
@@ -578,21 +567,21 @@
switch (MemBaseAddress)
{
case OCTOSPI1_BASE:
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR1);
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1);
start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos;
start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk;
length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos;
length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk;
break;
case FMC_BANK1:
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR1);
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1);
start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos;
start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk;
length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos;
length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk;
break;
case FMC_BANK3:
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM3_NSWMR1);
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1);
start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos;
start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk;
length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos;
@@ -618,14 +607,14 @@
switch (MemBaseAddress)
{
case OCTOSPI1_BASE:
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR2);
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2);
start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos;
start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk;
length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos;
length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk;
break;
case FMC_BANK1:
- register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR2);
+ register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2);
start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos;
start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk;
length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos;
@@ -729,16 +718,12 @@
uint32_t i;
/* check entry parameters */
- if ( ( !(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
- && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
- || ( ( pMPCBB_desc->SecureRWIllegalMode
- != GTZC_MPCBB_SRWILADIS_ENABLE)
- && ( pMPCBB_desc->SecureRWIllegalMode
- != GTZC_MPCBB_SRWILADIS_DISABLE))
- || ( ( pMPCBB_desc->InvertSecureState
- != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
- && ( pMPCBB_desc->InvertSecureState
- != GTZC_MPCBB_INVSECSTATE_INVERTED)))
+ if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
+ || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
+ && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
+ || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
+ && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
{
return HAL_ERROR;
}
@@ -795,8 +780,8 @@
uint32_t i;
/* check entry parameters */
- if ( !(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
- && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
+ if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
+ && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
{
return HAL_ERROR;
}
@@ -820,8 +805,7 @@
pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
size_mask = (1UL << (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE)) - 1U;
/* limitation: code not portable with memory > 256K */
- pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->LCKVTR1)
- & size_mask;
+ pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->LCKVTR1)& size_mask;
/* read vector register information */
size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
@@ -860,26 +844,26 @@
/* check entry parameters and deduce physical base address */
end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
- if ( ( (IS_ADDRESS_IN_NS(SRAM1, MemAddress))
- && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U )
+ if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB1_S;
base_address = SRAM1_BASE_NS;
}
- else if ( ( (IS_ADDRESS_IN_S(SRAM1, MemAddress))
- && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U )
+ else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB1_S;
base_address = SRAM1_BASE_S;
}
- else if ( ( (IS_ADDRESS_IN_NS(SRAM2, MemAddress))
- && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U )
+ else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB2_S;
base_address = SRAM2_BASE_NS;
}
- else if ( ( (IS_ADDRESS_IN_S(SRAM2, MemAddress))
- && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U )
+ else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
+ && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB2_S;
base_address = SRAM2_BASE_S;
@@ -955,25 +939,25 @@
/* check entry parameters and deduce physical base address */
end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
- if ( (IS_ADDRESS_IN_NS(SRAM1, MemAddress))
+ if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM1, end_address)))
{
mpcbb_ptr = GTZC_MPCBB1_S;
base_address = SRAM1_BASE_NS;
}
- else if ( (IS_ADDRESS_IN_S(SRAM1, MemAddress))
+ else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM1, end_address)))
{
mpcbb_ptr = GTZC_MPCBB1_S;
base_address = SRAM1_BASE_S;
}
- else if ( (IS_ADDRESS_IN_NS(SRAM2, MemAddress))
+ else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM2, end_address)))
{
mpcbb_ptr = GTZC_MPCBB2_S;
base_address = SRAM2_BASE_NS;
}
- else if ( (IS_ADDRESS_IN_S(SRAM2, MemAddress))
+ else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM2, end_address)))
{
mpcbb_ptr = GTZC_MPCBB2_S;
@@ -991,8 +975,8 @@
for (i = 0U; i < NbBlocks; i++)
{
- pMemAttributes[i] = READ_BIT(mpcbb_ptr->VCTR[offset_reg_start],
- 1UL << (offset_bit_start % 32U))
+ pMemAttributes[i] = READ_BIT(mpcbb_ptr->VCTR[offset_reg_start],
+ 1UL << (offset_bit_start % 32U))
>> (offset_bit_start % 32U);
offset_bit_start++;
@@ -1034,20 +1018,19 @@
}
/* check entry parameters */
- if ( (IS_ADDRESS_IN(SRAM1, MemAddress))
+ if ((IS_ADDRESS_IN(SRAM1, MemAddress))
&& (IS_ADDRESS_IN(SRAM1, (MemAddress
- + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- - 1U))))
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
/* limitation: code not portable with memory > 256K */
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->LCKVTR1;
}
- else if ( (IS_ADDRESS_IN(SRAM2, MemAddress))
+ else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
&& (IS_ADDRESS_IN(SRAM2, (MemAddress
- + ( NbSuperBlocks
- * GTZC_MPCBB_SUPERBLOCK_SIZE)
- - 1U))))
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
/* limitation: code not portable with memory > 256K */
@@ -1117,20 +1100,19 @@
}
/* check entry parameters */
- if ( (IS_ADDRESS_IN(SRAM1, MemAddress))
+ if ((IS_ADDRESS_IN(SRAM1, MemAddress))
&& (IS_ADDRESS_IN(SRAM1, (MemAddress
- + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- - 1U))))
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
/* limitation: code not portable with memory > 256K */
reg_mpcbb = GTZC_MPCBB1_S->LCKVTR1;
}
- else if ( (IS_ADDRESS_IN(SRAM2, MemAddress))
+ else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
&& (IS_ADDRESS_IN(SRAM2, (MemAddress
- + ( NbSuperBlocks
- * GTZC_MPCBB_SUPERBLOCK_SIZE)
- - 1U))))
+ + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
+ - 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
/* limitation: code not portable with memory > 256K */
@@ -1147,8 +1129,8 @@
for (i = 0U; i < NbSuperBlocks; i++)
{
- pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
- >> (offset_bit_start % 32U);
+ pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
+ >> (offset_bit_start % 32U);
offset_bit_start++;
}
@@ -1235,9 +1217,8 @@
uint32_t register_address;
/* check entry parameters */
- if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
- || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U)
- && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
@@ -1252,8 +1233,7 @@
else
{
/* common case where only one peripheral is configured */
- register_address = (uint32_t)&(GTZC_TZIC->IER1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
@@ -1272,9 +1252,8 @@
uint32_t register_address;
/* check entry parameters */
- if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
- || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U)
- && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
@@ -1289,8 +1268,7 @@
else
{
/* common case where only one peripheral is configured */
- register_address = (uint32_t)&(GTZC_TZIC->IER1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
@@ -1317,9 +1295,8 @@
uint32_t register_address;
/* check entry parameters */
- if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
- || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U)
- && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
@@ -1348,10 +1325,9 @@
else
{
/* common case where only one peripheral is concerned */
- register_address = (uint32_t)&(GTZC_TZIC->SR1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZIC->SR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
*pFlag = READ_BIT(*(__IO uint32_t *)register_address,
- 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
+ 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
}
return HAL_OK;
@@ -1369,9 +1345,8 @@
uint32_t register_address;
/* check entry parameters */
- if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
- || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U)
- && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
+ if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
+ || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
@@ -1386,8 +1361,7 @@
else
{
/* common case where only one peripheral is configured */
- register_address = (uint32_t)&(GTZC_TZIC->FCR1)
- + (4U * GTZC_GET_REG_INDEX(PeriphId));
+ register_address = (uint32_t) &(GTZC_TZIC->FCR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
@@ -1428,7 +1402,7 @@
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
- if(flag != 0U)
+ if (flag != 0U)
{
WRITE_REG(GTZC_TZIC->FCR1, flag);
@@ -1452,7 +1426,7 @@
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
- if(flag != 0U)
+ if (flag != 0U)
{
WRITE_REG(GTZC_TZIC->FCR2, flag);
@@ -1476,7 +1450,7 @@
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
- if(flag != 0U)
+ if (flag != 0U)
{
WRITE_REG(GTZC_TZIC->FCR3, flag);
diff --git a/Src/stm32l5xx_hal_icache.c b/Src/stm32l5xx_hal_icache.c
index 469018d..afa6e23 100644
--- a/Src/stm32l5xx_hal_icache.c
+++ b/Src/stm32l5xx_hal_icache.c
@@ -44,7 +44,8 @@
@ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete()
may be called to wait for the end of the invalidate procedure automatically
- initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable()
+ initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable().
+ The cache operation is bypassed during the invalidation procedure.
(#) Use the performance monitoring counters for Hit and Miss with the following
functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(),
@@ -216,8 +217,12 @@
{
if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
- break;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
}
}
@@ -306,8 +311,12 @@
{
if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
- break;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
}
}
}
diff --git a/Src/stm32l5xx_hal_irda.c b/Src/stm32l5xx_hal_irda.c
index 6b3ac43..533c84f 100644
--- a/Src/stm32l5xx_hal_irda.c
+++ b/Src/stm32l5xx_hal_irda.c
@@ -613,43 +613,45 @@
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
- hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
- hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
- hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
- hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_IRDA_ERROR_CB_ID :
- hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
- hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
- hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
- hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
case HAL_IRDA_MSPINIT_CB_ID :
- hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
- hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -2242,7 +2244,7 @@
uint32_t tmpreg;
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the communication parameters */
diff --git a/Src/stm32l5xx_hal_iwdg.c b/Src/stm32l5xx_hal_iwdg.c
index 2897c5a..c6ec541 100644
--- a/Src/stm32l5xx_hal_iwdg.c
+++ b/Src/stm32l5xx_hal_iwdg.c
@@ -47,7 +47,7 @@
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
- This frequency being subject to variations as mentioned above, the
+ This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining
@@ -65,13 +65,13 @@
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
+ (++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@@ -125,7 +125,8 @@
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
*/
@@ -196,11 +197,14 @@
tickstart = HAL_GetTick();
/* Wait for register to be updated */
- while (hiwdg->Instance->SR != 0x00u)
+ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
- return HAL_TIMEOUT;
+ if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -223,6 +227,7 @@
return HAL_OK;
}
+
/**
* @}
*/
@@ -242,7 +247,6 @@
* @{
*/
-
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
@@ -258,6 +262,7 @@
return HAL_OK;
}
+
/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_lptim.c b/Src/stm32l5xx_hal_lptim.c
index 2bb1654..ed74a34 100644
--- a/Src/stm32l5xx_hal_lptim.c
+++ b/Src/stm32l5xx_hal_lptim.c
@@ -189,12 +189,12 @@
* @{
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \
- (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() :\
- ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT())
+ (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() :\
+ ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT())
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \
- (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() :\
- ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT())
+ (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() :\
+ ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT())
/**
* @}
*/
@@ -213,8 +213,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -251,19 +251,17 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
- }
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
- {
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@@ -322,21 +320,18 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
- }
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
- {
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
}
- /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
/* Set initialization parameters */
@@ -355,19 +350,21 @@
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- /* Configure the active edge or edges used by the counter only if LPTIM is
- * clocked by an external clock source
- */
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ /* Configure LPTIM external clock polarity and digital filter */
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ hlptim->Init.UltraLowPowerClock.SampleTime);
}
+ /* Configure LPTIM external trigger */
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge |
+ hlptim->Init.Trigger.SampleTime);
}
/* Write to LPTIMx CFGR */
@@ -481,8 +478,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
- * @brief Start-Stop operation functions.
- *
+ * @brief Start-Stop operation functions.
+ *
@verbatim
==============================================================================
##### LPTIM Start Stop operation functions #####
@@ -1631,7 +1628,8 @@
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1712,7 +1710,8 @@
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1815,8 +1814,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
- * @brief Read operation functions.
- *
+ * @brief Read operation functions.
+ *
@verbatim
==============================================================================
##### LPTIM Read operation functions #####
@@ -1873,8 +1872,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
- * @brief LPTIM IRQ handler.
- *
+ * @brief LPTIM IRQ handler.
+ *
@verbatim
==============================================================================
##### LPTIM IRQ handler and callbacks #####
@@ -2426,8 +2425,8 @@
*/
/** @defgroup LPTIM_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
@@ -2504,8 +2503,7 @@
{
result = HAL_TIMEOUT;
}
- }
- while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+ } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
}
diff --git a/Src/stm32l5xx_hal_mmc.c b/Src/stm32l5xx_hal_mmc.c
index 9128570..44d48a2 100644
--- a/Src/stm32l5xx_hal_mmc.c
+++ b/Src/stm32l5xx_hal_mmc.c
@@ -105,7 +105,7 @@
(+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
@@ -129,18 +129,18 @@
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
- You could also check the DMA transfer process through the MMC Tx interrupt event.
+ You could also check the DMA transfer process through the MMC Tx interrupt event.
(+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
This function allows the read of 512 bytes blocks.
- You can choose either one block read operation or multiple block read operation
+ You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Tx interrupt event.
*** MMC card information ***
- ===========================
+ ===========================
[..]
(+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
It returns useful information about the MMC card such as block size, card type,
@@ -281,6 +281,10 @@
#define MMC_EXT_CSD_PWR_CL_52_POS 16
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
#endif
+
+/* Frequencies used in the driver for clock divider calculation */
+#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
/**
* @}
*/
@@ -300,7 +304,8 @@
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
-static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex,
+ uint32_t Timeout);
static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed);
/**
@@ -312,8 +317,8 @@
*/
/** @addtogroup MMC_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
+ * @brief Initialization and de-initialization functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -335,7 +340,7 @@
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
- if(hmmc == NULL)
+ if (hmmc == NULL)
{
return HAL_ERROR;
}
@@ -348,7 +353,7 @@
assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
- if(hmmc->State == HAL_MMC_STATE_RESET)
+ if (hmmc->State == HAL_MMC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
@@ -363,7 +368,7 @@
hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback;
hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback;
- if(hmmc->MspInitCallback == NULL)
+ if (hmmc->MspInitCallback == NULL)
{
hmmc->MspInitCallback = HAL_MMC_MspInit;
}
@@ -379,7 +384,7 @@
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize the Card parameters */
- if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
+ if (HAL_MMC_InitCard(hmmc) == HAL_ERROR)
{
return HAL_ERROR;
}
@@ -428,11 +433,15 @@
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
if (sdmmc_clk == 0U)
{
- hmmc->State = HAL_MMC_STATE_READY;
- hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
- return HAL_ERROR;
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
}
- Init.ClockDiv = sdmmc_clk/(2U*400000U);
+ Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ);
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
+#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
(void)SDMMC_Init(hmmc->Instance, Init);
@@ -442,12 +451,12 @@
/* wait 74 Cycles: required power up waiting time before starting
the MMC initialization sequence */
- sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
- HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
@@ -456,7 +465,7 @@
/* Card initialization */
errorstate = MMC_InitCard(hmmc);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
@@ -465,7 +474,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -485,7 +494,7 @@
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
- if(hmmc == NULL)
+ if (hmmc == NULL)
{
return HAL_ERROR;
}
@@ -499,7 +508,7 @@
MMC_PowerOFF(hmmc);
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- if(hmmc->MspDeInitCallback == NULL)
+ if (hmmc->MspDeInitCallback == NULL)
{
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
}
@@ -553,8 +562,8 @@
*/
/** @addtogroup MMC_Exported_Functions_Group2
- * @brief Data transfer functions
- *
+ * @brief Data transfer functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -579,7 +588,8 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -588,22 +598,40 @@
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -622,10 +650,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
@@ -639,7 +667,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -650,12 +678,13 @@
/* Poll on SDMMC flags */
dataremaining = config.DataLength;
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
@@ -670,23 +699,23 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
+ hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Send stop transmission command in case of multiblock read */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -697,7 +726,7 @@
}
/* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -705,7 +734,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -713,7 +742,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -752,7 +781,8 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -761,22 +791,40 @@
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -795,10 +843,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
@@ -812,7 +860,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -823,12 +871,13 @@
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc,
+ SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
@@ -843,7 +892,7 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -852,14 +901,14 @@
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Send stop transmission command in case of multiblock write */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -870,7 +919,7 @@
}
/* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -878,7 +927,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -886,7 +935,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -926,28 +975,47 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -969,10 +1037,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
@@ -987,7 +1055,7 @@
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -996,7 +1064,8 @@
return HAL_ERROR;
}
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_RXFIFOHF));
return HAL_OK;
}
@@ -1019,28 +1088,47 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -1063,12 +1151,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
- hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
@@ -1080,7 +1168,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1090,7 +1178,8 @@
}
/* Enable transfer interrupts */
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_TXFIFOHE));
return HAL_OK;
}
@@ -1113,28 +1202,47 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -1157,12 +1265,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
@@ -1176,7 +1284,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1209,28 +1317,47 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+ uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
@@ -1253,13 +1380,13 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
@@ -1273,7 +1400,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1308,26 +1435,37 @@
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
- if(end_add < start_add)
+ if (end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(end_add > (hmmc->MmcCard.LogBlockNbr))
+ if (end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check if the card command class supports erase command */
- if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1336,7 +1474,7 @@
return HAL_ERROR;
}
- if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1353,7 +1491,7 @@
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1364,7 +1502,7 @@
/* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1375,7 +1513,7 @@
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -1405,33 +1543,33 @@
uint32_t context = hmmc->Context;
/* Check for SDMMC interrupt flags */
- if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+ if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Read_IT(hmmc);
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
- SDMMC_IT_RXFIFOHF);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \
+ SDMMC_IT_RXFIFOHF);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
- if((context & MMC_CONTEXT_DMA) != 0U)
+ if ((context & MMC_CONTEXT_DMA) != 0U)
{
hmmc->Instance->DLEN = 0;
hmmc->Instance->DCTRL = 0;
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
- if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
@@ -1446,7 +1584,7 @@
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
- if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
@@ -1454,7 +1592,7 @@
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
- if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
@@ -1463,13 +1601,13 @@
#endif
}
}
- else if((context & MMC_CONTEXT_IT) != 0U)
+ else if ((context & MMC_CONTEXT_IT) != 0U)
{
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
- if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
@@ -1484,7 +1622,7 @@
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
- if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
@@ -1507,27 +1645,28 @@
}
}
- else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
+ else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Write_IT(hmmc);
}
- else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL |
+ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
}
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
}
@@ -1536,17 +1675,17 @@
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* Disable all interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP;
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT);
- if((context & MMC_CONTEXT_IT) != 0U)
+ if ((context & MMC_CONTEXT_IT) != 0U)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
@@ -1556,9 +1695,9 @@
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
- else if((context & MMC_CONTEXT_DMA) != 0U)
+ else if ((context & MMC_CONTEXT_DMA) != 0U)
{
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
/* Disable Internal DMA */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
@@ -1579,13 +1718,13 @@
}
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
- if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
+ if (READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
{
/* Current buffer is buffer0, Transfer complete for buffer1 */
- if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->Write_DMADblBuf1CpltCallback(hmmc);
@@ -1605,7 +1744,7 @@
else /* MMC_DMA_BUFFER1 */
{
/* Current buffer is buffer1, Transfer complete for buffer0 */
- if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->Write_DMADblBuf0CpltCallback(hmmc);
@@ -1641,11 +1780,11 @@
}
/**
-* @brief Return the MMC error code
-* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
+ * @brief Return the MMC error code
+ * @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
-* @retval MMC Error Code
-*/
+ * @retval MMC Error Code
+ */
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
{
return hmmc->ErrorCode;
@@ -1731,11 +1870,12 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
+ pMMC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
@@ -1745,64 +1885,64 @@
/* Process locked */
__HAL_LOCK(hmmc);
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
- case HAL_MMC_TX_CPLT_CB_ID :
- hmmc->TxCpltCallback = pCallback;
- break;
- case HAL_MMC_RX_CPLT_CB_ID :
- hmmc->RxCpltCallback = pCallback;
- break;
- case HAL_MMC_ERROR_CB_ID :
- hmmc->ErrorCallback = pCallback;
- break;
- case HAL_MMC_ABORT_CB_ID :
- hmmc->AbortCpltCallback = pCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Read_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Read_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Write_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Write_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = pCallback;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = pCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = pCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = pCallback;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1843,64 +1983,64 @@
/* Process locked */
__HAL_LOCK(hmmc);
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
- case HAL_MMC_TX_CPLT_CB_ID :
- hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
- break;
- case HAL_MMC_RX_CPLT_CB_ID :
- hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
- break;
- case HAL_MMC_ERROR_CB_ID :
- hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
- break;
- case HAL_MMC_ABORT_CB_ID :
- hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback;
- break;
- case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback;
- break;
- case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback;
- break;
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = HAL_MMC_MspInit;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_MMC_MSP_INIT_CB_ID :
- hmmc->MspInitCallback = HAL_MMC_MspInit;
- break;
- case HAL_MMC_MSP_DEINIT_CB_ID :
- hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
- break;
- default :
- /* Update the error code */
- hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1922,8 +2062,8 @@
*/
/** @addtogroup MMC_Exported_Functions_Group3
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -2007,12 +2147,12 @@
pCSD->Reserved2 = 0U; /*!< Reserved */
- if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
+ if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
{
return HAL_ERROR;
}
- if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
+ if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
{
pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
@@ -2030,10 +2170,10 @@
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
- hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
hmmc->MmcCard.LogBlockSize = 512U;
}
- else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
+ else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
{
hmmc->MmcCard.BlockNbr = block_nbr;
hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
@@ -2061,7 +2201,7 @@
pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
- pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
+ pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
@@ -2079,7 +2219,7 @@
pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
- pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
+ pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
@@ -2112,7 +2252,7 @@
* @brief Returns information the information of the card which are stored on
* the Extended CSD register.
* @param hmmc Pointer to MMC handle
- * @param pExtCSD Pointer to a memory area (512 bytes) that contains all
+ * @param pExtCSD Pointer to a memory area (512 bytes) that contains all
* Extended CSD register parameters
* @param Timeout Specify timeout value
* @retval HAL status
@@ -2125,13 +2265,13 @@
uint32_t count;
uint32_t *tmp_buf;
- if(NULL == pExtCSD)
+ if (NULL == pExtCSD)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
@@ -2151,11 +2291,11 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Send ExtCSD Read command to Card */
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2165,32 +2305,33 @@
}
/* Poll on SDMMC flags */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR |
+ SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
*tmp_buf = SDMMC_ReadFIFO(hmmc->Instance);
tmp_buf++;
}
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
+ hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2198,7 +2339,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2206,7 +2347,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2268,17 +2409,17 @@
errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT);
}
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
- if(WideMode == SDMMC_BUS_WIDE_8B)
+ if (WideMode == SDMMC_BUS_WIDE_8B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
}
- else if(WideMode == SDMMC_BUS_WIDE_4B)
+ else if (WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
}
- else if(WideMode == SDMMC_BUS_WIDE_1B)
+ else if (WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
}
@@ -2289,14 +2430,14 @@
}
/* Check for switch error and violation of the trial number of sending CMD 13 */
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -2304,7 +2445,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -2336,7 +2477,7 @@
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2383,16 +2524,20 @@
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
- errorstate = MMC_DDR_Mode(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
{
- hmmc->ErrorCode |= errorstate;
+ /* DDR mode not supported with CLKDIV = 0 */
+ errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
}
}
}
@@ -2400,7 +2545,7 @@
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2417,16 +2562,20 @@
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
- errorstate = MMC_DDR_Mode(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
{
- hmmc->ErrorCode |= errorstate;
+ /* DDR mode not supported with CLKDIV = 0 */
+ errorstate = MMC_DDR_Mode(hmmc, ENABLE);
+ if (errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
}
}
}
@@ -2444,7 +2593,7 @@
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2463,7 +2612,7 @@
{
/* High Speed DDR mode activated */
errorstate = MMC_DDR_Mode(hmmc, DISABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2472,7 +2621,7 @@
{
/* High Speed mode activated */
errorstate = MMC_HighSpeed(hmmc, DISABLE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2514,7 +2663,7 @@
uint32_t resp1 = 0U;
errorstate = MMC_SendStatus(hmmc, &resp1);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -2535,8 +2684,8 @@
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
@@ -2550,11 +2699,11 @@
hmmc->Context = MMC_CONTEXT_NONE;
CardState = HAL_MMC_GetCardState(hmmc);
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2572,8 +2721,8 @@
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
- __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
@@ -2584,11 +2733,11 @@
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
- if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
- if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2611,17 +2760,20 @@
* @param hmmc Pointer to MMC handle
* @param EraseType Specifies the type of erase to be performed
* This parameter can be one of the following values:
- * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
- * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
- * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
- * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified by CMD35 & 36
- * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
- * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks previously identified
+ * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
+ * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
+ * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified
+ * by CMD35 & 36
+ * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
+ * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks
+ * previously identified
* @param BlockStartAdd Start Block address
* @param BlockEndAdd End Block address
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType,
+ uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
uint32_t errorstate;
uint32_t start_add = BlockStartAdd;
@@ -2632,34 +2784,45 @@
assert_param(IS_MMC_ERASE_TYPE(EraseType));
/* Check the coherence between start and end address */
- if(end_add < start_add)
+ if (end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
/* Check that the end address is not out of range of device memory */
- if(end_add > (hmmc->MmcCard.LogBlockNbr))
+ if (end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
/* Check if the card command class supports erase command */
- if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
return HAL_ERROR;
}
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check that the card is not locked */
- if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
hmmc->State = HAL_MMC_STATE_READY;
@@ -2675,22 +2838,22 @@
/* Send CMD35 MMC_ERASE_GRP_START with start address as argument */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Send CMD36 MMC_ERASE_GRP_END with end address as argument */
errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Send CMD38 ERASE with erase type as argument */
errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2))
{
/* Wait that the device is ready by checking the D0 line */
- while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
- if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
{
errorstate = HAL_MMC_ERROR_TIMEOUT;
}
@@ -2707,13 +2870,13 @@
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
- if(errorstate != HAL_MMC_ERROR_TIMEOUT)
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
@@ -2746,19 +2909,19 @@
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Index : 165 - Value : 0x01 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Wait that the device is ready by checking the D0 line */
- while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+ while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
- if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
{
errorstate = HAL_MMC_ERROR_TIMEOUT;
}
@@ -2767,14 +2930,14 @@
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -2782,7 +2945,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -2808,13 +2971,13 @@
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
- if(errorstate != HAL_MMC_ERROR_TIMEOUT)
+ if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
@@ -2842,8 +3005,10 @@
* @param SRTMode Specifies the type of erase to be performed
* This parameter can be one of the following values:
* @arg HAL_MMC_SRT_ERASE Information removed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character
+ * followed by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+ * its complement then a random character
* @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
* @retval HAL status
*/
@@ -2855,28 +3020,28 @@
assert_param(IS_MMC_SRT_TYPE(SRTMode));
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Get the supported values by the device */
- if(HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
+ if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check the value passed as parameter is supported by the device */
- if((SRTMode & srt) != 0U)
+ if ((SRTMode & srt) != 0U)
{
/* Index : 16 - Value : SRTMode */
srt |= ((POSITION_VAL(SRTMode)) << 4U);
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U)));
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -2884,7 +3049,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -2919,7 +3084,7 @@
}
/* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -2943,15 +3108,17 @@
* @param SupportedSRT pointer for supported SRT value
* This parameter is a bit field of the following values:
* @arg HAL_MMC_SRT_ERASE Information removed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase
- * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character
+ * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed
+ * by an erase
+ * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
+ * its complement then a random character
* @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT)
{
/* Check the state of the driver */
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
@@ -2997,7 +3164,7 @@
MMC_InitTypeDef Init;
/* Check the power State */
- if(SDMMC_GetPowerState(hmmc->Instance) == 0U)
+ if (SDMMC_GetPowerState(hmmc->Instance) == 0U)
{
/* Power off */
return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
@@ -3005,7 +3172,7 @@
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -3021,7 +3188,7 @@
/* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */
/* MMC Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -3031,7 +3198,7 @@
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -3047,9 +3214,9 @@
/* Get the Card Class */
hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
- /* Select the Card */
+ /* Select the Card */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -3062,12 +3229,12 @@
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
-
+
/* Get Extended CSD parameters */
if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
{
@@ -3076,7 +3243,7 @@
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -3105,21 +3272,21 @@
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
- while(validvoltage == 0U)
+ while (validvoltage == 0U)
{
- if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ if (count++ == SDMMC_MAX_VOLT_TRIAL)
{
return HAL_MMC_ERROR_INVALID_VOLTRANGE;
}
/* SEND CMD1 APP_CMD with voltage range as argument */
errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3166,14 +3333,14 @@
{
uint32_t errorstate;
- if(pCardStatus == NULL)
+ if (pCardStatus == NULL)
{
return HAL_MMC_ERROR_PARAM;
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
@@ -3192,7 +3359,8 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
+ uint16_t FieldIndex, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -3217,7 +3385,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -3227,17 +3395,17 @@
}
/* Poll on SDMMC flags */
- while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
- /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
- /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
- if ((i + count) == ((uint32_t)FieldIndex/4U))
+ /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
+ /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
+ if ((i + count) == ((uint32_t)FieldIndex / 4U))
{
*pFieldData = tmp_data;
}
@@ -3245,18 +3413,18 @@
i += 8U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
- hmmc->State= HAL_MMC_STATE_READY;
+ hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Get error state */
- if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -3264,7 +3432,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -3272,7 +3440,7 @@
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
- else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
@@ -3287,7 +3455,7 @@
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
@@ -3309,14 +3477,14 @@
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count, data;
- uint8_t* tmp;
+ uint8_t *tmp;
tmp = hmmc->pRxBuffPtr;
if (hmmc->RxXferSize >= 32U)
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tmp = (uint8_t)(data & 0xFFU);
@@ -3343,14 +3511,14 @@
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count, data;
- uint8_t* tmp;
+ uint8_t *tmp;
tmp = hmmc->pTxBuffPtr;
if (hmmc->TxXferSize >= 32U)
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tmp);
tmp++;
@@ -3378,36 +3546,37 @@
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t response = 0U, count;
+ uint32_t sdmmc_clk;
SDMMC_InitTypeDef Init;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
{
errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 185 - Value : 0 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
}
}
-
+
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
{
errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 185 - Value : 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
}
}
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -3415,7 +3584,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -3437,15 +3606,24 @@
{
Init.ClockDiv = hmmc->Init.ClockDiv;
(void)SDMMC_Init(hmmc->Instance, Init);
-
+
CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
}
else
{
- Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
- (void)SDMMC_Init(hmmc->Instance, Init);
-
- SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+ /* High Speed Clock should be less or equal to 52MHz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+ if (sdmmc_clk == 0U)
+ {
+ errorstate = SDMMC_ERROR_INVALID_PARAMETER;
+ }
+ else
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ);
+ (void)SDMMC_Init(hmmc->Instance, Init);
+
+ SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
+ }
}
}
}
@@ -3478,7 +3656,7 @@
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
@@ -3487,7 +3665,7 @@
else
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 2 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
@@ -3500,7 +3678,7 @@
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 5 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
@@ -3509,7 +3687,7 @@
else
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR);
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 6 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
@@ -3517,14 +3695,14 @@
}
}
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -3532,7 +3710,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
@@ -3582,12 +3760,12 @@
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t power_class, supported_pwr_class;
- if((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
+ if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
{
power_class = 0U; /* Default value after power-on or software reset */
/* Read the PowerClass field of the Extended CSD register */
- if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
+ if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
@@ -3600,24 +3778,27 @@
if (Speed == SDMMC_SPEED_MODE_DDR)
{
/* Field PWR_CL_DDR_52_xxx [238 or 239] */
- supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) & 0x000000FFU);
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) &
+ 0x000000FFU);
}
else if (Speed == SDMMC_SPEED_MODE_HIGH)
{
/* Field PWR_CL_52_xxx [200 or 202] */
- supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_52_POS) & 0x000000FFU);
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) &
+ 0x000000FFU);
}
else
{
/* Field PWR_CL_26_xxx [201 or 203] */
- supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU);
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) &
+ 0x000000FFU);
}
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
- if(Wide == SDMMC_BUS_WIDE_8B)
+ if (Wide == SDMMC_BUS_WIDE_8B)
{
- /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */
+ /* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */
supported_pwr_class = (supported_pwr_class >> 4U);
}
@@ -3626,14 +3807,14 @@
/* Need to change current power class */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U)));
- if(errorstate == HAL_MMC_ERROR_NONE)
+ if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
@@ -3641,7 +3822,7 @@
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
+ } while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
diff --git a/Src/stm32l5xx_hal_mmc_ex.c b/Src/stm32l5xx_hal_mmc_ex.c
index b8fd8f2..0f40291 100644
--- a/Src/stm32l5xx_hal_mmc_ex.c
+++ b/Src/stm32l5xx_hal_mmc_ex.c
@@ -15,7 +15,8 @@
The MMC Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
- (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
+ (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and
+ HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
@@ -60,8 +61,8 @@
/** @addtogroup MMCEx_Exported_Functions_Group1
- * @brief Multibuffer functions
- *
+ * @brief Multibuffer functions
+ *
@verbatim
==============================================================================
##### Multibuffer functions #####
@@ -82,13 +83,14 @@
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0,
+ uint32_t *pDataBuffer1, uint32_t BufferSize)
{
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
- hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
- hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
- hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize);
+ hmmc->Instance->IDMABASE0 = (uint32_t) pDataBuffer0 ;
+ hmmc->Instance->IDMABASE1 = (uint32_t) pDataBuffer1 ;
+ hmmc->Instance->IDMABSIZE = (uint32_t)(MMC_BLOCKSIZE * BufferSize);
return HAL_OK;
}
@@ -100,27 +102,48 @@
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
@@ -152,7 +175,7 @@
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -161,14 +184,15 @@
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
@@ -181,27 +205,48 @@
/**
* @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+ */
+HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t add = BlockAdd;
- if(hmmc->State == HAL_MMC_STATE_READY)
+ if (hmmc->State == HAL_MMC_STATE_READY)
{
- if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
+ /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
+ if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+ {
+ if ((NumberOfBlocks % 8U) != 0U)
+ {
+ /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
+ return HAL_ERROR;
+ }
+
+ if ((BlockAdd % 8U) != 0U)
+ {
+ /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
+ return HAL_ERROR;
+ }
+ }
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
@@ -232,7 +277,7 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -241,14 +286,15 @@
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
- if(errorstate != HAL_MMC_ERROR_NONE)
+ if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
+ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
@@ -270,9 +316,10 @@
* transfer use BUFFER0.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
+HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer)
{
- if(Buffer == MMC_DMA_BUFFER0)
+ if (Buffer == MMC_DMA_BUFFER0)
{
/* change the buffer0 address */
hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
diff --git a/Src/stm32l5xx_hal_nand.c b/Src/stm32l5xx_hal_nand.c
index 19a5fb8..a169a19 100644
--- a/Src/stm32l5xx_hal_nand.c
+++ b/Src/stm32l5xx_hal_nand.c
@@ -181,7 +181,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
}
/* Initialize NAND control Interface */
@@ -221,7 +221,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspDeInit(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Configure the NAND registers with their reset values */
(void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
@@ -284,7 +284,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Rising edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
@@ -298,7 +298,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Level pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
@@ -312,7 +312,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Falling edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
@@ -326,7 +326,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt FIFO empty pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
@@ -380,7 +380,7 @@
{
__IO uint32_t data = 0;
__IO uint32_t data1 = 0;
- uint32_t deviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -396,18 +396,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
__DSB();
/* Read the electronic signature from NAND flash */
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
- data = *(__IO uint32_t *)deviceAddress;
+ data = *(__IO uint32_t *)deviceaddress;
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
@@ -417,8 +417,8 @@
}
else
{
- data = *(__IO uint32_t *)deviceAddress;
- data1 = *((__IO uint32_t *)deviceAddress + 4);
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4);
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
@@ -449,7 +449,7 @@
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
- uint32_t deviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -465,10 +465,10 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -519,7 +519,10 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -536,16 +539,16 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -553,22 +556,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -576,31 +579,31 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
@@ -625,25 +628,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *buff = *(uint8_t *)deviceAddress;
+ *buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -674,7 +677,10 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -691,16 +697,16 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -708,22 +714,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -731,31 +737,31 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -779,25 +785,36 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
+ /* Calculate PageSize */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+ {
+ hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+ }
+ else
+ {
+ /* Do nothing */
+ /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+ }
+
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *buff = *(uint16_t *)deviceAddress;
+ *buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -828,7 +845,10 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -845,18 +865,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -864,22 +884,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -887,26 +907,26 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -914,12 +934,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *(__IO uint8_t *)deviceAddress = *buff;
+ *(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -941,13 +961,13 @@
}
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -978,7 +998,10 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -995,18 +1018,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -1014,22 +1037,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1037,39 +1060,50 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
+ /* Calculate PageSize */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
+ {
+ hnand->Config.PageSize = hnand->Config.PageSize / 2U;
+ }
+ else
+ {
+ /* Do nothing */
+ /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
+ }
+
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *(__IO uint16_t *)deviceAddress = *buff;
+ *(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1091,13 +1125,13 @@
}
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1128,7 +1162,11 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -1145,78 +1183,78 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) read loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -1240,25 +1278,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *buff = *(uint8_t *)deviceAddress;
+ *buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1289,7 +1327,11 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -1306,78 +1348,78 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) read loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -1401,25 +1443,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *buff = *(uint16_t *)deviceAddress;
+ *buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1450,7 +1492,11 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -1467,77 +1513,77 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Page address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) write loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1545,12 +1591,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *(__IO uint8_t *)deviceAddress = *buff;
+ *(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1572,13 +1618,13 @@
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1609,7 +1655,11 @@
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
@@ -1626,77 +1676,77 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) write loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1704,12 +1754,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *(__IO uint16_t *)deviceAddress = *buff;
+ *(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1731,13 +1781,13 @@
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1763,7 +1813,7 @@
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
- uint32_t DeviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1779,19 +1829,19 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- DeviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
__DSB();
/* Update the NAND controller state */
@@ -1980,7 +2030,7 @@
__HAL_UNLOCK(hnand);
return status;
}
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -2142,17 +2192,17 @@
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
uint32_t data;
- uint32_t DeviceAddress;
+ uint32_t deviceaddress;
UNUSED(hnand);
/* Identify the device address */
- DeviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
- data = *(__IO uint8_t *)DeviceAddress;
+ data = *(__IO uint8_t *)deviceaddress;
/* Return the status */
if ((data & NAND_ERROR) == NAND_ERROR)
diff --git a/Src/stm32l5xx_hal_nor.c b/Src/stm32l5xx_hal_nor.c
index 9bcbfd5..3e05cb8 100644
--- a/Src/stm32l5xx_hal_nor.c
+++ b/Src/stm32l5xx_hal_nor.c
@@ -472,9 +472,12 @@
{
/* Read the NOR IDs */
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE3_ADDR);
}
/* Check the NOR controller state */
@@ -739,7 +742,9 @@
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize)
{
- uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
+ uint32_t deviceaddress;
+ uint32_t size = uwBufferSize;
+ uint32_t address = uwAddress;
uint16_t *data = pData;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
@@ -870,7 +875,7 @@
/* Initialize variables */
p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
- p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U*(uwBufferSize - 1U)));
+ p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
@@ -900,7 +905,7 @@
while (p_currentaddress <= p_endaddress)
{
NOR_WRITE(p_currentaddress, *data);
-
+
data++;
p_currentaddress ++;
}
@@ -1389,7 +1394,8 @@
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
- uint16_t tmpSR1, tmpSR2;
+ uint16_t tmpsr1;
+ uint16_t tmpsr2;
uint32_t tickstart;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
@@ -1414,29 +1420,29 @@
}
/* Read NOR status register (DQ6 and DQ5) */
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS ;
}
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
status = HAL_NOR_STATUS_ONGOING;
}
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS;
}
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
return HAL_NOR_STATUS_ERROR;
}
@@ -1447,21 +1453,21 @@
do
{
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
- tmpSR2 = *(__IO uint16_t*)(Address);
+ tmpsr2 = *(__IO uint16_t *)(Address);
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_NOR_STATUS_TIMEOUT;
}
}
- } while ((tmpSR2 & NOR_MASK_STATUS_DQ7) == 0U);
+ } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
- tmpSR1 = *(__IO uint16_t*)(Address);
- if((tmpSR1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
+ tmpsr1 = *(__IO uint16_t *)(Address);
+ if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
{
/* Clear the Status Register */
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
diff --git a/Src/stm32l5xx_hal_opamp.c b/Src/stm32l5xx_hal_opamp.c
index 7733ee0..a8b8c68 100644
--- a/Src/stm32l5xx_hal_opamp.c
+++ b/Src/stm32l5xx_hal_opamp.c
@@ -1154,11 +1154,6 @@
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_opamp_ex.c b/Src/stm32l5xx_hal_opamp_ex.c
index e595694..02f716c 100644
--- a/Src/stm32l5xx_hal_opamp_ex.c
+++ b/Src/stm32l5xx_hal_opamp_ex.c
@@ -45,11 +45,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+/** @defgroup OPAMPEx_Exported_Functions OPAMPEx Extended Exported Functions
* @{
*/
-/** @addtogroup OPAMPEx_Exported_Functions_Group1
+/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended operation functions
* @brief Extended operation functions
*
@verbatim
@@ -365,7 +365,7 @@
* @}
*/
-/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
+/** @defgroup OPAMPEx_Exported_Functions_Group2 Extended Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
diff --git a/Src/stm32l5xx_hal_pcd.c b/Src/stm32l5xx_hal_pcd.c
index 6434928..cb35389 100644
--- a/Src/stm32l5xx_hal_pcd.c
+++ b/Src/stm32l5xx_hal_pcd.c
@@ -206,7 +206,7 @@
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
-
+
return HAL_OK;
}
@@ -298,7 +298,9 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -508,7 +510,8 @@
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -581,7 +584,8 @@
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -654,7 +658,8 @@
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -727,7 +732,8 @@
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1357,7 +1363,8 @@
* @param ep_type endpoint type
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
@@ -1534,10 +1541,7 @@
__HAL_LOCK(hpcd);
(void)USB_EPSetStall(hpcd->Instance, ep);
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
- }
+
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -1672,6 +1676,7 @@
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
{
wIstr = hpcd->Instance->ISTR;
+
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
@@ -1754,8 +1759,11 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
+ {
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
}
}
}
@@ -1842,9 +1850,8 @@
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- /* Manage all non bulk transaction or Bulk Single Buffer Transaction */
- if ((ep->type != EP_TYPE_BULK) ||
- ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
+ /* Manage Bulk Single Buffer Transaction */
+ if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))
{
/* multi-packet on the NON control IN endpoint */
TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
@@ -1876,7 +1883,7 @@
(void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
- /* bulk in double buffer enable in case of transferLen> Ep_Mps */
+ /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
@@ -1922,7 +1929,7 @@
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
- /* Check if Buffer1 is in blocked sate which requires to toggle */
+ /* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
@@ -2000,6 +2007,9 @@
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2070,6 +2080,9 @@
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2077,7 +2090,7 @@
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- /*need to Free USB Buff*/
+ /* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
diff --git a/Src/stm32l5xx_hal_pcd_ex.c b/Src/stm32l5xx_hal_pcd_ex.c
index 3f7e500..0035920 100644
--- a/Src/stm32l5xx_hal_pcd_ex.c
+++ b/Src/stm32l5xx_hal_pcd_ex.c
@@ -78,10 +78,8 @@
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress)
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+ uint16_t ep_kind, uint32_t pmaadress)
{
PCD_EPTypeDef *ep;
diff --git a/Src/stm32l5xx_hal_rcc.c b/Src/stm32l5xx_hal_rcc.c
index 696606a..bab519c 100644
--- a/Src/stm32l5xx_hal_rcc.c
+++ b/Src/stm32l5xx_hal_rcc.c
@@ -65,8 +65,8 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
+ * @{
+ */
#define LSI_TIMEOUT_VALUE 7UL /* 7 ms (maximum 6ms + 1) */
#define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
@@ -255,7 +255,11 @@
{
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -283,12 +287,17 @@
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_SYSCLKSOURCE_STATUS_MSI)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
/* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */
- CLEAR_BIT(RCC->CR, RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_PLLON |
+ RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);
/* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */
/* Get start tick */
@@ -297,19 +306,33 @@
#if defined(RCC_PLLSAI2_SUPPORT)
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
#else
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)
-
-#endif
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
+#endif /* RCC_PLLSAI2_SUPPORT */
+
/* Reset PLLCFGR register */
CLEAR_REG(RCC->PLLCFGR);
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4);
@@ -334,7 +357,11 @@
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -500,7 +527,11 @@
{
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
@@ -522,7 +553,11 @@
{
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -559,7 +594,11 @@
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -573,7 +612,11 @@
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -618,7 +661,11 @@
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -638,7 +685,11 @@
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -674,7 +725,11 @@
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -691,7 +746,11 @@
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -724,7 +783,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -761,7 +824,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -775,7 +842,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -789,7 +860,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -804,7 +879,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -818,7 +897,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -850,7 +933,11 @@
{
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -867,7 +954,11 @@
{
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -902,7 +993,11 @@
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -928,7 +1023,11 @@
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -953,7 +1052,11 @@
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -1162,7 +1265,11 @@
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ {
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -1222,8 +1329,8 @@
*/
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
- *
+ * @brief RCC clocks control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -1647,8 +1754,8 @@
*/
/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions
- * @brief Attributes management functions.
- *
+ * @brief Attributes management functions.
+ *
@verbatim
===============================================================================
##### RCC attributes functions #####
diff --git a/Src/stm32l5xx_hal_rcc_ex.c b/Src/stm32l5xx_hal_rcc_ex.c
index 32c7083..584ee45 100644
--- a/Src/stm32l5xx_hal_rcc_ex.c
+++ b/Src/stm32l5xx_hal_rcc_ex.c
@@ -40,8 +40,8 @@
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
- * @{
- */
+ * @{
+ */
#define PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
@@ -71,8 +71,8 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
- * @{
- */
+ * @{
+ */
static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *pPllSai1, uint32_t Divider);
static uint32_t RCCEx_PLLSAI1_GetVCOFreq(void);
@@ -91,8 +91,8 @@
*/
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
+ * @brief Extended Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
@@ -276,7 +276,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
- ret = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ {
+ ret = HAL_TIMEOUT;
+ }
break;
}
}
@@ -308,7 +312,11 @@
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
- ret = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
+ {
+ ret = HAL_TIMEOUT;
+ }
break;
}
}
@@ -661,7 +669,7 @@
/* Configure the OctoSPI clock source */
__HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
-
+
if (PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL)
{
/* Enable PLL48M1CLK output clock */
@@ -1597,8 +1605,8 @@
*/
/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
- * @brief Extended Clock management functions
- *
+ * @brief Extended Clock management functions
+ *
@verbatim
===============================================================================
##### Extended clock management functions #####
@@ -1642,7 +1650,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -1672,7 +1684,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -1702,7 +1718,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -1743,7 +1763,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -1773,7 +1797,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -1803,7 +1831,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -2013,8 +2045,8 @@
#if defined(CRS)
/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
- * @brief Extended Clock Recovery System Control functions
- *
+ * @brief Extended Clock Recovery System Control functions
+ *
@verbatim
===============================================================================
##### Extended Clock Recovery System Control functions #####
@@ -2031,7 +2063,7 @@
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
- directly reload value with target and sychronization frequencies values
+ directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which
(+++) Resets CRS registers to their default values.
(+++) Configures CRS registers with synchronization configuration
@@ -2073,8 +2105,8 @@
This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
@endverbatim
- * @{
- */
+ * @{
+ */
/**
* @brief Start automatic synchronization for polling mode.
@@ -2152,24 +2184,25 @@
}
/**
-* @brief Wait for CRS Synchronization status.
-* @param Timeout Duration of the timeout
-* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
-* frequency.
-* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
-* @retval Combination of Synchronization status
-* This parameter can be a combination of the following values:
-* @arg @ref RCC_CRS_TIMEOUT
-* @arg @ref RCC_CRS_SYNCOK
-* @arg @ref RCC_CRS_SYNCWARN
-* @arg @ref RCC_CRS_SYNCERR
-* @arg @ref RCC_CRS_SYNCMISS
-* @arg @ref RCC_CRS_TRIMOVF
-*/
+ * @brief Wait for CRS Synchronization status.
+ * @param Timeout Duration of the timeout
+ * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
+ * frequency.
+ * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+ * @retval Combination of Synchronization status
+ * This parameter can be a combination of the following values:
+ * @arg @ref RCC_CRS_TIMEOUT
+ * @arg @ref RCC_CRS_SYNCOK
+ * @arg @ref RCC_CRS_SYNCWARN
+ * @arg @ref RCC_CRS_SYNCERR
+ * @arg @ref RCC_CRS_SYNCMISS
+ * @arg @ref RCC_CRS_TRIMOVF
+ */
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
{
uint32_t crsstatus = RCC_CRS_NONE;
uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
/* Get timeout */
tickstart = HAL_GetTick();
@@ -2181,7 +2214,7 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- crsstatus = RCC_CRS_TIMEOUT;
+ status = HAL_TIMEOUT;
}
}
/* Check CRS SYNCOK flag */
@@ -2240,9 +2273,13 @@
/* frequency error counter reached a zero value */
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
}
- }
- while (RCC_CRS_NONE == crsstatus);
+ } while ((crsstatus == RCC_CRS_NONE) && (status == HAL_OK));
+ if (crsstatus == RCC_CRS_NONE)
+ {
+ crsstatus = RCC_CRS_TIMEOUT;
+ }
+
return crsstatus;
}
@@ -2374,8 +2411,8 @@
*/
/** @addtogroup RCCEx_Private_Functions
- * @{
- */
+ * @{
+ */
static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
{
@@ -2399,7 +2436,11 @@
{
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -2421,7 +2462,11 @@
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -2443,7 +2488,11 @@
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -2523,7 +2572,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -2578,7 +2631,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -2655,7 +2712,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
@@ -2687,7 +2748,11 @@
{
if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
{
- status = HAL_TIMEOUT;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
+ {
+ status = HAL_TIMEOUT;
+ }
break;
}
}
diff --git a/Src/stm32l5xx_hal_rng.c b/Src/stm32l5xx_hal_rng.c
index c009a58..b3cc17f 100644
--- a/Src/stm32l5xx_hal_rng.c
+++ b/Src/stm32l5xx_hal_rng.c
@@ -115,11 +115,7 @@
*/
/* Health test control register information to use in CCM algorithm */
#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
-#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
-#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */
-#else /* RNG_VER_3_2 */
-#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */
-#endif /* RNG_VER_3_0 || RNG_VER_3_1 */
+#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliancy */
/**
* @}
*/
@@ -134,14 +130,6 @@
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
-/** @addtogroup RNG_Private_Functions
- * @{
- */
-HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
-
-/**
- * @}
- */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_Exported_Functions
@@ -239,9 +227,13 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
@@ -261,9 +253,13 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_ERROR;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+ {
+ hrng->State = HAL_RNG_STATE_ERROR;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
@@ -307,11 +303,15 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+ return HAL_ERROR;
+ }
}
}
@@ -677,11 +677,15 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+ return HAL_ERROR;
+ }
}
}
diff --git a/Src/stm32l5xx_hal_rng_ex.c b/Src/stm32l5xx_hal_rng_ex.c
index 718721b..b6ea20a 100644
--- a/Src/stm32l5xx_hal_rng_ex.c
+++ b/Src/stm32l5xx_hal_rng_ex.c
@@ -44,12 +44,8 @@
* @{
*/
/* Health test control register information to use in CCM algorithm */
-#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */
-#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
-#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */
-#else /* RNG_VER_3_2 */
-#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */
-#endif /* RNG_VER_3_1 || RNG_VER_3_0 */
+#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
+#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliancy */
/**
* @}
*/
@@ -64,14 +60,6 @@
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
-/** @addtogroup RNG_Private_Functions
- * @{
- */
-HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
-
-/**
- * @}
- */
/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -164,9 +152,13 @@
{
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ /* New check to avoid false timeout detection in case of prememption */
+ if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
}
diff --git a/Src/stm32l5xx_hal_rtc.c b/Src/stm32l5xx_hal_rtc.c
index 3784bc4..bf83d47 100644
--- a/Src/stm32l5xx_hal_rtc.c
+++ b/Src/stm32l5xx_hal_rtc.c
@@ -872,10 +872,10 @@
/* Set the RTC_TR register */
WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK));
- /* Clear the bits to be configured */
+ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
CLEAR_BIT(RTC->CR, RTC_CR_BKP);
- /* Configure the RTC_CR register */
+ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation));
/* Exit Initialization mode */
@@ -1075,6 +1075,73 @@
}
/**
+ * @brief Daylight Saving Time, Add one hour to the calendar in one single operation
+ * without going through the initialization procedure.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_ADD1H);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Substract one hour from the calendar in one
+ * single operation without going through the initialization procedure.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_SUB1H);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Set the store operation bit.
+ * @note It can be used by the software in order to memorize the DST status.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_BKP);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Clear the store operation bit.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ CLEAR_BIT(RTC->CR, RTC_CR_BKP);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Read the store operation bit.
+ * @param hrtc RTC handle
+ * @retval operation see RTC_StoreOperation_Definitions
+ */
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ return READ_BIT(RTC->CR, RTC_CR_BKP);
+}
+
+
+/**
* @}
*/
@@ -1186,7 +1253,7 @@
}
/* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+ subsecondtmpreg = (uint32_t)(((uint32_t)(sAlarm->AlarmTime.SubSeconds) & RTC_ALRMBSSR_SS_Msk) | (uint32_t)(sAlarm->AlarmSubSecondMask));
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
@@ -1330,7 +1397,7 @@
((uint32_t)sAlarm->AlarmMask));
}
/* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+ subsecondtmpreg = (uint32_t)(((uint32_t)(sAlarm->AlarmTime.SubSeconds) & RTC_ALRMBSSR_SS_Msk) | (uint32_t)(sAlarm->AlarmSubSecondMask));
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
@@ -1657,7 +1724,7 @@
UNUSED(hrtc);
/* Clear RSF flag */
- SET_BIT(RTC->ICSR, RTC_RSF_MASK);
+ CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF);
tickstart = HAL_GetTick();
diff --git a/Src/stm32l5xx_hal_rtc_ex.c b/Src/stm32l5xx_hal_rtc_ex.c
index b39715a..cc3a806 100644
--- a/Src/stm32l5xx_hal_rtc_ex.c
+++ b/Src/stm32l5xx_hal_rtc_ex.c
@@ -233,15 +233,12 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- /* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
-
- /* Get the RTC_CR register and clear the bits to be configured */
- CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
-
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ /* Get the RTC_CR register and clear the bits to be configured */
+ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
+
/* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */
SET_BIT(RTC->CR, (uint32_t)TimeStampEdge);
@@ -251,6 +248,9 @@
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
+
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -1525,32 +1525,29 @@
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ /* Mask flag only supported by TAMPER 1, 2 and 3 */
+ assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_3)));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ /* Trigger and Filter have exclusive configurations */
+ assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL)))
+ || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))));
/* Configuration register 2 */
tmpreg = READ_REG(TAMP->CR2);
tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos));
- if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE))
{
tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos);
}
if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
{
- /* Feature only supported by TAMPER 1, 2 and 3 */
- if (sTamper->Tamper < RTC_TAMPER_4)
- {
- tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos);
- }
- else
- {
- return HAL_ERROR;
- }
+ tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos);
}
if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
@@ -1633,7 +1630,7 @@
assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase));
assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag));
/* Mask flag only supported by TAMPER 1, 2 and 3 */
- assert_param(!((sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (i > RTC_TAMPER_3)));
+ assert_param(!((sAllTamper->TampInput[i].MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE) && (i >= RTC_TAMPER_MASKABLE_NB)));
}
assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection));
#endif /* #ifdef USE_FULL_ASSERT */
@@ -1775,12 +1772,13 @@
UNUSED(hrtc);
/* Disable all actives tampers but not passives tampers */
CLEAR_BIT(TAMP->CR1, ATamp_mask);
- /* Disable no erase and mask */
- CLEAR_BIT(TAMP->CR2, (ATamp_mask | ((ATamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << TAMP_CR2_TAMP1MSK_Pos)));
/* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */
WRITE_REG(TAMP->SCR, ATamp_mask);
+ /* Disable no erase and mask */
+ CLEAR_BIT(TAMP->CR2, (ATamp_mask | ((ATamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << TAMP_CR2_TAMP1MSK_Pos)));
+
/* Clear all active tampers interrupt mode configuration but not passives tampers */
CLEAR_BIT(TAMP->IER, ATamp_mask);
@@ -2516,6 +2514,82 @@
the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file
*/
}
+
+/**
+ * @brief Enable Temperature Monitoring.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ SET_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN);
+}
+
+/**
+ * @brief Disable Temperature Monitoring.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN);
+}
+
+/**
+ * @brief Enable Voltage Monitoring.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ SET_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN);
+}
+
+/**
+ * @brief Disable Voltage Monitoring.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN);
+}
+
+/**
+ * @brief Enable WUT Monitoring.
+ * @note Voltage and temperature monitor periodic enable by RTC WakeUp Timer (WUT).
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ SET_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN);
+}
+
+/**
+ * @brief Disable WUT Monitoring.
+ * @note Voltage and temperature monitor periodic Disable by RTC WakeUp Timer (WUT).
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+ CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN);
+}
+
+
/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_sd.c b/Src/stm32l5xx_hal_sd.c
index 2789511..06d2f59 100644
--- a/Src/stm32l5xx_hal_sd.c
+++ b/Src/stm32l5xx_hal_sd.c
@@ -268,38 +268,42 @@
/** @addtogroup SD_Private_Defines
* @{
*/
+/* Frequencies used in the driver for clock divider calculation */
+#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */
+#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */
+#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */
+/* Private macro -------------------------------------------------------------*/
+#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \
+ DLYB_SDMMC1 : DLYB_SDMMC2 )
+#elif defined (DLYB_SDMMC1)
+#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
+#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
-#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
-#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \
- DLYB_SDMMC1 : DLYB_SDMMC2 )
-#elif defined (DLYB_SDMMC1)
-#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
-#endif
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SD_Private_Functions SD Private Functions
* @{
*/
-static uint32_t SD_InitCard (SD_HandleTypeDef *hsd);
-static uint32_t SD_PowerON (SD_HandleTypeDef *hsd);
-static uint32_t SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd);
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static void SD_PowerOFF (SD_HandleTypeDef *hsd);
-static void SD_Write_IT (SD_HandleTypeDef *hsd);
-static void SD_Read_IT (SD_HandleTypeDef *hsd);
-static uint32_t SD_HighSpeed (SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
+static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
-static uint32_t SD_UltraHighSpeed (SD_HandleTypeDef *hsd);
-static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd);
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd);
+static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
#endif /* USE_SD_TRANSCEIVER */
/**
* @}
@@ -311,8 +315,8 @@
*/
/** @addtogroup SD_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
- *
+ * @brief Initialization and de-initialization functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -334,11 +338,12 @@
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStatusTypeDef CardStatus;
- uint32_t speedgrade, unitsize;
+ uint32_t speedgrade;
+ uint32_t unitsize;
uint32_t tickstart;
/* Check the SD handle allocation */
- if(hsd == NULL)
+ if (hsd == NULL)
{
return HAL_ERROR;
}
@@ -351,7 +356,7 @@
assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));
- if(hsd->State == HAL_SD_STATE_RESET)
+ if (hsd->State == HAL_SD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
@@ -362,7 +367,7 @@
{
hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT;
}
-#endif
+#endif /*USE_SD_TRANSCEIVER */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_SD_STATE_RESET only */
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
@@ -380,7 +385,7 @@
}
#endif /* USE_SD_TRANSCEIVER */
- if(hsd->MspInitCallback == NULL)
+ if (hsd->MspInitCallback == NULL)
{
hsd->MspInitCallback = HAL_SD_MspInit;
}
@@ -401,7 +406,7 @@
return HAL_ERROR;
}
- if( HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
+ if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK)
{
return HAL_ERROR;
}
@@ -425,19 +430,19 @@
}
/* Configure the bus wide */
- if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
+ if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK)
{
return HAL_ERROR;
}
/* Verify that SD card is ready to use after Initialization */
tickstart = HAL_GetTick();
- while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
+ while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER))
{
- if((HAL_GetTick()-tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -477,21 +482,23 @@
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
if (sdmmc_clk == 0U)
{
- hsd->State = HAL_SD_STATE_READY;
- hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
- return HAL_ERROR;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
}
- Init.ClockDiv = sdmmc_clk/(2U*400000U);
+ Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ);
#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
/* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
}
#elif defined (USE_SD_DIRPOL)
- /* Set Transceiver polarity */
- hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
+ /* Set Transceiver polarity */
+ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
@@ -502,12 +509,12 @@
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
- sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
- HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
+ sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+ HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
@@ -516,7 +523,7 @@
/* Card initialization */
errorstate = SD_InitCard(hsd);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
@@ -525,7 +532,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -545,7 +552,7 @@
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
{
/* Check the SD handle allocation */
- if(hsd == NULL)
+ if (hsd == NULL)
{
return HAL_ERROR;
}
@@ -560,7 +567,7 @@
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
- if(hsd->DriveTransceiver_1_8V_Callback == NULL)
+ if (hsd->DriveTransceiver_1_8V_Callback == NULL)
{
hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
}
@@ -575,7 +582,7 @@
SD_PowerOFF(hsd);
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
- if(hsd->MspDeInitCallback == NULL)
+ if (hsd->MspDeInitCallback == NULL)
{
hsd->MspDeInitCallback = HAL_SD_MspDeInit;
}
@@ -629,8 +636,8 @@
*/
/** @addtogroup SD_Exported_Functions_Group2
- * @brief Data transfer functions
- *
+ * @brief Data transfer functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -655,26 +662,29 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count, data, dataremaining;
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -685,7 +695,7 @@
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -698,10 +708,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Read block(s) in polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
@@ -715,7 +725,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -727,12 +737,12 @@
/* Poll on SDMMC flags */
dataremaining = config.DataLength;
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hsd->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
@@ -747,26 +757,26 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
/* Send stop transmission command in case of multiblock read */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -779,7 +789,7 @@
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -788,7 +798,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -797,7 +807,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -837,26 +847,29 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
+ uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
- uint32_t count, data, dataremaining;
+ uint32_t count;
+ uint32_t data;
+ uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -867,7 +880,7 @@
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -880,10 +893,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
@@ -897,7 +910,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -909,12 +922,13 @@
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+ SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
@@ -929,7 +943,7 @@
dataremaining -= 32U;
}
- if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -939,16 +953,16 @@
return HAL_TIMEOUT;
}
}
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
/* Send stop transmission command in case of multiblock write */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -961,7 +975,7 @@
}
/* Get error state */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -970,7 +984,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -979,7 +993,7 @@
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1020,23 +1034,24 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1050,7 +1065,7 @@
hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1063,10 +1078,10 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Read Blocks in IT mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
@@ -1080,7 +1095,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1090,7 +1105,8 @@
return HAL_ERROR;
}
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_RXFIFOHF));
return HAL_OK;
}
@@ -1113,23 +1129,24 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1143,7 +1160,7 @@
hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1157,12 +1174,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
- hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
@@ -1174,7 +1191,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1185,7 +1202,8 @@
}
/* Enable transfer interrupts */
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_FLAG_TXFIFOHE));
return HAL_OK;
}
@@ -1208,23 +1226,24 @@
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1238,7 +1257,7 @@
hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1252,12 +1271,12 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMABASE0 = (uint32_t) pData ;
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Read Blocks in DMA mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
@@ -1271,7 +1290,7 @@
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1306,23 +1325,24 @@
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+ uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
- if(NULL == pData)
+ if (NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1336,7 +1356,7 @@
hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -1351,13 +1371,13 @@
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMABASE0 = (uint32_t) pData ;
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Write Blocks in Polling mode */
- if(NumberOfBlocks > 1U)
+ if (NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
@@ -1371,7 +1391,7 @@
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1407,17 +1427,17 @@
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
- if(end_add < start_add)
+ if (end_add < start_add)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
- if(end_add > (hsd->SdCard.LogBlockNbr))
+ if (end_add > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -1426,7 +1446,7 @@
hsd->State = HAL_SD_STATE_BUSY;
/* Check if the card command class supports erase command */
- if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
+ if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1435,7 +1455,7 @@
return HAL_ERROR;
}
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1445,18 +1465,18 @@
}
/* Get start and end block for high capacity cards */
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
start_add *= 512U;
end_add *= 512U;
}
/* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD32 SD_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1467,7 +1487,7 @@
/* Send CMD33 SD_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1479,7 +1499,7 @@
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hsd->Instance, 0UL);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -1509,28 +1529,28 @@
uint32_t context = hsd->Context;
/* Check for SDMMC interrupt flags */
- if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Read_IT(hsd);
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND);
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\
- SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
- SDMMC_IT_RXFIFOHF);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \
+ SDMMC_IT_RXFIFOHF);
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
- if((context & SD_CONTEXT_IT) != 0U)
+ if ((context & SD_CONTEXT_IT) != 0U)
{
- if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -1546,7 +1566,7 @@
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
- if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->RxCpltCallback(hsd);
@@ -1563,17 +1583,17 @@
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
- else if((context & SD_CONTEXT_DMA) != 0U)
+ else if ((context & SD_CONTEXT_DMA) != 0U)
{
hsd->Instance->DLEN = 0;
hsd->Instance->DCTRL = 0;
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
- if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -1586,7 +1606,7 @@
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
- if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
@@ -1594,7 +1614,7 @@
HAL_SD_TxCpltCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
- if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+ if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->RxCpltCallback(hsd);
@@ -1609,27 +1629,28 @@
}
}
- else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+ else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Write_IT(hsd);
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR |
+ SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
}
@@ -1638,17 +1659,17 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Disable all interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
- __SDMMC_CMDTRANS_DISABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP;
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT);
- if((context & SD_CONTEXT_IT) != 0U)
+ if ((context & SD_CONTEXT_IT) != 0U)
{
/* Set the SD state to ready to be able to start again the process */
hsd->State = HAL_SD_STATE_READY;
@@ -1659,9 +1680,9 @@
HAL_SD_ErrorCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
- else if((context & SD_CONTEXT_DMA) != 0U)
+ else if ((context & SD_CONTEXT_DMA) != 0U)
{
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Disable Internal DMA */
__HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC);
@@ -1682,13 +1703,13 @@
}
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC);
- if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
+ if (READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U)
{
/* Current buffer is buffer0, Transfer complete for buffer1 */
- if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->Write_DMADblBuf1CpltCallback(hsd);
@@ -1708,7 +1729,7 @@
else /* SD_DMA_BUFFER1 */
{
/* Current buffer is buffer1, Transfer complete for buffer0 */
- if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
+ if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->Write_DMADblBuf0CpltCallback(hsd);
@@ -1743,11 +1764,11 @@
}
/**
-* @brief Return the SD error code
-* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
+ * @brief Return the SD error code
+ * @param hsd : Pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
-* @retval SD Error Code
-*/
+ * @retval SD Error Code
+ */
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
{
return hsd->ErrorCode;
@@ -1849,11 +1870,12 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID,
+ pSD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
@@ -1863,64 +1885,64 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SD_TX_CPLT_CB_ID :
- hsd->TxCpltCallback = pCallback;
- break;
- case HAL_SD_RX_CPLT_CB_ID :
- hsd->RxCpltCallback = pCallback;
- break;
- case HAL_SD_ERROR_CB_ID :
- hsd->ErrorCallback = pCallback;
- break;
- case HAL_SD_ABORT_CB_ID :
- hsd->AbortCpltCallback = pCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Read_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Read_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Write_DMADblBuf0CpltCallback = pCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Write_DMADblBuf1CpltCallback = pCallback;
- break;
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = pCallback;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = pCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = pCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = pCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = pCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Read_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Read_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Write_DMADblBuf0CpltCallback = pCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Write_DMADblBuf1CpltCallback = pCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = pCallback;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1961,64 +1983,64 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
{
- case HAL_SD_TX_CPLT_CB_ID :
- hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
- break;
- case HAL_SD_RX_CPLT_CB_ID :
- hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
- break;
- case HAL_SD_ERROR_CB_ID :
- hsd->ErrorCallback = HAL_SD_ErrorCallback;
- break;
- case HAL_SD_ABORT_CB_ID :
- hsd->AbortCpltCallback = HAL_SD_AbortCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback;
- break;
- case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
- hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback;
- break;
- case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
- hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback;
- break;
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = HAL_SD_MspInit;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = HAL_SD_MspDeInit;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID :
+ hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback;
+ break;
+ case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID :
+ hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_SD_MSP_INIT_CB_ID :
- hsd->MspInitCallback = HAL_SD_MspInit;
- break;
- case HAL_SD_MSP_DEINIT_CB_ID :
- hsd->MspDeInitCallback = HAL_SD_MspDeInit;
- break;
- default :
- /* Update the error code */
- hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -2046,7 +2068,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
@@ -2056,7 +2078,7 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->DriveTransceiver_1_8V_Callback = pCallback;
}
@@ -2086,7 +2108,7 @@
/* Process locked */
__HAL_LOCK(hsd);
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback;
}
@@ -2110,8 +2132,8 @@
*/
/** @addtogroup SD_Exported_Functions_Group3
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -2193,7 +2215,7 @@
pCSD->Reserved2 = 0U; /*!< Reserved */
- if(hsd->SdCard.CardType == CARD_SDSC)
+ if (hsd->SdCard.CardType == CARD_SDSC)
{
pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
@@ -2211,10 +2233,10 @@
hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
- hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
hsd->SdCard.LogBlockSize = 512U;
}
- else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
+ else if (hsd->SdCard.CardType == CARD_SDHC_SDXC)
{
/* Byte 7 */
pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
@@ -2245,7 +2267,7 @@
pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
- pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+ pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
@@ -2263,7 +2285,7 @@
pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
- pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+ pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
@@ -2286,7 +2308,7 @@
HAL_StatusTypeDef status = HAL_OK;
errorstate = SD_SendSDStatus(hsd, sd_status);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2324,7 +2346,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2372,6 +2394,7 @@
{
SDMMC_InitTypeDef Init;
uint32_t errorstate;
+ uint32_t sdmmc_clk;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@@ -2380,19 +2403,19 @@
/* Change State */
hsd->State = HAL_SD_STATE_BUSY;
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
- if(WideMode == SDMMC_BUS_WIDE_8B)
+ if (WideMode == SDMMC_BUS_WIDE_8B)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
- else if(WideMode == SDMMC_BUS_WIDE_4B)
+ else if (WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SD_WideBus_Enable(hsd);
hsd->ErrorCode |= errorstate;
}
- else if(WideMode == SDMMC_BUS_WIDE_1B)
+ else if (WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SD_WideBus_Disable(hsd);
@@ -2410,7 +2433,7 @@
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2418,39 +2441,94 @@
}
else
{
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hsd->Init.ClockEdge;
- Init.ClockPowerSave = hsd->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+ if (sdmmc_clk != 0U)
+ {
+ /* Configure the SDMMC peripheral */
+ Init.ClockEdge = hsd->Init.ClockEdge;
+ Init.ClockPowerSave = hsd->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
- /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
- if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV)
- {
- Init.ClockDiv = hsd->Init.ClockDiv;
- }
- else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
- {
- /* UltraHigh speed SD card,user Clock div */
- Init.ClockDiv = hsd->Init.ClockDiv;
- }
- else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
- {
- /* High speed SD card, Max Frequency = 50Mhz */
- Init.ClockDiv = SDMMC_HSpeed_CLK_DIV;
+ /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */
+ if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ)))
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ {
+ /* UltraHigh speed SD card,user Clock div */
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ {
+ /* High speed SD card, Max Frequency = 50Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+ else
+ {
+ /* No High speed SD card, Max Frequency = 25Mhz */
+ if (hsd->Init.ClockDiv == 0U)
+ {
+ if (sdmmc_clk > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ else
+ {
+ if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+ {
+ Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
+ }
+ else
+ {
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ }
+ }
+ }
+
+#if (USE_SD_TRANSCEIVER != 0U)
+ Init.TranceiverPresent = hsd->Init.TranceiverPresent;
+#endif /* USE_SD_TRANSCEIVER */
+
+ (void)SDMMC_Init(hsd->Instance, Init);
}
else
{
- /* No High speed SD card, Max Frequency = 25Mhz */
- Init.ClockDiv = SDMMC_NSpeed_CLK_DIV;
+ hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER;
+ status = HAL_ERROR;
}
-
- (void)SDMMC_Init(hsd->Instance, Init);
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2492,7 +2570,7 @@
{
switch (SpeedMode)
{
- case SDMMC_SPEED_MODE_AUTO:
+ case SDMMC_SPEED_MODE_AUTO:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
@@ -2523,7 +2601,7 @@
}
break;
}
- case SDMMC_SPEED_MODE_ULTRA:
+ case SDMMC_SPEED_MODE_ULTRA:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
@@ -2543,7 +2621,7 @@
}
break;
}
- case SDMMC_SPEED_MODE_DDR:
+ case SDMMC_SPEED_MODE_DDR:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
@@ -2563,11 +2641,11 @@
}
break;
}
- case SDMMC_SPEED_MODE_HIGH:
+ case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2583,23 +2661,23 @@
}
break;
}
- case SDMMC_SPEED_MODE_DEFAULT:
- break;
- default:
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- status = HAL_ERROR;
- break;
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
}
}
else
{
switch (SpeedMode)
{
- case SDMMC_SPEED_MODE_AUTO:
+ case SDMMC_SPEED_MODE_AUTO:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2614,11 +2692,11 @@
}
break;
}
- case SDMMC_SPEED_MODE_HIGH:
+ case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2634,23 +2712,23 @@
}
break;
}
- case SDMMC_SPEED_MODE_DEFAULT:
- break;
- case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
- default:
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- status = HAL_ERROR;
- break;
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
}
}
#else
switch (SpeedMode)
{
- case SDMMC_SPEED_MODE_AUTO:
+ case SDMMC_SPEED_MODE_AUTO:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2665,11 +2743,11 @@
}
break;
}
- case SDMMC_SPEED_MODE_HIGH:
+ case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
- (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+ (hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
/* Enable High Speed */
if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
@@ -2685,13 +2763,13 @@
}
break;
}
- case SDMMC_SPEED_MODE_DEFAULT:
- break;
- case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
- default:
- hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
- status = HAL_ERROR;
- break;
+ case SDMMC_SPEED_MODE_DEFAULT:
+ break;
+ case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
+ default:
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ status = HAL_ERROR;
+ break;
}
#endif /* USE_SD_TRANSCEIVER */
@@ -2709,7 +2787,7 @@
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
@@ -2734,7 +2812,7 @@
uint32_t resp1 = 0;
errorstate = SD_SendStatus(hsd, &resp1);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
}
@@ -2755,8 +2833,8 @@
HAL_SD_CardStateTypeDef CardState;
/* DIsable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
@@ -2770,11 +2848,11 @@
hsd->Context = SD_CONTEXT_NONE;
CardState = HAL_SD_GetCardState(hsd);
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2792,8 +2870,8 @@
HAL_SD_CardStateTypeDef CardState;
/* Disable All interrupts */
- __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
- SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
+ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* If IDMA Context, disable Internal DMA */
hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
@@ -2804,12 +2882,12 @@
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
- if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
- if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
return HAL_ERROR;
}
@@ -2851,17 +2929,17 @@
uint16_t sd_rca = 1U;
/* Check the power State */
- if(SDMMC_GetPowerState(hsd->Instance) == 0U)
+ if (SDMMC_GetPowerState(hsd->Instance) == 0U)
{
/* Power off */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2875,24 +2953,24 @@
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
}
- if(hsd->SdCard.CardType != CARD_SECURED)
+ if (hsd->SdCard.CardType != CARD_SECURED)
{
/* Get the SD card RCA */
hsd->SdCard.RelCardAdd = sd_rca;
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2917,7 +2995,7 @@
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2936,7 +3014,8 @@
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
__IO uint32_t count = 0U;
- uint32_t response = 0U, validvoltage = 0U;
+ uint32_t response = 0U;
+ uint32_t validvoltage = 0U;
uint32_t errorstate;
#if (USE_SD_TRANSCEIVER != 0U)
uint32_t tickstart = HAL_GetTick();
@@ -2944,19 +3023,19 @@
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->SdCard.CardVersion = CARD_V1_X;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2967,29 +3046,30 @@
hsd->SdCard.CardVersion = CARD_V2_X;
}
- if( hsd->SdCard.CardVersion == CARD_V2_X)
+ if (hsd->SdCard.CardVersion == CARD_V2_X)
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
}
/* SD CARD */
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
+ while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD41 */
- errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
- if(errorstate != HAL_SD_ERROR_NONE)
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY |
+ SD_SWITCH_1_8V_CAPACITY);
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3003,18 +3083,18 @@
count++;
}
- if(count >= SDMMC_MAX_VOLT_TRIAL)
+ if (count >= SDMMC_MAX_VOLT_TRIAL)
{
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
- if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
- if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
+ if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
{
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
@@ -3023,15 +3103,15 @@
/* Send CMD11 to switch 1.8V mode */
errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Check to CKSTOP */
- while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
+ while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
{
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3041,7 +3121,7 @@
hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
/* Check to BusyD0 */
- if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
+ if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
{
/* Error when activate Voltage Switch in SDMMC Peripheral */
return SDMMC_ERROR_UNSUPPORTED_FEATURE;
@@ -3059,9 +3139,9 @@
hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
/* Check VSWEND Flag */
- while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
+ while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
{
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3071,7 +3151,7 @@
hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
/* Check BusyD0 status */
- if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
+ if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
{
/* Error when enabling 1.8V mode */
return HAL_SD_ERROR_INVALID_VOLTRANGE;
@@ -3119,14 +3199,14 @@
uint32_t *pData = pSDstatus;
/* Check SD response */
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Set block size for card if it is not equal to current block size for card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
@@ -3134,7 +3214,7 @@
/* Send CMD55 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
@@ -3151,39 +3231,39 @@
/* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
/* Get status data */
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
*pData = SDMMC_ReadFIFO(hsd->Instance);
pData++;
}
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
return HAL_SD_ERROR_RX_OVERRUN;
}
@@ -3197,7 +3277,7 @@
*pData = SDMMC_ReadFIFO(hsd->Instance);
pData++;
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
@@ -3220,14 +3300,14 @@
{
uint32_t errorstate;
- if(pCardStatus == NULL)
+ if (pCardStatus == NULL)
{
return HAL_SD_ERROR_PARAM;
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3248,31 +3328,31 @@
uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* If requested card supports wide bus operation */
- if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3295,31 +3375,31 @@
uint32_t scr[2U] = {0UL, 0UL};
uint32_t errorstate;
- if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* If requested card supports 1 bit mode operation */
- if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
+ if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3350,14 +3430,14 @@
/* Set Block Size To 8 Bytes */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -3372,14 +3452,15 @@
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
errorstate = SDMMC_CmdSendSCR(hsd->Instance);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
- if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
+ if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U))
{
tempscr[0] = SDMMC_ReadFIFO(hsd->Instance);
tempscr[1] = SDMMC_ReadFIFO(hsd->Instance);
@@ -3387,25 +3468,25 @@
}
- if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
- if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
+ if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
return HAL_SD_ERROR_DATA_TIMEOUT;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
- else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
+ else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
@@ -3417,10 +3498,10 @@
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
- *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+ *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \
((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
scr++;
- *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+ *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \
((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
}
@@ -3436,15 +3517,16 @@
*/
static void SD_Read_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count, data;
- uint8_t* tmp;
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
tmp = hsd->pRxBuffPtr;
if (hsd->RxXferSize >= 32U)
{
/* Read data from SDMMC Rx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hsd->Instance);
*tmp = (uint8_t)(data & 0xFFU);
@@ -3470,15 +3552,16 @@
*/
static void SD_Write_IT(SD_HandleTypeDef *hsd)
{
- uint32_t count, data;
- uint8_t* tmp;
+ uint32_t count;
+ uint32_t data;
+ uint8_t *tmp;
tmp = hsd->pTxBuffPtr;
if (hsd->TxXferSize >= 32U)
{
/* Write data to SDMMC Tx FIFO */
- for(count = 0U; count < 8U; count++)
+ for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tmp);
tmp++;
@@ -3509,16 +3592,17 @@
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
+ uint32_t count;
+ uint32_t loop = 0 ;
uint32_t Timeout = HAL_GetTick();
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
@@ -3540,27 +3624,28 @@
(void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
- errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
+ errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN);
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
for (count = 0U; count < 8U; count++)
{
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
}
loop ++;
}
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_SD_ERROR_TIMEOUT;
}
}
@@ -3596,7 +3681,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode HS is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3620,16 +3705,17 @@
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
+ uint32_t count;
+ uint32_t loop = 0 ;
uint32_t Timeout = HAL_GetTick();
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
@@ -3648,32 +3734,33 @@
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+ if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
for (count = 0U; count < 8U; count++)
{
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
}
loop ++;
}
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_SD_ERROR_TIMEOUT;
}
}
@@ -3709,7 +3796,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode HS is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3723,7 +3810,7 @@
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
/* Enable DelayBlock Peripheral */
/* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
- MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1);
+ MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1);
if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
@@ -3748,16 +3835,17 @@
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
uint32_t SD_hs[16] = {0};
- uint32_t count, loop = 0 ;
+ uint32_t count;
+ uint32_t loop = 0 ;
uint32_t Timeout = HAL_GetTick();
- if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
- /* Standard Speed Card <= 12.5Mhz */
- return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ /* Standard Speed Card <= 12.5Mhz */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
+ if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
@@ -3776,32 +3864,33 @@
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
+ if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
- while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
+ while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND |
+ SDMMC_FLAG_DATAEND))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
for (count = 0U; count < 8U; count++)
{
- SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
+ SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance);
}
loop ++;
}
- if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
+ if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
- hsd->State= HAL_SD_STATE_READY;
+ hsd->State = HAL_SD_STATE_READY;
return HAL_SD_ERROR_TIMEOUT;
}
}
@@ -3837,7 +3926,7 @@
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode is ok */
- if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
+ if ((((uint8_t *)SD_hs)[13] & 2U) != 2U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
@@ -3851,7 +3940,7 @@
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
/* Enable DelayBlock Peripheral */
/* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */
- MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_0);
+ MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0);
if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
diff --git a/Src/stm32l5xx_hal_sd_ex.c b/Src/stm32l5xx_hal_sd_ex.c
index ef291b2..56d8fa4 100644
--- a/Src/stm32l5xx_hal_sd_ex.c
+++ b/Src/stm32l5xx_hal_sd_ex.c
@@ -14,7 +14,8 @@
[..]
The SD Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function.
- (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
+ (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer()
+ and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
@@ -57,8 +58,8 @@
*/
/** @addtogroup SDEx_Exported_Functions_Group1
- * @brief Multibuffer functions
- *
+ * @brief Multibuffer functions
+ *
@verbatim
==============================================================================
##### Multibuffer functions #####
@@ -79,13 +80,14 @@
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1,
+ uint32_t BufferSize)
{
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
- hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0;
- hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1;
- hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize);
+ hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0;
+ hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1;
+ hsd->Instance->IDMABSIZE = (uint32_t)(BLOCKSIZE * BufferSize);
return HAL_OK;
}
@@ -97,7 +99,8 @@
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hsd: SD handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
@@ -107,12 +110,13 @@
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t add = BlockAdd;
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -135,7 +139,7 @@
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_BUSY;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -151,7 +155,7 @@
hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -160,14 +164,15 @@
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
+ SDMMC_IT_IDMABTC));
return HAL_OK;
}
@@ -180,22 +185,24 @@
/**
* @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
- * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
+ * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before
+ * call this function.
* @param hsd: SD handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
- uint32_t DmaBase0_reg, DmaBase1_reg;
+ uint32_t DmaBase0_reg;
+ uint32_t DmaBase1_reg;
uint32_t add = BlockAdd;
- if(hsd->State == HAL_SD_STATE_READY)
+ if (hsd->State == HAL_SD_STATE_READY)
{
- if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
@@ -216,7 +223,7 @@
hsd->State = HAL_SD_STATE_BUSY;
- if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ if (hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
@@ -230,7 +237,7 @@
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hsd->Instance, &config);
- __SDMMC_CMDTRANS_ENABLE( hsd->Instance);
+ __SDMMC_CMDTRANS_ENABLE(hsd->Instance);
hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
@@ -239,14 +246,15 @@
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
- if(errorstate != HAL_SD_ERROR_NONE)
+ if (errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
- __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC));
+ __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
+ SDMMC_IT_IDMABTC));
return HAL_OK;
}
@@ -268,9 +276,10 @@
* transfer use BUFFER0.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
+HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer,
+ uint32_t *pDataBuffer)
{
- if(Buffer == SD_DMA_BUFFER0)
+ if (Buffer == SD_DMA_BUFFER0)
{
/* change the buffer0 address */
hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
diff --git a/Src/stm32l5xx_hal_smartcard.c b/Src/stm32l5xx_hal_smartcard.c
index 75a6777..1eb6858 100644
--- a/Src/stm32l5xx_hal_smartcard.c
+++ b/Src/stm32l5xx_hal_smartcard.c
@@ -2345,7 +2345,7 @@
uint32_t tmpreg;
SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the parameters */
@@ -2370,8 +2370,7 @@
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode;
+ tmpreg = ((uint32_t)(hsmartcard->Init.Parity)) | ((uint32_t)(hsmartcard->Init.Mode)) | ((uint32_t)(hsmartcard->Init.WordLength));
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
diff --git a/Src/stm32l5xx_hal_smartcard_ex.c b/Src/stm32l5xx_hal_smartcard_ex.c
index c7d3100..9017dc5 100644
--- a/Src/stm32l5xx_hal_smartcard_ex.c
+++ b/Src/stm32l5xx_hal_smartcard_ex.c
@@ -458,8 +458,8 @@
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
{
diff --git a/Src/stm32l5xx_hal_smbus_ex.c b/Src/stm32l5xx_hal_smbus_ex.c
new file mode 100644
index 0000000..a66237e
--- /dev/null
+++ b/Src/stm32l5xx_hal_smbus_ex.c
@@ -0,0 +1,156 @@
+/**
+ ******************************************************************************
+ * @file stm32l5xx_hal_smbus_ex.c
+ * @author MCD Application Team
+ * @brief SMBUS Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SMBUS Extended peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SMBUS peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SMBUS interface for STM32L5xx
+ devices contains the following additional features
+
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_SMBUSEx_EnableFastModePlus()
+ (++) HAL_SMBUSEx_DisableFastModePlus()
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUSEx SMBUSEx
+ * @brief SMBUS Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * @note For all I2C4 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * @note For all I2C4 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l5xx_hal_spi.c b/Src/stm32l5xx_hal_spi.c
index 9fd89ca..406a6b7 100644
--- a/Src/stm32l5xx_hal_spi.c
+++ b/Src/stm32l5xx_hal_spi.c
@@ -1007,6 +1007,9 @@
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
@@ -1173,12 +1176,16 @@
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
/* Read 16bit CRC */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
/* Read 8bit CRC */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
@@ -1190,7 +1197,9 @@
goto error;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
@@ -1235,6 +1244,9 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
uint16_t initial_TxXferCount;
uint16_t initial_RxXferCount;
uint32_t tmp_mode;
@@ -1476,12 +1488,16 @@
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
/* Read 16bit CRC */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
/* Read 8bit CRC */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -1493,7 +1509,9 @@
goto error;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
@@ -3048,6 +3066,9 @@
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -3072,12 +3093,16 @@
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* Read 16bit CRC */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
/* Read 8bit CRC */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -3087,7 +3112,9 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
@@ -3152,6 +3179,9 @@
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -3175,7 +3205,9 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
@@ -3185,7 +3217,9 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
#endif /* USE_SPI_CRC */
@@ -3520,8 +3554,12 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 8bit CRC to flush Data Register */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
@@ -3628,8 +3666,12 @@
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 16bit CRC to flush Data Register */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -3684,8 +3726,12 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 8bit CRC to flush Data Register */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
@@ -3738,8 +3784,12 @@
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 16bit CRC to flush Data Register */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -3914,6 +3964,7 @@
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
+ __IO uint32_t tmpreg;
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
@@ -3929,8 +3980,10 @@
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
- /* Read 8bit CRC to flush Data Register */
- READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
+ /* Flush Data Register by a blank read */
+ tmpreg = READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
if (Timeout != HAL_MAX_DELAY)
diff --git a/Src/stm32l5xx_hal_sram.c b/Src/stm32l5xx_hal_sram.c
index b3ca520..d6a10db 100644
--- a/Src/stm32l5xx_hal_sram.c
+++ b/Src/stm32l5xx_hal_sram.c
@@ -127,9 +127,6 @@
* @{
*/
-/**
- @cond 0
- */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -138,9 +135,6 @@
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
-/**
- @endcond
- */
/* Exported functions --------------------------------------------------------*/
@@ -197,7 +191,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/* Initialize SRAM control Interface */
@@ -208,7 +202,7 @@
/* Initialize SRAM extended mode timing Interface */
(void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
- hsram->Init.ExtendedMode);
+ hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
@@ -238,7 +232,7 @@
#else
/* De-Initialize the low level hardware (MSP) */
HAL_SRAM_MspDeInit(hsram);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/* Configure the SRAM registers with their reset values */
(void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
@@ -686,7 +680,7 @@
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -727,7 +721,7 @@
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -909,7 +903,7 @@
__HAL_UNLOCK(hsram);
return status;
}
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
@@ -1037,9 +1031,6 @@
*/
/**
- @cond 0
- */
-/**
* @brief DMA SRAM process complete callback.
* @param hdma : DMA handle
* @retval None
@@ -1058,7 +1049,7 @@
hsram->DmaXferCpltCallback(hdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
@@ -1080,7 +1071,7 @@
hsram->DmaXferCpltCallback(hdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
@@ -1102,11 +1093,8 @@
hsram->DmaXferErrorCallback(hdma);
#else
HAL_SRAM_DMA_XferErrorCallback(hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
-/**
- @endcond
- */
/**
* @}
diff --git a/Src/stm32l5xx_hal_tim.c b/Src/stm32l5xx_hal_tim.c
index feabba4..36d72c6 100644
--- a/Src/stm32l5xx_hal_tim.c
+++ b/Src/stm32l5xx_hal_tim.c
@@ -504,7 +504,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
@@ -563,6 +563,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1079,6 +1080,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1099,6 +1101,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1119,6 +1122,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1138,6 +1142,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1715,6 +1720,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1735,6 +1741,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1754,6 +1761,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Capture/Compare 3 request */
@@ -1773,6 +1781,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2068,7 +2077,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2150,7 +2159,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2302,12 +2311,12 @@
/* Set the TIM channel state */
if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2324,6 +2333,23 @@
return HAL_ERROR;
}
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2338,6 +2364,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -2357,6 +2384,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -2376,6 +2404,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -2395,6 +2424,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2406,23 +2436,6 @@
break;
}
- /* Enable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- {
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- {
- __HAL_TIM_ENABLE(htim);
- }
- }
- else
- {
- __HAL_TIM_ENABLE(htim);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -2677,11 +2690,12 @@
/**
* @brief Starts the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2696,9 +2710,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2713,7 +2727,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2733,11 +2747,12 @@
/**
* @brief Stops the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2749,7 +2764,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -2775,11 +2790,12 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2794,9 +2810,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2811,7 +2827,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2837,11 +2853,12 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2859,7 +2876,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -3131,7 +3148,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3144,7 +3161,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3157,9 +3174,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3249,7 +3266,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3285,7 +3302,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3298,7 +3315,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3311,9 +3328,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3411,7 +3428,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3451,12 +3468,12 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData1 == NULL) && (Length > 0U))
{
@@ -3476,12 +3493,12 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData2 == NULL) && (Length > 0U))
{
@@ -3501,16 +3518,16 @@
else
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3544,6 +3561,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3568,6 +3586,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3593,6 +3612,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -3606,6 +3626,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the Peripheral */
@@ -3684,7 +3705,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -4523,8 +4544,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4540,8 +4562,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4557,8 +4580,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4574,8 +4598,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4591,8 +4616,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4608,8 +4634,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4625,8 +4652,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4846,8 +4874,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4863,8 +4892,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4880,8 +4910,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4897,8 +4928,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4914,8 +4946,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4931,8 +4964,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4948,8 +4982,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -6337,12 +6372,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
+
return channel_state;
}
@@ -6355,7 +6390,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
+
return htim->DMABurstState;
}
@@ -6419,14 +6454,14 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6435,7 +6470,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6444,7 +6479,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6453,7 +6488,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -6524,7 +6559,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6534,7 +6569,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6544,7 +6579,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6554,7 +6589,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
diff --git a/Src/stm32l5xx_hal_tim_ex.c b/Src/stm32l5xx_hal_tim_ex.c
index f98b64b..e17e55a 100644
--- a/Src/stm32l5xx_hal_tim_ex.c
+++ b/Src/stm32l5xx_hal_tim_ex.c
@@ -333,9 +333,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -345,7 +345,7 @@
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
+
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@@ -413,9 +413,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -499,12 +499,12 @@
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -534,6 +534,7 @@
/* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
@@ -635,7 +636,7 @@
{
return HAL_ERROR;
}
-
+
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
@@ -899,6 +900,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -918,6 +920,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -937,6 +940,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -1353,6 +1357,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -1372,6 +1377,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1391,6 +1397,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1513,8 +1520,10 @@
/**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1523,22 +1532,28 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
@@ -1554,8 +1569,10 @@
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1579,8 +1596,10 @@
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1589,8 +1608,10 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1599,22 +1620,28 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -1636,8 +1663,10 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1667,8 +1696,10 @@
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -2399,15 +2430,17 @@
/* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
- do
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
{
- if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM)
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
{
- return HAL_OK;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
}
- } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
-
- return HAL_TIMEOUT;
+ }
}
break;
}
@@ -2420,15 +2453,17 @@
/* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
- do
+ while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
{
- if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM)
+ if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
{
- return HAL_OK;
+ /* New check to avoid false timeout detection in case of preemption */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+ {
+ return HAL_TIMEOUT;
+ }
}
- } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
-
- return HAL_TIMEOUT;
+ }
}
break;
}
@@ -2559,12 +2594,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
+
return channel_state;
}
/**
@@ -2631,7 +2666,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -2640,7 +2675,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -2649,7 +2684,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -2658,7 +2693,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -2683,7 +2718,7 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -2706,13 +2741,13 @@
{
/* nothing to do */
}
-
+
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
diff --git a/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c
index cc7a033..9e487f2 100644
--- a/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c
@@ -7,8 +7,8 @@
* This file overrides the native HAL time base functions (defined as weak)
* to use the RTC WAKEUP for the time base generation:
* + Initializes the RTC peripheral and configures the wakeup timer to be
- * incremented each 1ms
- * + The wakeup feature is configured to assert an interrupt each 1ms
+ * incremented each 1ms when uwTickFreq is set to default value, else
+ * 10 ms or 100 ms, depending of above global variable value.
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
* + HSE (default), LSE or LSI can be selected as RTC clock source
@verbatim
@@ -21,14 +21,6 @@
(#) Add this file and the RTC HAL drivers to your project and uncomment
HAL_RTC_MODULE_ENABLED define in stm32l5xx_hal_conf.h
- [..]
- (@) HAL RTC alarm and HAL RTC wakeup drivers canÂ’t be used with low power modes:
- The wake up capability of the RTC may be intrusive in case of prior low power mode
- configuration requiring different wake up sources.
- Application/Example behavior is no more guaranteed
- (@) The stm32l5xx_hal_timebase_tim use is recommended for the Applications/Examples
- requiring low power modes
-
@endverbatim
******************************************************************************
* @attention
@@ -79,7 +71,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-RTC_HandleTypeDef hRTC_Handle;
+RTC_HandleTypeDef hRTC_Handle = {.Init = {0}};
/* Private function prototypes -----------------------------------------------*/
void RTC_IRQHandler(void);
@@ -101,122 +93,147 @@
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
+ HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t counter = 0U;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+ /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+ if ((uint32_t)uwTickFreq != 0U)
+ {
#ifdef RTC_CLOCK_SOURCE_LSE
- /* Configue LSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.LSEState = RCC_LSE_ON_RTC_ONLY;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ /* Configue LSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON_RTC_ONLY;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#elif defined (RTC_CLOCK_SOURCE_LSI)
- /* Configue LSI as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
- RCC_OscInitStruct.LSIState = RCC_LSI_ON;
- RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ /* Configue LSI as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.LSIDiv = RCC_LSI_DIV1;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#elif defined (RTC_CLOCK_SOURCE_HSE)
- /* Configue HSE as RTC clock soucre */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ /* Configue HSE as RTC clock source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32;
#else
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
- {
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ status = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ if(status == HAL_OK)
{
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
/* Enable RTC Clock */
- __HAL_RCC_RTC_ENABLE();
- __HAL_RCC_RTCAPB_CLK_ENABLE();
-
- /* The time base should be 1ms
- Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
- HSE as RTC clock
- Time base = ((99 + 1) * (4 + 1)) / 500kHz
- = 1ms
- LSE as RTC clock
- Time base = ((31 + 1) * (0 + 1)) / 32.768kHz
- = ~1ms
- LSI as RTC clock
- Time base = ((31 + 1) * (0 + 1)) / 32kHz
- = 1ms
- */
- hRTC_Handle.Instance = RTC;
- hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
- hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
- hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
- hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
- hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
- hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
- if (HAL_RTC_Init(&hRTC_Handle) != HAL_OK)
+ if(status == HAL_OK)
{
- return HAL_ERROR;
- }
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+ __HAL_RCC_RTCAPB_CLK_ENABLE();
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
-
- /* Disable the Wake-up Timer */
- __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
-
- /* Wait till RTC WUTWF flag is set */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == 0U)
- {
- if(counter++ == (SystemCoreClock / 56U))
+ /* The time base should be 1ms
+ Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+ HSE as RTC clock
+ Time base = ((99 + 1) * (4 + 1)) / 500kHz
+ = 1ms
+ LSE as RTC clock
+ Time base = ((31 + 1) * (0 + 1)) / 32.768kHz
+ = ~1ms
+ LSI as RTC clock
+ Time base = ((31 + 1) * (0 + 1)) / 32kHz
+ = 1ms
+ */
+ hRTC_Handle.Instance = RTC;
+ hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
+ hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
+ hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
+ hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
+ hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+ hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+ status = HAL_RTC_Init(&hRTC_Handle);
+ if(status == HAL_OK)
{
- return HAL_ERROR;
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+ /* Disable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+
+ /* Wait till RTC WUTWF flag is set */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == 0U)
+ {
+ if (counter++ == (SystemCoreClock / 56U))
+ {
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Clear PWR wake up Flag */
+ __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
+
+ /* Clear RTC Wake Up timer Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
+
+ /* Configure the Wake-up Timer counter */
+ hRTC_Handle.Instance->WUTR = 0U;
+
+ /* Clear the Wake-up Timer clock source bits in CR register */
+ hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
+
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ /* Configure the Interrupt in the RTC_CR register */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
+
+ /* Enable the Wake-up Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+ HAL_NVIC_EnableIRQ(RTC_IRQn);
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
}
}
-
- /* Clear PWR wake up Flag */
- __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
-
- /* Clear RTC Wake Up timer Flag */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
-
- /* Configure the Wake-up Timer counter */
- hRTC_Handle.Instance->WUTR = 0U;
-
- /* Clear the Wake-up Timer clock source bits in CR register */
- hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
-
- /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-
- /* Configure the Interrupt in the RTC_CR register */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
-
- /* Enable the Wake-up Timer */
- __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
-
- HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_IRQn);
-
- return HAL_OK;
}
}
- return HAL_ERROR;
+ else
+ {
+ status = HAL_ERROR;
+ }
+ return status;
}
/**
diff --git a/Src/stm32l5xx_hal_timebase_tim_template.c b/Src/stm32l5xx_hal_timebase_tim_template.c
index 0e0f38d..7dead0e 100644
--- a/Src/stm32l5xx_hal_timebase_tim_template.c
+++ b/Src/stm32l5xx_hal_timebase_tim_template.c
@@ -4,9 +4,9 @@
* @author MCD Application Team
* @brief Template for HAL time base based on the peripheral hardware TIM6.
*
- * This file override the native HAL time base functions (defined as weak)
+ * This file overrides the native HAL time base functions (defined as weak)
* the TIM time base:
- * + Initializes the TIM6 peripheral to generate a Period elapsed Event each 1ms
+ * + Initializes the TIM peripheral to generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
@verbatim
@@ -64,7 +64,7 @@
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority: Tick interrupt priority.
+ * @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
@@ -73,57 +73,84 @@
uint32_t uwTimclock, uwAPB1Prescaler;
uint32_t uwPrescalerValue;
uint32_t pFLatency;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Configure the TIM6 IRQ priority */
- HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority, 0U);
-
- /* Enable the TIM6 global Interrupt */
- HAL_NVIC_EnableIRQ(TIM6_IRQn);
-
- /* Enable TIM6 clock */
- __HAL_RCC_TIM6_CLK_ENABLE();
-
- /* Get clock configuration */
- HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
-
- /* Get APB1 prescaler */
- uwAPB1Prescaler = clkconfig.APB1CLKDivider;
-
- /* Compute TIM6 clock */
- if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+ if ((uint32_t)uwTickFreq != 0U)
{
- uwTimclock = HAL_RCC_GetPCLK1Freq();
+ /* Enable TIM6 clock */
+ __HAL_RCC_TIM6_CLK_ENABLE();
+
+ /* Get clock configuration */
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+ /* Get APB1 prescaler */
+ uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+
+ /* Compute TIM6 clock */
+ if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ {
+ uwTimclock = HAL_RCC_GetPCLK1Freq();
+ }
+ else
+ {
+ uwTimclock = 2U * HAL_RCC_GetPCLK1Freq();
+ }
+
+ /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
+ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U);
+
+ /* Initialize TIM6 */
+ TimHandle.Instance = TIM6;
+
+ /* Initialize TIMx peripheral as follows:
+ + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ + ClockDivision = 0
+ + Counter direction = Up
+ */
+ TimHandle.Init.Period = (1000000U / 1000U) - 1U;
+ TimHandle.Init.Prescaler = uwPrescalerValue;
+ TimHandle.Init.ClockDivision = 0;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ {
+ /* Start the TIM time Base generation in interrupt mode */
+ if (HAL_TIM_Base_Start_IT(&TimHandle) == HAL_OK)
+ {
+ /* Enable the TIM6 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM6_IRQn);
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ /*Configure the TIM6 IRQ priority */
+ HAL_NVIC_SetPriority(TIM6_IRQn, TickPriority ,0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
}
else
{
- uwTimclock = 2U*HAL_RCC_GetPCLK1Freq();
- }
-
- /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
- uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
-
- /* Initialize TIM6 */
- TimHandle.Instance = TIM6;
-
- /* Initialize TIMx peripheral as follow:
- + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
- + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
- + ClockDivision = 0
- + Counter direction = Up
- */
- TimHandle.Init.Period = (1000000U / 1000U) - 1U;
- TimHandle.Init.Prescaler = uwPrescalerValue;
- TimHandle.Init.ClockDivision = 0;
- TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
- TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
- {
- /* Start the TIM time Base generation in interrupt mode */
- return HAL_TIM_Base_Start_IT(&TimHandle);
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_ERROR;
+ return status;
}
/**
@@ -151,7 +178,7 @@
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM6 interrupt took place, inside
- * HAL_TIM6_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim TIM handle
* @retval None
diff --git a/Src/stm32l5xx_hal_tsc.c b/Src/stm32l5xx_hal_tsc.c
index e3db4fb..17edc20 100644
--- a/Src/stm32l5xx_hal_tsc.c
+++ b/Src/stm32l5xx_hal_tsc.c
@@ -257,6 +257,7 @@
assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
+ assert_param(IS_TSC_PG_PRESC_VS_CTPL(htsc->Init.PulseGeneratorPrescaler, htsc->Init.CTPulseLowLength));
assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
@@ -430,7 +431,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
+ pTSC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
diff --git a/Src/stm32l5xx_hal_uart.c b/Src/stm32l5xx_hal_uart.c
index d6e7fec..e826144 100644
--- a/Src/stm32l5xx_hal_uart.c
+++ b/Src/stm32l5xx_hal_uart.c
@@ -1370,6 +1370,16 @@
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
return(UART_Start_Receive_IT(huart, pData, Size));
}
else
@@ -1479,6 +1489,16 @@
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+
return(UART_Start_Receive_DMA(huart, pData, Size));
}
else
@@ -3012,7 +3032,6 @@
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- tmpreg |= (uint32_t)huart->FifoMode;
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
diff --git a/Src/stm32l5xx_hal_uart_ex.c b/Src/stm32l5xx_hal_uart_ex.c
index aa75591..d51e0ea 100644
--- a/Src/stm32l5xx_hal_uart_ex.c
+++ b/Src/stm32l5xx_hal_uart_ex.c
@@ -977,8 +977,8 @@
uint8_t tx_fifo_depth;
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
{
diff --git a/Src/stm32l5xx_hal_usart_ex.c b/Src/stm32l5xx_hal_usart_ex.c
index 597cdee..a8d5645 100644
--- a/Src/stm32l5xx_hal_usart_ex.c
+++ b/Src/stm32l5xx_hal_usart_ex.c
@@ -503,8 +503,8 @@
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
{
diff --git a/Src/stm32l5xx_ll_adc.c b/Src/stm32l5xx_ll_adc.c
index 195558e..aca110e 100644
--- a/Src/stm32l5xx_ll_adc.c
+++ b/Src/stm32l5xx_ll_adc.c
@@ -825,6 +825,11 @@
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
@@ -941,6 +946,12 @@
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution if feature ADC group injected contexts queue is enabled
+ * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+ * using successively several times this function will appear as
+ * having no effect.
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
diff --git a/Src/stm32l5xx_ll_fmc.c b/Src/stm32l5xx_ll_fmc.c
index 220210f..1b5f0b4 100644
--- a/Src/stm32l5xx_ll_fmc.c
+++ b/Src/stm32l5xx_ll_fmc.c
@@ -58,7 +58,7 @@
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
-#if ((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED) || defined HAL_NAND_MODULE_ENABLED )
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
@@ -86,15 +86,9 @@
/* --- BWTR Register ---*/
/* BWTR register clear mask */
-#if defined(FMC_BWTRx_BUSTURN)
#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
-#else
-#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
- FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD |\
- FMC_BWTRx_DATAHLD))
-#endif /* FMC_BWTRx_BUSTURN */
/* --- PCR Register ---*/
/* PCR register clear mask */
@@ -176,7 +170,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_InitTypeDef *Init)
+ FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
@@ -290,11 +284,8 @@
SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
break;
- case FMC_NORSRAM_BANK4 :
- SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
- break;
-
default :
+ SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
break;
}
}
@@ -310,7 +301,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@@ -350,11 +341,8 @@
CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
break;
- case FMC_NORSRAM_BANK4 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
- break;
-
default :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
break;
}
@@ -370,7 +358,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
- FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr;
@@ -399,7 +387,7 @@
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
{
- tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
}
@@ -420,7 +408,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
- FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
@@ -434,9 +423,7 @@
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
-#if defined(FMC_BWTRx_BUSTURN)
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-#endif /* FMC_BWTRx_BUSTURN */
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
@@ -445,12 +432,8 @@
((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
-#if defined(FMC_BWTRx_BUSTURN)
Timing->AccessMode |
((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
-#else
- Timing->AccessMode));
-#endif /* FMC_BWTRx_BUSTURN */
}
else
{
@@ -605,7 +588,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
- FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -636,7 +619,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
- FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -758,7 +741,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
- uint32_t Timeout)
+ uint32_t Timeout)
{
uint32_t tickstart;
diff --git a/Src/stm32l5xx_ll_icache.c b/Src/stm32l5xx_ll_icache.c
new file mode 100644
index 0000000..c71bcf9
--- /dev/null
+++ b/Src/stm32l5xx_ll_icache.c
@@ -0,0 +1,139 @@
+/**
+ ******************************************************************************
+ * @file stm32l5xx_ll_icache.c
+ * @author MCD Application Team
+ * @brief ICACHE LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_ll_icache.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32L5xx_LL_Driver
+ * @{
+ */
+
+#if defined(ICACHE)
+
+/** @defgroup ICACHE_LL ICACHE
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ICACHE_LL_Private_Macros ICACHE Private Macros
+ * @{
+ */
+
+#define IS_LL_ICACHE_REGION(__VALUE__) (((__VALUE__) == LL_ICACHE_REGION_0) || \
+ ((__VALUE__) == LL_ICACHE_REGION_1) || \
+ ((__VALUE__) == LL_ICACHE_REGION_2) || \
+ ((__VALUE__) == LL_ICACHE_REGION_3))
+
+#define IS_LL_ICACHE_REGION_SIZE(__VALUE__) (((__VALUE__) == LL_ICACHE_REGIONSIZE_2MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_4MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_8MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_16MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_32MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_64MB) || \
+ ((__VALUE__) == LL_ICACHE_REGIONSIZE_128MB))
+
+#define IS_LL_ICACHE_MASTER_PORT(__VALUE__) (((__VALUE__) == LL_ICACHE_MASTER1_PORT) || \
+ ((__VALUE__) == LL_ICACHE_MASTER2_PORT))
+
+#define IS_LL_ICACHE_OUTPUT_BURST(__VALUE__) (((__VALUE__) == LL_ICACHE_OUTPUT_BURST_WRAP) || \
+ ((__VALUE__) == LL_ICACHE_OUTPUT_BURST_INCR))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ICACHE_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ICACHE_LL_EF_REGION_Init
+ * @{
+ */
+
+/**
+ * @brief Configure and enable the memory remapped region.
+ * @note The Instruction Cache and corresponding region must be disabled.
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_ICACHE_REGION_0
+ * @arg @ref LL_ICACHE_REGION_1
+ * @arg @ref LL_ICACHE_REGION_2
+ * @arg @ref LL_ICACHE_REGION_3
+ * @param ICACHE_RegionStruct pointer to a @ref LL_ICACHE_RegionTypeDef structure.
+ * @retval None
+ */
+void LL_ICACHE_ConfigRegion(uint32_t Region, LL_ICACHE_RegionTypeDef *ICACHE_RegionStruct)
+{
+ __IO uint32_t *reg;
+ uint32_t value;
+
+ /* Check the parameters */
+ assert_param(IS_LL_ICACHE_REGION(Region));
+ assert_param(IS_LL_ICACHE_REGION_SIZE(ICACHE_RegionStruct->Size));
+ assert_param(IS_LL_ICACHE_MASTER_PORT(ICACHE_RegionStruct->TrafficRoute));
+ assert_param(IS_LL_ICACHE_OUTPUT_BURST(ICACHE_RegionStruct->OutputBurstType));
+
+ /* Get region control register address */
+ reg = &(ICACHE->CRR0) + (1U * Region);
+
+ /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */
+ /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */
+ /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */
+ /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */
+ /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */
+ /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */
+ /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */
+ value = ((ICACHE_RegionStruct->BaseAddress & 0x1FFFFFFFU) >> 21U) & (0xFFU & ~(ICACHE_RegionStruct->Size - 1U));
+ value |= ((ICACHE_RegionStruct->RemapAddress >> 5U) & ((uint32_t)(0x7FFU & ~(ICACHE_RegionStruct->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos));
+ value |= (ICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | ICACHE_RegionStruct->TrafficRoute | ICACHE_RegionStruct->OutputBurstType;
+ *reg = (value | ICACHE_CRRx_REN); /* Configure and enable region */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ICACHE */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l5xx_ll_lptim.c b/Src/stm32l5xx_ll_lptim.c
index c6c00f2..e85c8c9 100644
--- a/Src/stm32l5xx_ll_lptim.c
+++ b/Src/stm32l5xx_ll_lptim.c
@@ -48,22 +48,22 @@
* @{
*/
#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
- || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+ || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
@@ -266,8 +266,7 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- }
- while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@@ -298,8 +297,7 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- }
- while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ } while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_REPOK(LPTIMx);
}
diff --git a/Src/stm32l5xx_ll_rcc.c b/Src/stm32l5xx_ll_rcc.c
index 1fc0990..6742a14 100644
--- a/Src/stm32l5xx_ll_rcc.c
+++ b/Src/stm32l5xx_ll_rcc.c
@@ -24,7 +24,8 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
+
/** @addtogroup STM32L5xx_LL_Driver
* @{
*/
@@ -43,25 +44,25 @@
* @{
*/
#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
+ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE))
+ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE))
#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
+ || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
#define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))
@@ -89,17 +90,17 @@
/** @defgroup RCC_LL_Private_Functions RCC Private Functions
* @{
*/
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-uint32_t RCC_PLL_GetFreqDomain_SAI(void);
-uint32_t RCC_PLL_GetFreqDomain_48M(void);
-uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
-uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
-uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
-uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
+static uint32_t RCC_GetSystemClockFreq(void);
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+static uint32_t RCC_PLL_GetFreqDomain_SAI(void);
+static uint32_t RCC_PLL_GetFreqDomain_48M(void);
+static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
+static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
+static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
+static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
/**
* @}
*/
@@ -1284,7 +1285,7 @@
* @brief Return SYSTEM clock frequency
* @retval SYSTEM clock frequency (in Hz)
*/
-uint32_t RCC_GetSystemClockFreq(void)
+static uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency;
@@ -1326,7 +1327,7 @@
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK clock frequency (in Hz)
*/
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
@@ -1337,7 +1338,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
@@ -1348,7 +1349,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
@@ -1358,7 +1359,7 @@
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
-uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq, pllsource;
@@ -1398,7 +1399,7 @@
* @brief Return PLL clock frequency used for SAI domain
* @retval PLL clock frequency (in Hz)
*/
-uint32_t RCC_PLL_GetFreqDomain_SAI(void)
+static uint32_t RCC_PLL_GetFreqDomain_SAI(void)
{
uint32_t pllinputfreq, plloutputfreq, pllsource;
uint32_t plln, pllpdiv;
@@ -1451,7 +1452,7 @@
* @brief Return PLL clock frequency used for 48 MHz domain
* @retval PLL clock frequency (in Hz)
*/
-uint32_t RCC_PLL_GetFreqDomain_48M(void)
+static uint32_t RCC_PLL_GetFreqDomain_48M(void)
{
uint32_t pllinputfreq, pllsource;
@@ -1492,7 +1493,7 @@
* @brief Return PLLSAI1 clock frequency used for SAI domain
* @retval PLLSAI1 clock frequency (in Hz)
*/
-uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
+static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
{
uint32_t pllinputfreq, plloutputfreq, pllsource;
uint32_t plln, pllpdiv;
@@ -1544,7 +1545,7 @@
* @brief Return PLLSAI1 clock frequency used for 48Mhz domain
* @retval PLLSAI1 clock frequency (in Hz)
*/
-uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
+static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
{
uint32_t pllinputfreq, pllsource;
@@ -1584,7 +1585,7 @@
* @brief Return PLLSAI1 clock frequency used for ADC domain
* @retval PLLSAI1 clock frequency (in Hz)
*/
-uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
+static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
{
uint32_t pllinputfreq, pllsource;
@@ -1624,7 +1625,7 @@
* @brief Return PLLSAI2 clock frequency used for SAI domain
* @retval PLLSAI2 clock frequency (in Hz)
*/
-uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
+static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
{
uint32_t pllinputfreq, plloutputfreq, pllsource;
uint32_t plln, pllpdiv;
diff --git a/Src/stm32l5xx_ll_rng.c b/Src/stm32l5xx_ll_rng.c
index a9b9739..193a736 100644
--- a/Src/stm32l5xx_ll_rng.c
+++ b/Src/stm32l5xx_ll_rng.c
@@ -42,7 +42,7 @@
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RNG_LL_Private_Macros
+/** @defgroup RNG_LL_Private_Macros RNG Private Macros
* @{
*/
#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
diff --git a/Src/stm32l5xx_ll_sdmmc.c b/Src/stm32l5xx_ll_sdmmc.c
index 7975f91..afd32fd 100644
--- a/Src/stm32l5xx_ll_sdmmc.c
+++ b/Src/stm32l5xx_ll_sdmmc.c
@@ -178,8 +178,8 @@
*/
/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization/de-initialization functions #####
@@ -210,12 +210,12 @@
assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
/* Set SDMMC configuration parameters */
- tmpreg |= (Init.ClockEdge |\
- Init.ClockPowerSave |\
- Init.BusWide |\
- Init.HardwareFlowControl |\
+ tmpreg |= (Init.ClockEdge | \
+ Init.ClockPowerSave | \
+ Init.BusWide | \
+ Init.HardwareFlowControl | \
Init.ClockDiv
- );
+ );
/* Write to SDMMC CLKCR */
MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
@@ -229,8 +229,8 @@
*/
/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### I/O operation functions #####
@@ -273,8 +273,8 @@
*/
/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -362,9 +362,9 @@
SDMMCx->ARG = Command->Argument;
/* Set SDMMC command parameters */
- tmpreg |= (uint32_t)(Command->CmdIndex |\
- Command->Response |\
- Command->WaitForInterrupt |\
+ tmpreg |= (uint32_t)(Command->CmdIndex | \
+ Command->Response | \
+ Command->WaitForInterrupt | \
Command->CPSM);
/* Write to SDMMC CMD register */
@@ -416,7 +416,7 @@
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
-HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data)
{
uint32_t tmpreg = 0;
@@ -434,9 +434,9 @@
SDMMCx->DLEN = Data->DataLength;
/* Set the SDMMC data configuration parameters */
- tmpreg |= (uint32_t)(Data->DataBlockSize |\
- Data->TransferDir |\
- Data->TransferMode |\
+ tmpreg |= (uint32_t)(Data->DataBlockSize | \
+ Data->TransferDir | \
+ Data->TransferMode | \
Data->DPSM);
/* Write to SDMMC DCTRL */
@@ -492,8 +492,8 @@
/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### Commands management functions #####
@@ -788,7 +788,7 @@
* @param addr: Address of the card to be selected
* @retval HAL status
*/
-uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
@@ -1201,7 +1201,7 @@
(void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
/* Check for error conditions */
- errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT);
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT);
return errorstate;
}
@@ -1212,8 +1212,8 @@
/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
- * @brief Responses functions
- *
+ * @brief Responses functions
+ *
@verbatim
===============================================================================
##### Responses management functions #####
@@ -1237,7 +1237,7 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
- uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+ uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1246,16 +1246,16 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT |
+ SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
@@ -1270,7 +1270,7 @@
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
/* Check response received is of desired command */
- if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
{
return SDMMC_ERROR_CMD_CRC_FAIL;
}
@@ -1278,79 +1278,79 @@
/* We have received response, retrieve it for analysis */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
- if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+ if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
{
return SDMMC_ERROR_NONE;
}
- else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+ else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
{
return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
}
- else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+ else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
{
return SDMMC_ERROR_ADDR_MISALIGNED;
}
- else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+ else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
{
return SDMMC_ERROR_BLOCK_LEN_ERR;
}
- else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+ else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
{
return SDMMC_ERROR_ERASE_SEQ_ERR;
}
- else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+ else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
{
return SDMMC_ERROR_BAD_ERASE_PARAM;
}
- else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+ else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
{
return SDMMC_ERROR_WRITE_PROT_VIOLATION;
}
- else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+ else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
{
return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
}
- else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+ else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
{
return SDMMC_ERROR_COM_CRC_FAILED;
}
- else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+ else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
{
return SDMMC_ERROR_ILLEGAL_CMD;
}
- else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+ else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
{
return SDMMC_ERROR_CARD_ECC_FAILED;
}
- else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+ else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
{
return SDMMC_ERROR_CC_ERR;
}
- else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+ else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
{
return SDMMC_ERROR_STREAM_READ_UNDERRUN;
}
- else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+ else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
{
return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
}
- else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+ else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
{
return SDMMC_ERROR_CID_CSD_OVERWRITE;
}
- else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+ else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
{
return SDMMC_ERROR_WP_ERASE_SKIP;
}
- else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+ else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
{
return SDMMC_ERROR_CARD_ECC_DISABLED;
}
- else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+ else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
{
return SDMMC_ERROR_ERASE_RESET;
}
- else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+ else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
{
return SDMMC_ERROR_AKE_SEQ_ERR;
}
@@ -1370,7 +1370,7 @@
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1379,8 +1379,8 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
@@ -1414,7 +1414,7 @@
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1423,10 +1423,10 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
@@ -1456,7 +1456,7 @@
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1465,16 +1465,16 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
@@ -1486,7 +1486,7 @@
}
/* Check response received is of desired command */
- if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
+ if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)
{
return SDMMC_ERROR_CMD_CRC_FAIL;
}
@@ -1497,17 +1497,18 @@
/* We have received response, retrieve it. */
response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);
- if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+ if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD |
+ SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
{
- *pRCA = (uint16_t) (response_r1 >> 16);
+ *pRCA = (uint16_t)(response_r1 >> 16);
return SDMMC_ERROR_NONE;
}
- else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+ else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
{
return SDMMC_ERROR_ILLEGAL_CMD;
}
- else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+ else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
{
return SDMMC_ERROR_COM_CRC_FAILED;
}
@@ -1527,7 +1528,7 @@
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1536,10 +1537,10 @@
return SDMMC_ERROR_TIMEOUT;
}
sta_reg = SDMMCx->STA;
- }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
- ((sta_reg & SDMMC_FLAG_CMDACT) != 0U ));
+ } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) ||
+ ((sta_reg & SDMMC_FLAG_CMDACT) != 0U));
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
@@ -1547,7 +1548,7 @@
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
}
- else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
+ else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
@@ -1559,7 +1560,7 @@
/* Nothing to do */
}
- if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
+ if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))
{
/* Card is SD V2.0 compliant */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);
@@ -1587,7 +1588,7 @@
{
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U);
do
{
@@ -1596,7 +1597,7 @@
return SDMMC_ERROR_TIMEOUT;
}
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+ } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
diff --git a/Src/stm32l5xx_ll_spi.c b/Src/stm32l5xx_ll_spi.c
index eb406a5..00f1124 100644
--- a/Src/stm32l5xx_ll_spi.c
+++ b/Src/stm32l5xx_ll_spi.c
@@ -232,6 +232,12 @@
SPI_CR2_DS | SPI_CR2_SSOE,
SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+ /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
+ if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
+ {
+ LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
+ }
+
/*---------------------------- SPIx CRCPR Configuration ----------------------
* Configure SPIx CRCPR with parameters:
* - CRCPoly: CRCPOLY[15:0] bits
diff --git a/Src/stm32l5xx_ll_usart.c b/Src/stm32l5xx_ll_usart.c
index 36001d3..14c09d1 100644
--- a/Src/stm32l5xx_ll_usart.c
+++ b/Src/stm32l5xx_ll_usart.c
@@ -66,9 +66,6 @@
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
-#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
@@ -290,9 +287,6 @@
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-
- /* Check BRR is lower than or equal to 0xFFFF */
- assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
/*---------------------------- USART PRESC Configuration -----------------------
@@ -352,37 +346,25 @@
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
- /*---------------------------- USART CR2 Configuration -----------------------*/
- /* If Clock signal has to be output */
- if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
- {
- /* Deactivate Clock signal delivery :
- * - Disable Clock Output: USART_CR2_CLKEN cleared
- */
- LL_USART_DisableSCLKOutput(USARTx);
- }
- else
- {
- /* Ensure USART instance is USART capable */
- assert_param(IS_USART_INSTANCE(USARTx));
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
- /* Check clock related parameters */
- assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
- assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
- assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Clock signal related bits) with parameters:
- * - Enable Clock Output: USART_CR2_CLKEN set
- * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
- * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
- * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
- */
- MODIFY_REG(USARTx->CR2,
- USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
- USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
- }
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
/* Else (USART not in Disabled state => return ERROR */
else
diff --git a/Src/stm32l5xx_ll_usb.c b/Src/stm32l5xx_ll_usb.c
index c6a748f..34e33d2 100644
--- a/Src/stm32l5xx_ll_usb.c
+++ b/Src/stm32l5xx_ll_usb.c
@@ -56,8 +56,8 @@
/**
* @brief Initializes the USB Core
- * @param USBx: USB Instance
- * @param cfg : pointer to a USB_CfgTypeDef structure that contains
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -78,7 +78,7 @@
/**
* @brief USB_EnableGlobalInt
* Enables the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
@@ -103,7 +103,7 @@
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
@@ -123,11 +123,11 @@
}
/**
- * @brief USB_SetCurrentMode : Set functional mode
- * @param USBx : Selected device
- * @param mode : current core mode
+ * @brief USB_SetCurrentMode Set functional mode
+ * @param USBx Selected device
+ * @param mode current core mode
* This parameter can be one of the these values:
- * @arg USB_DEVICE_MODE: Peripheral mode
+ * @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
@@ -144,10 +144,10 @@
}
/**
- * @brief USB_DevInit : Initializes the USB controller registers
+ * @brief USB_DevInit Initializes the USB controller registers
* for device mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_CfgTypeDef structure that contains
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -157,13 +157,13 @@
UNUSED(cfg);
/* Init Device */
- /*CNTR_FRES = 1*/
+ /* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
- /*CNTR_FRES = 0*/
+ /* CNTR_FRES = 0 */
USBx->CNTR = 0U;
- /*Clear pending interrupts*/
+ /* Clear pending interrupts */
USBx->ISTR = 0U;
/*Set Btable Address*/
@@ -172,71 +172,11 @@
return HAL_OK;
}
-/**
- * @brief USB_SetDevSpeed :Initializes the device speed
- * depending on the PHY type and the enumeration speed of the device.
- * @param USBx Selected device
- * @param speed device speed
- * @retval Hal status
- */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(speed);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_FlushTxFifo : Flush a Tx FIFO
- * @param USBx : Selected device
- * @param num : FIFO number
- * This parameter can be a value from 1 to 15
- 15 means Flush all Tx FIFOs
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(num);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_FlushRxFifo : Flush Rx FIFO
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-
- return HAL_OK;
-}
-
+#if defined (HAL_PCD_MODULE_ENABLED)
/**
* @brief Activate and configure an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -297,9 +237,11 @@
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@@ -309,6 +251,7 @@
{
/* Set the endpoint as double buffered */
PCD_SET_EP_DBUF(USBx, ep->num);
+
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
@@ -327,7 +270,6 @@
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
if (ep->type != EP_TYPE_ISOC)
{
/* Configure NAK status for the Endpoint */
@@ -348,8 +290,8 @@
/**
* @brief De-activate and de-initialize an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -359,12 +301,14 @@
if (ep->is_in != 0U)
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
@@ -390,6 +334,7 @@
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
+
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
@@ -400,21 +345,21 @@
}
/**
- * @brief USB_EPStartXfer : setup and starts a transfer over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @brief USB_EPStartXfer setup and starts a transfer over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
- uint16_t pmabuffer;
uint32_t len;
+ uint16_t pmabuffer;
uint16_t wEPVal;
/* IN endpoint */
if (ep->is_in == 1U)
{
- /* Multi packet transfer */
+ /*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
@@ -499,10 +444,11 @@
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
- /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer*/
+ /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
+
/* disable double buffer mode */
PCD_CLEAR_EP_DBUF(USBx, ep->num);
@@ -518,21 +464,73 @@
/* manage isochronous double buffer IN mode */
else
{
- /* Write the data to the USB endpoint */
+ /* enable double buffer */
+ PCD_SET_EP_DBUF(USBx, ep->num);
+
+ /* each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ if (len > 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ if (len > 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
}
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
}
}
@@ -542,7 +540,7 @@
{
if (ep->doublebuffer == 0U)
{
- /* Multi packet transfer*/
+ /* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
@@ -554,21 +552,22 @@
ep->xfer_len = 0U;
}
/* configure and validate Rx endpoint */
- /*Set RX buffer count*/
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
else
{
- /*First Transfer Coming From HAL_PCD_EP_Receive & From ISR*/
- /*Set the Double buffer counter*/
+ /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
+ /* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
- /*Coming from ISR*/
+
+ /* Coming from ISR */
if (ep->xfer_count != 0U)
{
- /* update last value to check if there is blocking state*/
+ /* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
+
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
@@ -577,10 +576,10 @@
}
}
}
- /*iso out double */
+ /* iso out double */
else if (ep->type == EP_TYPE_ISOC)
{
- /* Multi packet transfer*/
+ /* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
@@ -605,54 +604,11 @@
return HAL_OK;
}
-/**
- * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param src : pointer to source buffer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to write
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(src);
- UNUSED(ch_ep_num);
- UNUSED(len);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param dest : destination pointer
- * @param len : Number of bytes to read
- * @retval pointer to destination buffer
- */
-void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(dest);
- UNUSED(len);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return ((void *)NULL);
-}
-
-/**
- * @brief USB_EPSetStall : set a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @brief USB_EPSetStall set a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -670,9 +626,9 @@
}
/**
- * @brief USB_EPClearStall : Clear a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @brief USB_EPClearStall Clear a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -693,17 +649,18 @@
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure VALID status for the Endpoint*/
+ /* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
}
return HAL_OK;
}
+#endif
/**
- * @brief USB_StopDevice : Stop the usb device mode
- * @param USBx : Selected device
+ * @brief USB_StopDevice Stop the usb device mode
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
@@ -721,9 +678,9 @@
}
/**
- * @brief USB_SetDevAddress : Stop the usb device mode
- * @param USBx : Selected device
- * @param address : new device address to be assigned
+ * @brief USB_SetDevAddress Stop the usb device mode
+ * @param USBx Selected device
+ * @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
@@ -739,8 +696,8 @@
}
/**
- * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
@@ -752,8 +709,8 @@
}
/**
- * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
@@ -765,8 +722,8 @@
}
/**
- * @brief USB_ReadInterrupts: return the global USB interrupt status
- * @param USBx : Selected device
+ * @brief USB_ReadInterrupts return the global USB interrupt status
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
@@ -778,113 +735,8 @@
}
/**
- * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief Returns Device OUT EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device OUT EP Interrupt register
- */
-uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(epnum);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief Returns Device IN EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device IN EP Interrupt register
- */
-uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(epnum);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief USB_ClearInterrupts: clear a USB interrupt
- * @param USBx Selected device
- * @param interrupt flag
- * @retval None
- */
-void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(interrupt);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-}
-
-/**
- * @brief Prepare the EP0 to start the first control setup
- * @param USBx Selected device
- * @param psetup pointer to setup packet
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(psetup);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
* @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
- * @param USBx Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
@@ -895,13 +747,14 @@
}
/**
- * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
- * @param USBx Selected device
+ * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
{
USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
+
return HAL_OK;
}
@@ -910,7 +763,7 @@
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
- * @param wNBytes: no. of bytes to be copied.
+ * @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
@@ -941,10 +794,10 @@
/**
* @brief Copy data from packet memory area (PMA) to user memory buffer
- * @param USBx: USB peripheral instance register address.
+ * @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
- * @param wNBytes: no. of bytes to be copied.
+ * @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
diff --git a/_htmresc/Add button.svg b/_htmresc/Add button.svg
new file mode 100644
index 0000000..c211545
--- /dev/null
+++ b/_htmresc/Add button.svg
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 200 200"><g fill="#13254a"><path d="M100 .212C44.868.212 0 44.889 0 99.788c0 55.132 44.868 100 100 100s100-44.868 100-100C200 44.889 155.132.212 100 .212zm0 181.164c-44.974 0-81.587-36.614-81.587-81.587 0-44.762 36.614-81.164 81.587-81.164 44.995 0 81.587 36.402 81.587 81.164 0 44.973-36.592 81.587-81.587 81.587z" style="fill: #e6007e;"/><path d="M141.1 88.127h-29.439V58.688c0-6.392-5.185-11.598-11.598-11.598-6.413 0-11.619 5.206-11.619 11.598v29.439H58.476c-6.392 0-11.598 5.185-11.598 11.598 0 6.413 5.206 11.619 11.598 11.619h29.968v29.968c0 6.392 5.206 11.598 11.619 11.598 6.413 0 11.598-5.206 11.598-11.598v-29.968H141.1c6.392 0 11.598-5.206 11.598-11.619 0-6.413-5.206-11.598-11.598-11.598z" style="fill: #e6007e;"/></g></svg>
diff --git a/_htmresc/Update.svg b/_htmresc/Update.svg
new file mode 100644
index 0000000..f88381f
--- /dev/null
+++ b/_htmresc/Update.svg
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 200 200"><g fill="#03234b"><path d="M170.934 64.569l-.04-.055-29.049 40.038-.057.079h14.867a59.366 59.366 0 0 1-1.488 15.615c-1.158 5.318-3.807 13.448-9.848 21.977-2.766 4.118-6.375 7.726-9.208 10.408-3.426 2.857-7.461 6.095-12 8.376-8.121 4.568-17.881 7.138-28.225 7.432-10.907.248-20.201-2.61-26.072-5.052-8.283-3.479-14.111-7.807-16.85-10.078-1.254-.956-2.25-1.907-3.057-2.676a28.662 28.662 0 0 0-1.157-1.069 158.874 158.874 0 0 0-1.479-1.362l-4.435-3.956 3.569 4.81.183.243c.2.263.548.722 1.048 1.389.276.334.579.747.93 1.226l.008.01c.689.939 1.546 2.107 2.664 3.322 3 3.536 8.178 8.801 15.808 13.801 5.969 3.866 15.672 8.901 28.001 10.935a79.05 79.05 0 0 0 12.485.998c7.97 0 15.651-1.228 22.828-3.649 6.366-1.877 12.192-4.981 17.053-7.771 6.16-3.936 10.817-7.586 14.654-11.488 8.084-7.899 14.884-17.913 19.15-28.199 3.259-7.594 5.456-15.727 6.529-24.175l.055-.425.083-.641H200l-29.066-40.063zM58.159 99.232l-12.655.563c-.097-.881-.159-1.986-.227-3.474a59.184 59.184 0 0 1 1.446-16.56c1.157-5.316 3.804-13.444 9.848-21.977 2.168-3.228 5.009-6.44 9.208-10.415 3.41-2.849 7.432-6.08 12.005-8.375 8.114-4.568 17.87-7.138 28.213-7.432 10.9-.25 20.196 2.607 26.072 5.045 8.258 3.473 14.105 7.812 16.857 10.091 1.257.951 2.253 1.904 3.057 2.673l.017.016c.43.411.801.766 1.136 1.051.475.438.841.777 1.091 1.01l.138.128.248.229 4.04 3.613-3.165-4.456c-.058-.083-.312-.417-.73-.971l-.507-.67a28.922 28.922 0 0 1-.901-1.192l-.02-.027c-.69-.945-1.548-2.121-2.677-3.346-3.002-3.537-8.182-8.803-15.813-13.801-5.964-3.865-15.662-8.9-27.997-10.935-8.484-1.363-21.496-2.009-35.313 2.651-6.355 1.88-12.186 4.983-17.054 7.772-6.163 3.944-10.82 7.595-14.654 11.488-8.079 7.894-14.882 17.909-19.155 28.2-3.268 7.624-5.463 15.757-6.523 24.173-.436 3.281-.642 5.421-.664 6.926L0 101.831l30.683 38.727.042.053 27.38-41.298.054-.081z" style="fill: #e6007e;"/></g></svg>
diff --git a/_htmresc/favicon.png b/_htmresc/favicon.png
new file mode 100644
index 0000000..06713ee
--- /dev/null
+++ b/_htmresc/favicon.png
Binary files differ
diff --git a/_htmresc/mini-st_2020.css b/_htmresc/mini-st_2020.css
new file mode 100644
index 0000000..986f4d4
--- /dev/null
+++ b/_htmresc/mini-st_2020.css
@@ -0,0 +1,1711 @@
+@charset "UTF-8";
+/*
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
+
+html {
+ font-size: 13.5px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.25;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 400; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
+h3 {
+ font-size: calc(1rem * var(--heading-ratio) ); }
+
+h4 {
+ font-size: calc(1rem * var(--heading-ratio)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(3 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0714285714rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 2rem;
+ font-weight: 800;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0714285714rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+ --card-back-color: #e5b8b7;
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
+
+.card.error {
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
+
+.card > .sectione.dark {
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 500;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0714285714rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0714285714rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0714285714rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
+
+header {
+ height: 2.75rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ margin: 0;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0; }
+ table caption {
+ font-size: 1rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0714285714rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 100%; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex: .2 0 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: .8 0 0;
+ margin-left: 0;
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: auto;
+ border: 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0714285714rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #ffffff;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(1 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.4;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.25rem;
+ cursor: pointer;
+ transition: background 0.2s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 100%; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.tertiary {
+ --mark-back-color: #3cb4e6; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progress module CSS variable definitions */
+:root {
+ --progress-back-color: #3cb4e6;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26).
+*/
+span.icon-st-update {
+ background-image: url("Update.svg"); }
+span.icon-st-add {
+ background-image: url("Add button.svg"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/_htmresc/st_logo_2020.png b/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000..d6cebb5
--- /dev/null
+++ b/_htmresc/st_logo_2020.png
Binary files differ
