Release v1.5.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index e6635d1..7d29c4f 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -241,7 +241,7 @@
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -313,8 +313,8 @@
#endif /* STM32L4 */
#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#endif
#if defined(STM32H7)
@@ -579,8 +579,7 @@
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) \
- || defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
@@ -955,7 +954,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1014,7 +1013,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1449,6 +1448,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1507,13 +1530,13 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1539,10 +1562,10 @@
*/
#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
@@ -3219,9 +3242,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@@ -3349,7 +3371,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined STM32WL
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3457,9 +3479,9 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
@@ -3472,7 +3494,7 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3727,9 +3749,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32L4)
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif
+#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/
diff --git a/Inc/stm32wbxx_hal.h b/Inc/stm32wbxx_hal.h
index b69544f..4e130d4 100644
--- a/Inc/stm32wbxx_hal.h
+++ b/Inc/stm32wbxx_hal.h
@@ -38,23 +38,26 @@
* @{
*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
- * @{
- */
-
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
-#define HAL_TICK_FREQ_10HZ 100U
-#define HAL_TICK_FREQ_100HZ 10U
-#define HAL_TICK_FREQ_1KHZ 1U
-#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
/**
* @}
*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
@@ -594,8 +597,8 @@
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
-uint32_t HAL_GetTickFreq(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
@@ -630,7 +633,7 @@
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
-extern uint32_t uwTickFreq;
+extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
diff --git a/Inc/stm32wbxx_hal_adc.h b/Inc/stm32wbxx_hal_adc.h
index 51790fc..0968ba9 100644
--- a/Inc/stm32wbxx_hal_adc.h
+++ b/Inc/stm32wbxx_hal_adc.h
@@ -125,8 +125,8 @@
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
- Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
- to free the IRQ vector sequencer.
+ Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
+ Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
diff --git a/Inc/stm32wbxx_hal_exti.h b/Inc/stm32wbxx_hal_exti.h
index e169796..a122369 100644
--- a/Inc/stm32wbxx_hal_exti.h
+++ b/Inc/stm32wbxx_hal_exti.h
@@ -105,18 +105,39 @@
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)
+#else
+#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u)
+#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u)
+#endif
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
+#else
+#define EXTI_LINE_23 (EXTI_RESERVED | EXTI_REG1 | 0x17u)
+#endif
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
+#else
+#define EXTI_LINE_25 (EXTI_RESERVED | EXTI_REG1 | 0x19u)
+#endif
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
+#else
+#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
+#endif
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
+#else
+#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu)
+#endif
#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
@@ -128,7 +149,7 @@
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
-#if defined (STM32WB55xx)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
#else
#define EXTI_LINE_43 (EXTI_RESERVED | EXTI_REG2 | 0x0Bu)
@@ -170,7 +191,7 @@
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
-#if defined (STM32WB55xx)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define EXTI_GPIOD 0x00000003u
#endif
#define EXTI_GPIOE 0x00000004u
@@ -261,7 +282,7 @@
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
-#if defined (STM32WB55xx)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
diff --git a/Inc/stm32wbxx_hal_flash.h b/Inc/stm32wbxx_hal_flash.h
index 548518f..683e0f2 100644
--- a/Inc/stm32wbxx_hal_flash.h
+++ b/Inc/stm32wbxx_hal_flash.h
@@ -46,7 +46,7 @@
*/
typedef struct
{
- uint32_t TypeErase; /*!< Mass erase or page erase.
+ uint32_t TypeErase; /*!< Page erase.
This parameter can be a value of @ref FLASH_TYPE_ERASE */
uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled
This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */
@@ -222,7 +222,6 @@
* @{
*/
#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER /*!< Flash mass erase activation*/
/**
* @}
*/
@@ -853,8 +852,7 @@
#define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL))
-#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
- ((__VALUE__) == FLASH_TYPEERASE_MASSERASE))
+#define IS_FLASH_TYPEERASE(__VALUE__) ((__VALUE__) == FLASH_TYPEERASE_PAGES)
#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
diff --git a/Inc/stm32wbxx_hal_gpio_ex.h b/Inc/stm32wbxx_hal_gpio_ex.h
index fc10f8e..3000c6d 100644
--- a/Inc/stm32wbxx_hal_gpio_ex.h
+++ b/Inc/stm32wbxx_hal_gpio_ex.h
@@ -53,7 +53,7 @@
*
*/
-#if defined (STM32WB55xx) || defined (STM32WB50xx)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx)
/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
*_____________________________________________________________________________________________
@@ -355,7 +355,6 @@
/**
* @brief AF 15 selection
*/
-
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
@@ -363,6 +362,241 @@
#endif
+#if defined (STM32WB35xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
+#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
+#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
+#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
+#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
+#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
+#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
+#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
+#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */
+#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */
+#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */
+#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_SPI1 ((uint8_t)0x03) /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
+#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
+#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
+#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
+#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
+#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
+#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
+#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+ #define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /*!< QUADSPI Alternate Function mapping */
+#define GPIO_AF10_USB ((uint8_t)0x0A) /*!< USB Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */
+#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
+
+#endif
+
+#if defined (STM32WB30xx)
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
+#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
+#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
+#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
+#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
+#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
+#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
+#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
+#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */
+#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */
+#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */
+#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */
+
+ /**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
+#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
+#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
+#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
+#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
+#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
+#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
+
+#endif
+
/**
* @}
@@ -380,7 +614,7 @@
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{
*/
-#if defined (STM32WB55xx)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
((__GPIOx__) == (GPIOB))? 1uL :\
((__GPIOx__) == (GPIOC))? 2uL :\
diff --git a/Inc/stm32wbxx_hal_i2s.h b/Inc/stm32wbxx_hal_i2s.h
new file mode 100644
index 0000000..b1fcb0a
--- /dev/null
+++ b/Inc/stm32wbxx_hal_i2s.h
@@ -0,0 +1,546 @@
+/**
+ ******************************************************************************
+ * @file stm32wbxx_hal_i2s.h
+ * @author MCD Application Team
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBxx_HAL_I2S_H
+#define STM32WBxx_HAL_I2S_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal_def.h"
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup STM32WBxx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
+} HAL_I2S_StateTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
+typedef struct __I2S_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+{
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
+
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_Error */
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
+ void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
+ void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
+ void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
+ void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
+
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+} I2S_HandleTypeDef;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL I2S Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
+ HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
+ HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
+ HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
+ HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
+ HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
+ HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
+
+} HAL_I2S_CallbackIDTypeDef;
+
+/**
+ * @brief HAL I2S Callback pointer definition
+ */
+typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
+
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+ * @{
+ */
+/** @defgroup I2S_Error I2S Error
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode I2S Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX (0x00000000U)
+#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard I2S Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILIPS (0x00000000U)
+#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format I2S Data Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
+#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K (192000U)
+#define I2S_AUDIOFREQ_96K (96000U)
+#define I2S_AUDIOFREQ_48K (48000U)
+#define I2S_AUDIOFREQ_44K (44100U)
+#define I2S_AUDIOFREQ_32K (32000U)
+#define I2S_AUDIOFREQ_22K (22050U)
+#define I2S_AUDIOFREQ_16K (16000U)
+#define I2S_AUDIOFREQ_11K (11025U)
+#define I2S_AUDIOFREQ_8K (8000U)
+#define I2S_AUDIOFREQ_DEFAULT (2U)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW (0x00000000U)
+#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flags_Definition I2S Flags Definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+
+#define I2S_FLAG_MASK (SPI_SR_RXNE\
+ | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2S_Exported_macros I2S Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+
+/** @brief Enable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief Disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief Enable the specified I2S interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
+/** @brief Disable the specified I2S interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__ specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ }while(0U)
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg_udr = 0x00U;\
+ tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of I2S SR regsiter.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun error flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_CHSIDE: Channel side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
+ & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of I2S CR2 regsiter.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if I2S Mode parameter is in allowed range.
+ * @param __MODE__ specifies the I2S Mode.
+ * This parameter can be a value of @ref I2S_Mode
+ * @retval None
+ */
+#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
+ ((__MODE__) == I2S_MODE_SLAVE_RX) || \
+ ((__MODE__) == I2S_MODE_MASTER_TX) || \
+ ((__MODE__) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
+ ((__STANDARD__) == I2S_STANDARD_MSB) || \
+ ((__STANDARD__) == I2S_STANDARD_LSB) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
+ ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+
+/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__ specifies the I2S serial clock steady state.
+ * This parameter can be a value of @ref I2S_Clock_Polarity
+ * @retval None
+ */
+#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
+ ((__CPOL__) == I2S_CPOL_HIGH))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBxx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32wbxx_hal_pwr.h b/Inc/stm32wbxx_hal_pwr.h
index 58f0bc3..df07fd2 100644
--- a/Inc/stm32wbxx_hal_pwr.h
+++ b/Inc/stm32wbxx_hal_pwr.h
@@ -235,12 +235,22 @@
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\
- (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
- ((((((uint8_t)(__FLAG__)) >> 5U) == 2U)) ?\
- (PWR->SR2 & (1U << ((__FLAG__) & 31U))) :\
- (PWR->EXTSCR & (1U << ((__FLAG__) & 31U))) ) )
-
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \
+ ( \
+ PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \
+ ) \
+ : \
+ ( \
+ (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \
+ ( \
+ PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \
+ ) \
+ : \
+ ( \
+ PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \
+ ) \
+ ) \
+ )
/** @brief Clear a specific PWR flag.
* @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_SB}
@@ -280,13 +290,18 @@
*
* @retval None
*/
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\
- ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
- (PWR->SCR = (__FLAG__)) : (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) :\
- ( (((uint8_t)(__FLAG__)) == PWR_FLAG_CRITICAL_RF_PHASE) ?\
- SET_BIT (PWR->EXTSCR, PWR_EXTSCR_CCRPF) : ( ((((uint8_t)((__FLAG__)) & 31U) <= PWR_EXTSCR_C1STOPF_Pos) ?\
- SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C1CSSF): SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C2CSSF)) ) ))
-
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \
+ ( \
+ PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \
+ ) \
+ : \
+ ( \
+ (((__FLAG__)) == PWR_FLAG_WU) ? \
+ (PWR->SCR = PWR_SCR_CWUF) : \
+ (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \
+ ) \
+ )
+
/**
* @brief Enable the PVD Extended Interrupt C1 Line.
* @retval None
diff --git a/Inc/stm32wbxx_hal_pwr_ex.h b/Inc/stm32wbxx_hal_pwr_ex.h
index b7367f4..612cfa2 100644
--- a/Inc/stm32wbxx_hal_pwr_ex.h
+++ b/Inc/stm32wbxx_hal_pwr_ex.h
@@ -323,62 +323,62 @@
* - XX : Status register (2 bits)
* - 01: SR1 register
* - 10: SR2 register
- * - 11: C2_SCR register
+ * - 11: EXTSCR register
* The only exception is PWR_FLAG_WUF, encompassing all
* wake-up flags and set to PWR_SR1_WUF.
* @{
*/
/*--------------------------------SR1-------------------------------*/
-#define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */
+#define PWR_FLAG_WUF1 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos) /*!< Wakeup event on wakeup pin 1 */
#if defined(PWR_CR3_EWUP2)
-#define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */
+#define PWR_FLAG_WUF2 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos) /*!< Wakeup event on wakeup pin 2 */
#endif
#if defined(PWR_CR3_EWUP3)
-#define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */
+#define PWR_FLAG_WUF3 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos) /*!< Wakeup event on wakeup pin 3 */
#endif
-#define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */
+#define PWR_FLAG_WUF4 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF4_Pos) /*!< Wakeup event on wakeup pin 4 */
#if defined(PWR_CR3_EWUP5)
-#define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */
+#define PWR_FLAG_WUF5 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF5_Pos) /*!< Wakeup event on wakeup pin 5 */
#endif
-#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
+#define PWR_FLAG_WU (PWR_FLAG_REG_SR1 | PWR_SR1_WUF) /*!< Encompass wakeup event on all wakeup pins */
#if defined(PWR_CR5_SMPSEN)
-#define PWR_FLAG_FRCBYPI (0x0027U) /*!< SMPS Forced in Bypass Interrupt Flag */
+#define PWR_FLAG_FRCBYPI (PWR_FLAG_REG_SR1 | PWR_SR1_SMPSFBF_Pos) /*!< SMPS Forced in Bypass Interrupt Flag */
#endif
-#define PWR_FLAG_BHWF (0x0029U) /*!< BLE_Host WakeUp Flag */
-#define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */
-#define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */
-#define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */
-#define PWR_FLAG_HOLDC2I (0x002EU) /*!< CPU2 on-Hold Interrupt Flag */
-#define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */
+#define PWR_FLAG_BHWF (PWR_FLAG_REG_SR1 | PWR_SR1_BLEWUF_Pos) /*!< BLE_Host WakeUp Flag */
+#define PWR_FLAG_RFPHASEI (PWR_FLAG_REG_SR1 | PWR_SR1_CRPEF_Pos) /*!< Radio Phase Interrupt Flag */
+#define PWR_FLAG_BLEACTI (PWR_FLAG_REG_SR1 | PWR_SR1_BLEAF_Pos) /*!< BLE Activity Interrupt Flag */
+#define PWR_FLAG_802ACTI (PWR_FLAG_REG_SR1 | PWR_SR1_802AF_Pos) /*!< 802.15.4 Activity Interrupt Flag */
+#define PWR_FLAG_HOLDC2I (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos) /*!< CPU2 on-Hold Interrupt Flag */
+#define PWR_FLAG_WUFI (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos) /*!< Wakeup on internal wakeup line */
/*--------------------------------SR2-------------------------------*/
#if defined(PWR_CR5_SMPSEN)
-#define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */
-#define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */
+#define PWR_FLAG_SMPSRDYF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSBF_Pos) /*!< SMPS Ready Flag */
+#define PWR_FLAG_SMPSBYPF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSF_Pos) /*!< SMPS Bypass Flag */
#endif
-#define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */
-#define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */
+#define PWR_FLAG_REGLPS (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos) /*!< Low-power regulator start flag */
+#define PWR_FLAG_REGLPF (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos) /*!< Low-power regulator flag */
#if defined(PWR_CR1_VOS)
-#define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */
+#define PWR_FLAG_VOSF (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos) /*!< Voltage scaling flag */
#endif
-#define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */
+#define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */
-#define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */
-#define PWR_FLAG_PVMO3 (0x004EU) /*!< Power Voltage Monitoring 3 output flag */
+#define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */
+#define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */
/*------------------------------EXTSCR---------------------------*/
-#define PWR_FLAG_SB (0x0068U) /*!< System Standby flag for CPU1 */
-#define PWR_FLAG_STOP (0x0069U) /*!< System Stop flag for CPU1 */
+#define PWR_FLAG_SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU1 */
+#define PWR_FLAG_STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU1 */
-#define PWR_FLAG_C2SB (0x006AU) /*!< System Standby flag for CPU2 */
-#define PWR_FLAG_C2STOP (0x006BU) /*!< System Stop flag for CPU2 */
+#define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */
+#define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU2 */
-#define PWR_FLAG_CRITICAL_RF_PHASE (0x006DU) /*!< Critical radio system phase flag */
-#define PWR_FLAG_C1DEEPSLEEP (0x006EU) /*!< CPU1 DeepSleep Flag */
-#define PWR_FLAG_C2DEEPSLEEP (0x006FU) /*!< CPU2 DeepSleep Flag */
+#define PWR_FLAG_CRITICAL_RF_PHASE (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_CRPF_Pos | (PWR_EXTSCR_CCRPF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< Critical radio system phase flag */
+#define PWR_FLAG_C1DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1DS_Pos) /*!< CPU1 DeepSleep Flag */
+#define PWR_FLAG_C2DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2DS_Pos) /*!< CPU2 DeepSleep Flag */
/**
* @}
*/
@@ -436,6 +436,19 @@
* @}
*/
+/** @defgroup PWR_FLAG_REG PWR flag register
+ * @{
+ */
+#define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */
+#define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */
+#define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */
+#define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */
+#define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */
+#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos | PWR_EXTSCR_CCRPF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/Inc/stm32wbxx_hal_rcc.h b/Inc/stm32wbxx_hal_rcc.h
index 36c647b..1643d2f 100644
--- a/Inc/stm32wbxx_hal_rcc.h
+++ b/Inc/stm32wbxx_hal_rcc.h
@@ -120,9 +120,9 @@
#if defined(SAI1)
#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \
- (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
- (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \
- (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK)) == 0U))
+ (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \
+ (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \
+ (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK | RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK)) == 0U))
#endif
#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
((__RANGE__) == RCC_MSIRANGE_1) || \
@@ -164,7 +164,14 @@
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
-#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) )
+#if defined(RCC_MCO3_SUPPORT)
+#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \
+ ((__MCOX__) == RCC_MCO2) || \
+ ((__MCOX__) == RCC_MCO3))
+#else
+#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || \
+ ((__MCOX__) == RCC_MCO2))
+#endif
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
@@ -510,6 +517,9 @@
#define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */
#endif
#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
+#if defined(SPI_I2S_SUPPORT)
+#define RCC_PLL_I2SCLK RCC_PLLCFGR_PLLPEN /*!< PLLI2SCLK selection from main PLL */
+#endif
/**
* @}
*/
@@ -629,7 +639,9 @@
*/
#define RCC_MCO1 0x00000000U /*!< MCO1 index */
#define RCC_MCO2 0x00000001U /*!< MCO2 index */
+#if defined(RCC_MCO3_SUPPORT)
#define RCC_MCO3 0x00000002U /*!< MCO3 index */
+#endif
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/
/**
@@ -729,7 +741,9 @@
#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
+#if defined(SAI1)
#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */
+#endif
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
@@ -1216,7 +1230,7 @@
#define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
-#if defined(GPIOD)
+#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@@ -2921,6 +2935,7 @@
* @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz)
* @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG
* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz)
+ * @arg @ref RCC_PLL_I2SCLK This Clock is used to generate the clock for the I2S
* @retval None
*/
#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
diff --git a/Inc/stm32wbxx_hal_rcc_ex.h b/Inc/stm32wbxx_hal_rcc_ex.h
index 230929e..789a288 100644
--- a/Inc/stm32wbxx_hal_rcc_ex.h
+++ b/Inc/stm32wbxx_hal_rcc_ex.h
@@ -59,7 +59,14 @@
/** @addtogroup RCCEx_Private_Macros
* @{
*/
-#define IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) )
+#if defined(RCC_LSCO3_SUPPORT)
+#define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \
+ ((__LSCOX__) == RCC_LSCO2) || \
+ ((__LSCOX__) == RCC_LSCO3))
+#else
+#define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \
+ ((__LSCOX__) == RCC_LSCO2))
+#endif
#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
((__SOURCE__) == RCC_LSCOSOURCE_LSE))
@@ -67,8 +74,8 @@
#if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
@@ -79,10 +86,25 @@
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
(((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS))
+#elif defined(LPUART1) && defined(USB) && defined(RCC_SMPS_SUPPORT) && defined(SPI_I2S_SUPPORT)
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
+ (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S))
#else
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
@@ -118,9 +140,9 @@
#endif
#if defined(SAI1)
-#define IS_RCC_SAI1CLK(__SOURCE__) \
+#define IS_RCC_SAI1CLK(__SOURCE__) \
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
- ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
#endif
@@ -145,6 +167,7 @@
((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))
+#if defined(USB)
#if defined(SAI1)
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
@@ -157,17 +180,24 @@
((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
#endif
+#endif
-#if defined(SAI1)
+#if defined(STM32WB55xx) || defined (STM32WB5Mxx)
+#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
+#elif defined(STM32WB35xx)
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#else
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
- ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#endif
@@ -190,6 +220,14 @@
((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE))
#endif
+#if defined(SPI_I2S_SUPPORT)
+#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_I2SCLKSOURCE_NONE) || \
+ ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \
+ ((__SOURCE__) == RCC_I2SCLKSOURCE_PIN))
+#endif
+
#if defined(SAI1)
#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
@@ -299,8 +337,10 @@
This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
#endif
+#if defined(USB)
uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG).
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+#endif
uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB).
This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
@@ -322,6 +362,11 @@
uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor.
This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */
#endif
+
+#if defined(SPI_I2S_SUPPORT)
+ uint32_t I2sClockSelection; /*!< Specifies I2s clock source.
+ This parameter can be a value of @ref RCCEx_I2s_Clock_Source */
+#endif
} RCC_PeriphCLKInitTypeDef;
@@ -389,7 +434,9 @@
*/
#define RCC_LSCO1 0x00000000U /*!< LSCO1 index */
#define RCC_LSCO2 0x00000001U /*!< LSCO2 index */
+#if defined(RCC_LSCO3_SUPPORT)
#define RCC_LSCO3 0x00000002U /*!< LSCO3 index */
+#endif
/**
* @}
*/
@@ -421,7 +468,9 @@
#define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */
#endif
#define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */
+#if defined(USB)
#define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */
+#endif
#define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */
#define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */
#define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */
@@ -429,6 +478,9 @@
#if defined(RCC_SMPS_SUPPORT)
#define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */
#endif
+#if defined(SPI_I2S_SUPPORT)
+#define RCC_PERIPHCLK_I2S 0x00004000U /*!< I2S Peripheral Clock Selection */
+#endif
/**
* @}
*/
@@ -527,24 +579,30 @@
* @}
*/
+#if defined(USB)
/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
* @{
*/
#define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */
+#if defined(SAI1)
#define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */
+#endif
#define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */
#define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */
/**
* @}
*/
+#endif
/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
* @{
*/
#define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */
-#if defined(SAI1)
+#if defined(STM32WB55xx) || defined (STM32WB5Mxx)
#define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */
+#elif defined(STM32WB35xx)
+#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */
#endif
#define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */
#define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */
@@ -611,6 +669,19 @@
*/
#endif
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_NONE LL_RCC_I2S_CLKSOURCE_NONE /*!< No clock selected as I2S clock */
+#define RCC_I2SCLKSOURCE_PLL LL_RCC_I2S_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S clock source */
+#define RCC_I2SCLKSOURCE_HSI LL_RCC_I2S_CLKSOURCE_HSI /*!< HSI clock selected as I2S clock */
+#define RCC_I2SCLKSOURCE_PIN LL_RCC_I2S_CLKSOURCE_PIN /*!< External clock selected as I2S clock */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
*/
@@ -1068,20 +1139,20 @@
* @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock
* @retval None
*/
-#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
- do { \
- if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \
+#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
+ do { \
+ if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \
|| ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE) \
|| ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48)) \
- { \
+ { \
LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__)); \
- } \
- else \
- { \
+ } \
+ else \
+ { \
uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK); \
- LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \
+ LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \
LL_RCC_SetCLK48ClockSource(tmp); \
- } \
+ } \
} while(0U)
/** @brief Macro to get the direct RNG clock.
@@ -1094,6 +1165,7 @@
*/
#define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)
+#if defined(USB)
/** @brief Macro to configure the USB clock (USBCLK).
*
* @note USB and RNG peripherals share the same 48MHz clock source.
@@ -1116,14 +1188,17 @@
* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)
+#endif
/** @brief Macro to configure the ADC interface clock.
* @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
- * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
+ * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*)
* @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock
* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
+ * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*)
+ * @note (*) Value not defined for all devices
* @retval None
*/
#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__)
@@ -1131,9 +1206,11 @@
/** @brief Macro to get the ADC clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
- * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
+ * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock (*)
* @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock
* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
+ * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock (*)
+ * @note (*) Value not defined for all devices
*/
#define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)
@@ -1217,6 +1294,28 @@
* @{
*/
+#if defined(SPI_I2S_SUPPORT)
+/** @brief Macro to configure the I2S clock (I2SCLK).
+ * @param __I2S_CLKSOURCE__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock
+ * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock
+ * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock
+ * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock
+ * @retval None
+ */
+#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S_CLKSOURCE__)
+
+/** @brief Macro to get the I2S clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock
+ * @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock
+ * @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock
+ * @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE)
+#endif
+
#if defined(SAI1)
/** @brief Enable PLLSAI1RDY interrupt.
* @retval None
diff --git a/Inc/stm32wbxx_hal_tim.h b/Inc/stm32wbxx_hal_tim.h
index ce4b09e..bf05e3b 100644
--- a/Inc/stm32wbxx_hal_tim.h
+++ b/Inc/stm32wbxx_hal_tim.h
@@ -523,6 +523,15 @@
* @}
*/
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+ * @{
+ */
+#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
+/**
+ * @}
+ */
+
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
@@ -1313,6 +1322,31 @@
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+mode.
+ */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+ * @brief Get update interrupt flag (UIF) copy status.
+ * @param __COUNTER__ Counter value.
+ * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+ */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
@@ -1331,6 +1365,8 @@
/**
* @brief Set the TIM Counter Register value on runtime.
+ * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+ * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
@@ -1640,29 +1676,29 @@
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
- ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || \
- ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || \
- ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || \
- ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || \
- ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || \
- ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || \
- ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || \
- ((__BASE__) == TIM_DMABASE_BDTR) || \
- ((__BASE__) == TIM_DMABASE_OR) || \
- ((__BASE__) == TIM_DMABASE_CCMR3) || \
- ((__BASE__) == TIM_DMABASE_CCR5) || \
- ((__BASE__) == TIM_DMABASE_CCR6) || \
- ((__BASE__) == TIM_DMABASE_AF1) || \
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR) || \
+ ((__BASE__) == TIM_DMABASE_OR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR5) || \
+ ((__BASE__) == TIM_DMABASE_CCR6) || \
+ ((__BASE__) == TIM_DMABASE_AF1) || \
((__BASE__) == TIM_DMABASE_AF2))
#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
@@ -1673,6 +1709,9 @@
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+ ((__MODE__) == TIM_UIFREMAP_ENALE))
+
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
diff --git a/Inc/stm32wbxx_ll_adc.h b/Inc/stm32wbxx_ll_adc.h
index e11d35c..4fbb1fd 100644
--- a/Inc/stm32wbxx_ll_adc.h
+++ b/Inc/stm32wbxx_ll_adc.h
@@ -1272,7 +1272,7 @@
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
@@ -1466,7 +1466,7 @@
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
@@ -2340,9 +2340,12 @@
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
- * - Do not use with interruption or DMA since these modes
- * have to clear immediately the EOC flag to free the
- * IRQ vector sequencer.
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@@ -2393,9 +2396,12 @@
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
- * - Do not use with interruption or DMA since these modes
- * have to clear immediately the EOC flag to free the
- * IRQ vector sequencer.
+ * - It is not recommended to use with interruption or DMA
+ * since these modes have to clear immediately the EOC flag
+ * (by CPU to free the IRQ pending event or by DMA).
+ * Auto wait will work but fort a very short time, discarding
+ * its intended benefit (except specific case of high load of CPU
+ * or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
@@ -2549,7 +2555,7 @@
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
@@ -3126,7 +3132,7 @@
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
@@ -3621,7 +3627,7 @@
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (4)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
* @arg @ref LL_ADC_CHANNEL_VBAT (4)
*
diff --git a/Inc/stm32wbxx_ll_comp.h b/Inc/stm32wbxx_ll_comp.h
index 49d720e..4348e8c 100644
--- a/Inc/stm32wbxx_ll_comp.h
+++ b/Inc/stm32wbxx_ll_comp.h
@@ -293,7 +293,7 @@
/**
* @brief Set window mode of a pair of comparators instances
- * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * (2 consecutive COMP instances COMP<x> and COMP<x+1>).
* @rmtoll CSR WINMODE LL_COMP_SetCommonWindowMode
* @param COMPxy_COMMON Comparator common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
@@ -311,7 +311,7 @@
/**
* @brief Get window mode of a pair of comparators instances
- * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * (2 consecutive COMP instances COMP<x> and COMP<x+1>).
* @rmtoll CSR WINMODE LL_COMP_GetCommonWindowMode
* @param COMPxy_COMMON Comparator common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
diff --git a/Inc/stm32wbxx_ll_exti.h b/Inc/stm32wbxx_ll_exti.h
index d2ef804..7f9f596 100644
--- a/Inc/stm32wbxx_ll_exti.h
+++ b/Inc/stm32wbxx_ll_exti.h
@@ -107,16 +107,26 @@
#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
+#endif
#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
+#endif
#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
+#endif
#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
+#endif
+
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \
LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \
LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \
@@ -127,6 +137,16 @@
LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \
LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_28 | \
LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) /*!< All Extended line not reserved*/
+#else
+#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \
+ LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \
+ LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \
+ LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \
+ LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | \
+ LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \
+ LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_22 | \
+ LL_EXTI_LINE_24 | LL_EXTI_LINE_29 | LL_EXTI_LINE_30) /*!< All Extended line not reserved*/
+#endif
#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
@@ -136,14 +156,14 @@
#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */
#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */
-#if defined (STM32WB55xx)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */
#endif
#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */
#define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */
#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */
#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */
-#if defined (STM32WB55xx)
+#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_43 | \
@@ -243,7 +263,7 @@
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
* @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -264,17 +284,18 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
* @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_23 (*)
* @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_25 (*)
+ * @arg @ref LL_EXTI_LINE_28 (*)
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
@@ -285,7 +306,7 @@
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
* @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -306,17 +327,18 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
* @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_23 (*)
* @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_25 (*)
+ * @arg @ref LL_EXTI_LINE_28 (*)
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
@@ -327,7 +349,7 @@
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
* @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
@@ -353,7 +375,7 @@
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
* @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
@@ -379,7 +401,7 @@
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
* @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -400,17 +422,18 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
* @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_23 (*)
* @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_25 (*)
+ * @arg @ref LL_EXTI_LINE_28 (*)
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
@@ -421,7 +444,7 @@
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
* @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -442,17 +465,18 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
* @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_23 (*)
* @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_25 (*)
+ * @arg @ref LL_EXTI_LINE_28 (*)
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
@@ -463,7 +487,7 @@
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
* @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
@@ -489,7 +513,7 @@
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
* @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
@@ -515,7 +539,7 @@
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
* @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -536,17 +560,18 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
* @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_23 (*)
* @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_25 (*)
+ * @arg @ref LL_EXTI_LINE_28 (*)
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
+ * (*) value not defined in all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
@@ -557,7 +582,7 @@
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
* @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -578,17 +603,18 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
* @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_23 (*)
* @arg @ref LL_EXTI_LINE_24
- * @arg @ref LL_EXTI_LINE_25
- * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_25 (*)
+ * @arg @ref LL_EXTI_LINE_28 (*)
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
+ * (*) value not defined in all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
@@ -599,7 +625,7 @@
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
* @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
@@ -625,7 +651,7 @@
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
* @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
@@ -659,7 +685,7 @@
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -679,9 +705,9 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
@@ -692,7 +718,7 @@
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
* @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -712,9 +738,9 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
@@ -728,7 +754,6 @@
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
@@ -742,7 +767,6 @@
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
@@ -753,7 +777,7 @@
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -773,9 +797,8 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
@@ -786,7 +809,7 @@
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
* @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -806,9 +829,9 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
@@ -822,7 +845,7 @@
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
@@ -836,7 +859,6 @@
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
@@ -847,7 +869,7 @@
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -867,9 +889,9 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * (*) value not defined in all devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
@@ -881,7 +903,7 @@
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
* @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
+ * @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
@@ -901,9 +923,9 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * (*) value not defined in all devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
@@ -918,7 +940,6 @@
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
@@ -932,7 +953,6 @@
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
- * @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
@@ -979,9 +999,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
@@ -1000,9 +1021,10 @@
* condition.
* @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
@@ -1041,9 +1063,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
@@ -1063,9 +1086,10 @@
* condition.
* @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
@@ -1097,9 +1121,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
@@ -1111,9 +1136,10 @@
* @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
* @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
@@ -1160,9 +1186,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
@@ -1182,9 +1209,10 @@
* condition.
* @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
@@ -1222,9 +1250,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
@@ -1243,9 +1272,10 @@
* In this case, both generate a trigger condition.
* @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
@@ -1277,9 +1307,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
@@ -1292,7 +1323,7 @@
* @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
* @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @retval State of bit (1 or 0).
@@ -1339,9 +1370,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
@@ -1359,9 +1391,10 @@
* register (by writing a 1 into the bit)
* @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
@@ -1403,9 +1436,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
@@ -1419,9 +1453,10 @@
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
@@ -1455,9 +1490,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
@@ -1471,9 +1507,10 @@
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
@@ -1507,9 +1544,10 @@
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_20 (*)
+ * @arg @ref LL_EXTI_LINE_21 (*)
+ * @arg @ref LL_EXTI_LINE_31 (*)
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
@@ -1523,9 +1561,10 @@
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
+ * (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
diff --git a/Inc/stm32wbxx_ll_lptim.h b/Inc/stm32wbxx_ll_lptim.h
index 5a0e723..fdc820b 100644
--- a/Inc/stm32wbxx_ll_lptim.h
+++ b/Inc/stm32wbxx_ll_lptim.h
@@ -370,7 +370,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@@ -423,7 +423,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
/**
@@ -690,8 +690,7 @@
/**
* @brief Set LPTIM input 1 source (default GPIO).
- * @rmtoll OR OR_0 LL_LPTIM_SetInput1Src
- * @rmtoll OR OR_1 LL_LPTIM_SetInput1Src
+ * @rmtoll OR OR LL_LPTIM_SetInput1Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
@@ -702,12 +701,12 @@
*/
__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
- WRITE_REG(LPTIMx->OR, Src);
+ MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
}
/**
* @brief Set LPTIM input 2 source (default GPIO).
- * @rmtoll OR OR_0 LL_LPTIM_SetInput2Src
+ * @rmtoll OR OR LL_LPTIM_SetInput2Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
@@ -716,7 +715,7 @@
*/
__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
- WRITE_REG(LPTIMx->OR, Src);
+ MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
}
/**
@@ -766,7 +765,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@@ -1035,7 +1034,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@@ -1065,7 +1064,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@@ -1087,7 +1086,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@@ -1109,7 +1108,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@@ -1131,7 +1130,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@@ -1153,7 +1152,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@@ -1175,7 +1174,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@@ -1197,7 +1196,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@@ -1238,7 +1237,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@@ -1271,7 +1270,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@@ -1304,7 +1303,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@@ -1337,7 +1336,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@@ -1366,11 +1365,11 @@
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@@ -1399,11 +1398,11 @@
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@@ -1432,11 +1431,11 @@
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
diff --git a/Inc/stm32wbxx_ll_rcc.h b/Inc/stm32wbxx_ll_rcc.h
index 37cf247..e448827 100644
--- a/Inc/stm32wbxx_ll_rcc.h
+++ b/Inc/stm32wbxx_ll_rcc.h
@@ -124,6 +124,12 @@
#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
#endif /* HSI48_VALUE */
+
+#if defined(SPI_I2S_SUPPORT)
+#if !defined (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+#endif
/**
* @}
*/
@@ -292,7 +298,6 @@
* @}
*/
-
/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
* @{
*/
@@ -377,13 +382,13 @@
* @}
*/
+#if defined(RCC_SMPS_SUPPORT)
/** @defgroup RCC_LL_EC_SMPS_CLKSOURCE SMPS clock switch
* @{
*/
#define LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as SMPS clock */
#define LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0 /*!< MSI selection as SMPS clock */
#define LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1 /*!< HSE selection as SMPS clock */
-
/**
* @}
*/
@@ -395,7 +400,6 @@
#define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */
#define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */
#define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */
-
/**
* @}
*/
@@ -407,13 +411,10 @@
#define LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0 /*!< SMPS clock division 1 */
#define LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1 /*!< SMPS clock division 2 */
#define LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1) /*!< SMPS clock division 3 */
-
/**
* @}
*/
-
-
-
+#endif
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
@@ -437,6 +438,7 @@
* @}
*/
+#if defined(LPUART1)
/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE
* @{
*/
@@ -447,6 +449,7 @@
/**
* @}
*/
+#endif
/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE
* @{
@@ -478,6 +481,7 @@
* @}
*/
+#if defined(SAI1)
/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE
* @{
*/
@@ -488,6 +492,7 @@
/**
* @}
*/
+#endif
/** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE
* @{
@@ -519,8 +524,10 @@
* @{
*/
#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/
-#if defined(SAI1)
+#if defined(STM32WB55xx) || defined (STM32WB5Mxx)
#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/
+#elif defined(STM32WB35xx)
+#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock*/
#endif
#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/
#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/
@@ -538,6 +545,19 @@
* @}
*/
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup RCC_LL_EC_I2SCLKSOURCE Peripheral I2S clock source selection
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as I2S clock*/
+#define LL_RCC_I2S_CLKSOURCE_HSI RCC_CCIPR_I2SSEL_0 /*!< HSI clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2SSEL_1 /*!< PLL clock used as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2SSEL /*!< External clock used as I2S clock source */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup RCC_LL_EC_USART1 USART1
* @{
*/
@@ -587,7 +607,7 @@
/** @defgroup RCC_LL_EC_CLK48 CLK48
* @{
*/
-#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB clock source selection bits */
+#define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< CLK48 clock source selection bits */
/**
* @}
*/
@@ -616,6 +636,16 @@
* @}
*/
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup RCC_LL_EC_I2S I2S
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2SSEL /*!< I2S clock source selection bits */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
@@ -734,6 +764,7 @@
*/
+#if defined(SAI1)
/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ)
* @{
*/
@@ -799,6 +830,7 @@
/**
* @}
*/
+#endif
/**
* @}
@@ -968,6 +1000,60 @@
#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
(((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
+#if defined(SPI_I2S_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+ * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLM__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLM_DIV_1
+ * @arg @ref LL_RCC_PLLM_DIV_2
+ * @arg @ref LL_RCC_PLLM_DIV_3
+ * @arg @ref LL_RCC_PLLM_DIV_4
+ * @arg @ref LL_RCC_PLLM_DIV_5
+ * @arg @ref LL_RCC_PLLM_DIV_6
+ * @arg @ref LL_RCC_PLLM_DIV_7
+ * @arg @ref LL_RCC_PLLM_DIV_8
+ * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86
+ * @param __PLLP__ This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLP_DIV_2
+ * @arg @ref LL_RCC_PLLP_DIV_3
+ * @arg @ref LL_RCC_PLLP_DIV_4
+ * @arg @ref LL_RCC_PLLP_DIV_5
+ * @arg @ref LL_RCC_PLLP_DIV_6
+ * @arg @ref LL_RCC_PLLP_DIV_7
+ * @arg @ref LL_RCC_PLLP_DIV_8
+ * @arg @ref LL_RCC_PLLP_DIV_9
+ * @arg @ref LL_RCC_PLLP_DIV_10
+ * @arg @ref LL_RCC_PLLP_DIV_11
+ * @arg @ref LL_RCC_PLLP_DIV_12
+ * @arg @ref LL_RCC_PLLP_DIV_13
+ * @arg @ref LL_RCC_PLLP_DIV_14
+ * @arg @ref LL_RCC_PLLP_DIV_15
+ * @arg @ref LL_RCC_PLLP_DIV_16
+ * @arg @ref LL_RCC_PLLP_DIV_17
+ * @arg @ref LL_RCC_PLLP_DIV_18
+ * @arg @ref LL_RCC_PLLP_DIV_19
+ * @arg @ref LL_RCC_PLLP_DIV_20
+ * @arg @ref LL_RCC_PLLP_DIV_21
+ * @arg @ref LL_RCC_PLLP_DIV_22
+ * @arg @ref LL_RCC_PLLP_DIV_23
+ * @arg @ref LL_RCC_PLLP_DIV_24
+ * @arg @ref LL_RCC_PLLP_DIV_25
+ * @arg @ref LL_RCC_PLLP_DIV_26
+ * @arg @ref LL_RCC_PLLP_DIV_27
+ * @arg @ref LL_RCC_PLLP_DIV_28
+ * @arg @ref LL_RCC_PLLP_DIV_29
+ * @arg @ref LL_RCC_PLLP_DIV_30
+ * @arg @ref LL_RCC_PLLP_DIV_31
+ * @arg @ref LL_RCC_PLLP_DIV_32
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
+ (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
+#endif
+
/**
* @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
@@ -2580,9 +2666,10 @@
* @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource
* @param CLK48xSource This parameter can be one of the following values:
* @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
- * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
* @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
+ * @note (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)
@@ -2590,6 +2677,7 @@
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource);
}
+#if defined(USB)
/**
* @brief Configure USB clock source
* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
@@ -2604,6 +2692,7 @@
{
LL_RCC_SetCLK48ClockSource(USBxSource);
}
+#endif
/**
* @brief Configure RNG clock source
@@ -2617,10 +2706,10 @@
* @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
* @param CLK48xSource This parameter can be one of the following values:
* @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
- * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
* @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
-
+ * @note (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t CLK48xSource)
@@ -2638,9 +2727,11 @@
* @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
* @param ADCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
+ * @note (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
@@ -2648,6 +2739,23 @@
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
}
+#if defined(SPI_I2S_SUPPORT)
+/**
+ * @brief Configure I2Sx clock source
+ * @rmtoll CCIPR I2SSEL LL_RCC_SetI2SClockSource
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2SSEL, I2SxSource);
+}
+#endif
+
/**
* @brief Get USARTx clock source
* @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource
@@ -2761,16 +2869,18 @@
* @param CLK48x This parameter can be one of the following values:
* @arg @ref LL_RCC_CLK48_CLKSOURCE
* @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
- * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1 (*)
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
+ * @note (*) Value not defined for all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x));
}
+#if defined(USB)
/**
* @brief Get USBx clock source
* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
@@ -2786,6 +2896,7 @@
{
return LL_RCC_GetCLK48ClockSource(USBx);
}
+#endif
/**
* @brief Get ADCx clock source
@@ -2794,15 +2905,34 @@
* @arg @ref LL_RCC_ADC_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
* @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI (*)
+ * @note (*) Value not defined for all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
}
+#if defined(SPI_I2S_SUPPORT)
+/**
+ * @brief Get I2Sx clock source
+ * @rmtoll CCIPR I2SSEL LL_RCC_GetI2SClockSource
+ * @param I2Sx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+ return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
+}
+#endif
/**
* @}
*/
@@ -4403,7 +4533,9 @@
* @{
*/
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+#if defined(RCC_SMPS_SUPPORT)
uint32_t LL_RCC_GetSMPSClockFreq(void);
+#endif
uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
#if defined(LPUART1)
@@ -4415,10 +4547,15 @@
#endif
uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource);
uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+#if defined(USB)
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
uint32_t LL_RCC_GetRTCClockFreq(void);
uint32_t LL_RCC_GetRFWKPClockFreq(void);
+#if defined(SPI_I2S_SUPPORT)
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#endif
/**
* @}
*/
diff --git a/Inc/stm32wbxx_ll_spi.h b/Inc/stm32wbxx_ll_spi.h
index 65ddb0f..9230ff7 100644
--- a/Inc/stm32wbxx_ll_spi.h
+++ b/Inc/stm32wbxx_ll_spi.h
@@ -1405,6 +1405,872 @@
* @}
*/
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup I2S_LL I2S
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_LL_EC_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+ Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+ and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2S_ReadReg function
+ * @{
+ */
+#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
+#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
+#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+ * @{
+ */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
+#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+ * @{
+ */
+#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
+#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
+#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
+#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
+#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+ * @{
+ */
+#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @{
+ */
+#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @{
+ */
+
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Select I2S mode and Enable I2S peripheral
+ * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
+ * I2SCFGR I2SE LL_I2S_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Disable I2S peripheral
+ * @rmtoll I2SCFGR I2SE LL_I2S_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Check if I2S peripheral is enabled
+ * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_SetDataFormat
+ * @param SPIx SPI Instance
+ * @param DataFormat This parameter can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+ * @brief Get I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_GetDataFormat
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+ * @brief Set I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+ * @brief Get I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+ * @brief Set I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+ * @brief Get I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+ * @brief Set I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+ * @brief Get I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+ * @brief Set I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+ * @brief Get I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+ * @brief Set I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
+ * @param SPIx SPI Instance
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+ * @brief Get I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+ * @brief Enable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Disable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Check if the master clock ouput (Pin MCK) is enabled
+ * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
+}
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+/**
+ * @brief Enable asynchronous start
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+ * @brief Disable asynchronous start
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+}
+
+/**
+ * @brief Check if asynchronous start is enabled
+ * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
+}
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+ * @brief Get busy flag
+ * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Get underrun error flag
+ * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+ * @brief Get channel side flag.
+ * @note 0: Channel Left has to be transmitted or has been received\n
+ * 1: Channel Right has to be transmitted or has been received\n
+ * It has no significance in PCM mode.
+ * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+ return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Clear underrun error flag
+ * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Enable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Enable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Disable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Disable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Disable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Check if ERR IT is enabled
+ * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+ * @brief Check if RXNE IT is enabled
+ * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if TXE IT is enabled
+ * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+ * @brief Write 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
#endif /* defined (SPI1) || defined (SPI2) */
/**
diff --git a/Inc/stm32wbxx_ll_system.h b/Inc/stm32wbxx_ll_system.h
index 89bacd0..fa349bc 100644
--- a/Inc/stm32wbxx_ll_system.h
+++ b/Inc/stm32wbxx_ll_system.h
@@ -58,6 +58,16 @@
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
* @{
*/
+/**
+ * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
+ */
+#define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0,
+ VREF_SC0 in STM32WB datasheet */
+#define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1,
+ VREF_SC1 in STM32WB datasheet */
+/**
+ * @}
+ */
/**
* @}
@@ -1877,6 +1887,24 @@
}
/**
+ * @brief Get the VREFBUF trimming value for VRS=0 (VREF_SC0)
+ * @retval Between 0 and 0x3F
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_SC0_GetCalibration(void)
+{
+ return (uint32_t)(*VREFBUF_SC0_CAL_ADDR);
+}
+
+/**
+ * @brief Get the VREFBUF trimming value for VRS=1 (VREF_SC1)
+ * @retval Between 0 and 0x3F
+ */
+__STATIC_INLINE uint32_t LL_VREFBUF_SC1_GetCalibration(void)
+{
+ return (uint32_t)(*VREFBUF_SC1_CAL_ADDR);
+}
+
+/**
* @brief Check if Voltage reference buffer is ready
* @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
* @retval State of bit (1 or 0).
@@ -1898,6 +1926,11 @@
/**
* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
+ * @note Each VrefBuf voltage scale is calibrated in production for each device,
+ * data stored in flash memory.
+ * Functions @ref LL_VREFBUF_SC0_GetCalibration and
+ * @ref LL_VREFBUF_SC0_GetCalibration can be used to retrieve
+ * these calibration data.
* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
* @param Value Between 0 and 0x3F
* @retval None
diff --git a/Inc/stm32wbxx_ll_tim.h b/Inc/stm32wbxx_ll_tim.h
index f7d2fc5..05256d9 100644
--- a/Inc/stm32wbxx_ll_tim.h
+++ b/Inc/stm32wbxx_ll_tim.h
@@ -120,30 +120,9 @@
#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
/* Generic bit definitions for TIMx_AF1 register */
-#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */
-#if defined(COMP1) && defined(COMP2)
-#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */
-#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */
-#endif /* COMP1 && COMP2 */
#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
-#if defined(COMP1) && defined(COMP2)
-#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */
-#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */
-#endif /* COMP1 && COMP2 */
#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
-/* Generic bit definitions for TIMx_AF2 register */
-#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */
-#if defined(COMP1) && defined(COMP2)
-#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */
-#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */
-#endif /* COMP1 && COMP2 */
-#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */
-#if defined(COMP1) && defined(COMP2)
-#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */
-#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */
-#endif /* COMP1 && COMP2 */
-
/* Remap mask definitions */
#define TIMx_OR_RMP_SHIFT 16U
#define TIMx_OR_RMP_MASK 0x0000FFFFU
@@ -252,13 +231,14 @@
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
@@ -1141,7 +1121,7 @@
/** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap
* @{
*/
-#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
+#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
/**
* @}
@@ -1681,7 +1661,7 @@
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
@@ -1726,6 +1706,16 @@
}
/**
+ * @brief Indicate whether update interrupt flag (UIF) copy is set.
+ * @param Counter Counter value
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+{
+ return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
* @}
*/
@@ -3295,8 +3285,8 @@
* @brief Select the external trigger (ETR) input source.
* @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports ETR source selection.
- * @note When this function is called with LL_TIM_ETRSOURCE_GPIO,
- * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or
+ * @note When this function is called with LL_TIM_ETRSOURCE_GPIO,
+ * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or
* LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping
* capability configured through the function @ref LL_TIM_SetRemap().
* @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
@@ -3715,7 +3705,7 @@
* TIM2_OR TI4_RMP LL_TIM_SetRemap\n
* TIM2_OR TI1_RMP LL_TIM_SetRemap\n
* TIM16_OR TI1_RMP LL_TIM_SetRemap\n
- * TIM17_OR TI1_RMP LL_TIM_SetRemap\n
+ * TIM17_OR TI1_RMP LL_TIM_SetRemap
* @param TIMx Timer instance
* @param Remap Remap param depends on the TIMx. Description available only
* in CHM version of the User Manual (not in .pdf).
diff --git a/README.md b/README.md
index a8437c1..d12c0a3 100644
--- a/README.md
+++ b/README.md
@@ -34,10 +34,13 @@
HAL Driver WB | CMSIS Device WB | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
-Tag v1.1.0 | Tag v1.1.0 | Tag v4.5_cm4 | Tag v1.1.0 (and following, if any, till next new tag)
-Tag v1.2.0 | Tag v1.2.0 | Tag v5.4.0_cm4 | Tag v1.2.0 (and following, if any, till next new tag)
-Tag v1.3.0 | Tag v1.3.0 | Tag v5.4.0_cm4 | Tag v1.3.0 (and following, if any, till next new tag)
-Tag v1.4.0 | Tag v1.4.0 | Tag v5.4.0_cm4 | Tag v1.4.0 (and following, if any, till next new tag)
+Tag v1.1.0 | Tag v1.1.0 | Tag v4.5_cm4 | Tag v1.1.0 (and following, if any, till next tag)
+Tag v1.2.0 | Tag v1.2.0 | Tag v5.4.0_cm4 | Tag v1.2.0 (and following, if any, till next tag)
+Tag v1.3.0 | Tag v1.3.0 | Tag v5.4.0_cm4 | Tag v1.3.0 (and following, if any, till next tag)
+Tag v1.4.0 | Tag v1.3.0 | Tag v5.4.0_cm4 | Tag v1.4.0 (and following, if any, till next tag)
+Tag v1.5.0 | Tag v1.4.0 | Tag v5.4.0_cm4 | Tag v1.5.0 (and following, if any, till next tag)
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32wbxx_hal_driver/blob/master/Release_Notes.html).
The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB).
diff --git a/Release_Notes.html b/Release_Notes.html
index b1fbd9f..73eb139 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -46,9 +46,65 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section5" checked aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-November-2019</label>
+<input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.5.0 / 12-February-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
+<h3 id="introduction-of-stm32wb5m-stm32wb35xx-and-stm32wb30xx-product">Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product</h3>
+<p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
+<p>Added features:</p>
+<ul>
+<li>Introduction of I2S peripheral support. This only apply to STM32WB35xx.</li>
+</ul>
+<table>
+<thead>
+<tr class="header">
+<th>Peripheral</th>
+<th style="text-align: left;">Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td>HAL/LL</td>
+<td style="text-align: left;">VREFBUF trimming calibration must be written by software</td>
+</tr>
+<tr class="even">
+<td>HAL</td>
+<td style="text-align: left;">HAL_SetTickFreq() should update frequency on Systick_LOAD register and uwTickFreq correctly</td>
+</tr>
+<tr class="odd">
+<td>GPIO</td>
+<td style="text-align: left;">LL_GPIO_Init() generate undesired pulse</td>
+</tr>
+<tr class="even">
+<td>I2C</td>
+<td style="text-align: left;">HardFault in I2C_DMAXferCplt</td>
+</tr>
+<tr class="odd">
+<td>I2C</td>
+<td style="text-align: left;">Incorrectly enable interrupts in I2C_Enable_IRQ routine when InterruptRequest = I2C_XFER_CPLT_IT</td>
+</tr>
+<tr class="even">
+<td>RCC</td>
+<td style="text-align: left;">Cannot enable PLL if PLL OFF with identical PLL config</td>
+</tr>
+<tr class="odd">
+<td>RCC</td>
+<td style="text-align: left;">Clock reconfiguration issues once PLLSAI used</td>
+</tr>
+<tr class="even">
+<td>I2S</td>
+<td style="text-align: left;">Add peripheral for STM32WB35xx</td>
+</tr>
+</tbody>
+</table>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-December-2019</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
<h3 id="maitenance-release">Maitenance release</h3>
<table>
<thead>
@@ -92,7 +148,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -102,7 +158,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="maitenance-release-1">Maitenance release</h3>
<table>
<thead>
@@ -174,7 +230,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-1">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -184,7 +240,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3>
<p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p>
<table>
@@ -253,7 +309,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-2">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -263,7 +319,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p>
<table>
@@ -317,7 +373,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-3">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -327,7 +383,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p>
</div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c
index 4432f0b..a778bff 100644
--- a/Src/stm32wbxx_hal.c
+++ b/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
* @brief STM32WBxx HAL Driver version number
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32WBxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
+#define __STM32WBxx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
@@ -79,7 +79,7 @@
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
-uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
@@ -346,17 +346,29 @@
* @brief Set new tick Freq.
* @retval Status
*/
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
+ HAL_TickFreqTypeDef prevTickFreq;
+
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
+
+ if (status != HAL_OK)
+ {
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
+ }
}
return status;
@@ -366,7 +378,7 @@
* @brief Return tick frequency.
* @retval tick period in Hz
*/
-uint32_t HAL_GetTickFreq(void)
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
@@ -626,14 +638,31 @@
* This requires VDDA equal to or higher than 2.4 V.
* @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
+ * @note Retrieve the TrimmingValue from factory located at
+ * VREFBUF_SC0_CAL_ADDR or VREFBUF_SC1_CAL_ADDR addresses.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
{
+ uint32_t TrimmingValue;
+
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
LL_VREFBUF_SetVoltageScaling(VoltageScaling);
+
+ /* Restrieve Calibration data and store them into trimming field */
+ if (VoltageScaling == SYSCFG_VREFBUF_VOLTAGE_SCALE0)
+ {
+ TrimmingValue = ((uint32_t) *VREFBUF_SC0_CAL_ADDR) & 0x3FU;
+ }
+ else
+ {
+ TrimmingValue = ((uint32_t) *VREFBUF_SC1_CAL_ADDR) & 0x3FU;
+ }
+ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+ HAL_SYSCFG_VREFBUF_TrimmingConfig(TrimmingValue);
}
/**
@@ -655,6 +684,12 @@
/**
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
+ * @note Each VrefBuf voltage scale is calibrated in production for each device,
+ * data stored in flash memory.
+ * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and
+ * applies this calibration data as trimming value at each scale change.
+ * Therefore, optionally, function @ref HAL_SYSCFG_VREFBUF_TrimmingConfig
+ * can be used in a second time to fine tune the trimming.
* @param TrimmingValue specifies trimming code for VREFBUF calibration
* This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
* @retval None
diff --git a/Src/stm32wbxx_hal_flash.c b/Src/stm32wbxx_hal_flash.c
index ab3de96..57db37d 100644
--- a/Src/stm32wbxx_hal_flash.c
+++ b/Src/stm32wbxx_hal_flash.c
@@ -315,9 +315,9 @@
/* return adress being programmed */
param = pFlash.Address;
}
- else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U)
+ else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_PAGES)) != 0U)
{
- /* return page number being erased (0 for mass erase) */
+ /* return page number being erased */
param = pFlash.Page;
}
else
@@ -389,7 +389,6 @@
/**
* @brief FLASH end of operation interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase: 0
* Page Erase: Page which has been erased
* Program: Address which was selected for data program
* @retval None
@@ -407,7 +406,6 @@
/**
* @brief FLASH operation error interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase: 0
* Page Erase: Page number which returned an error
* Program: Address which was selected for data program
* @retval None
diff --git a/Src/stm32wbxx_hal_flash_ex.c b/Src/stm32wbxx_hal_flash_ex.c
index 14976bb..ce93882 100644
--- a/Src/stm32wbxx_hal_flash_ex.c
+++ b/Src/stm32wbxx_hal_flash_ex.c
@@ -98,7 +98,6 @@
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
* @{
*/
-static void FLASH_MassErase(void);
static void FLASH_AcknowledgePageErase(void);
static void FLASH_FlushCaches(void);
static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
@@ -139,7 +138,7 @@
* @{
*/
/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages.
+ * @brief Perform an erase of the specified FLASH memory pages.
* @note Before any operation, it is possible to check there is no operation suspended
* by call HAL_FLASHEx_IsOperationSuspended()
* @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
@@ -168,17 +167,7 @@
if (status == HAL_OK)
{
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /* Mass erase to be done */
- FLASH_MassErase();
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-
- /* If operation is completed or interrupted, no need to clear the Mass Erase Bit */
- }
- else
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES)
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
@@ -214,7 +203,7 @@
}
/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
+ * @brief Perform an erase of the specified FLASH memory pages with interrupt enabled.
* @note Before any operation, it is possible to check there is no operation suspended
* by call HAL_FLASHEx_IsOperationSuspended()
* @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that
@@ -250,15 +239,7 @@
/* Enable End of Operation and Error interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
- if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
- {
- /* Set Page to 0 for Interrupt callback managment */
- pFlash.Page = 0;
-
- /* Proceed to Mass Erase */
- FLASH_MassErase();
- }
- else
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_PAGES)
{
/* Erase by page to be done */
pFlash.NbPagesToErase = pEraseInit->NbPages;
@@ -514,16 +495,6 @@
*/
/**
- * @brief Mass erase of FLASH memory.
- * @retval None
- */
-static void FLASH_MassErase(void)
-{
- /* Set the Mass Erase Bit and start bit */
- SET_BIT(FLASH->CR, (FLASH_CR_MER | FLASH_CR_STRT));
-}
-
-/**
* @brief Erase the specified FLASH memory page.
* @param Page FLASH page to erase
* This parameter must be a value between 0 and (max number of pages in Flash - 1)
diff --git a/Src/stm32wbxx_hal_gpio.c b/Src/stm32wbxx_hal_gpio.c
index 078809e..852e018 100644
--- a/Src/stm32wbxx_hal_gpio.c
+++ b/Src/stm32wbxx_hal_gpio.c
@@ -188,26 +188,6 @@
if (iocurrent != 0x00u)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3u];
- temp &= ~(0xFu << ((position & 0x07u) * 4u));
- temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
- GPIOx->AFR[position >> 3u] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
- GPIOx->MODER = temp;
-
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@@ -233,6 +213,26 @@
temp |= ((GPIO_Init->Pull) << (position * 2u));
GPIOx->PUPDR = temp;
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3u];
+ temp &= ~(0xFu << ((position & 0x07u) * 4u));
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
+ GPIOx->AFR[position >> 3u] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
+ GPIOx->MODER = temp;
+
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@@ -314,9 +314,6 @@
tmp &= (0x0FUL << (4u * (position & 0x03u)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
{
- tmp = 0x0FuL << (4u * (position & 0x03u));
- SYSCFG->EXTICR[position >> 2u] &= ~tmp;
-
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
@@ -324,6 +321,9 @@
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
+
+ tmp = 0x0FuL << (4u * (position & 0x03u));
+ SYSCFG->EXTICR[position >> 2u] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@@ -333,14 +333,14 @@
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
}
position++;
diff --git a/Src/stm32wbxx_hal_i2c.c b/Src/stm32wbxx_hal_i2c.c
index 58a01f0..c047cd0 100644
--- a/Src/stm32wbxx_hal_i2c.c
+++ b/Src/stm32wbxx_hal_i2c.c
@@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (0x00000001U)
-#define I2C_XFER_RX_IT (0x00000002U)
-#define I2C_XFER_LISTEN_IT (0x00000004U)
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
-#define I2C_XFER_ERROR_IT (0x00000011U)
-#define I2C_XFER_CPLT_IT (0x00000012U)
-#define I2C_XFER_RELOAD_IT (0x00000012U)
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -410,6 +410,9 @@
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@@ -4251,9 +4254,21 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@@ -5001,6 +5016,7 @@
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
+ HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
@@ -5079,8 +5095,24 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hi2c->State;
+
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@@ -5369,9 +5401,27 @@
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@@ -5426,19 +5476,36 @@
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ __IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -5447,12 +5514,17 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ /* Fetch Last receive data if any */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmpreg = (uint8_t)hi2c->Instance->RXDR;
+ UNUSED(tmpreg);
+ }
+
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@@ -5466,6 +5538,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5500,6 +5573,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5546,12 +5620,26 @@
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -5565,6 +5653,9 @@
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@@ -5572,6 +5663,9 @@
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@@ -5608,7 +5702,6 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -5631,6 +5724,7 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5646,6 +5740,7 @@
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5660,6 +5755,7 @@
else
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5733,6 +5829,7 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -5752,7 +5849,6 @@
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@@ -5767,16 +5863,19 @@
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ tmppreviousstate = hi2c->PreviousState;
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
- if (hi2c->hdmatx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5792,13 +5891,20 @@
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
/* Abort DMA RX transfer if any */
- else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
- if (hi2c->hdmarx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5814,10 +5920,28 @@
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
- else if (hi2c->State == HAL_I2C_STATE_ABORT)
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Error callback treatment.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5831,6 +5955,8 @@
}
else
{
+ hi2c->PreviousState = I2C_STATE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -6041,30 +6167,16 @@
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if (hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->hdmatx != NULL)
{
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AbortCpltCallback(hi2c);
-#else
- HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmatx->XferAbortCallback = NULL;
}
- else
+ if (hi2c->hdmarx != NULL)
{
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ErrorCallback(hi2c);
-#else
- HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmarx->XferAbortCallback = NULL;
}
+
+ I2C_TreatErrorCallback(hi2c);
}
/**
@@ -6341,19 +6453,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -6379,7 +6491,7 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@@ -6433,19 +6545,19 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
diff --git a/Src/stm32wbxx_hal_i2s.c b/Src/stm32wbxx_hal_i2s.c
new file mode 100644
index 0000000..22a0782
--- /dev/null
+++ b/Src/stm32wbxx_hal_i2s.c
@@ -0,0 +1,1802 @@
+/**
+ ******************************************************************************
+ * @file stm32wbxx_hal_i2s.c
+ * @author MCD Application Team
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The I2S HAL driver can be used as follow:
+
+ (#) Declare a I2S_HandleTypeDef handle structure.
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+ (##) Enable the SPIx interface clock.
+ (##) I2S pins configuration:
+ (+++) Enable the clock for the I2S GPIOs.
+ (+++) Configure these I2S pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+ and HAL_I2S_Receive_IT() APIs).
+ (+++) Configure the I2Sx interrupt priority.
+ (+++) Enable the NVIC I2S IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+ and HAL_I2S_Receive_DMA() APIs:
+ (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream/Channel.
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Stream/Channel.
+
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+ using HAL_I2S_Init() function.
+
+ -@- The specific I2S interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+ -@- Make sure that either:
+ (+@) PLLPCLK output is configured or
+ (+@) HSI is enabled or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32wbxx_hal_conf.h file.
+
+ (#) Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ *** I2S HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of most used macros in I2S HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+ [..]
+ (@) You can refer to the I2S HAL driver header file for more useful macros
+
+ *** I2S HAL driver macros list ***
+ ===================================
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_I2S_RegisterCallback() allows to register following callbacks:
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+
+ [..]
+ By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
+ or HAL_I2S_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal.h"
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup STM32WBxx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2S I2S
+ * @brief I2S HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx peripheral.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t i2sdiv;
+ uint32_t i2sodd;
+ uint32_t packetlength;
+ uint32_t tmp;
+ uint32_t i2sclk = 0U;
+
+ /* Check the I2S handle allocation */
+ if (hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+
+ if (hi2s->State == HAL_I2S_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ /* Init the I2S Callback settings */
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hi2s->MspInitCallback == NULL)
+ {
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hi2s->MspInitCallback(hi2s);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ hi2s->Instance->I2SPR = 0x0002U;
+
+ /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing) ********************/
+ if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 16U;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 32U;
+ }
+
+ /* I2S standard */
+ if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
+ {
+ /* In I2S standard packet lenght is multiplied by 2 */
+ packetlength = packetlength * 2U;
+ }
+
+ /* Get the source clock value: based on System Clock value */
+ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+ else
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint32_t)(tmp & (uint32_t)1U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint32_t)(i2sodd << 8U);
+ }
+ else
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+ return HAL_ERROR;
+ }
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ /* And configure the I2S with the I2S_InitStruct values */
+ MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
+ (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
+ hi2s->Init.Standard | hi2s->Init.DataFormat | \
+ hi2s->Init.CPOL));
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
+ {
+ /* Write to SPIx I2SCFGR */
+ SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+ }
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the I2S peripheral
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Check the I2S handle allocation */
+ if (hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* Disable the I2S Peripheral Clock */
+ __HAL_I2S_DISABLE(hi2s);
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ if (hi2s->MspDeInitCallback == NULL)
+ {
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hi2s->MspDeInitCallback(hi2s);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_I2S_MspDeInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2S MSP Init
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S MSP DeInit
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User I2S Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2S Callback
+ * I2S callback is redirected to the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_Transmit()
+ (++) HAL_I2S_Receive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2S_Transmit_IT()
+ (++) HAL_I2S_Receive_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2S_Transmit_DMA()
+ (++) HAL_I2S_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2S_TxCpltCallback()
+ (++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR;
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ while (hi2s->TxXferCount > 0U)
+ {
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if an underrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+ }
+
+ /* Check if Slave mode is selected */
+ if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+ {
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Receive data */
+ while (hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
+ hi2s->RxXferCount--;
+
+ /* Check if an overrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Enable RXNE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
+ (uint32_t)hi2s->pTxBuffPtr,
+ (uint32_t)&hi2s->Instance->DR,
+ hi2s->TxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Tx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
+ hi2s->RxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Rx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
+}
+
+/**
+ * @brief Pauses the audio DMA Stream/Channel playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio DMA Stream/Channel playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the audio DMA Stream/Channel playing from the Media.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ */
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
+ {
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ uint32_t itsource = hi2s->Instance->CR2;
+ uint32_t itflag = hi2s->Instance->SR;
+
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
+ (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ return;
+ }
+
+ /* I2S in mode Tramitter -----------------------------------------------*/
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ return;
+ }
+
+ /* I2S interrupt error -------------------------------------------------*/
+ if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
+ {
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Tx Transfer Half completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S error callbacks
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2S state
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL state
+ */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->State;
+}
+
+/**
+ * @brief Return the I2S error code
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Error Code
+ */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ hi2s->TxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
+ HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S transmit process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Call user Tx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxHalfCpltCallback(hi2s);
+#else
+ HAL_I2S_TxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
+ {
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
+ HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Call user Rx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxHalfCpltCallback(hi2s);
+#else
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Disable Rx and Tx DMA Request */
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
+ HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
+
+ if (hi2s->TxXferCount == 0U)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
+ HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Receive data */
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
+ hi2s->RxXferCount--;
+
+ if (hi2s->RxXferCount == 0U)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
+ HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set to status*/
+ while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32wbxx_hal_irda.c b/Src/stm32wbxx_hal_irda.c
index 6768dcf..58aee4d 100644
--- a/Src/stm32wbxx_hal_irda.c
+++ b/Src/stm32wbxx_hal_irda.c
@@ -113,8 +113,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
- Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_IRDA_RegisterCallback() to register a user callback.
+ Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
@@ -129,9 +129,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
@@ -146,13 +146,13 @@
(+) MspDeInitCallback : IRDA MspDeInit.
[..]
- By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+ examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
- and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
+ and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -161,8 +161,8 @@
in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
- or @ref HAL_IRDA_Init() function.
+ using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
+ or HAL_IRDA_Init() function.
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
@@ -753,28 +753,28 @@
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_IRDA_Abort()
- (+) HAL_IRDA_AbortTransmit()
- (+) HAL_IRDA_AbortReceive()
- (+) HAL_IRDA_Abort_IT()
- (+) HAL_IRDA_AbortTransmit_IT()
- (+) HAL_IRDA_AbortReceive_IT()
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_IRDA_AbortCpltCallback()
- (+) HAL_IRDA_AbortTransmitCpltCallback()
- (+) HAL_IRDA_AbortReceiveCpltCallback()
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
diff --git a/Src/stm32wbxx_hal_lptim.c b/Src/stm32wbxx_hal_lptim.c
index 873f963..df3c8bf 100644
--- a/Src/stm32wbxx_hal_lptim.c
+++ b/Src/stm32wbxx_hal_lptim.c
@@ -174,7 +174,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
/** @addtogroup LPTIM_Private_Constants
* @{
*/
@@ -183,6 +182,25 @@
* @}
*/
+/* Private macro -------------------------------------------------------------*/
+/** @addtogroup LPTIM_Private_Macros
+ * @{
+ */
+#if defined(LPTIM2)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \
+ (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
+
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \
+ (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())
+#else
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()
+
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()
+#endif /* LPTIM2 */
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
@@ -235,16 +253,19 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@@ -278,13 +299,17 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
}
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
@@ -298,18 +323,28 @@
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ /* Glitch filters for internal triggers and external inputs are configured
+ * only if an internal clock source is provided to the LPTIM
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ /* Configure the active edge or edges used by the counter only if LPTIM is
+ * clocked by an external clock source
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ }
+
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge |
- hlptim->Init.Trigger.SampleTime);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge);
}
/* Write to LPTIMx CFGR */
@@ -1438,6 +1473,9 @@
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+ /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
+
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
@@ -1505,6 +1543,9 @@
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+ /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -1620,6 +1661,9 @@
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+ /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
+
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
@@ -1684,6 +1728,9 @@
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+ /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
+ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -2304,17 +2351,17 @@
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
- do
+ do
+ {
+ count--;
+ if (count == 0UL)
{
- count--;
- if (count == 0UL)
- {
- result = HAL_TIMEOUT;
- }
+ result = HAL_TIMEOUT;
}
- while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+ }
+ while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
- return result;
+ return result;
}
/**
@@ -2341,16 +2388,16 @@
/* Save LPTIM source clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
- break;
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
#if defined(LPTIM2)
- case LPTIM2_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
- break;
+ case LPTIM2_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
+ break;
#endif /* LPTIM2 */
- default:
- break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -2363,18 +2410,18 @@
/*********** Reset LPTIM ***********/
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_FORCE_RESET();
- __HAL_RCC_LPTIM1_RELEASE_RESET();
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
#if defined(LPTIM2)
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_FORCE_RESET();
- __HAL_RCC_LPTIM2_RELEASE_RESET();
- break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_FORCE_RESET();
+ __HAL_RCC_LPTIM2_RELEASE_RESET();
+ break;
#endif /* LPTIM2 */
- default:
- break;
+ default:
+ break;
}
/*********** Restore LPTIM Config ***********/
@@ -2383,16 +2430,16 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
+ break;
#if defined(LPTIM2)
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1);
- break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1);
+ break;
#endif /* LPTIM2 */
- default:
- break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -2427,16 +2474,16 @@
/* Restore LPTIM source kernel clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
#if defined(LPTIM2)
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
- break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
+ break;
#endif /* LPTIM2 */
- default:
- break;
+ default:
+ break;
}
}
diff --git a/Src/stm32wbxx_hal_pka.c b/Src/stm32wbxx_hal_pka.c
index cf93e7c..f4ef207 100644
--- a/Src/stm32wbxx_hal_pka.c
+++ b/Src/stm32wbxx_hal_pka.c
@@ -1770,46 +1770,7 @@
{
uint32_t position;
-#if defined(CORE_CM0PLUS)
- if (msb > 0x7FU)
- {
- position = 8UL;
- }
- else if (msb > 0x3FU)
- {
- position = 7UL;
- }
- else if (msb > 0x1FU)
- {
- position = 6UL;
- }
- else if (msb > 0x0FU)
- {
- position = 5UL;
- }
- else if (msb > 0x07U)
- {
- position = 4UL;
- }
- else if (msb > 0x03U)
- {
- position = 3UL;
- }
- else if (msb > 0x01U)
- {
- position = 2UL;
- }
- else if (msb > 0x00U)
- {
- position = 1UL;
- }
- else
- {
- position = 0UL;
- }
-#else
position = 32UL - __CLZ(msb);
-#endif
return (((byteNumber - 1UL) * 8UL) + position);
}
diff --git a/Src/stm32wbxx_hal_rcc.c b/Src/stm32wbxx_hal_rcc.c
index c6f2c02..79a4d41 100644
--- a/Src/stm32wbxx_hal_rcc.c
+++ b/Src/stm32wbxx_hal_rcc.c
@@ -76,7 +76,9 @@
#define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */
#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#if defined(SAI1)
#define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#endif
#define PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
@@ -272,6 +274,9 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
+ /* MSI PLL OFF */
+ LL_RCC_MSI_DisablePLLMode();
+
/* Set MSION bit */
LL_RCC_MSI_Enable();
@@ -378,6 +383,7 @@
* @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
+ * @note The PLL source is not updated when used as PLLSAI1 clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@@ -860,66 +866,126 @@
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
+ if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
{
- /* Check if the PLL is used as system clock or not */
- if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ const uint32_t temp_pllconfig = RCC->PLLCFGR;
+
+ /* PLL On ? */
+ if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
{
- if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+ /* Do nothing if PLL configuration is unchanged */
+ if ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+ ((READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
+ (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
+ (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
+ (READ_BIT(temp_pllconfig, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
{
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
- assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
- assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while (LL_RCC_PLL_IsReady() != 0U)
+ /* Check if the PLL is used as system clock or not */
+ if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+#if defined(SAI1)
+ /* Check if main PLL can be updated */
+ /* Not possible if the source is shared by other enabled PLLSAIx */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
+
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
+ }
+ else
+#endif
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, multiplication and division factors. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ,
+ RCC_OscInitStruct->PLL.PLLR);
+
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Enable PLL System Clock output. */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
}
}
-
- /* Configure the main PLL clock source, multiplication and division factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ,
- RCC_OscInitStruct->PLL.PLLR);
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Enable PLL System Clock output. */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while (LL_RCC_PLL_IsReady() == 0U)
+ else
{
- if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ /* PLL is already used as System core clock */
+ return HAL_ERROR;
}
}
else
{
+ /* PLL configuration is unchanged */
+ /* Re-enable PLL if it was disabled (ie. low power mode) */
+ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+ {
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Enable PLL System Clock output. */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
+ {
+ if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Check that PLL is not used as system clock or not */
+ if (temp_sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
+
/* Disable all PLL outputs to save power */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE);
@@ -932,9 +998,9 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till PLL is disabled */
- while (LL_RCC_PLL_IsReady() != 0U)
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
@@ -942,28 +1008,10 @@
}
}
}
- }
- else
- {
- /* Check if there is a request to disable the PLL used as System clock source */
- if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- {
- return HAL_ERROR;
- }
else
{
- /* Do not return HAL_ERROR if request repeats the current configuration */
- uint32_t pllcfgr = RCC->PLLCFGR;
-
- if ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
- ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
- (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
- (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
- (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
- {
- return HAL_ERROR;
- }
+ /* PLL is already used as System core clock */
+ return HAL_ERROR;
}
}
}
@@ -1302,7 +1350,8 @@
HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
}
- else
+#if defined(RCC_MCO3_SUPPORT)
+ else if (RCC_MCOx == RCC_MCO3)
{
/* MCO3 Clock Enable */
__MCO3_CLK_ENABLE();
@@ -1311,6 +1360,11 @@
GPIO_InitStruct.Alternate = GPIO_AF6_MCO;
HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct);
}
+#endif
+ else
+ {
+ ;
+ }
/* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv);
diff --git a/Src/stm32wbxx_hal_rcc_ex.c b/Src/stm32wbxx_hal_rcc_ex.c
index 968e90f..49d4943 100644
--- a/Src/stm32wbxx_hal_rcc_ex.c
+++ b/Src/stm32wbxx_hal_rcc_ex.c
@@ -42,7 +42,9 @@
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
* @{
*/
+#if defined(SAI1)
#define PLLSAI1_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#endif
#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
#define CLOCKSMPS_TIMEOUT_VALUE (5000U) /* 5 s */
@@ -55,9 +57,11 @@
#define LSCO2_GPIO_PORT GPIOH
#define LSCO2_PIN GPIO_PIN_3
+#if defined(RCC_LSCO3_SUPPORT)
#define __LSCO3_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define LSCO3_GPIO_PORT GPIOC
#define LSCO3_PIN GPIO_PIN_12
+#endif
#define LSI2_TIMEOUT_VALUE (3U) /* to be adjusted with DS */
@@ -128,16 +132,14 @@
* @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
* @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
* @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
- *
* @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
* @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
- *
* @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
- *
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
*
*
* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
@@ -170,12 +172,13 @@
/* SAI1 clock source config set later after clock selection check */
break;
+#if defined(SAI1)
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1 */
/* PLLSAI1 parameters N & P configuration and clock output (PLLSAI1ClockOut) */
ret = RCCEx_PLLSAI1_ConfigNP(&(PeriphClkInit->PLLSAI1));
/* SAI1 clock source config set later after clock selection check */
break;
-
+#endif
case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
/* SAI1 clock source config set later after clock selection check */
@@ -325,6 +328,7 @@
}
#endif
+#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
{
@@ -336,21 +340,21 @@
/* Enable PLLQ output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK);
}
-
#if defined(SAI1)
- if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
- {
- /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
+ if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
+ {
+ /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
+ ret = RCCEx_PLLSAI1_ConfigNQ(&(PeriphClkInit->PLLSAI1));
- if (ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
+ if (ret != HAL_OK)
+ {
+ /* set overall return value */
+ status = ret;
}
+ }
#endif
}
+#endif
/*-------------------------- RNG clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
@@ -384,17 +388,17 @@
}
#if defined(SAI1)
- if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
- {
- /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
- ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1));
+ if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
+ {
+ /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
+ ret = RCCEx_PLLSAI1_ConfigNR(&(PeriphClkInit->PLLSAI1));
- if (ret != HAL_OK)
- {
- /* set overall return value */
- status = ret;
- }
+ if (ret != HAL_OK)
+ {
+ /* set overall return value */
+ status = ret;
}
+ }
#endif
}
@@ -425,6 +429,24 @@
}
#endif
+#if defined(SPI_I2S_SUPPORT)
+ /*-------------------- I2S clock source configuration ----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+ /* Configure the I2S clock source */
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+
+ if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
+ {
+ /* Enable RCC_PLL_I2SCLK output */
+ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2SCLK);
+ }
+ }
+#endif
+
return status;
}
@@ -434,7 +456,7 @@
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals
* clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1,
- * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS).
+ * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS, I2S).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
@@ -457,12 +479,18 @@
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1;
#endif
+#if defined(USB)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
+#endif
#if defined(RCC_SMPS_SUPPORT)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS;
#endif
+#if defined(SPI_I2S_SUPPORT)
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
+#endif
+
#if defined(SAI1)
/* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
PeriphClkInit->PLLSAI1.PLLN = LL_RCC_PLLSAI1_GetN();
@@ -501,8 +529,10 @@
/* Get the RTC clock source ------------------------------------------------*/
PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+#if defined(USB)
/* Get the USB clock source ------------------------------------------------*/
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
+#endif
/* Get the RNG clock source ------------------------------------------------*/
PeriphClkInit->RngClockSelection = HAL_RCCEx_GetRngCLKSource();
@@ -520,6 +550,11 @@
/* Get the SMPS clock source -----------------------------------------------*/
PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE();
#endif
+
+#if defined(SPI_I2S_SUPPORT)
+ /* Get the I2S clock source -----------------------------------------------*/
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+#endif
}
/**
@@ -538,26 +573,26 @@
* @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
* @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
- *
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
* @retval Frequency in Hz
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
- uint32_t frequency;
-
+ uint32_t frequency = 0U;
+
#if defined(RCC_SMPS_SUPPORT)
uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos);
#endif
-
+
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-
+
if (PeriphClk == RCC_PERIPHCLK_RTC)
{
uint32_t rtcClockSource = LL_RCC_GetRTCClockSource();
-
+
if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSE) /* LSE clock used as RTC clock source */
{
if (LL_RCC_LSE_IsReady() == 1U)
@@ -566,7 +601,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */
@@ -579,7 +614,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_HSE_DIV32) /* HSE clock used as RTC clock source */
@@ -588,7 +623,7 @@
}
else /* No clock used as RTC clock source */
{
- frequency = 0;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
#if defined(SAI1)
@@ -596,49 +631,51 @@
{
switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE))
{
- case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
- if (LL_RCC_PLLSAI1_IsReady() == 1U)
- {
- frequency = RCC_PLLSAI1_GetFreqDomain_P();
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
- if (LL_RCC_PLL_IsReady() == 1U)
- {
- frequency = RCC_PLL_GetFreqDomain_P();
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default: /* External input clock used as SAI1 clock source */
- frequency = EXTERNAL_SAI1_CLOCK_VALUE;
- break;
+ case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+#if defined(SAI1)
+ case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
+ if (LL_RCC_PLLSAI1_IsReady() == 1U)
+ {
+ frequency = RCC_PLLSAI1_GetFreqDomain_P();
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+#endif
+
+ case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
+ if (LL_RCC_PLL_IsReady() == 1U)
+ {
+ frequency = RCC_PLL_GetFreqDomain_P();
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default: /* External input clock used as SAI1 clock source */
+ frequency = EXTERNAL_SAI1_CLOCK_VALUE;
+ break;
}
}
#endif
else if (PeriphClk == RCC_PERIPHCLK_RNG)
{
uint32_t rngClockSource = HAL_RCCEx_GetRngCLKSource();
-
+
if (rngClockSource == RCC_RNGCLKSOURCE_LSI) /* LSI clock used as RNG clock source */
{
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
@@ -649,7 +686,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (rngClockSource == RCC_RNGCLKSOURCE_LSE) /* LSE clock used as RNG clock source */
@@ -660,7 +697,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (rngClockSource == RCC_RNGCLKSOURCE_PLL) /* PLL clock divided by 3 used as RNG clock source */
@@ -671,7 +708,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (rngClockSource == RCC_RNGCLKSOURCE_MSI) /* MSI clock divided by 3 used as RNG clock source */
@@ -682,7 +719,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else /* HSI48 clock divided by 3 used as RNG clock source */
@@ -693,95 +730,97 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
}
+#if defined(USB)
else if (PeriphClk == RCC_PERIPHCLK_USB)
{
switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE))
{
#if defined(SAI1)
- case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
- if (LL_RCC_PLLSAI1_IsReady() == 1U)
- {
- frequency = RCC_PLLSAI1_GetFreqDomain_Q();
- }
- else
- {
- frequency = 0U;
- }
- break;
+ case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
+ if (LL_RCC_PLLSAI1_IsReady() == 1U)
+ {
+ frequency = RCC_PLLSAI1_GetFreqDomain_Q();
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
#endif
- case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady() == 1U)
- {
- frequency = RCC_PLL_GetFreqDomain_Q();
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
- if (LL_RCC_MSI_IsReady() == 1U)
- {
- frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default: /* HSI48 clock used as USB clock source */
- if (LL_RCC_HSI48_IsReady() == 1U)
- {
- frequency = HSI48_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
+
+ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady() == 1U)
+ {
+ frequency = RCC_PLL_GetFreqDomain_Q();
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
+ if (LL_RCC_MSI_IsReady() == 1U)
+ {
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default: /* HSI48 clock used as USB clock source */
+ if (LL_RCC_HSI48_IsReady() == 1U)
+ {
+ frequency = HSI48_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
}
}
-
+#endif
else if (PeriphClk == RCC_PERIPHCLK_USART1)
{
switch (LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE))
{
- case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady() == 1U)
- {
- frequency = LSE_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default: /* USART1 Clock is PCLK2 */
- frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
- LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB2Prescaler());
- break;
+ case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ frequency = LSE_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default: /* USART1 Clock is PCLK2 */
+ frequency = __LL_RCC_CALC_PCLK2_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
+ LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB2Prescaler());
+ break;
}
}
#if defined(LPUART1)
@@ -789,36 +828,36 @@
{
switch (LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE))
{
- case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
- if (LL_RCC_LSE_IsReady() == 1U)
- {
- frequency = LSE_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default: /* LPUART1 Clock is PCLK1 */
- frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
- LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
- break;
+ case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady() == 1U)
+ {
+ frequency = LSE_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default: /* LPUART1 Clock is PCLK1 */
+ frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
+ LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
+ break;
}
}
#endif
@@ -826,61 +865,71 @@
{
switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE))
{
-#if defined(SAI1)
- case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
- if (LL_RCC_PLLSAI1_IsReady() == 1U)
- {
- frequency = RCC_PLLSAI1_GetFreqDomain_R();
- }
- else
- {
- frequency = 0U;
- }
- break;
+#if defined(STM32WB55xx) || defined (STM32WB5Mxx)
+ case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
+ if (LL_RCC_PLLSAI1_IsReady() == 1U)
+ {
+ frequency = RCC_PLLSAI1_GetFreqDomain_R();
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+#elif defined(STM32WB35xx)
+ case LL_RCC_ADC_CLKSOURCE_HSI: /* HSI clock used as ADC clock source */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
#endif
- case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady() == 1U)
- {
- frequency = RCC_PLL_GetFreqDomain_P();
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default: /* No clock used as ADC clock source */
- frequency = 0;
- break;
+ case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */
+ if (LL_RCC_PLL_IsReady() == 1U)
+ {
+ frequency = RCC_PLL_GetFreqDomain_P();
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default: /* No clock used as ADC clock source */
+ break;
}
}
else if (PeriphClk == RCC_PERIPHCLK_I2C1)
{
switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE))
{
- case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default: /* I2C1 Clock is PCLK1 */
- frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
- LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
- break;
+ case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default: /* I2C1 Clock is PCLK1 */
+ frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
+ LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
+ break;
}
}
#if defined(I2C3)
@@ -888,32 +937,32 @@
{
switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE))
{
- case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
- frequency = HAL_RCC_GetSysClockFreq();
- break;
-
- case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- frequency = HSI_VALUE;
- }
- else
- {
- frequency = 0U;
- }
- break;
-
- default: /* I2C3 Clock is PCLK1 */
- frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
- LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
- break;
+ case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+ frequency = HAL_RCC_GetSysClockFreq();
+ break;
+
+ case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* Nothing to do as frequency already initialized to 0U */
+ }
+ break;
+
+ default: /* I2C3 Clock is PCLK1 */
+ frequency = __LL_RCC_CALC_PCLK1_FREQ(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), \
+ LL_RCC_GetAHBPrescaler()), LL_RCC_GetAPB1Prescaler());
+ break;
}
}
#endif
else if (PeriphClk == RCC_PERIPHCLK_LPTIM1)
{
uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
-
+
if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSI) /* LPTIM1 Clock is LSI Osc. */
{
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
@@ -924,7 +973,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */
@@ -935,7 +984,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */
@@ -946,7 +995,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else /* LPTIM1 Clock is PCLK1 */
@@ -957,7 +1006,7 @@
else if (PeriphClk == RCC_PERIPHCLK_LPTIM2)
{
uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
-
+
if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSI) /* LPTIM2 Clock is LSI Osc. */
{
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
@@ -968,7 +1017,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_HSI) /* LPTIM2 Clock is HSI Osc. */
@@ -979,7 +1028,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSE) /* LPTIM2 Clock is LSE Osc. */
@@ -990,7 +1039,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else /* LPTIM2 Clock is PCLK1 */
@@ -1001,7 +1050,7 @@
else if (PeriphClk == RCC_PERIPHCLK_RFWAKEUP)
{
uint32_t rfwkpClockSource = LL_RCC_GetRFWKPClockSource();
-
+
if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSE) /* LSE clock used as RF Wakeup clock source */
{
if (LL_RCC_LSE_IsReady() == 1U)
@@ -1010,7 +1059,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */
@@ -1023,7 +1072,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */
@@ -1032,14 +1081,14 @@
}
else /* No clock used as RF Wakeup clock source */
{
- frequency = 0;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
#if defined(RCC_SMPS_SUPPORT)
else if (PeriphClk == RCC_PERIPHCLK_SMPS)
{
uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource();
-
+
if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */
{
if (LL_RCC_HSI_IsReady() == 1U)
@@ -1049,7 +1098,7 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */
@@ -1061,41 +1110,62 @@
}
else
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */
{
switch (LL_RCC_MSI_GetRange())
{
- case LL_RCC_MSIRANGE_8:
- frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4];
- break;
- case LL_RCC_MSIRANGE_9:
- frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3];
- break;
- case LL_RCC_MSIRANGE_10:
- frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2];
- break;
- case LL_RCC_MSIRANGE_11:
- frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1];
- break;
- default:
- frequency = 0U;
- break;
+ case LL_RCC_MSIRANGE_8:
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_8) / SmpsPrescalerTable[smps_prescaler_index][4];
+ break;
+ case LL_RCC_MSIRANGE_9:
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_9) / SmpsPrescalerTable[smps_prescaler_index][3];
+ break;
+ case LL_RCC_MSIRANGE_10:
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_10) / SmpsPrescalerTable[smps_prescaler_index][2];
+ break;
+ case LL_RCC_MSIRANGE_11:
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGE_11) / SmpsPrescalerTable[smps_prescaler_index][1];
+ break;
+ default:
+ break;
}
frequency = frequency >> 1U; /* Systematic Div by 2 */
}
else /* SMPS has no Clock */
{
- frequency = 0U;
+ /* Nothing to do as frequency already initialized to 0U */
}
}
#endif
- else
+#if defined(SPI_I2S_SUPPORT)
+ if (PeriphClk == RCC_PERIPHCLK_I2S)
{
- frequency = 0U;
+ switch (LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE))
+ {
+ case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL */
+ frequency = RCC_PLL_GetFreqDomain_P();
+ break;
+
+ case LL_RCC_I2S_CLKSOURCE_NONE: /* No clock used as I2S clock source */
+ default:
+ break;
+ }
}
+#endif
return (frequency);
}
@@ -1334,7 +1404,7 @@
* @note PA2, PH3 or PC12 should be configured in alternate function mode.
* @param RCC_LSCOx specifies the output direction for the clock source.
* @arg @ref RCC_LSCO1 Clock source to output on LSCO1 pin(PA2)
- * @arg @ref RCC_LSCO2 Clock source to output on LSCO2 pin(PH13)
+ * @arg @ref RCC_LSCO2 Clock source to output on LSCO2 pin(PH3)
* @arg @ref RCC_LSCO3 Clock source to output on LSCO3 pin(PC12)
* @param RCC_LSCOSource specifies the clock source to output.
* This parameter can be one of the following values:
@@ -1378,7 +1448,8 @@
HAL_GPIO_Init(LSCO2_GPIO_PORT, &GPIO_InitStruct);
}
- else
+#if defined(RCC_LSCO3_SUPPORT)
+ else if (RCC_LSCOx == RCC_LSCO3)
{
/* LSCO3 Clock Enable */
__LSCO3_CLK_ENABLE();
@@ -1387,6 +1458,11 @@
GPIO_InitStruct.Alternate = GPIO_AF6_LSCO;
HAL_GPIO_Init(LSCO3_GPIO_PORT, &GPIO_InitStruct);
}
+#endif
+ else
+ {
+ ;
+ }
/* Update LSCOSEL clock source in Backup Domain control register */
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
diff --git a/Src/stm32wbxx_hal_smartcard.c b/Src/stm32wbxx_hal_smartcard.c
index a24a035..6f38d0c 100644
--- a/Src/stm32wbxx_hal_smartcard.c
+++ b/Src/stm32wbxx_hal_smartcard.c
@@ -107,8 +107,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
- Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
@@ -123,9 +123,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
@@ -140,13 +140,13 @@
(+) MspDeInitCallback : SMARTCARD MspDeInit.
[..]
- By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
+ examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
- and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -155,8 +155,8 @@
in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
- or @ref HAL_SMARTCARD_Init() function.
+ using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
+ or HAL_SMARTCARD_Init() function.
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
@@ -722,59 +722,59 @@
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
[..]
- (+) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
+ (##) Non-Blocking mode: The communication is performed using Interrupts
or DMA, the relevant API's return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
- (+) Blocking mode APIs are :
- (++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
+ (#) Blocking mode APIs are :
+ (##) HAL_SMARTCARD_Transmit()
+ (##) HAL_SMARTCARD_Receive()
- (+) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SMARTCARD_Transmit_IT()
- (++) HAL_SMARTCARD_Receive_IT()
- (++) HAL_SMARTCARD_IRQHandler()
+ (#) Non Blocking mode APIs with Interrupt are :
+ (##) HAL_SMARTCARD_Transmit_IT()
+ (##) HAL_SMARTCARD_Receive_IT()
+ (##) HAL_SMARTCARD_IRQHandler()
- (+) Non Blocking mode functions with DMA are :
- (++) HAL_SMARTCARD_Transmit_DMA()
- (++) HAL_SMARTCARD_Receive_DMA()
+ (#) Non Blocking mode functions with DMA are :
+ (##) HAL_SMARTCARD_Transmit_DMA()
+ (##) HAL_SMARTCARD_Receive_DMA()
- (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SMARTCARD_TxCpltCallback()
- (++) HAL_SMARTCARD_RxCpltCallback()
- (++) HAL_SMARTCARD_ErrorCallback()
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (##) HAL_SMARTCARD_TxCpltCallback()
+ (##) HAL_SMARTCARD_RxCpltCallback()
+ (##) HAL_SMARTCARD_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_SMARTCARD_Abort()
- (+) HAL_SMARTCARD_AbortTransmit()
- (+) HAL_SMARTCARD_AbortReceive()
- (+) HAL_SMARTCARD_Abort_IT()
- (+) HAL_SMARTCARD_AbortTransmit_IT()
- (+) HAL_SMARTCARD_AbortReceive_IT()
+ (##) HAL_SMARTCARD_Abort()
+ (##) HAL_SMARTCARD_AbortTransmit()
+ (##) HAL_SMARTCARD_AbortReceive()
+ (##) HAL_SMARTCARD_Abort_IT()
+ (##) HAL_SMARTCARD_AbortTransmit_IT()
+ (##) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_SMARTCARD_AbortCpltCallback()
- (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+ (##) HAL_SMARTCARD_AbortCpltCallback()
+ (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
diff --git a/Src/stm32wbxx_hal_tim.c b/Src/stm32wbxx_hal_tim.c
index eeec812..ce7a1e8 100644
--- a/Src/stm32wbxx_hal_tim.c
+++ b/Src/stm32wbxx_hal_tim.c
@@ -2625,10 +2625,10 @@
}
/* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@@ -2791,7 +2791,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
switch (Channel)
@@ -2835,7 +2835,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2881,7 +2881,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@@ -2931,7 +2931,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2986,7 +2986,7 @@
uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
{
@@ -3120,7 +3120,7 @@
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
diff --git a/Src/stm32wbxx_hal_wwdg.c b/Src/stm32wbxx_hal_wwdg.c
index 1195476..e70227c 100644
--- a/Src/stm32wbxx_hal_wwdg.c
+++ b/Src/stm32wbxx_hal_wwdg.c
@@ -32,12 +32,11 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @64 MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 64µs
- (++) Counter max (T[5;0] = 0x3F) @64 MHz (PCLK1) with prescaler dividing by 128:
+ (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 64us
+ (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: approximately 524.28ms
- ==============================================================================
##### How to use this driver #####
==============================================================================
@@ -67,26 +66,26 @@
[..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
- @ref HAL_WWDG_RegisterCallback() to register a user callback.
+ HAL_WWDG_RegisterCallback() to register a user callback.
- (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
+ (+) Function HAL_WWDG_RegisterCallback() allows to register following
callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
- the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
+ (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
takes as parameters the HAL peripheral handle and the Callback ID.
This function allows to reset following callbacks:
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
[..]
- When calling @ref HAL_WWDG_Init function, callbacks are reset to the
+ When calling HAL_WWDG_Init function, callbacks are reset to the
corresponding legacy weak (surcharged) functions:
- @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
[..]
diff --git a/Src/stm32wbxx_ll_gpio.c b/Src/stm32wbxx_ll_gpio.c
index 09853b4..daf9f6a 100644
--- a/Src/stm32wbxx_ll_gpio.c
+++ b/Src/stm32wbxx_ll_gpio.c
@@ -190,9 +190,6 @@
if (currentpin != 0x00u)
{
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
@@ -200,6 +197,12 @@
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
}
/* Pull-up Pull down resistor configuration*/
@@ -220,19 +223,13 @@
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
return (SUCCESS);
}
diff --git a/Src/stm32wbxx_ll_lptim.c b/Src/stm32wbxx_ll_lptim.c
index 16cde97..ea02936 100644
--- a/Src/stm32wbxx_ll_lptim.c
+++ b/Src/stm32wbxx_ll_lptim.c
@@ -207,16 +207,16 @@
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
- break;
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
#if defined(LPTIM2)
- case LPTIM2_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
- break;
+ case LPTIM2_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
+ break;
#endif /* LPTIM2 */
- default:
- break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -237,16 +237,16 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
- break;
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
#if defined(LPTIM2)
- case LPTIM2_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
- break;
+ case LPTIM2_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
+ break;
#endif /* LPTIM2 */
- default:
- break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -259,7 +259,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@@ -274,7 +275,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
diff --git a/Src/stm32wbxx_ll_rcc.c b/Src/stm32wbxx_ll_rcc.c
index 1a964c4..23aa838 100644
--- a/Src/stm32wbxx_ll_rcc.c
+++ b/Src/stm32wbxx_ll_rcc.c
@@ -72,6 +72,9 @@
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+#if defined(SPI_I2S_SUPPORT)
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
+#endif
/**
* @}
*/
@@ -81,7 +84,9 @@
* @{
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+#if defined(SAI1)
uint32_t RCC_PLL_GetFreqDomain_SAI(void);
+#endif
uint32_t RCC_PLL_GetFreqDomain_ADC(void);
uint32_t RCC_PLL_GetFreqDomain_48M(void);
@@ -91,6 +96,10 @@
uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
#endif
+#if defined(SPI_I2S_SUPPORT)
+uint32_t RCC_PLL_GetFreqDomain_I2S(void);
+#endif
+
uint32_t RCC_GetSystemClockFreq(void);
@@ -349,7 +358,6 @@
return smps_frequency;
}
-
#endif
/**
@@ -616,12 +624,15 @@
}
break;
+#if defined(SAI1)
case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
if (LL_RCC_PLLSAI1_IsReady() == 1U)
{
sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
}
break;
+#endif
+
case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
if (LL_RCC_PLL_IsReady() == 1U)
{
@@ -775,7 +786,7 @@
adc_frequency = RCC_GetSystemClockFreq();
break;
- case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ case LL_RCC_ADC_CLKSOURCE_PLL: /* PLL clock used as ADC clock source */
if (LL_RCC_PLL_IsReady() == 1U)
{
adc_frequency = RCC_PLL_GetFreqDomain_ADC();
@@ -874,6 +885,46 @@
return rfwkp_frequency;
}
+#if defined(SPI_I2S_SUPPORT)
+/**
+ * @brief Return I2Sx clock frequency
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE
+ * @retval I2S clock frequency (in Hz)
+ * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLLs (PLL) is not ready
+ */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+ uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+ /* I2SCLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+ case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */
+ if (LL_RCC_PLL_IsReady() == 1U)
+ {
+ i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
+ }
+ break;
+
+ case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
+ i2s_frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case LL_RCC_I2S_CLKSOURCE_HSI: /* HSI clock used as I2S clock source */
+ default:
+ if (LL_RCC_HSI_IsReady() == 1U)
+ {
+ i2s_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ return i2s_frequency;
+}
+#endif
/**
* @}
@@ -1312,6 +1363,36 @@
}
#endif
+#if defined(SPI_I2S_SUPPORT)
+/**
+ * @brief Return PLL clock frequency used for I2S domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_I2S(void)
+{
+ uint32_t pllinputfreq, pllsource;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ I2S Domain clock = PLL_VCO / PLLP
+ */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ default:
+ pllinputfreq = HSI_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
+ LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
+}
+#endif
+
/**
* @}
*/
diff --git a/Src/stm32wbxx_ll_spi.c b/Src/stm32wbxx_ll_spi.c
index 8d8c422..1301719 100644
--- a/Src/stm32wbxx_ll_spi.c
+++ b/Src/stm32wbxx_ll_spi.c
@@ -21,6 +21,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_ll_spi.h"
#include "stm32wbxx_ll_bus.h"
+#include "stm32wbxx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
@@ -232,6 +233,10 @@
status = SUCCESS;
}
+#if defined (SPI_I2S_SUPPORT)
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
return status;
}
@@ -268,6 +273,251 @@
* @}
*/
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ * @{
+ */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK 0x0002U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ * @{
+ */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI/I2S registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_DeInit(SPIx);
+}
+
+/**
+ * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are Initialized
+ * - ERROR: SPI registers are not Initialized
+ */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint32_t i2sdiv = 2U;
+ uint32_t i2sodd = 0U;
+ uint32_t packetlength = 1U;
+ uint32_t tmp;
+ uint32_t sourceclock;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(SPIx->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD);
+
+ /*---------------------------- SPIx I2SPR Configuration ----------------------
+ * Configure SPIx I2SPR with parameters:
+ * - MCLKOutput: SPI_I2SPR_MCKOE bit
+ * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ */
+
+ /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
+ */
+ if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing)
+ * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ */
+ if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32wbxx_ll_rcc.h file */
+ /* Get the I2S source clock value */
+ sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE);
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = ((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
+ I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
+ I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
+ I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
+ I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
+ I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
+}
+
+/**
+ * @brief Set linear and parity prescaler.
+ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+ /* Write to SPIx I2SPR */
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
#endif /* defined (SPI1) || defined (SPI2) */
/**
diff --git a/Src/stm32wbxx_ll_tim.c b/Src/stm32wbxx_ll_tim.c
index a3f240a..ba79b2a 100644
--- a/Src/stm32wbxx_ll_tim.c
+++ b/Src/stm32wbxx_ll_tim.c
@@ -262,7 +262,7 @@
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**
