drivers: adc: stm32f3 adc driver set common clock to HCLK

Set the synchronous clock mode to HCLK/1 (DIV1) or HCLK/2 (DIV2)
Both are valid common clock setting values.
The HCLK/1 (DIV1) is possible only if the ahb-prescaler = <1>
in the RCC_CFGR (see DTS).

Signed-off-by: Francois Ramu <francois.ramu@st.com>