Ulf Magnusson | bd6e044 | 2019-11-01 13:45:29 +0100 | [diff] [blame] | 1 | # General options signifying CPU capabilities of ARM SoCs |
Ioannis Glaropoulos | d61bac2 | 2019-02-08 14:13:33 +0100 | [diff] [blame] | 2 | |
Ioannis Glaropoulos | d61bac2 | 2019-02-08 14:13:33 +0100 | [diff] [blame] | 3 | # Copyright (c) 2018 Nordic Semiconductor ASA. |
Ioannis Glaropoulos | d61bac2 | 2019-02-08 14:13:33 +0100 | [diff] [blame] | 4 | # SPDX-License-Identifier: Apache-2.0 |
Ioannis Glaropoulos | d61bac2 | 2019-02-08 14:13:33 +0100 | [diff] [blame] | 5 | |
Piotr Zięcik | d393186 | 2018-08-09 14:47:27 +0200 | [diff] [blame] | 6 | config CPU_HAS_ARM_MPU |
| 7 | bool |
Piotr Zięcik | d393186 | 2018-08-09 14:47:27 +0200 | [diff] [blame] | 8 | select CPU_HAS_MPU |
| 9 | help |
| 10 | This option is enabled when the CPU has a Memory Protection Unit (MPU) |
David B. Kinder | ee47f7f | 2018-11-02 12:09:45 -0700 | [diff] [blame] | 11 | in ARM flavor. |
Piotr Zięcik | d393186 | 2018-08-09 14:47:27 +0200 | [diff] [blame] | 12 | |
| 13 | config CPU_HAS_NXP_MPU |
| 14 | bool |
Piotr Zięcik | d393186 | 2018-08-09 14:47:27 +0200 | [diff] [blame] | 15 | select CPU_HAS_MPU |
| 16 | help |
| 17 | This option is enabled when the CPU has a Memory Protection Unit (MPU) |
David B. Kinder | ee47f7f | 2018-11-02 12:09:45 -0700 | [diff] [blame] | 18 | in NXP flavor. |
Ioannis Glaropoulos | 1cc66cf | 2018-10-12 09:27:28 +0200 | [diff] [blame] | 19 | |
Ioannis Glaropoulos | cede12b | 2019-12-05 15:16:41 +0100 | [diff] [blame] | 20 | config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS |
| 21 | bool "Custom fixed SoC MPU region definition" |
| 22 | help |
| 23 | If enabled, this option signifies that the SoC will |
| 24 | define and configure its own fixed MPU regions in the |
| 25 | SoC definition. These fixed MPU regions are currently |
| 26 | used to set Flash and SRAM default access policies and |
| 27 | they are programmed at boot time. |
| 28 | |
Ioannis Glaropoulos | 1cc66cf | 2018-10-12 09:27:28 +0200 | [diff] [blame] | 29 | config CPU_HAS_ARM_SAU |
| 30 | bool |
Ioannis Glaropoulos | 1cc66cf | 2018-10-12 09:27:28 +0200 | [diff] [blame] | 31 | select CPU_HAS_TEE |
| 32 | help |
| 33 | MCU implements the ARM Security Attribution Unit (SAU). |
Piotr Mienkowski | 03eaafd | 2018-12-20 09:01:14 +0100 | [diff] [blame] | 34 | |
Ioannis Glaropoulos | 1d033a9 | 2018-12-21 22:52:42 +0100 | [diff] [blame] | 35 | config CPU_HAS_NRF_IDAU |
| 36 | bool |
Ioannis Glaropoulos | 397d193 | 2019-08-01 20:47:31 +0200 | [diff] [blame] | 37 | depends on SOC_SERIES_NRF91X || SOC_NRF5340_CPUAPP |
Ioannis Glaropoulos | 1d033a9 | 2018-12-21 22:52:42 +0100 | [diff] [blame] | 38 | select CPU_HAS_TEE |
| 39 | help |
| 40 | MCU implements the nRF (vendor-specific) Security Attribution Unit. |
| 41 | (IDAU: "Implementation-Defined Attribution Unit", in accordance with |
| 42 | ARM terminology). |
| 43 | |
Øyvind Rønningstad | 1d5cb92 | 2020-02-21 10:14:38 +0100 | [diff] [blame] | 44 | if CPU_HAS_NRF_IDAU |
| 45 | config NRF_SPU_FLASH_REGION_SIZE |
| 46 | hex |
| 47 | default 0x8000 if SOC_NRF9160 |
Øyvind Rønningstad | 1d5cb92 | 2020-02-21 10:14:38 +0100 | [diff] [blame] | 48 | default 0x4000 if SOC_NRF5340_CPUAPP |
| 49 | help |
| 50 | FLASH region size for the NRF_SPU peripheral |
| 51 | |
| 52 | config NRF_SPU_RAM_REGION_SIZE |
| 53 | hex |
| 54 | default 0x2000 if SOC_NRF9160 || SOC_NRF5340_CPUAPP |
| 55 | help |
| 56 | RAM region size for the NRF_SPU peripheral |
| 57 | endif |
| 58 | |
Piotr Mienkowski | 03eaafd | 2018-12-20 09:01:14 +0100 | [diff] [blame] | 59 | config HAS_SWO |
| 60 | bool |
Piotr Mienkowski | 03eaafd | 2018-12-20 09:01:14 +0100 | [diff] [blame] | 61 | help |
| 62 | When enabled, indicates that SoC has an SWO output |
Ulf Magnusson | f052de5 | 2019-10-25 13:25:46 +0200 | [diff] [blame] | 63 | |
| 64 | config SOC_PART_NUMBER |
| 65 | string |
| 66 | help |
| 67 | This string holds the full part number of the SoC. It is a hidden option |
| 68 | that you should not set directly. The part number selection choice defines |
| 69 | the default value for this string. |