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Ulf Magnussonbd6e0442019-11-01 13:45:29 +01001# General options signifying CPU capabilities of ARM SoCs
Ioannis Glaropoulosd61bac22019-02-08 14:13:33 +01002
Ioannis Glaropoulosd61bac22019-02-08 14:13:33 +01003# Copyright (c) 2018 Nordic Semiconductor ASA.
Ioannis Glaropoulosd61bac22019-02-08 14:13:33 +01004# SPDX-License-Identifier: Apache-2.0
Ioannis Glaropoulosd61bac22019-02-08 14:13:33 +01005
Piotr Zięcikd3931862018-08-09 14:47:27 +02006config CPU_HAS_ARM_MPU
7 bool
Piotr Zięcikd3931862018-08-09 14:47:27 +02008 select CPU_HAS_MPU
9 help
10 This option is enabled when the CPU has a Memory Protection Unit (MPU)
David B. Kinderee47f7f2018-11-02 12:09:45 -070011 in ARM flavor.
Piotr Zięcikd3931862018-08-09 14:47:27 +020012
13config CPU_HAS_NXP_MPU
14 bool
Piotr Zięcikd3931862018-08-09 14:47:27 +020015 select CPU_HAS_MPU
16 help
17 This option is enabled when the CPU has a Memory Protection Unit (MPU)
David B. Kinderee47f7f2018-11-02 12:09:45 -070018 in NXP flavor.
Ioannis Glaropoulos1cc66cf2018-10-12 09:27:28 +020019
Ioannis Glaropouloscede12b2019-12-05 15:16:41 +010020config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
21 bool "Custom fixed SoC MPU region definition"
22 help
23 If enabled, this option signifies that the SoC will
24 define and configure its own fixed MPU regions in the
25 SoC definition. These fixed MPU regions are currently
26 used to set Flash and SRAM default access policies and
27 they are programmed at boot time.
28
Ioannis Glaropoulos1cc66cf2018-10-12 09:27:28 +020029config CPU_HAS_ARM_SAU
30 bool
Ioannis Glaropoulos1cc66cf2018-10-12 09:27:28 +020031 select CPU_HAS_TEE
32 help
33 MCU implements the ARM Security Attribution Unit (SAU).
Piotr Mienkowski03eaafd2018-12-20 09:01:14 +010034
Ioannis Glaropoulos1d033a92018-12-21 22:52:42 +010035config CPU_HAS_NRF_IDAU
36 bool
Ioannis Glaropoulos397d1932019-08-01 20:47:31 +020037 depends on SOC_SERIES_NRF91X || SOC_NRF5340_CPUAPP
Ioannis Glaropoulos1d033a92018-12-21 22:52:42 +010038 select CPU_HAS_TEE
39 help
40 MCU implements the nRF (vendor-specific) Security Attribution Unit.
41 (IDAU: "Implementation-Defined Attribution Unit", in accordance with
42 ARM terminology).
43
Øyvind Rønningstad1d5cb922020-02-21 10:14:38 +010044if CPU_HAS_NRF_IDAU
45config NRF_SPU_FLASH_REGION_SIZE
46 hex
47 default 0x8000 if SOC_NRF9160
Øyvind Rønningstad1d5cb922020-02-21 10:14:38 +010048 default 0x4000 if SOC_NRF5340_CPUAPP
49 help
50 FLASH region size for the NRF_SPU peripheral
51
52config NRF_SPU_RAM_REGION_SIZE
53 hex
54 default 0x2000 if SOC_NRF9160 || SOC_NRF5340_CPUAPP
55 help
56 RAM region size for the NRF_SPU peripheral
57endif
58
Piotr Mienkowski03eaafd2018-12-20 09:01:14 +010059config HAS_SWO
60 bool
Piotr Mienkowski03eaafd2018-12-20 09:01:14 +010061 help
62 When enabled, indicates that SoC has an SWO output
Ulf Magnussonf052de52019-10-25 13:25:46 +020063
64config SOC_PART_NUMBER
65 string
66 help
67 This string holds the full part number of the SoC. It is a hidden option
68 that you should not set directly. The part number selection choice defines
69 the default value for this string.