Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016 Open-RnD Sp. z o.o. |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 3 | * Copyright (c) 2016 Linaro Limited. |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 4 | * |
David B. Kinder | ac74d8b | 2017-01-18 17:01:01 -0800 | [diff] [blame] | 5 | * SPDX-License-Identifier: Apache-2.0 |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
Kumar Gala | 989484b | 2020-03-24 14:28:48 -0500 | [diff] [blame] | 8 | #define DT_DRV_COMPAT st_stm32_uart |
| 9 | |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 10 | /** |
Ilya Tagunov | 84cffc7 | 2018-03-20 20:44:45 +0300 | [diff] [blame] | 11 | * @brief Driver for UART port on STM32 family processor. |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 12 | * @note LPUART and U(S)ART have the same base and |
| 13 | * majority of operations are performed the same way. |
| 14 | * Please validate for newly added series. |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 17 | #include <zephyr/kernel.h> |
| 18 | #include <zephyr/arch/cpu.h> |
| 19 | #include <zephyr/sys/__assert.h> |
Kumar Gala | aa2bdbe | 2018-10-31 12:44:45 -0500 | [diff] [blame] | 20 | #include <soc.h> |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 21 | #include <zephyr/init.h> |
| 22 | #include <zephyr/drivers/uart.h> |
| 23 | #include <zephyr/drivers/clock_control.h> |
| 24 | #include <zephyr/pm/policy.h> |
Erwan Gouriou | a439c04 | 2022-08-03 14:39:59 +0200 | [diff] [blame] | 25 | #include <zephyr/pm/device.h> |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 26 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 27 | #ifdef CONFIG_UART_ASYNC_API |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 28 | #include <zephyr/drivers/dma/dma_stm32.h> |
| 29 | #include <zephyr/drivers/dma.h> |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 30 | #endif |
| 31 | |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 32 | #include <zephyr/linker/sections.h> |
| 33 | #include <zephyr/drivers/clock_control/stm32_clock_control.h> |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 34 | #include "uart_stm32.h" |
| 35 | |
Gerard Marull-Paretas | e83fab3 | 2020-10-03 23:58:36 +0200 | [diff] [blame] | 36 | #include <stm32_ll_usart.h> |
| 37 | #include <stm32_ll_lpuart.h> |
| 38 | |
Gerard Marull-Paretas | fb60aab | 2022-05-06 10:25:46 +0200 | [diff] [blame] | 39 | #include <zephyr/logging/log.h> |
Pete Dietl | 060e39e | 2022-03-04 12:56:05 -0800 | [diff] [blame] | 40 | LOG_MODULE_REGISTER(uart_stm32, CONFIG_UART_LOG_LEVEL); |
Francois Ramu | d3ffa8d | 2019-11-12 16:13:03 +0100 | [diff] [blame] | 41 | |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 42 | /* This symbol takes the value 1 if one of the device instances */ |
Erwan Gouriou | 1ef9e9e | 2022-08-04 11:08:15 +0200 | [diff] [blame] | 43 | /* is configured in dts with a domain clock */ |
| 44 | #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT |
| 45 | #define STM32_UART_DOMAIN_CLOCK_SUPPORT 1 |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 46 | #else |
Erwan Gouriou | 1ef9e9e | 2022-08-04 11:08:15 +0200 | [diff] [blame] | 47 | #define STM32_UART_DOMAIN_CLOCK_SUPPORT 0 |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 48 | #endif |
| 49 | |
Kumar Gala | c2135f8 | 2020-05-07 12:22:26 -0500 | [diff] [blame] | 50 | #define HAS_LPUART_1 (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), \ |
| 51 | st_stm32_lpuart, okay)) |
Erwan Gouriou | 76313f0 | 2020-04-17 12:33:29 +0200 | [diff] [blame] | 52 | |
Yong Cong Sin | a6ebcdd | 2021-10-22 00:02:29 +0800 | [diff] [blame] | 53 | #if HAS_LPUART_1 |
| 54 | #ifdef USART_PRESC_PRESCALER |
| 55 | uint32_t lpuartdiv_calc(const uint64_t clock_rate, const uint16_t presc_idx, |
| 56 | const uint32_t baud_rate) |
| 57 | { |
| 58 | uint64_t lpuartdiv; |
| 59 | |
| 60 | lpuartdiv = clock_rate / LPUART_PRESCALER_TAB[presc_idx]; |
| 61 | lpuartdiv *= LPUART_LPUARTDIV_FREQ_MUL; |
| 62 | lpuartdiv += baud_rate / 2; |
| 63 | lpuartdiv /= baud_rate; |
| 64 | |
| 65 | return (uint32_t)lpuartdiv; |
| 66 | } |
| 67 | #else |
| 68 | uint32_t lpuartdiv_calc(const uint64_t clock_rate, const uint32_t baud_rate) |
| 69 | { |
| 70 | uint64_t lpuartdiv; |
| 71 | |
| 72 | lpuartdiv = clock_rate * LPUART_LPUARTDIV_FREQ_MUL; |
| 73 | lpuartdiv += baud_rate / 2; |
| 74 | lpuartdiv /= baud_rate; |
| 75 | |
| 76 | return (uint32_t)lpuartdiv; |
| 77 | } |
| 78 | #endif /* USART_PRESC_PRESCALER */ |
| 79 | #endif /* HAS_LPUART_1 */ |
| 80 | |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 81 | #ifdef CONFIG_PM |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 82 | static void uart_stm32_pm_policy_state_lock_get(const struct device *dev) |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 83 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 84 | struct uart_stm32_data *data = dev->data; |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 85 | |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 86 | if (!data->pm_policy_state_on) { |
| 87 | data->pm_policy_state_on = true; |
Carlo Caione | 69b28bf | 2022-04-07 13:06:12 +0200 | [diff] [blame] | 88 | pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 89 | } |
| 90 | } |
| 91 | |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 92 | static void uart_stm32_pm_policy_state_lock_put(const struct device *dev) |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 93 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 94 | struct uart_stm32_data *data = dev->data; |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 95 | |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 96 | if (data->pm_policy_state_on) { |
| 97 | data->pm_policy_state_on = false; |
Carlo Caione | 69b28bf | 2022-04-07 13:06:12 +0200 | [diff] [blame] | 98 | pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 99 | } |
| 100 | } |
| 101 | #endif /* CONFIG_PM */ |
| 102 | |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 103 | static inline void uart_stm32_set_baudrate(const struct device *dev, uint32_t baud_rate) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 104 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 105 | const struct uart_stm32_config *config = dev->config; |
| 106 | struct uart_stm32_data *data = dev->data; |
Erwan Gouriou | 69a2896 | 2019-05-20 17:15:02 +0200 | [diff] [blame] | 107 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 108 | uint32_t clock_rate; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 109 | |
| 110 | /* Get clock rate */ |
Erwan Gouriou | 1ef9e9e | 2022-08-04 11:08:15 +0200 | [diff] [blame] | 111 | if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 112 | if (clock_control_get_rate(data->clock, |
| 113 | (clock_control_subsys_t)&config->pclken[1], |
| 114 | &clock_rate) < 0) { |
| 115 | LOG_ERR("Failed call clock_control_get_rate(pclken[1])"); |
| 116 | return; |
| 117 | } |
| 118 | } else { |
| 119 | if (clock_control_get_rate(data->clock, |
| 120 | (clock_control_subsys_t)&config->pclken[0], |
| 121 | &clock_rate) < 0) { |
| 122 | LOG_ERR("Failed call clock_control_get_rate(pclken[0])"); |
| 123 | return; |
| 124 | } |
Francois Ramu | d3ffa8d | 2019-11-12 16:13:03 +0100 | [diff] [blame] | 125 | } |
Erwan Gouriou | 69a2896 | 2019-05-20 17:15:02 +0200 | [diff] [blame] | 126 | |
Erwan Gouriou | 76313f0 | 2020-04-17 12:33:29 +0200 | [diff] [blame] | 127 | #if HAS_LPUART_1 |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 128 | if (IS_LPUART_INSTANCE(config->usart)) { |
Yong Cong Sin | a6ebcdd | 2021-10-22 00:02:29 +0800 | [diff] [blame] | 129 | uint32_t lpuartdiv; |
| 130 | #ifdef USART_PRESC_PRESCALER |
| 131 | uint8_t presc_idx; |
| 132 | uint32_t presc_val; |
| 133 | |
| 134 | for (presc_idx = 0; presc_idx < ARRAY_SIZE(LPUART_PRESCALER_TAB); presc_idx++) { |
| 135 | lpuartdiv = lpuartdiv_calc(clock_rate, presc_idx, baud_rate); |
| 136 | if (lpuartdiv >= LPUART_BRR_MIN_VALUE && lpuartdiv <= LPUART_BRR_MASK) { |
| 137 | break; |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | if (presc_idx == ARRAY_SIZE(LPUART_PRESCALER_TAB)) { |
| 142 | LOG_ERR("Unable to set %s to %d", dev->name, baud_rate); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | presc_val = presc_idx << USART_PRESC_PRESCALER_Pos; |
| 147 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 148 | LL_LPUART_SetPrescaler(config->usart, presc_val); |
Yong Cong Sin | a6ebcdd | 2021-10-22 00:02:29 +0800 | [diff] [blame] | 149 | #else |
| 150 | lpuartdiv = lpuartdiv_calc(clock_rate, baud_rate); |
| 151 | if (lpuartdiv < LPUART_BRR_MIN_VALUE || lpuartdiv > LPUART_BRR_MASK) { |
| 152 | LOG_ERR("Unable to set %s to %d", dev->name, baud_rate); |
| 153 | return; |
| 154 | } |
| 155 | #endif /* USART_PRESC_PRESCALER */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 156 | LL_LPUART_SetBaudRate(config->usart, |
Erwan Gouriou | 69a2896 | 2019-05-20 17:15:02 +0200 | [diff] [blame] | 157 | clock_rate, |
| 158 | #ifdef USART_PRESC_PRESCALER |
Yong Cong Sin | a6ebcdd | 2021-10-22 00:02:29 +0800 | [diff] [blame] | 159 | presc_val, |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 160 | #endif |
Erwan Gouriou | 69a2896 | 2019-05-20 17:15:02 +0200 | [diff] [blame] | 161 | baud_rate); |
| 162 | } else { |
Erwan Gouriou | 76313f0 | 2020-04-17 12:33:29 +0200 | [diff] [blame] | 163 | #endif /* HAS_LPUART_1 */ |
Erwan Gouriou | 37c7b89 | 2021-01-08 10:54:46 +0100 | [diff] [blame] | 164 | #ifdef USART_CR1_OVER8 |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 165 | LL_USART_SetOverSampling(config->usart, |
Erwan Gouriou | 37c7b89 | 2021-01-08 10:54:46 +0100 | [diff] [blame] | 166 | LL_USART_OVERSAMPLING_16); |
| 167 | #endif |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 168 | LL_USART_SetBaudRate(config->usart, |
Erwan Gouriou | 69a2896 | 2019-05-20 17:15:02 +0200 | [diff] [blame] | 169 | clock_rate, |
| 170 | #ifdef USART_PRESC_PRESCALER |
| 171 | LL_USART_PRESCALER_DIV1, |
| 172 | #endif |
| 173 | #ifdef USART_CR1_OVER8 |
| 174 | LL_USART_OVERSAMPLING_16, |
| 175 | #endif |
| 176 | baud_rate); |
| 177 | |
Erwan Gouriou | 76313f0 | 2020-04-17 12:33:29 +0200 | [diff] [blame] | 178 | #if HAS_LPUART_1 |
Erwan Gouriou | 69a2896 | 2019-05-20 17:15:02 +0200 | [diff] [blame] | 179 | } |
Erwan Gouriou | 76313f0 | 2020-04-17 12:33:29 +0200 | [diff] [blame] | 180 | #endif /* HAS_LPUART_1 */ |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 181 | } |
| 182 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 183 | static inline void uart_stm32_set_parity(const struct device *dev, |
| 184 | uint32_t parity) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 185 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 186 | const struct uart_stm32_config *config = dev->config; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 187 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 188 | LL_USART_SetParity(config->usart, parity); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 189 | } |
| 190 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 191 | static inline uint32_t uart_stm32_get_parity(const struct device *dev) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 192 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 193 | const struct uart_stm32_config *config = dev->config; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 194 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 195 | return LL_USART_GetParity(config->usart); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 196 | } |
| 197 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 198 | static inline void uart_stm32_set_stopbits(const struct device *dev, |
| 199 | uint32_t stopbits) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 200 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 201 | const struct uart_stm32_config *config = dev->config; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 202 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 203 | LL_USART_SetStopBitsLength(config->usart, stopbits); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 204 | } |
| 205 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 206 | static inline uint32_t uart_stm32_get_stopbits(const struct device *dev) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 207 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 208 | const struct uart_stm32_config *config = dev->config; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 209 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 210 | return LL_USART_GetStopBitsLength(config->usart); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 211 | } |
| 212 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 213 | static inline void uart_stm32_set_databits(const struct device *dev, |
| 214 | uint32_t databits) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 215 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 216 | const struct uart_stm32_config *config = dev->config; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 217 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 218 | LL_USART_SetDataWidth(config->usart, databits); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 219 | } |
| 220 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 221 | static inline uint32_t uart_stm32_get_databits(const struct device *dev) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 222 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 223 | const struct uart_stm32_config *config = dev->config; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 224 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 225 | return LL_USART_GetDataWidth(config->usart); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 226 | } |
| 227 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 228 | static inline void uart_stm32_set_hwctrl(const struct device *dev, |
| 229 | uint32_t hwctrl) |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 230 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 231 | const struct uart_stm32_config *config = dev->config; |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 232 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 233 | LL_USART_SetHWFlowCtrl(config->usart, hwctrl); |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 234 | } |
| 235 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 236 | static inline uint32_t uart_stm32_get_hwctrl(const struct device *dev) |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 237 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 238 | const struct uart_stm32_config *config = dev->config; |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 239 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 240 | return LL_USART_GetHWFlowCtrl(config->usart); |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 241 | } |
| 242 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 243 | static inline uint32_t uart_stm32_cfg2ll_parity(enum uart_config_parity parity) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 244 | { |
| 245 | switch (parity) { |
| 246 | case UART_CFG_PARITY_ODD: |
| 247 | return LL_USART_PARITY_ODD; |
| 248 | case UART_CFG_PARITY_EVEN: |
| 249 | return LL_USART_PARITY_EVEN; |
| 250 | case UART_CFG_PARITY_NONE: |
| 251 | default: |
| 252 | return LL_USART_PARITY_NONE; |
| 253 | } |
| 254 | } |
| 255 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 256 | static inline enum uart_config_parity uart_stm32_ll2cfg_parity(uint32_t parity) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 257 | { |
| 258 | switch (parity) { |
| 259 | case LL_USART_PARITY_ODD: |
| 260 | return UART_CFG_PARITY_ODD; |
| 261 | case LL_USART_PARITY_EVEN: |
| 262 | return UART_CFG_PARITY_EVEN; |
| 263 | case LL_USART_PARITY_NONE: |
| 264 | default: |
| 265 | return UART_CFG_PARITY_NONE; |
| 266 | } |
| 267 | } |
| 268 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 269 | static inline uint32_t uart_stm32_cfg2ll_stopbits(enum uart_config_stop_bits sb) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 270 | { |
| 271 | switch (sb) { |
| 272 | /* Some MCU's don't support 0.5 stop bits */ |
| 273 | #ifdef LL_USART_STOPBITS_0_5 |
| 274 | case UART_CFG_STOP_BITS_0_5: |
| 275 | return LL_USART_STOPBITS_0_5; |
| 276 | #endif /* LL_USART_STOPBITS_0_5 */ |
| 277 | case UART_CFG_STOP_BITS_1: |
| 278 | return LL_USART_STOPBITS_1; |
| 279 | /* Some MCU's don't support 1.5 stop bits */ |
| 280 | #ifdef LL_USART_STOPBITS_1_5 |
| 281 | case UART_CFG_STOP_BITS_1_5: |
| 282 | return LL_USART_STOPBITS_1_5; |
| 283 | #endif /* LL_USART_STOPBITS_1_5 */ |
| 284 | case UART_CFG_STOP_BITS_2: |
| 285 | default: |
| 286 | return LL_USART_STOPBITS_2; |
| 287 | } |
| 288 | } |
| 289 | |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 290 | static inline enum uart_config_stop_bits uart_stm32_ll2cfg_stopbits(uint32_t sb) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 291 | { |
| 292 | switch (sb) { |
| 293 | /* Some MCU's don't support 0.5 stop bits */ |
| 294 | #ifdef LL_USART_STOPBITS_0_5 |
| 295 | case LL_USART_STOPBITS_0_5: |
| 296 | return UART_CFG_STOP_BITS_0_5; |
| 297 | #endif /* LL_USART_STOPBITS_0_5 */ |
| 298 | case LL_USART_STOPBITS_1: |
| 299 | return UART_CFG_STOP_BITS_1; |
| 300 | /* Some MCU's don't support 1.5 stop bits */ |
| 301 | #ifdef LL_USART_STOPBITS_1_5 |
| 302 | case LL_USART_STOPBITS_1_5: |
| 303 | return UART_CFG_STOP_BITS_1_5; |
| 304 | #endif /* LL_USART_STOPBITS_1_5 */ |
| 305 | case LL_USART_STOPBITS_2: |
| 306 | default: |
| 307 | return UART_CFG_STOP_BITS_2; |
| 308 | } |
| 309 | } |
| 310 | |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 311 | static inline uint32_t uart_stm32_cfg2ll_databits(enum uart_config_data_bits db, |
| 312 | enum uart_config_parity p) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 313 | { |
| 314 | switch (db) { |
Benoit Leforestier | 9fee67d | 2019-03-22 14:19:57 +0100 | [diff] [blame] | 315 | /* Some MCU's don't support 7B or 9B datawidth */ |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 316 | #ifdef LL_USART_DATAWIDTH_7B |
| 317 | case UART_CFG_DATA_BITS_7: |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 318 | if (p == UART_CFG_PARITY_NONE) { |
| 319 | return LL_USART_DATAWIDTH_7B; |
| 320 | } else { |
| 321 | return LL_USART_DATAWIDTH_8B; |
| 322 | } |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 323 | #endif /* LL_USART_DATAWIDTH_7B */ |
Benoit Leforestier | 9fee67d | 2019-03-22 14:19:57 +0100 | [diff] [blame] | 324 | #ifdef LL_USART_DATAWIDTH_9B |
| 325 | case UART_CFG_DATA_BITS_9: |
| 326 | return LL_USART_DATAWIDTH_9B; |
| 327 | #endif /* LL_USART_DATAWIDTH_9B */ |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 328 | case UART_CFG_DATA_BITS_8: |
| 329 | default: |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 330 | if (p == UART_CFG_PARITY_NONE) { |
| 331 | return LL_USART_DATAWIDTH_8B; |
| 332 | #ifdef LL_USART_DATAWIDTH_9B |
| 333 | } else { |
| 334 | return LL_USART_DATAWIDTH_9B; |
| 335 | #endif |
| 336 | } |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 337 | return LL_USART_DATAWIDTH_8B; |
| 338 | } |
| 339 | } |
| 340 | |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 341 | static inline enum uart_config_data_bits uart_stm32_ll2cfg_databits(uint32_t db, |
| 342 | uint32_t p) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 343 | { |
| 344 | switch (db) { |
Benoit Leforestier | 9fee67d | 2019-03-22 14:19:57 +0100 | [diff] [blame] | 345 | /* Some MCU's don't support 7B or 9B datawidth */ |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 346 | #ifdef LL_USART_DATAWIDTH_7B |
| 347 | case LL_USART_DATAWIDTH_7B: |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 348 | if (p == LL_USART_PARITY_NONE) { |
| 349 | return UART_CFG_DATA_BITS_7; |
| 350 | } else { |
| 351 | return UART_CFG_DATA_BITS_6; |
| 352 | } |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 353 | #endif /* LL_USART_DATAWIDTH_7B */ |
Benoit Leforestier | 9fee67d | 2019-03-22 14:19:57 +0100 | [diff] [blame] | 354 | #ifdef LL_USART_DATAWIDTH_9B |
| 355 | case LL_USART_DATAWIDTH_9B: |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 356 | if (p == LL_USART_PARITY_NONE) { |
| 357 | return UART_CFG_DATA_BITS_9; |
| 358 | } else { |
| 359 | return UART_CFG_DATA_BITS_8; |
| 360 | } |
Benoit Leforestier | 9fee67d | 2019-03-22 14:19:57 +0100 | [diff] [blame] | 361 | #endif /* LL_USART_DATAWIDTH_9B */ |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 362 | case LL_USART_DATAWIDTH_8B: |
| 363 | default: |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 364 | if (p == LL_USART_PARITY_NONE) { |
| 365 | return UART_CFG_DATA_BITS_8; |
| 366 | } else { |
| 367 | return UART_CFG_DATA_BITS_7; |
| 368 | } |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 369 | } |
| 370 | } |
| 371 | |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 372 | /** |
| 373 | * @brief Get LL hardware flow control define from |
| 374 | * Zephyr hardware flow control option. |
| 375 | * @note Supports only UART_CFG_FLOW_CTRL_RTS_CTS. |
| 376 | * @param fc: Zephyr hardware flow control option. |
| 377 | * @retval LL_USART_HWCONTROL_RTS_CTS, or LL_USART_HWCONTROL_NONE. |
| 378 | */ |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 379 | static inline uint32_t uart_stm32_cfg2ll_hwctrl(enum uart_config_flow_control fc) |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 380 | { |
| 381 | if (fc == UART_CFG_FLOW_CTRL_RTS_CTS) { |
| 382 | return LL_USART_HWCONTROL_RTS_CTS; |
| 383 | } |
| 384 | |
| 385 | return LL_USART_HWCONTROL_NONE; |
| 386 | } |
| 387 | |
| 388 | /** |
Yannis Damigos | a4b448e | 2020-02-06 20:36:03 +0200 | [diff] [blame] | 389 | * @brief Get Zephyr hardware flow control option from |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 390 | * LL hardware flow control define. |
| 391 | * @note Supports only LL_USART_HWCONTROL_RTS_CTS. |
Yannis Damigos | a4b448e | 2020-02-06 20:36:03 +0200 | [diff] [blame] | 392 | * @param fc: LL hardware flow control definition. |
Kumar Gala | 6115346 | 2020-02-06 11:30:05 -0600 | [diff] [blame] | 393 | * @retval UART_CFG_FLOW_CTRL_RTS_CTS, or UART_CFG_FLOW_CTRL_NONE. |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 394 | */ |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 395 | static inline enum uart_config_flow_control uart_stm32_ll2cfg_hwctrl(uint32_t fc) |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 396 | { |
| 397 | if (fc == LL_USART_HWCONTROL_RTS_CTS) { |
| 398 | return UART_CFG_FLOW_CTRL_RTS_CTS; |
| 399 | } |
| 400 | |
Kumar Gala | 6115346 | 2020-02-06 11:30:05 -0600 | [diff] [blame] | 401 | return UART_CFG_FLOW_CTRL_NONE; |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 402 | } |
| 403 | |
Daniel Leung | 4e1692f | 2021-05-26 12:33:37 -0700 | [diff] [blame] | 404 | #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 405 | static int uart_stm32_configure(const struct device *dev, |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 406 | const struct uart_config *cfg) |
| 407 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 408 | const struct uart_stm32_config *config = dev->config; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 409 | struct uart_stm32_data *data = dev->data; |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 410 | const uint32_t parity = uart_stm32_cfg2ll_parity(cfg->parity); |
| 411 | const uint32_t stopbits = uart_stm32_cfg2ll_stopbits(cfg->stop_bits); |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 412 | const uint32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits, |
| 413 | cfg->parity); |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 414 | const uint32_t flowctrl = uart_stm32_cfg2ll_hwctrl(cfg->flow_ctrl); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 415 | |
| 416 | /* Hardware doesn't support mark or space parity */ |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 417 | if ((cfg->parity == UART_CFG_PARITY_MARK) || |
| 418 | (cfg->parity == UART_CFG_PARITY_SPACE)) { |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 419 | return -ENOTSUP; |
| 420 | } |
| 421 | |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 422 | /* Driver does not supports parity + 9 databits */ |
| 423 | if ((cfg->parity != UART_CFG_PARITY_NONE) && |
| 424 | (cfg->data_bits == UART_CFG_DATA_BITS_9)) { |
| 425 | return -ENOTSUP; |
| 426 | } |
| 427 | |
Erwan Gouriou | 76313f0 | 2020-04-17 12:33:29 +0200 | [diff] [blame] | 428 | #if defined(LL_USART_STOPBITS_0_5) && HAS_LPUART_1 |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 429 | if (IS_LPUART_INSTANCE(config->usart) && |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 430 | (cfg->stop_bits == UART_CFG_STOP_BITS_0_5)) { |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 431 | return -ENOTSUP; |
| 432 | } |
| 433 | #else |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 434 | if (cfg->stop_bits == UART_CFG_STOP_BITS_0_5) { |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 435 | return -ENOTSUP; |
| 436 | } |
| 437 | #endif |
| 438 | |
Erwan Gouriou | 76313f0 | 2020-04-17 12:33:29 +0200 | [diff] [blame] | 439 | #if defined(LL_USART_STOPBITS_1_5) && HAS_LPUART_1 |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 440 | if (IS_LPUART_INSTANCE(config->usart) && |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 441 | (cfg->stop_bits == UART_CFG_STOP_BITS_1_5)) { |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 442 | return -ENOTSUP; |
| 443 | } |
| 444 | #else |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 445 | if (cfg->stop_bits == UART_CFG_STOP_BITS_1_5) { |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 446 | return -ENOTSUP; |
| 447 | } |
| 448 | #endif |
| 449 | |
Benoit Leforestier | 9fee67d | 2019-03-22 14:19:57 +0100 | [diff] [blame] | 450 | /* Driver doesn't support 5 or 6 databits and potentially 7 or 9 */ |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 451 | if ((cfg->data_bits == UART_CFG_DATA_BITS_5) || |
| 452 | (cfg->data_bits == UART_CFG_DATA_BITS_6) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 453 | #ifndef LL_USART_DATAWIDTH_7B |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 454 | || (cfg->data_bits == UART_CFG_DATA_BITS_7) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 455 | #endif /* LL_USART_DATAWIDTH_7B */ |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 456 | || (cfg->data_bits == UART_CFG_DATA_BITS_9)) { |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 457 | return -ENOTSUP; |
| 458 | } |
| 459 | |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 460 | /* Driver supports only RTS CTS flow control */ |
Erwan Gouriou | 5e56170 | 2021-02-11 09:55:38 +0100 | [diff] [blame] | 461 | if (cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 462 | if (!IS_UART_HWFLOW_INSTANCE(config->usart) || |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 463 | UART_CFG_FLOW_CTRL_RTS_CTS != cfg->flow_ctrl) { |
| 464 | return -ENOTSUP; |
| 465 | } |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 466 | } |
| 467 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 468 | LL_USART_Disable(config->usart); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 469 | |
| 470 | if (parity != uart_stm32_get_parity(dev)) { |
| 471 | uart_stm32_set_parity(dev, parity); |
| 472 | } |
| 473 | |
| 474 | if (stopbits != uart_stm32_get_stopbits(dev)) { |
| 475 | uart_stm32_set_stopbits(dev, stopbits); |
| 476 | } |
| 477 | |
| 478 | if (databits != uart_stm32_get_databits(dev)) { |
| 479 | uart_stm32_set_databits(dev, databits); |
| 480 | } |
| 481 | |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 482 | if (flowctrl != uart_stm32_get_hwctrl(dev)) { |
| 483 | uart_stm32_set_hwctrl(dev, flowctrl); |
| 484 | } |
| 485 | |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 486 | if (cfg->baudrate != data->baud_rate) { |
| 487 | uart_stm32_set_baudrate(dev, cfg->baudrate); |
| 488 | data->baud_rate = cfg->baudrate; |
| 489 | } |
| 490 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 491 | LL_USART_Enable(config->usart); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 492 | return 0; |
| 493 | }; |
| 494 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 495 | static int uart_stm32_config_get(const struct device *dev, |
| 496 | struct uart_config *cfg) |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 497 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 498 | struct uart_stm32_data *data = dev->data; |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 499 | |
| 500 | cfg->baudrate = data->baud_rate; |
| 501 | cfg->parity = uart_stm32_ll2cfg_parity(uart_stm32_get_parity(dev)); |
| 502 | cfg->stop_bits = uart_stm32_ll2cfg_stopbits( |
| 503 | uart_stm32_get_stopbits(dev)); |
| 504 | cfg->data_bits = uart_stm32_ll2cfg_databits( |
Nicolas VINCENT | 573eec1 | 2021-03-10 13:23:00 +0100 | [diff] [blame] | 505 | uart_stm32_get_databits(dev), uart_stm32_get_parity(dev)); |
Georgij Cernysiov | 78eed34 | 2019-03-15 19:51:09 +0100 | [diff] [blame] | 506 | cfg->flow_ctrl = uart_stm32_ll2cfg_hwctrl( |
| 507 | uart_stm32_get_hwctrl(dev)); |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 508 | return 0; |
| 509 | } |
Daniel Leung | 4e1692f | 2021-05-26 12:33:37 -0700 | [diff] [blame] | 510 | #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 511 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 512 | static int uart_stm32_poll_in(const struct device *dev, unsigned char *c) |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 513 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 514 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 515 | |
Kiril Zyapkov | 7a602fc | 2018-11-02 15:34:56 +0200 | [diff] [blame] | 516 | /* Clear overrun error flag */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 517 | if (LL_USART_IsActiveFlag_ORE(config->usart)) { |
| 518 | LL_USART_ClearFlag_ORE(config->usart); |
Kiril Zyapkov | 7a602fc | 2018-11-02 15:34:56 +0200 | [diff] [blame] | 519 | } |
| 520 | |
Francois Ramu | 860bd87 | 2022-01-28 16:52:28 +0100 | [diff] [blame] | 521 | /* |
| 522 | * On stm32 F4X, F1X, and F2X, the RXNE flag is affected (cleared) by |
| 523 | * the uart_err_check function call (on errors flags clearing) |
| 524 | */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 525 | if (!LL_USART_IsActiveFlag_RXNE(config->usart)) { |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 526 | return -1; |
| 527 | } |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 528 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 529 | *c = (unsigned char)LL_USART_ReceiveData8(config->usart); |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 530 | |
| 531 | return 0; |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 532 | } |
| 533 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 534 | static void uart_stm32_poll_out(const struct device *dev, |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 535 | unsigned char c) |
| 536 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 537 | const struct uart_stm32_config *config = dev->config; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 538 | #ifdef CONFIG_PM |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 539 | struct uart_stm32_data *data = dev->data; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 540 | #endif |
Johann Fischer | 5e5ea9a | 2022-07-13 16:50:25 +0200 | [diff] [blame] | 541 | unsigned int key; |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 542 | |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 543 | /* Wait for TXE flag to be raised |
| 544 | * When TXE flag is raised, we lock interrupts to prevent interrupts (notably that of usart) |
| 545 | * or thread switch. Then, we can safely send our character. The character sent will be |
| 546 | * interlaced with the characters potentially send with interrupt transmission API |
| 547 | */ |
Julien D'ascenzio | d42cef1 | 2021-11-08 12:47:25 +0100 | [diff] [blame] | 548 | while (1) { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 549 | if (LL_USART_IsActiveFlag_TXE(config->usart)) { |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 550 | key = irq_lock(); |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 551 | if (LL_USART_IsActiveFlag_TXE(config->usart)) { |
Julien D'ascenzio | d42cef1 | 2021-11-08 12:47:25 +0100 | [diff] [blame] | 552 | break; |
| 553 | } |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 554 | irq_unlock(key); |
| 555 | } |
Anas Nashif | 4c32258 | 2019-06-04 10:52:23 -0400 | [diff] [blame] | 556 | } |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 557 | |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 558 | #ifdef CONFIG_PM |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 559 | |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 560 | /* If an interrupt transmission is in progress, the pm constraint is already managed by the |
| 561 | * call of uart_stm32_irq_tx_[en|dis]able |
| 562 | */ |
| 563 | if (!data->tx_poll_stream_on && !data->tx_int_stream_on) { |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 564 | data->tx_poll_stream_on = true; |
| 565 | |
| 566 | /* Don't allow system to suspend until stream |
| 567 | * transmission has completed |
| 568 | */ |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 569 | uart_stm32_pm_policy_state_lock_get(dev); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 570 | |
| 571 | /* Enable TC interrupt so we can release suspend |
| 572 | * constraint when done |
| 573 | */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 574 | LL_USART_EnableIT_TC(config->usart); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 575 | } |
| 576 | #endif /* CONFIG_PM */ |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 577 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 578 | LL_USART_TransmitData8(config->usart, (uint8_t)c); |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 579 | irq_unlock(key); |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 580 | } |
| 581 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 582 | static int uart_stm32_err_check(const struct device *dev) |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 583 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 584 | const struct uart_stm32_config *config = dev->config; |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 585 | uint32_t err = 0U; |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 586 | |
Francois Ramu | 860bd87 | 2022-01-28 16:52:28 +0100 | [diff] [blame] | 587 | /* Check for errors, then clear them. |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 588 | * Some SoC clear all error flags when at least |
Francois Ramu | 860bd87 | 2022-01-28 16:52:28 +0100 | [diff] [blame] | 589 | * one is cleared. (e.g. F4X, F1X, and F2X). |
| 590 | * The stm32 F4X, F1X, and F2X also reads the usart DR when clearing Errors |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 591 | */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 592 | if (LL_USART_IsActiveFlag_ORE(config->usart)) { |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 593 | err |= UART_ERROR_OVERRUN; |
| 594 | } |
| 595 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 596 | if (LL_USART_IsActiveFlag_PE(config->usart)) { |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 597 | err |= UART_ERROR_PARITY; |
| 598 | } |
| 599 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 600 | if (LL_USART_IsActiveFlag_FE(config->usart)) { |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 601 | err |= UART_ERROR_FRAMING; |
| 602 | } |
| 603 | |
Andrea Campanella | b2190fd | 2021-12-21 16:09:15 +0000 | [diff] [blame] | 604 | #if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT) |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 605 | if (LL_USART_IsActiveFlag_LBD(config->usart)) { |
Andrea Campanella | b2190fd | 2021-12-21 16:09:15 +0000 | [diff] [blame] | 606 | err |= UART_BREAK; |
| 607 | } |
| 608 | |
| 609 | if (err & UART_BREAK) { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 610 | LL_USART_ClearFlag_LBD(config->usart); |
Andrea Campanella | b2190fd | 2021-12-21 16:09:15 +0000 | [diff] [blame] | 611 | } |
| 612 | #endif |
Francois Ramu | 860bd87 | 2022-01-28 16:52:28 +0100 | [diff] [blame] | 613 | /* Clearing error : |
| 614 | * the stm32 F4X, F1X, and F2X sw sequence is reading the usart SR |
| 615 | * then the usart DR to clear the Error flags ORE, PE, FE, NE |
| 616 | * --> so is the RXNE flag also cleared ! |
| 617 | */ |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 618 | if (err & UART_ERROR_OVERRUN) { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 619 | LL_USART_ClearFlag_ORE(config->usart); |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | if (err & UART_ERROR_PARITY) { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 623 | LL_USART_ClearFlag_PE(config->usart); |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 624 | } |
| 625 | |
| 626 | if (err & UART_ERROR_FRAMING) { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 627 | LL_USART_ClearFlag_FE(config->usart); |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 628 | } |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 629 | /* Clear noise error as well, |
| 630 | * it is not represented by the errors enum |
| 631 | */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 632 | LL_USART_ClearFlag_NE(config->usart); |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 633 | |
| 634 | return err; |
| 635 | } |
| 636 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 637 | static inline void __uart_stm32_get_clock(const struct device *dev) |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 638 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 639 | struct uart_stm32_data *data = dev->data; |
Kumar Gala | b275fec | 2021-02-11 11:49:24 -0600 | [diff] [blame] | 640 | const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 641 | |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 642 | data->clock = clk; |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 643 | } |
| 644 | |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 645 | #ifdef CONFIG_UART_INTERRUPT_DRIVEN |
| 646 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 647 | static int uart_stm32_fifo_fill(const struct device *dev, |
| 648 | const uint8_t *tx_data, |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 649 | int size) |
| 650 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 651 | const struct uart_stm32_config *config = dev->config; |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 652 | uint8_t num_tx = 0U; |
Johann Fischer | 5e5ea9a | 2022-07-13 16:50:25 +0200 | [diff] [blame] | 653 | unsigned int key; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 654 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 655 | if (!LL_USART_IsActiveFlag_TXE(config->usart)) { |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 656 | return num_tx; |
| 657 | } |
| 658 | |
| 659 | /* Lock interrupts to prevent nested interrupts or thread switch */ |
| 660 | key = irq_lock(); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 661 | |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 662 | while ((size - num_tx > 0) && |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 663 | LL_USART_IsActiveFlag_TXE(config->usart)) { |
Georgij Cernysiov | 3de55da | 2019-02-06 23:31:24 +0100 | [diff] [blame] | 664 | /* TXE flag will be cleared with byte write to DR|RDR register */ |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 665 | |
| 666 | /* Send a character (8bit , parity none) */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 667 | LL_USART_TransmitData8(config->usart, tx_data[num_tx++]); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 668 | } |
| 669 | |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 670 | irq_unlock(key); |
| 671 | |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 672 | return num_tx; |
| 673 | } |
| 674 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 675 | static int uart_stm32_fifo_read(const struct device *dev, uint8_t *rx_data, |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 676 | const int size) |
| 677 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 678 | const struct uart_stm32_config *config = dev->config; |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 679 | uint8_t num_rx = 0U; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 680 | |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 681 | while ((size - num_rx > 0) && |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 682 | LL_USART_IsActiveFlag_RXNE(config->usart)) { |
Georgij Cernysiov | 3de55da | 2019-02-06 23:31:24 +0100 | [diff] [blame] | 683 | /* RXNE flag will be cleared upon read from DR|RDR register */ |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 684 | |
| 685 | /* Receive a character (8bit , parity none) */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 686 | rx_data[num_rx++] = LL_USART_ReceiveData8(config->usart); |
Kiril Zyapkov | 7a602fc | 2018-11-02 15:34:56 +0200 | [diff] [blame] | 687 | |
| 688 | /* Clear overrun error flag */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 689 | if (LL_USART_IsActiveFlag_ORE(config->usart)) { |
| 690 | LL_USART_ClearFlag_ORE(config->usart); |
Francois Ramu | 860bd87 | 2022-01-28 16:52:28 +0100 | [diff] [blame] | 691 | /* |
| 692 | * On stm32 F4X, F1X, and F2X, the RXNE flag is affected (cleared) by |
| 693 | * the uart_err_check function call (on errors flags clearing) |
| 694 | */ |
Kiril Zyapkov | 7a602fc | 2018-11-02 15:34:56 +0200 | [diff] [blame] | 695 | } |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 696 | } |
Georgij Cernysiov | 3de55da | 2019-02-06 23:31:24 +0100 | [diff] [blame] | 697 | |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 698 | return num_rx; |
| 699 | } |
| 700 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 701 | static void uart_stm32_irq_tx_enable(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 702 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 703 | const struct uart_stm32_config *config = dev->config; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 704 | #ifdef CONFIG_PM |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 705 | struct uart_stm32_data *data = dev->data; |
Johann Fischer | 5e5ea9a | 2022-07-13 16:50:25 +0200 | [diff] [blame] | 706 | unsigned int key; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 707 | #endif |
Julien D'ascenzio | d42cef1 | 2021-11-08 12:47:25 +0100 | [diff] [blame] | 708 | |
| 709 | #ifdef CONFIG_PM |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 710 | key = irq_lock(); |
Julien D'ascenzio | 7b21050 | 2021-10-26 18:03:31 +0200 | [diff] [blame] | 711 | data->tx_poll_stream_on = false; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 712 | data->tx_int_stream_on = true; |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 713 | uart_stm32_pm_policy_state_lock_get(dev); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 714 | #endif |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 715 | LL_USART_EnableIT_TC(config->usart); |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 716 | |
| 717 | #ifdef CONFIG_PM |
| 718 | irq_unlock(key); |
| 719 | #endif |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 720 | } |
| 721 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 722 | static void uart_stm32_irq_tx_disable(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 723 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 724 | const struct uart_stm32_config *config = dev->config; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 725 | #ifdef CONFIG_PM |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 726 | struct uart_stm32_data *data = dev->data; |
Johann Fischer | 5e5ea9a | 2022-07-13 16:50:25 +0200 | [diff] [blame] | 727 | unsigned int key; |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 728 | |
| 729 | key = irq_lock(); |
| 730 | #endif |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 731 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 732 | LL_USART_DisableIT_TC(config->usart); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 733 | |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 734 | #ifdef CONFIG_PM |
| 735 | data->tx_int_stream_on = false; |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 736 | uart_stm32_pm_policy_state_lock_put(dev); |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 737 | #endif |
Julien D'ascenzio | d42cef1 | 2021-11-08 12:47:25 +0100 | [diff] [blame] | 738 | |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 739 | #ifdef CONFIG_PM |
Julien D'ascenzio | e4234ae | 2021-12-01 10:19:44 +0100 | [diff] [blame] | 740 | irq_unlock(key); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 741 | #endif |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 742 | } |
| 743 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 744 | static int uart_stm32_irq_tx_ready(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 745 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 746 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 747 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 748 | return LL_USART_IsActiveFlag_TXE(config->usart) && |
| 749 | LL_USART_IsEnabledIT_TC(config->usart); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 750 | } |
| 751 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 752 | static int uart_stm32_irq_tx_complete(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 753 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 754 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 755 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 756 | return LL_USART_IsActiveFlag_TC(config->usart); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 757 | } |
| 758 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 759 | static void uart_stm32_irq_rx_enable(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 760 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 761 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 762 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 763 | LL_USART_EnableIT_RXNE(config->usart); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 764 | } |
| 765 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 766 | static void uart_stm32_irq_rx_disable(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 767 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 768 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 769 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 770 | LL_USART_DisableIT_RXNE(config->usart); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 771 | } |
| 772 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 773 | static int uart_stm32_irq_rx_ready(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 774 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 775 | const struct uart_stm32_config *config = dev->config; |
Francois Ramu | 860bd87 | 2022-01-28 16:52:28 +0100 | [diff] [blame] | 776 | /* |
| 777 | * On stm32 F4X, F1X, and F2X, the RXNE flag is affected (cleared) by |
| 778 | * the uart_err_check function call (on errors flags clearing) |
| 779 | */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 780 | return LL_USART_IsActiveFlag_RXNE(config->usart); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 781 | } |
| 782 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 783 | static void uart_stm32_irq_err_enable(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 784 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 785 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 786 | |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 787 | /* Enable FE, ORE interruptions */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 788 | LL_USART_EnableIT_ERROR(config->usart); |
Ilya Tagunov | 967c31b | 2018-03-29 19:40:00 +0300 | [diff] [blame] | 789 | #if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT) |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 790 | /* Enable Line break detection */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 791 | if (IS_UART_LIN_INSTANCE(config->usart)) { |
| 792 | LL_USART_EnableIT_LBD(config->usart); |
Ilya Tagunov | 967c31b | 2018-03-29 19:40:00 +0300 | [diff] [blame] | 793 | } |
Maciej Debski | eaff37e | 2017-08-09 11:23:04 +0200 | [diff] [blame] | 794 | #endif |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 795 | /* Enable parity error interruption */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 796 | LL_USART_EnableIT_PE(config->usart); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 797 | } |
| 798 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 799 | static void uart_stm32_irq_err_disable(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 800 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 801 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 802 | |
Ilya Tagunov | 967c31b | 2018-03-29 19:40:00 +0300 | [diff] [blame] | 803 | /* Disable FE, ORE interruptions */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 804 | LL_USART_DisableIT_ERROR(config->usart); |
Ilya Tagunov | 967c31b | 2018-03-29 19:40:00 +0300 | [diff] [blame] | 805 | #if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT) |
| 806 | /* Disable Line break detection */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 807 | if (IS_UART_LIN_INSTANCE(config->usart)) { |
| 808 | LL_USART_DisableIT_LBD(config->usart); |
Ilya Tagunov | 967c31b | 2018-03-29 19:40:00 +0300 | [diff] [blame] | 809 | } |
Maciej Debski | eaff37e | 2017-08-09 11:23:04 +0200 | [diff] [blame] | 810 | #endif |
Ilya Tagunov | 967c31b | 2018-03-29 19:40:00 +0300 | [diff] [blame] | 811 | /* Disable parity error interruption */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 812 | LL_USART_DisableIT_PE(config->usart); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 813 | } |
| 814 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 815 | static int uart_stm32_irq_is_pending(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 816 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 817 | const struct uart_stm32_config *config = dev->config; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 818 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 819 | return ((LL_USART_IsActiveFlag_RXNE(config->usart) && |
| 820 | LL_USART_IsEnabledIT_RXNE(config->usart)) || |
| 821 | (LL_USART_IsActiveFlag_TC(config->usart) && |
| 822 | LL_USART_IsEnabledIT_TC(config->usart))); |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 823 | } |
| 824 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 825 | static int uart_stm32_irq_update(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 826 | { |
| 827 | return 1; |
| 828 | } |
| 829 | |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 830 | static void uart_stm32_irq_callback_set(const struct device *dev, |
Paul Sokolovsky | 57286af | 2018-07-16 21:12:26 +0300 | [diff] [blame] | 831 | uart_irq_callback_user_data_t cb, |
| 832 | void *cb_data) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 833 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 834 | struct uart_stm32_data *data = dev->data; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 835 | |
| 836 | data->user_cb = cb; |
Paul Sokolovsky | 57286af | 2018-07-16 21:12:26 +0300 | [diff] [blame] | 837 | data->user_data = cb_data; |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 838 | } |
| 839 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 840 | #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ |
| 841 | |
| 842 | #ifdef CONFIG_UART_ASYNC_API |
| 843 | |
| 844 | static inline void async_user_callback(struct uart_stm32_data *data, |
| 845 | struct uart_event *event) |
| 846 | { |
| 847 | if (data->async_cb) { |
| 848 | data->async_cb(data->uart_dev, event, data->async_user_data); |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | static inline void async_evt_rx_rdy(struct uart_stm32_data *data) |
| 853 | { |
| 854 | LOG_DBG("rx_rdy: (%d %d)", data->dma_rx.offset, data->dma_rx.counter); |
| 855 | |
| 856 | struct uart_event event = { |
| 857 | .type = UART_RX_RDY, |
| 858 | .data.rx.buf = data->dma_rx.buffer, |
| 859 | .data.rx.len = data->dma_rx.counter - data->dma_rx.offset, |
| 860 | .data.rx.offset = data->dma_rx.offset |
| 861 | }; |
| 862 | |
Alexander Shuklin | 6831b8b | 2021-02-04 12:00:49 +0300 | [diff] [blame] | 863 | /* update the current pos for new data */ |
| 864 | data->dma_rx.offset = data->dma_rx.counter; |
| 865 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 866 | /* send event only for new data */ |
| 867 | if (event.data.rx.len > 0) { |
| 868 | async_user_callback(data, &event); |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | static inline void async_evt_rx_err(struct uart_stm32_data *data, int err_code) |
| 873 | { |
| 874 | LOG_DBG("rx error: %d", err_code); |
| 875 | |
| 876 | struct uart_event event = { |
| 877 | .type = UART_RX_STOPPED, |
| 878 | .data.rx_stop.reason = err_code, |
| 879 | .data.rx_stop.data.len = data->dma_rx.counter, |
| 880 | .data.rx_stop.data.offset = 0, |
| 881 | .data.rx_stop.data.buf = data->dma_rx.buffer |
| 882 | }; |
| 883 | |
| 884 | async_user_callback(data, &event); |
| 885 | } |
| 886 | |
| 887 | static inline void async_evt_tx_done(struct uart_stm32_data *data) |
| 888 | { |
| 889 | LOG_DBG("tx done: %d", data->dma_tx.counter); |
| 890 | |
| 891 | struct uart_event event = { |
| 892 | .type = UART_TX_DONE, |
| 893 | .data.tx.buf = data->dma_tx.buffer, |
| 894 | .data.tx.len = data->dma_tx.counter |
| 895 | }; |
| 896 | |
| 897 | /* Reset tx buffer */ |
| 898 | data->dma_tx.buffer_length = 0; |
| 899 | data->dma_tx.counter = 0; |
| 900 | |
| 901 | async_user_callback(data, &event); |
| 902 | } |
| 903 | |
| 904 | static inline void async_evt_tx_abort(struct uart_stm32_data *data) |
| 905 | { |
| 906 | LOG_DBG("tx abort: %d", data->dma_tx.counter); |
| 907 | |
| 908 | struct uart_event event = { |
| 909 | .type = UART_TX_ABORTED, |
| 910 | .data.tx.buf = data->dma_tx.buffer, |
| 911 | .data.tx.len = data->dma_tx.counter |
| 912 | }; |
| 913 | |
| 914 | /* Reset tx buffer */ |
| 915 | data->dma_tx.buffer_length = 0; |
| 916 | data->dma_tx.counter = 0; |
| 917 | |
| 918 | async_user_callback(data, &event); |
| 919 | } |
| 920 | |
| 921 | static inline void async_evt_rx_buf_request(struct uart_stm32_data *data) |
| 922 | { |
| 923 | struct uart_event evt = { |
| 924 | .type = UART_RX_BUF_REQUEST, |
| 925 | }; |
| 926 | |
| 927 | async_user_callback(data, &evt); |
| 928 | } |
| 929 | |
| 930 | static inline void async_evt_rx_buf_release(struct uart_stm32_data *data) |
| 931 | { |
| 932 | struct uart_event evt = { |
| 933 | .type = UART_RX_BUF_RELEASED, |
| 934 | .data.rx_buf.buf = data->dma_rx.buffer, |
| 935 | }; |
| 936 | |
| 937 | async_user_callback(data, &evt); |
| 938 | } |
| 939 | |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 940 | static inline void async_timer_start(struct k_work_delayable *work, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 941 | int32_t timeout) |
| 942 | { |
Krzysztof Chruscinski | c590b35 | 2021-10-01 15:47:40 +0200 | [diff] [blame] | 943 | if ((timeout != SYS_FOREVER_US) && (timeout != 0)) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 944 | /* start timer */ |
Krzysztof Chruscinski | c590b35 | 2021-10-01 15:47:40 +0200 | [diff] [blame] | 945 | LOG_DBG("async timer started for %d us", timeout); |
| 946 | k_work_reschedule(work, K_USEC(timeout)); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 947 | } |
| 948 | } |
| 949 | |
| 950 | static void uart_stm32_dma_rx_flush(const struct device *dev) |
| 951 | { |
| 952 | struct dma_status stat; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 953 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 954 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 955 | if (dma_get_status(data->dma_rx.dma_dev, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 956 | data->dma_rx.dma_channel, &stat) == 0) { |
| 957 | size_t rx_rcv_len = data->dma_rx.buffer_length - |
| 958 | stat.pending_length; |
| 959 | if (rx_rcv_len > data->dma_rx.offset) { |
| 960 | data->dma_rx.counter = rx_rcv_len; |
| 961 | |
| 962 | async_evt_rx_rdy(data); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 963 | } |
| 964 | } |
| 965 | } |
| 966 | |
| 967 | #endif /* CONFIG_UART_ASYNC_API */ |
| 968 | |
Erwan Gouriou | 79ff645 | 2021-09-21 09:34:09 +0200 | [diff] [blame] | 969 | #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || \ |
| 970 | defined(CONFIG_UART_ASYNC_API) || \ |
| 971 | defined(CONFIG_PM) |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 972 | |
Tomasz Bursztyka | 4dcfb55 | 2020-06-17 14:58:56 +0200 | [diff] [blame] | 973 | static void uart_stm32_isr(const struct device *dev) |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 974 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 975 | struct uart_stm32_data *data = dev->data; |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 976 | #if defined(CONFIG_PM) || defined(CONFIG_UART_ASYNC_API) |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 977 | const struct uart_stm32_config *config = dev->config; |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 978 | #endif |
| 979 | |
| 980 | #ifdef CONFIG_PM |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 981 | if (LL_USART_IsEnabledIT_TC(config->usart) && |
| 982 | LL_USART_IsActiveFlag_TC(config->usart)) { |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 983 | |
| 984 | if (data->tx_poll_stream_on) { |
Yegor Yefremov | 1155d46 | 2022-03-07 22:53:16 +0100 | [diff] [blame] | 985 | /* A poll stream transmission just completed, |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 986 | * allow system to suspend |
| 987 | */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 988 | LL_USART_DisableIT_TC(config->usart); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 989 | data->tx_poll_stream_on = false; |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 990 | uart_stm32_pm_policy_state_lock_put(dev); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 991 | } |
Yegor Yefremov | 1155d46 | 2022-03-07 22:53:16 +0100 | [diff] [blame] | 992 | /* Stream transmission was either async or IRQ based, |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 993 | * constraint will be released at the same time TC IT |
| 994 | * is disabled |
| 995 | */ |
| 996 | } |
| 997 | #endif |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 998 | |
Shlomi Vaknin | 1b4f7e5 | 2021-05-17 23:06:51 +0300 | [diff] [blame] | 999 | #ifdef CONFIG_UART_INTERRUPT_DRIVEN |
| 1000 | if (data->user_cb) { |
| 1001 | data->user_cb(dev, data->user_data); |
| 1002 | } |
| 1003 | #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ |
| 1004 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1005 | #ifdef CONFIG_UART_ASYNC_API |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1006 | if (LL_USART_IsEnabledIT_IDLE(config->usart) && |
| 1007 | LL_USART_IsActiveFlag_IDLE(config->usart)) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1008 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1009 | LL_USART_ClearFlag_IDLE(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1010 | |
| 1011 | LOG_DBG("idle interrupt occurred"); |
| 1012 | |
| 1013 | /* Start the RX timer */ |
| 1014 | async_timer_start(&data->dma_rx.timeout_work, |
| 1015 | data->dma_rx.timeout); |
| 1016 | |
| 1017 | if (data->dma_rx.timeout == 0) { |
| 1018 | uart_stm32_dma_rx_flush(dev); |
| 1019 | } |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1020 | } else if (LL_USART_IsEnabledIT_TC(config->usart) && |
| 1021 | LL_USART_IsActiveFlag_TC(config->usart)) { |
Zisis Adamos | 7235b09 | 2021-03-30 12:20:46 +0200 | [diff] [blame] | 1022 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1023 | LL_USART_DisableIT_TC(config->usart); |
| 1024 | LL_USART_ClearFlag_TC(config->usart); |
Zisis Adamos | 7235b09 | 2021-03-30 12:20:46 +0200 | [diff] [blame] | 1025 | /* Generate TX_DONE event when transmission is done */ |
| 1026 | async_evt_tx_done(data); |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1027 | |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 1028 | #ifdef CONFIG_PM |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 1029 | uart_stm32_pm_policy_state_lock_put(dev); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 1030 | #endif |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1031 | } else if (LL_USART_IsEnabledIT_RXNE(config->usart) && |
| 1032 | LL_USART_IsActiveFlag_RXNE(config->usart)) { |
Francois Ramu | cf60639 | 2021-11-08 11:43:53 +0100 | [diff] [blame] | 1033 | #ifdef USART_SR_RXNE |
| 1034 | /* clear the RXNE flag, because Rx data was not read */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1035 | LL_USART_ClearFlag_RXNE(config->usart); |
Francois Ramu | cf60639 | 2021-11-08 11:43:53 +0100 | [diff] [blame] | 1036 | #else |
Francois Ramu | 95e2c39 | 2021-10-26 11:39:57 +0200 | [diff] [blame] | 1037 | /* clear the RXNE by flushing the fifo, because Rx data was not read */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1038 | LL_USART_RequestRxDataFlush(config->usart); |
Francois Ramu | cf60639 | 2021-11-08 11:43:53 +0100 | [diff] [blame] | 1039 | #endif /* USART_SR_RXNE */ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1040 | } |
| 1041 | |
| 1042 | /* Clear errors */ |
| 1043 | uart_stm32_err_check(dev); |
| 1044 | #endif /* CONFIG_UART_ASYNC_API */ |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 1045 | } |
Erwan Gouriou | 79ff645 | 2021-09-21 09:34:09 +0200 | [diff] [blame] | 1046 | #endif /* CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API || CONFIG_PM */ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1047 | |
| 1048 | #ifdef CONFIG_UART_ASYNC_API |
| 1049 | |
| 1050 | static int uart_stm32_async_callback_set(const struct device *dev, |
| 1051 | uart_callback_t callback, |
| 1052 | void *user_data) |
| 1053 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1054 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1055 | |
| 1056 | data->async_cb = callback; |
| 1057 | data->async_user_data = user_data; |
| 1058 | |
| 1059 | return 0; |
| 1060 | } |
| 1061 | |
| 1062 | static inline void uart_stm32_dma_tx_enable(const struct device *dev) |
| 1063 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1064 | const struct uart_stm32_config *config = dev->config; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1065 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1066 | LL_USART_EnableDMAReq_TX(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1067 | } |
| 1068 | |
| 1069 | static inline void uart_stm32_dma_tx_disable(const struct device *dev) |
| 1070 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1071 | const struct uart_stm32_config *config = dev->config; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1072 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1073 | LL_USART_DisableDMAReq_TX(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1074 | } |
| 1075 | |
| 1076 | static inline void uart_stm32_dma_rx_enable(const struct device *dev) |
| 1077 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1078 | const struct uart_stm32_config *config = dev->config; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1079 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1080 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1081 | LL_USART_EnableDMAReq_RX(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1082 | |
| 1083 | data->dma_rx.enabled = true; |
| 1084 | } |
| 1085 | |
| 1086 | static inline void uart_stm32_dma_rx_disable(const struct device *dev) |
| 1087 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1088 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1089 | |
| 1090 | data->dma_rx.enabled = false; |
| 1091 | } |
| 1092 | |
| 1093 | static int uart_stm32_async_rx_disable(const struct device *dev) |
| 1094 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1095 | const struct uart_stm32_config *config = dev->config; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1096 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1097 | struct uart_event disabled_event = { |
| 1098 | .type = UART_RX_DISABLED |
| 1099 | }; |
| 1100 | |
| 1101 | if (!data->dma_rx.enabled) { |
| 1102 | async_user_callback(data, &disabled_event); |
| 1103 | return -EFAULT; |
| 1104 | } |
| 1105 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1106 | LL_USART_DisableIT_IDLE(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1107 | |
| 1108 | uart_stm32_dma_rx_flush(dev); |
| 1109 | |
| 1110 | async_evt_rx_buf_release(data); |
| 1111 | |
| 1112 | uart_stm32_dma_rx_disable(dev); |
| 1113 | |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 1114 | (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1115 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1116 | dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1117 | |
| 1118 | data->rx_next_buffer = NULL; |
| 1119 | data->rx_next_buffer_len = 0; |
| 1120 | |
Yegor Yefremov | 1155d46 | 2022-03-07 22:53:16 +0100 | [diff] [blame] | 1121 | /* When async rx is disabled, enable interruptible instance of uart to function normally */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1122 | LL_USART_EnableIT_RXNE(config->usart); |
Manojkumar Subramaniam | d79d26f | 2021-08-23 02:04:05 +0800 | [diff] [blame] | 1123 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1124 | LOG_DBG("rx: disabled"); |
| 1125 | |
| 1126 | async_user_callback(data, &disabled_event); |
| 1127 | |
| 1128 | return 0; |
| 1129 | } |
| 1130 | |
| 1131 | void uart_stm32_dma_tx_cb(const struct device *dma_dev, void *user_data, |
| 1132 | uint32_t channel, int status) |
| 1133 | { |
| 1134 | const struct device *uart_dev = user_data; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1135 | struct uart_stm32_data *data = uart_dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1136 | struct dma_status stat; |
| 1137 | unsigned int key = irq_lock(); |
| 1138 | |
| 1139 | /* Disable TX */ |
| 1140 | uart_stm32_dma_tx_disable(uart_dev); |
| 1141 | |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 1142 | (void)k_work_cancel_delayable(&data->dma_tx.timeout_work); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1143 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1144 | if (!dma_get_status(data->dma_tx.dma_dev, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1145 | data->dma_tx.dma_channel, &stat)) { |
| 1146 | data->dma_tx.counter = data->dma_tx.buffer_length - |
| 1147 | stat.pending_length; |
| 1148 | } |
| 1149 | |
Prema Jonathan van Win | 76dee39 | 2021-05-03 11:24:38 +0300 | [diff] [blame] | 1150 | data->dma_tx.buffer_length = 0; |
| 1151 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1152 | irq_unlock(key); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1153 | } |
| 1154 | |
| 1155 | static void uart_stm32_dma_replace_buffer(const struct device *dev) |
| 1156 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1157 | const struct uart_stm32_config *config = dev->config; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1158 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1159 | |
Yegor Yefremov | 1155d46 | 2022-03-07 22:53:16 +0100 | [diff] [blame] | 1160 | /* Replace the buffer and reload the DMA */ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1161 | LOG_DBG("Replacing RX buffer: %d", data->rx_next_buffer_len); |
| 1162 | |
| 1163 | /* reload DMA */ |
| 1164 | data->dma_rx.offset = 0; |
| 1165 | data->dma_rx.counter = 0; |
| 1166 | data->dma_rx.buffer = data->rx_next_buffer; |
| 1167 | data->dma_rx.buffer_length = data->rx_next_buffer_len; |
| 1168 | data->dma_rx.blk_cfg.block_size = data->dma_rx.buffer_length; |
| 1169 | data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; |
| 1170 | data->rx_next_buffer = NULL; |
| 1171 | data->rx_next_buffer_len = 0; |
| 1172 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1173 | dma_reload(data->dma_rx.dma_dev, data->dma_rx.dma_channel, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1174 | data->dma_rx.blk_cfg.source_address, |
| 1175 | data->dma_rx.blk_cfg.dest_address, |
| 1176 | data->dma_rx.blk_cfg.block_size); |
| 1177 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1178 | dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1179 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1180 | LL_USART_ClearFlag_IDLE(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1181 | |
| 1182 | /* Request next buffer */ |
| 1183 | async_evt_rx_buf_request(data); |
| 1184 | } |
| 1185 | |
| 1186 | void uart_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data, |
| 1187 | uint32_t channel, int status) |
| 1188 | { |
| 1189 | const struct device *uart_dev = user_data; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1190 | struct uart_stm32_data *data = uart_dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1191 | |
| 1192 | if (status != 0) { |
| 1193 | async_evt_rx_err(data, status); |
| 1194 | return; |
| 1195 | } |
| 1196 | |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 1197 | (void)k_work_cancel_delayable(&data->dma_rx.timeout_work); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1198 | |
| 1199 | /* true since this functions occurs when buffer if full */ |
| 1200 | data->dma_rx.counter = data->dma_rx.buffer_length; |
| 1201 | |
| 1202 | async_evt_rx_rdy(data); |
| 1203 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1204 | if (data->rx_next_buffer != NULL) { |
| 1205 | async_evt_rx_buf_release(data); |
| 1206 | |
| 1207 | /* replace the buffer when the current |
| 1208 | * is full and not the same as the next |
| 1209 | * one. |
| 1210 | */ |
| 1211 | uart_stm32_dma_replace_buffer(uart_dev); |
| 1212 | } else { |
| 1213 | /* Buffer full without valid next buffer, |
| 1214 | * an UART_RX_DISABLED event must be generated, |
| 1215 | * but uart_stm32_async_rx_disable() cannot be |
| 1216 | * called in ISR context. So force the RX timeout |
| 1217 | * to minimum value and let the RX timeout to do the job. |
| 1218 | */ |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 1219 | k_work_reschedule(&data->dma_rx.timeout_work, K_TICKS(1)); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | static int uart_stm32_async_tx(const struct device *dev, |
| 1224 | const uint8_t *tx_data, size_t buf_size, int32_t timeout) |
| 1225 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1226 | const struct uart_stm32_config *config = dev->config; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1227 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1228 | int ret; |
| 1229 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1230 | if (data->dma_tx.dma_dev == NULL) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1231 | return -ENODEV; |
| 1232 | } |
| 1233 | |
| 1234 | if (data->dma_tx.buffer_length != 0) { |
| 1235 | return -EBUSY; |
| 1236 | } |
| 1237 | |
| 1238 | data->dma_tx.buffer = (uint8_t *)tx_data; |
| 1239 | data->dma_tx.buffer_length = buf_size; |
| 1240 | data->dma_tx.timeout = timeout; |
| 1241 | |
| 1242 | LOG_DBG("tx: l=%d", data->dma_tx.buffer_length); |
| 1243 | |
Zisis Adamos | 7235b09 | 2021-03-30 12:20:46 +0200 | [diff] [blame] | 1244 | /* Clear TC flag */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1245 | LL_USART_ClearFlag_TC(config->usart); |
Zisis Adamos | 7235b09 | 2021-03-30 12:20:46 +0200 | [diff] [blame] | 1246 | |
| 1247 | /* Enable TC interrupt so we can signal correct TX done */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1248 | LL_USART_EnableIT_TC(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1249 | |
| 1250 | /* set source address */ |
| 1251 | data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer; |
| 1252 | data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length; |
| 1253 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1254 | ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1255 | &data->dma_tx.dma_cfg); |
| 1256 | |
| 1257 | if (ret != 0) { |
| 1258 | LOG_ERR("dma tx config error!"); |
| 1259 | return -EINVAL; |
| 1260 | } |
| 1261 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1262 | if (dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel)) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1263 | LOG_ERR("UART err: TX DMA start failed!"); |
| 1264 | return -EFAULT; |
| 1265 | } |
| 1266 | |
| 1267 | /* Start TX timer */ |
| 1268 | async_timer_start(&data->dma_tx.timeout_work, data->dma_tx.timeout); |
| 1269 | |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 1270 | #ifdef CONFIG_PM |
Erwan Gouriou | 79ff645 | 2021-09-21 09:34:09 +0200 | [diff] [blame] | 1271 | |
| 1272 | /* Do not allow system to suspend until transmission has completed */ |
Gerard Marull-Paretas | 5a71eeb | 2022-01-20 16:06:28 +0100 | [diff] [blame] | 1273 | uart_stm32_pm_policy_state_lock_get(dev); |
Erwan Gouriou | a3de3df | 2021-09-14 09:27:56 +0200 | [diff] [blame] | 1274 | #endif |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1275 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1276 | /* Enable TX DMA requests */ |
| 1277 | uart_stm32_dma_tx_enable(dev); |
| 1278 | |
| 1279 | return 0; |
| 1280 | } |
| 1281 | |
| 1282 | static int uart_stm32_async_rx_enable(const struct device *dev, |
| 1283 | uint8_t *rx_buf, size_t buf_size, int32_t timeout) |
| 1284 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1285 | const struct uart_stm32_config *config = dev->config; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1286 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1287 | int ret; |
| 1288 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1289 | if (data->dma_rx.dma_dev == NULL) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1290 | return -ENODEV; |
| 1291 | } |
| 1292 | |
| 1293 | if (data->dma_rx.enabled) { |
| 1294 | LOG_WRN("RX was already enabled"); |
| 1295 | return -EBUSY; |
| 1296 | } |
| 1297 | |
| 1298 | data->dma_rx.offset = 0; |
| 1299 | data->dma_rx.buffer = rx_buf; |
| 1300 | data->dma_rx.buffer_length = buf_size; |
| 1301 | data->dma_rx.counter = 0; |
| 1302 | data->dma_rx.timeout = timeout; |
| 1303 | |
| 1304 | /* Disable RX interrupts to let DMA to handle it */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1305 | LL_USART_DisableIT_RXNE(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1306 | |
| 1307 | data->dma_rx.blk_cfg.block_size = buf_size; |
| 1308 | data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer; |
| 1309 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1310 | ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1311 | &data->dma_rx.dma_cfg); |
| 1312 | |
| 1313 | if (ret != 0) { |
| 1314 | LOG_ERR("UART ERR: RX DMA config failed!"); |
| 1315 | return -EINVAL; |
| 1316 | } |
| 1317 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1318 | if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1319 | LOG_ERR("UART ERR: RX DMA start failed!"); |
| 1320 | return -EFAULT; |
| 1321 | } |
| 1322 | |
| 1323 | /* Enable RX DMA requests */ |
| 1324 | uart_stm32_dma_rx_enable(dev); |
| 1325 | |
| 1326 | /* Enable IRQ IDLE to define the end of a |
| 1327 | * RX DMA transaction. |
| 1328 | */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1329 | LL_USART_ClearFlag_IDLE(config->usart); |
| 1330 | LL_USART_EnableIT_IDLE(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1331 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1332 | LL_USART_EnableIT_ERROR(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1333 | |
| 1334 | /* Request next buffer */ |
| 1335 | async_evt_rx_buf_request(data); |
| 1336 | |
| 1337 | LOG_DBG("async rx enabled"); |
| 1338 | |
| 1339 | return ret; |
| 1340 | } |
| 1341 | |
| 1342 | static int uart_stm32_async_tx_abort(const struct device *dev) |
| 1343 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1344 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1345 | size_t tx_buffer_length = data->dma_tx.buffer_length; |
| 1346 | struct dma_status stat; |
| 1347 | |
| 1348 | if (tx_buffer_length == 0) { |
| 1349 | return -EFAULT; |
| 1350 | } |
| 1351 | |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 1352 | (void)k_work_cancel_delayable(&data->dma_tx.timeout_work); |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1353 | if (!dma_get_status(data->dma_tx.dma_dev, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1354 | data->dma_tx.dma_channel, &stat)) { |
| 1355 | data->dma_tx.counter = tx_buffer_length - stat.pending_length; |
| 1356 | } |
| 1357 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1358 | dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1359 | async_evt_tx_abort(data); |
| 1360 | |
| 1361 | return 0; |
| 1362 | } |
| 1363 | |
| 1364 | static void uart_stm32_async_rx_timeout(struct k_work *work) |
| 1365 | { |
Yong Cong Sin | 731241f | 2022-01-19 12:07:51 +0800 | [diff] [blame] | 1366 | struct k_work_delayable *dwork = k_work_delayable_from_work(work); |
| 1367 | struct uart_dma_stream *rx_stream = CONTAINER_OF(dwork, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1368 | struct uart_dma_stream, timeout_work); |
| 1369 | struct uart_stm32_data *data = CONTAINER_OF(rx_stream, |
| 1370 | struct uart_stm32_data, dma_rx); |
| 1371 | const struct device *dev = data->uart_dev; |
| 1372 | |
| 1373 | LOG_DBG("rx timeout"); |
| 1374 | |
| 1375 | if (data->dma_rx.counter == data->dma_rx.buffer_length) { |
| 1376 | uart_stm32_async_rx_disable(dev); |
| 1377 | } else { |
| 1378 | uart_stm32_dma_rx_flush(dev); |
| 1379 | } |
| 1380 | } |
| 1381 | |
| 1382 | static void uart_stm32_async_tx_timeout(struct k_work *work) |
| 1383 | { |
Yong Cong Sin | 731241f | 2022-01-19 12:07:51 +0800 | [diff] [blame] | 1384 | struct k_work_delayable *dwork = k_work_delayable_from_work(work); |
| 1385 | struct uart_dma_stream *tx_stream = CONTAINER_OF(dwork, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1386 | struct uart_dma_stream, timeout_work); |
| 1387 | struct uart_stm32_data *data = CONTAINER_OF(tx_stream, |
| 1388 | struct uart_stm32_data, dma_tx); |
| 1389 | const struct device *dev = data->uart_dev; |
| 1390 | |
| 1391 | uart_stm32_async_tx_abort(dev); |
| 1392 | |
| 1393 | LOG_DBG("tx: async timeout"); |
| 1394 | } |
| 1395 | |
| 1396 | static int uart_stm32_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, |
| 1397 | size_t len) |
| 1398 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1399 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1400 | |
| 1401 | LOG_DBG("replace buffer (%d)", len); |
| 1402 | data->rx_next_buffer = buf; |
| 1403 | data->rx_next_buffer_len = len; |
| 1404 | |
| 1405 | return 0; |
| 1406 | } |
| 1407 | |
| 1408 | static int uart_stm32_async_init(const struct device *dev) |
| 1409 | { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1410 | const struct uart_stm32_config *config = dev->config; |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1411 | struct uart_stm32_data *data = dev->data; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1412 | |
| 1413 | data->uart_dev = dev; |
| 1414 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1415 | if (data->dma_rx.dma_dev != NULL) { |
| 1416 | if (!device_is_ready(data->dma_rx.dma_dev)) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1417 | return -ENODEV; |
| 1418 | } |
| 1419 | } |
| 1420 | |
Erwan Gouriou | 13c2351 | 2021-03-01 11:59:57 +0100 | [diff] [blame] | 1421 | if (data->dma_tx.dma_dev != NULL) { |
Georgij Cernysiov | 64c804a | 2022-05-06 08:47:03 +0200 | [diff] [blame] | 1422 | if (!device_is_ready(data->dma_tx.dma_dev)) { |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1423 | return -ENODEV; |
| 1424 | } |
| 1425 | } |
| 1426 | |
| 1427 | /* Disable both TX and RX DMA requests */ |
| 1428 | uart_stm32_dma_rx_disable(dev); |
| 1429 | uart_stm32_dma_tx_disable(dev); |
| 1430 | |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 1431 | k_work_init_delayable(&data->dma_rx.timeout_work, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1432 | uart_stm32_async_rx_timeout); |
Francois Ramu | 962d6b1 | 2021-04-08 12:09:58 +0200 | [diff] [blame] | 1433 | k_work_init_delayable(&data->dma_tx.timeout_work, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1434 | uart_stm32_async_tx_timeout); |
| 1435 | |
| 1436 | /* Configure dma rx config */ |
| 1437 | memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg)); |
| 1438 | |
| 1439 | #if defined(CONFIG_SOC_SERIES_STM32F1X) || \ |
| 1440 | defined(CONFIG_SOC_SERIES_STM32F2X) || \ |
| 1441 | defined(CONFIG_SOC_SERIES_STM32F4X) || \ |
| 1442 | defined(CONFIG_SOC_SERIES_STM32L1X) |
| 1443 | data->dma_rx.blk_cfg.source_address = |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1444 | LL_USART_DMA_GetRegAddr(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1445 | #else |
| 1446 | data->dma_rx.blk_cfg.source_address = |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1447 | LL_USART_DMA_GetRegAddr(config->usart, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1448 | LL_USART_DMA_REG_DATA_RECEIVE); |
| 1449 | #endif |
| 1450 | |
| 1451 | data->dma_rx.blk_cfg.dest_address = 0; /* dest not ready */ |
| 1452 | |
| 1453 | if (data->dma_rx.src_addr_increment) { |
| 1454 | data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; |
| 1455 | } else { |
| 1456 | data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; |
| 1457 | } |
| 1458 | |
| 1459 | if (data->dma_rx.dst_addr_increment) { |
| 1460 | data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; |
| 1461 | } else { |
| 1462 | data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; |
| 1463 | } |
| 1464 | |
| 1465 | /* RX disable circular buffer */ |
| 1466 | data->dma_rx.blk_cfg.source_reload_en = 0; |
| 1467 | data->dma_rx.blk_cfg.dest_reload_en = 0; |
| 1468 | data->dma_rx.blk_cfg.fifo_mode_control = data->dma_rx.fifo_threshold; |
| 1469 | |
| 1470 | data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg; |
| 1471 | data->dma_rx.dma_cfg.user_data = (void *)dev; |
| 1472 | data->rx_next_buffer = NULL; |
| 1473 | data->rx_next_buffer_len = 0; |
| 1474 | |
| 1475 | /* Configure dma tx config */ |
| 1476 | memset(&data->dma_tx.blk_cfg, 0, sizeof(data->dma_tx.blk_cfg)); |
| 1477 | |
| 1478 | #if defined(CONFIG_SOC_SERIES_STM32F1X) || \ |
| 1479 | defined(CONFIG_SOC_SERIES_STM32F2X) || \ |
| 1480 | defined(CONFIG_SOC_SERIES_STM32F4X) || \ |
| 1481 | defined(CONFIG_SOC_SERIES_STM32L1X) |
| 1482 | data->dma_tx.blk_cfg.dest_address = |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1483 | LL_USART_DMA_GetRegAddr(config->usart); |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1484 | #else |
| 1485 | data->dma_tx.blk_cfg.dest_address = |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1486 | LL_USART_DMA_GetRegAddr(config->usart, |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1487 | LL_USART_DMA_REG_DATA_TRANSMIT); |
| 1488 | #endif |
| 1489 | |
| 1490 | data->dma_tx.blk_cfg.source_address = 0; /* not ready */ |
| 1491 | |
| 1492 | if (data->dma_tx.src_addr_increment) { |
| 1493 | data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; |
| 1494 | } else { |
| 1495 | data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; |
| 1496 | } |
| 1497 | |
| 1498 | if (data->dma_tx.dst_addr_increment) { |
| 1499 | data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; |
| 1500 | } else { |
| 1501 | data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; |
| 1502 | } |
| 1503 | |
| 1504 | data->dma_tx.blk_cfg.fifo_mode_control = data->dma_tx.fifo_threshold; |
| 1505 | |
| 1506 | data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg; |
| 1507 | data->dma_tx.dma_cfg.user_data = (void *)dev; |
| 1508 | |
| 1509 | return 0; |
| 1510 | } |
| 1511 | |
| 1512 | #endif /* CONFIG_UART_ASYNC_API */ |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 1513 | |
Marcus Shawcroft | d3ea539 | 2016-10-24 08:38:49 +0100 | [diff] [blame] | 1514 | static const struct uart_driver_api uart_stm32_driver_api = { |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1515 | .poll_in = uart_stm32_poll_in, |
| 1516 | .poll_out = uart_stm32_poll_out, |
Georgij Cernysiov | c74c131 | 2019-02-14 10:50:19 +0100 | [diff] [blame] | 1517 | .err_check = uart_stm32_err_check, |
Daniel Leung | 4e1692f | 2021-05-26 12:33:37 -0700 | [diff] [blame] | 1518 | #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 1519 | .configure = uart_stm32_configure, |
| 1520 | .config_get = uart_stm32_config_get, |
Daniel Leung | 4e1692f | 2021-05-26 12:33:37 -0700 | [diff] [blame] | 1521 | #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 1522 | #ifdef CONFIG_UART_INTERRUPT_DRIVEN |
| 1523 | .fifo_fill = uart_stm32_fifo_fill, |
| 1524 | .fifo_read = uart_stm32_fifo_read, |
| 1525 | .irq_tx_enable = uart_stm32_irq_tx_enable, |
| 1526 | .irq_tx_disable = uart_stm32_irq_tx_disable, |
| 1527 | .irq_tx_ready = uart_stm32_irq_tx_ready, |
Paul Sokolovsky | 0fdc9b5 | 2017-05-11 17:57:29 +0300 | [diff] [blame] | 1528 | .irq_tx_complete = uart_stm32_irq_tx_complete, |
Maciek Borzecki | 0cd7ff8 | 2016-03-13 19:37:25 +0100 | [diff] [blame] | 1529 | .irq_rx_enable = uart_stm32_irq_rx_enable, |
| 1530 | .irq_rx_disable = uart_stm32_irq_rx_disable, |
| 1531 | .irq_rx_ready = uart_stm32_irq_rx_ready, |
| 1532 | .irq_err_enable = uart_stm32_irq_err_enable, |
| 1533 | .irq_err_disable = uart_stm32_irq_err_disable, |
| 1534 | .irq_is_pending = uart_stm32_irq_is_pending, |
| 1535 | .irq_update = uart_stm32_irq_update, |
| 1536 | .irq_callback_set = uart_stm32_irq_callback_set, |
| 1537 | #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1538 | #ifdef CONFIG_UART_ASYNC_API |
| 1539 | .callback_set = uart_stm32_async_callback_set, |
| 1540 | .tx = uart_stm32_async_tx, |
| 1541 | .tx_abort = uart_stm32_async_tx_abort, |
| 1542 | .rx_enable = uart_stm32_async_rx_enable, |
| 1543 | .rx_disable = uart_stm32_async_rx_disable, |
| 1544 | .rx_buf_rsp = uart_stm32_async_rx_buf_rsp, |
| 1545 | #endif /* CONFIG_UART_ASYNC_API */ |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1546 | }; |
| 1547 | |
| 1548 | /** |
| 1549 | * @brief Initialize UART channel |
| 1550 | * |
| 1551 | * This routine is called to reset the chip in a quiescent state. |
| 1552 | * It is assumed that this function is called only once per UART. |
| 1553 | * |
| 1554 | * @param dev UART device struct |
| 1555 | * |
| 1556 | * @return 0 |
| 1557 | */ |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 1558 | static int uart_stm32_init(const struct device *dev) |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1559 | { |
Gerard Marull-Paretas | 1674fec | 2022-01-18 16:58:32 +0100 | [diff] [blame] | 1560 | const struct uart_stm32_config *config = dev->config; |
| 1561 | struct uart_stm32_data *data = dev->data; |
Kumar Gala | a1b77fd | 2020-05-27 11:26:57 -0500 | [diff] [blame] | 1562 | uint32_t ll_parity; |
| 1563 | uint32_t ll_datawidth; |
Erwan Gouriou | 0b9c584 | 2020-10-16 17:20:00 +0200 | [diff] [blame] | 1564 | int err; |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 1565 | |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1566 | __uart_stm32_get_clock(dev); |
Henrik Brix Andersen | 9456eca | 2022-08-08 16:05:16 +0200 | [diff] [blame] | 1567 | |
| 1568 | if (!device_is_ready(data->clock)) { |
| 1569 | LOG_ERR("clock control device not ready"); |
| 1570 | return -ENODEV; |
| 1571 | } |
| 1572 | |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1573 | /* enable clock */ |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1574 | err = clock_control_on(data->clock, (clock_control_subsys_t)&config->pclken[0]); |
| 1575 | if (err != 0) { |
| 1576 | LOG_ERR("Could not enable (LP)UART clock"); |
| 1577 | return err; |
| 1578 | } |
| 1579 | |
Erwan Gouriou | 1ef9e9e | 2022-08-04 11:08:15 +0200 | [diff] [blame] | 1580 | if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1581 | err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), |
| 1582 | (clock_control_subsys_t) &config->pclken[1], |
| 1583 | NULL); |
| 1584 | if (err != 0) { |
Erwan Gouriou | 1ef9e9e | 2022-08-04 11:08:15 +0200 | [diff] [blame] | 1585 | LOG_ERR("Could not select UART domain clock"); |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1586 | return err; |
| 1587 | } |
Erwan Gouriou | 9062e97 | 2018-12-07 11:09:28 +0100 | [diff] [blame] | 1588 | } |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1589 | |
Erwan Gouriou | 252a623 | 2020-06-05 10:57:52 +0200 | [diff] [blame] | 1590 | /* Configure dt provided device signals when available */ |
Gerard Marull-Paretas | 21a2719 | 2021-09-07 16:39:45 +0200 | [diff] [blame] | 1591 | err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); |
Erwan Gouriou | 0b9c584 | 2020-10-16 17:20:00 +0200 | [diff] [blame] | 1592 | if (err < 0) { |
| 1593 | return err; |
Erwan Gouriou | 252a623 | 2020-06-05 10:57:52 +0200 | [diff] [blame] | 1594 | } |
| 1595 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1596 | LL_USART_Disable(config->usart); |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1597 | |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 1598 | /* TX/RX direction */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1599 | LL_USART_SetTransferDirection(config->usart, |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 1600 | LL_USART_DIRECTION_TX_RX); |
| 1601 | |
Pauli Salmenrinne | 30003ff | 2020-03-18 13:40:21 +0200 | [diff] [blame] | 1602 | /* Determine the datawidth and parity. If we use other parity than |
| 1603 | * 'none' we must use datawidth = 9 (to get 8 databit + 1 parity bit). |
| 1604 | */ |
| 1605 | if (config->parity == 2) { |
| 1606 | /* 8 databit, 1 parity bit, parity even */ |
| 1607 | ll_parity = LL_USART_PARITY_EVEN; |
| 1608 | ll_datawidth = LL_USART_DATAWIDTH_9B; |
| 1609 | } else if (config->parity == 1) { |
| 1610 | /* 8 databit, 1 parity bit, parity odd */ |
| 1611 | ll_parity = LL_USART_PARITY_ODD; |
| 1612 | ll_datawidth = LL_USART_DATAWIDTH_9B; |
| 1613 | } else { /* Default to 8N0, but show warning if invalid value */ |
| 1614 | if (config->parity != 0) { |
| 1615 | LOG_WRN("Invalid parity setting '%d'." |
| 1616 | "Defaulting to 'none'.", config->parity); |
| 1617 | } |
| 1618 | /* 8 databit, parity none */ |
| 1619 | ll_parity = LL_USART_PARITY_NONE; |
| 1620 | ll_datawidth = LL_USART_DATAWIDTH_8B; |
| 1621 | } |
| 1622 | |
| 1623 | /* Set datawidth and parity, 1 start bit, 1 stop bit */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1624 | LL_USART_ConfigCharacter(config->usart, |
Pauli Salmenrinne | 30003ff | 2020-03-18 13:40:21 +0200 | [diff] [blame] | 1625 | ll_datawidth, |
| 1626 | ll_parity, |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 1627 | LL_USART_STOPBITS_1); |
| 1628 | |
Georgij Cernysiov | 04da64d | 2019-02-08 18:39:35 +0100 | [diff] [blame] | 1629 | if (config->hw_flow_control) { |
| 1630 | uart_stm32_set_hwctrl(dev, LL_USART_HWCONTROL_RTS_CTS); |
| 1631 | } |
| 1632 | |
Pushpal Sidhu | acd0e25 | 2019-01-07 13:52:24 -0800 | [diff] [blame] | 1633 | /* Set the default baudrate */ |
| 1634 | uart_stm32_set_baudrate(dev, data->baud_rate); |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 1635 | |
Jonathan Hahn | 32f9dcf | 2022-01-01 23:41:19 +0100 | [diff] [blame] | 1636 | /* Enable the single wire / half-duplex mode */ |
| 1637 | if (config->single_wire) { |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1638 | LL_USART_EnableHalfDuplex(config->usart); |
Jonathan Hahn | 32f9dcf | 2022-01-01 23:41:19 +0100 | [diff] [blame] | 1639 | } |
| 1640 | |
Peter Maxwell Warasila | 3c09c21 | 2022-05-09 16:28:51 -0400 | [diff] [blame] | 1641 | #ifdef LL_USART_TXRX_SWAPPED |
| 1642 | if (config->tx_rx_swap) { |
| 1643 | LL_USART_SetTXRXSwap(config->usart, LL_USART_TXRX_SWAPPED); |
| 1644 | } |
| 1645 | #endif |
| 1646 | |
Jonathan Hahn | 05cc2e1 | 2022-04-25 20:12:25 +0200 | [diff] [blame] | 1647 | #ifdef LL_USART_RXPIN_LEVEL_INVERTED |
| 1648 | if (config->rx_invert) { |
| 1649 | LL_USART_SetRXPinLevel(config->usart, LL_USART_RXPIN_LEVEL_INVERTED); |
| 1650 | } |
| 1651 | #endif |
| 1652 | |
| 1653 | #ifdef LL_USART_TXPIN_LEVEL_INVERTED |
| 1654 | if (config->tx_invert) { |
| 1655 | LL_USART_SetTXPinLevel(config->usart, LL_USART_TXPIN_LEVEL_INVERTED); |
| 1656 | } |
| 1657 | #endif |
| 1658 | |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1659 | LL_USART_Enable(config->usart); |
Erwan Gouriou | da210ba | 2017-09-21 15:20:53 +0200 | [diff] [blame] | 1660 | |
Erwan Gouriou | 80b8c50 | 2018-06-13 11:32:38 +0200 | [diff] [blame] | 1661 | #ifdef USART_ISR_TEACK |
| 1662 | /* Wait until TEACK flag is set */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1663 | while (!(LL_USART_IsActiveFlag_TEACK(config->usart))) { |
Anas Nashif | 4c32258 | 2019-06-04 10:52:23 -0400 | [diff] [blame] | 1664 | } |
Erwan Gouriou | 80b8c50 | 2018-06-13 11:32:38 +0200 | [diff] [blame] | 1665 | #endif /* !USART_ISR_TEACK */ |
| 1666 | |
| 1667 | #ifdef USART_ISR_REACK |
Erwan Gouriou | 13a9657 | 2018-06-18 18:01:06 +0200 | [diff] [blame] | 1668 | /* Wait until REACK flag is set */ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1669 | while (!(LL_USART_IsActiveFlag_REACK(config->usart))) { |
Anas Nashif | 4c32258 | 2019-06-04 10:52:23 -0400 | [diff] [blame] | 1670 | } |
Erwan Gouriou | 80b8c50 | 2018-06-13 11:32:38 +0200 | [diff] [blame] | 1671 | #endif /* !USART_ISR_REACK */ |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1672 | |
Gerard Marull-Paretas | e101cc7 | 2022-01-25 16:21:36 +0100 | [diff] [blame] | 1673 | #if defined(CONFIG_PM) || \ |
| 1674 | defined(CONFIG_UART_INTERRUPT_DRIVEN) || \ |
| 1675 | defined(CONFIG_UART_ASYNC_API) |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1676 | config->irq_config_func(dev); |
Gerard Marull-Paretas | e101cc7 | 2022-01-25 16:21:36 +0100 | [diff] [blame] | 1677 | #endif /* CONFIG_PM || CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API */ |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1678 | |
Erwan Gouriou | 4422de5 | 2022-08-03 14:39:48 +0200 | [diff] [blame] | 1679 | #if defined(CONFIG_PM) |
| 1680 | if (config->wakeup_source) { |
| 1681 | /* Enable ability to wakeup device in Stop mode |
| 1682 | * Effect depends on CONFIG_PM_DEVICE status: |
| 1683 | * CONFIG_PM_DEVICE=n : Always active |
| 1684 | * CONFIG_PM_DEVICE=y : Controlled by pm_device_wakeup_enable() |
| 1685 | */ |
| 1686 | LL_USART_EnableInStopMode(config->usart); |
| 1687 | } |
| 1688 | #endif /* CONFIG_PM */ |
| 1689 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1690 | #ifdef CONFIG_UART_ASYNC_API |
| 1691 | return uart_stm32_async_init(dev); |
| 1692 | #else |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1693 | return 0; |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1694 | #endif |
Maciek Borzecki | 5a73ca6 | 2016-03-03 15:33:20 +0100 | [diff] [blame] | 1695 | } |
| 1696 | |
Erwan Gouriou | a439c04 | 2022-08-03 14:39:59 +0200 | [diff] [blame] | 1697 | #ifdef CONFIG_PM_DEVICE |
| 1698 | static void uart_stm32_suspend_setup(const struct device *dev) |
| 1699 | { |
| 1700 | const struct uart_stm32_config *config = dev->config; |
| 1701 | |
| 1702 | #ifdef USART_ISR_BUSY |
| 1703 | /* Make sure that no USART transfer is on-going */ |
| 1704 | while (LL_USART_IsActiveFlag_BUSY(config->usart) == 1) { |
| 1705 | } |
| 1706 | #endif |
| 1707 | while (LL_USART_IsActiveFlag_TC(config->usart) == 0) { |
| 1708 | } |
| 1709 | #ifdef USART_ISR_REACK |
| 1710 | /* Make sure that USART is ready for reception */ |
| 1711 | while (LL_USART_IsActiveFlag_REACK(config->usart) == 0) { |
| 1712 | } |
| 1713 | #endif |
| 1714 | /* Clear OVERRUN flag */ |
| 1715 | LL_USART_ClearFlag_ORE(config->usart); |
| 1716 | } |
| 1717 | |
| 1718 | static int uart_stm32_pm_action(const struct device *dev, |
| 1719 | enum pm_device_action action) |
| 1720 | { |
| 1721 | const struct uart_stm32_config *config = dev->config; |
| 1722 | struct uart_stm32_data *data = dev->data; |
| 1723 | int err; |
| 1724 | |
| 1725 | |
| 1726 | switch (action) { |
| 1727 | case PM_DEVICE_ACTION_RESUME: |
| 1728 | /* Set pins to active state */ |
| 1729 | err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); |
| 1730 | if (err < 0) { |
| 1731 | return err; |
| 1732 | } |
| 1733 | |
| 1734 | /* enable clock */ |
| 1735 | err = clock_control_on(data->clock, (clock_control_subsys_t)&config->pclken[0]); |
| 1736 | if (err != 0) { |
| 1737 | LOG_ERR("Could not enable (LP)UART clock"); |
| 1738 | return err; |
| 1739 | } |
| 1740 | break; |
| 1741 | case PM_DEVICE_ACTION_SUSPEND: |
| 1742 | uart_stm32_suspend_setup(dev); |
Erwan Gouriou | e89e4b5 | 2022-08-03 10:47:34 +0200 | [diff] [blame^] | 1743 | /* Stop device clock. Note: fixed clocks are not handled yet. */ |
Erwan Gouriou | a439c04 | 2022-08-03 14:39:59 +0200 | [diff] [blame] | 1744 | err = clock_control_off(data->clock, (clock_control_subsys_t)&config->pclken[0]); |
| 1745 | if (err != 0) { |
| 1746 | LOG_ERR("Could not enable (LP)UART clock"); |
| 1747 | return err; |
| 1748 | } |
| 1749 | |
| 1750 | /* Move pins to sleep state */ |
| 1751 | err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); |
Erwan Gouriou | e89e4b5 | 2022-08-03 10:47:34 +0200 | [diff] [blame^] | 1752 | if (err == -ENOENT) { |
| 1753 | /* Warn but don't block PM suspend */ |
| 1754 | LOG_WRN("(LP)UART pinctrl sleep state not available "); |
| 1755 | } else if (err < 0) { |
Erwan Gouriou | a439c04 | 2022-08-03 14:39:59 +0200 | [diff] [blame] | 1756 | return err; |
| 1757 | } |
| 1758 | break; |
| 1759 | default: |
| 1760 | return -ENOTSUP; |
| 1761 | } |
| 1762 | |
| 1763 | return 0; |
| 1764 | } |
| 1765 | #endif /* CONFIG_PM_DEVICE */ |
| 1766 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1767 | #ifdef CONFIG_UART_ASYNC_API |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1768 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1769 | /* src_dev and dest_dev should be 'MEMORY' or 'PERIPHERAL'. */ |
| 1770 | #define UART_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1771 | .dma_dev = DEVICE_DT_GET(STM32_DMA_CTLR(index, dir)), \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1772 | .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \ |
| 1773 | .dma_cfg = { \ |
Francois Ramu | 744e1dc | 2021-08-09 16:32:57 +0200 | [diff] [blame] | 1774 | .dma_slot = STM32_DMA_SLOT(index, dir, slot),\ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1775 | .channel_direction = STM32_DMA_CONFIG_DIRECTION( \ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1776 | STM32_DMA_CHANNEL_CONFIG(index, dir)),\ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1777 | .channel_priority = STM32_DMA_CONFIG_PRIORITY( \ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1778 | STM32_DMA_CHANNEL_CONFIG(index, dir)), \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1779 | .source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE(\ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1780 | STM32_DMA_CHANNEL_CONFIG(index, dir)),\ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1781 | .dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE(\ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1782 | STM32_DMA_CHANNEL_CONFIG(index, dir)),\ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1783 | .source_burst_length = 1, /* SINGLE transfer */ \ |
| 1784 | .dest_burst_length = 1, \ |
| 1785 | .block_count = 1, \ |
| 1786 | .dma_callback = uart_stm32_dma_##dir##_cb, \ |
| 1787 | }, \ |
| 1788 | .src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1789 | STM32_DMA_CHANNEL_CONFIG(index, dir)), \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1790 | .dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1791 | STM32_DMA_CHANNEL_CONFIG(index, dir)), \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1792 | .fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD( \ |
Francois Ramu | 30fd022 | 2021-06-18 15:52:30 +0200 | [diff] [blame] | 1793 | STM32_DMA_FEATURES(index, dir)), \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1794 | |
| 1795 | #endif |
| 1796 | |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1797 | #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API) || \ |
| 1798 | defined(CONFIG_PM) |
Erwan Gouriou | 6275513 | 2020-02-28 14:54:37 +0100 | [diff] [blame] | 1799 | #define STM32_UART_IRQ_HANDLER_DECL(index) \ |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1800 | static void uart_stm32_irq_config_func_##index(const struct device *dev); |
Erwan Gouriou | 6275513 | 2020-02-28 14:54:37 +0100 | [diff] [blame] | 1801 | #define STM32_UART_IRQ_HANDLER(index) \ |
Tomasz Bursztyka | e18fcbb | 2020-04-30 20:33:38 +0200 | [diff] [blame] | 1802 | static void uart_stm32_irq_config_func_##index(const struct device *dev) \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1803 | { \ |
Erwan Gouriou | ccd6b72 | 2020-06-05 09:48:29 +0200 | [diff] [blame] | 1804 | IRQ_CONNECT(DT_INST_IRQN(index), \ |
| 1805 | DT_INST_IRQ(index, priority), \ |
Kumar Gala | c49b162 | 2020-12-11 10:12:30 -0600 | [diff] [blame] | 1806 | uart_stm32_isr, DEVICE_DT_INST_GET(index), \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1807 | 0); \ |
Erwan Gouriou | ccd6b72 | 2020-06-05 09:48:29 +0200 | [diff] [blame] | 1808 | irq_enable(DT_INST_IRQN(index)); \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1809 | } |
| 1810 | #else |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1811 | #define STM32_UART_IRQ_HANDLER_DECL(index) /* Not used */ |
| 1812 | #define STM32_UART_IRQ_HANDLER(index) /* Not used */ |
| 1813 | #endif |
| 1814 | |
Gerard Marull-Paretas | e101cc7 | 2022-01-25 16:21:36 +0100 | [diff] [blame] | 1815 | #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API) || \ |
| 1816 | defined(CONFIG_PM) |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1817 | #define STM32_UART_IRQ_HANDLER_FUNC(index) \ |
| 1818 | .irq_config_func = uart_stm32_irq_config_func_##index, |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1819 | #else |
| 1820 | #define STM32_UART_IRQ_HANDLER_FUNC(index) /* Not used */ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1821 | #endif |
| 1822 | |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1823 | #ifdef CONFIG_UART_ASYNC_API |
| 1824 | #define UART_DMA_CHANNEL(index, dir, DIR, src, dest) \ |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1825 | .dma_##dir = { \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1826 | COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ |
| 1827 | (UART_DMA_CHANNEL_INIT(index, dir, DIR, src, dest)), \ |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1828 | (NULL)) \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1829 | }, |
| 1830 | |
| 1831 | #else |
| 1832 | #define UART_DMA_CHANNEL(index, dir, DIR, src, dest) |
| 1833 | #endif |
| 1834 | |
Erwan Gouriou | 4422de5 | 2022-08-03 14:39:48 +0200 | [diff] [blame] | 1835 | #ifdef CONFIG_PM |
| 1836 | #define STM32_UART_PM_WAKEUP(index) \ |
| 1837 | .wakeup_source = DT_INST_PROP(index, wakeup_source), |
| 1838 | #else |
| 1839 | #define STM32_UART_PM_WAKEUP(index) /* Not used */ |
| 1840 | #endif |
| 1841 | |
Erwan Gouriou | 6275513 | 2020-02-28 14:54:37 +0100 | [diff] [blame] | 1842 | #define STM32_UART_INIT(index) \ |
Gerard Marull-Paretas | e3f4907 | 2021-09-09 22:41:35 +0200 | [diff] [blame] | 1843 | STM32_UART_IRQ_HANDLER_DECL(index) \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1844 | \ |
Gerard Marull-Paretas | 5dc6ed3 | 2021-12-23 12:33:03 +0100 | [diff] [blame] | 1845 | PINCTRL_DT_INST_DEFINE(index); \ |
Erwan Gouriou | 252a623 | 2020-06-05 10:57:52 +0200 | [diff] [blame] | 1846 | \ |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1847 | static const struct stm32_pclken pclken_##index[] = \ |
| 1848 | STM32_DT_INST_CLOCKS(index);\ |
| 1849 | \ |
Erwan Gouriou | 6275513 | 2020-02-28 14:54:37 +0100 | [diff] [blame] | 1850 | static const struct uart_stm32_config uart_stm32_cfg_##index = { \ |
Gerard Marull-Paretas | 32a3a02 | 2022-01-25 16:14:12 +0100 | [diff] [blame] | 1851 | .usart = (USART_TypeDef *)DT_INST_REG_ADDR(index), \ |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1852 | .pclken = pclken_##index, \ |
| 1853 | .pclk_len = DT_INST_NUM_CLOCKS(index), \ |
Erwan Gouriou | ccd6b72 | 2020-06-05 09:48:29 +0200 | [diff] [blame] | 1854 | .hw_flow_control = DT_INST_PROP(index, hw_flow_control), \ |
Gerard Marull-Paretas | c759a35 | 2021-11-17 14:01:42 +0100 | [diff] [blame] | 1855 | .parity = DT_INST_ENUM_IDX_OR(index, parity, UART_CFG_PARITY_NONE), \ |
Gerard Marull-Paretas | 21a2719 | 2021-09-07 16:39:45 +0200 | [diff] [blame] | 1856 | .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ |
Artur Lipowski | bb85759 | 2022-05-10 12:18:28 +0200 | [diff] [blame] | 1857 | .single_wire = DT_INST_PROP_OR(index, single_wire, false), \ |
Alexander Mihajlovic | 4ff4991 | 2022-04-02 15:21:01 +0200 | [diff] [blame] | 1858 | .tx_rx_swap = DT_INST_PROP_OR(index, tx_rx_swap, false), \ |
Erwan Gouriou | 4422de5 | 2022-08-03 14:39:48 +0200 | [diff] [blame] | 1859 | .rx_invert = DT_INST_PROP(index, rx_invert), \ |
| 1860 | .tx_invert = DT_INST_PROP(index, tx_invert), \ |
Gerard Marull-Paretas | e101cc7 | 2022-01-25 16:21:36 +0100 | [diff] [blame] | 1861 | STM32_UART_IRQ_HANDLER_FUNC(index) \ |
Erwan Gouriou | 4422de5 | 2022-08-03 14:39:48 +0200 | [diff] [blame] | 1862 | STM32_UART_PM_WAKEUP(index) \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1863 | }; \ |
| 1864 | \ |
Erwan Gouriou | 6275513 | 2020-02-28 14:54:37 +0100 | [diff] [blame] | 1865 | static struct uart_stm32_data uart_stm32_data_##index = { \ |
Erwan Gouriou | ccd6b72 | 2020-06-05 09:48:29 +0200 | [diff] [blame] | 1866 | .baud_rate = DT_INST_PROP(index, current_speed), \ |
Shlomi Vaknin | b4afd1a | 2021-01-16 18:44:24 +0200 | [diff] [blame] | 1867 | UART_DMA_CHANNEL(index, rx, RX, PERIPHERAL, MEMORY) \ |
| 1868 | UART_DMA_CHANNEL(index, tx, TX, MEMORY, PERIPHERAL) \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1869 | }; \ |
| 1870 | \ |
Erwan Gouriou | a439c04 | 2022-08-03 14:39:59 +0200 | [diff] [blame] | 1871 | PM_DEVICE_DT_INST_DEFINE(index, uart_stm32_pm_action); \ |
| 1872 | \ |
Kumar Gala | c49b162 | 2020-12-11 10:12:30 -0600 | [diff] [blame] | 1873 | DEVICE_DT_INST_DEFINE(index, \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1874 | &uart_stm32_init, \ |
Erwan Gouriou | a439c04 | 2022-08-03 14:39:59 +0200 | [diff] [blame] | 1875 | PM_DEVICE_DT_INST_GET(index), \ |
Erwan Gouriou | 6275513 | 2020-02-28 14:54:37 +0100 | [diff] [blame] | 1876 | &uart_stm32_data_##index, &uart_stm32_cfg_##index, \ |
Maureen Helm | ad14505 | 2021-10-14 09:38:10 -0500 | [diff] [blame] | 1877 | PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \ |
Florian Vaussard | f27a5a3 | 2017-05-01 15:21:52 +0200 | [diff] [blame] | 1878 | &uart_stm32_driver_api); \ |
| 1879 | \ |
Erwan Gouriou | 6275513 | 2020-02-28 14:54:37 +0100 | [diff] [blame] | 1880 | STM32_UART_IRQ_HANDLER(index) |
Erwan Gouriou | 8c079e9 | 2016-11-14 11:53:52 +0100 | [diff] [blame] | 1881 | |
Martí Bolívar | 7e0eed9 | 2020-05-06 11:23:07 -0700 | [diff] [blame] | 1882 | DT_INST_FOREACH_STATUS_OKAY(STM32_UART_INIT) |