Release v1.2.1
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 1b36402..299ed70 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
/**
* @}
*/
@@ -315,6 +314,11 @@
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
@@ -591,24 +595,24 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@@ -769,49 +773,6 @@
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-/** @brief Constants defining the events that can be selected to configure the
- * set/reset crossbar of a timer output
- */
-#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
-#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
-#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
-#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
-#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
-#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
-#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
-#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
-#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
-
-#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
-#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
-#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
-#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
-#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
-#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
-#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
-#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
-#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
-
-/** @brief Constants defining the event filtering applied to external events
- * by a timer
- */
-#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
-
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
@@ -964,6 +925,11 @@
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
+#endif
/**
* @}
@@ -975,15 +941,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
- #define I2S_IT_TXE I2S_IT_TXP
- #define I2S_IT_RXNE I2S_IT_RXP
+#define I2S_IT_TXE I2S_IT_TXP
+#define I2S_IT_RXNE I2S_IT_RXP
- #define I2S_FLAG_TXE I2S_FLAG_TXP
- #define I2S_FLAG_RXNE I2S_FLAG_RXP
+#define I2S_FLAG_TXE I2S_FLAG_TXP
+#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
@@ -1018,7 +984,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1118,16 +1084,16 @@
#if defined(STM32H7)
- #define SPI_FLAG_TXE SPI_FLAG_TXP
- #define SPI_FLAG_RXNE SPI_FLAG_RXP
+#define SPI_FLAG_TXE SPI_FLAG_TXP
+#define SPI_FLAG_RXNE SPI_FLAG_RXP
- #define SPI_IT_TXE SPI_IT_TXP
- #define SPI_IT_RXNE SPI_IT_RXP
+#define SPI_IT_TXE SPI_IT_TXP
+#define SPI_IT_RXNE SPI_IT_RXP
- #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
- #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
- #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
- #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
@@ -1454,7 +1420,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@@ -1476,7 +1442,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@@ -1490,7 +1456,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1498,7 +1465,8 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
@@ -1521,9 +1489,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
@@ -1533,7 +1501,8 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
@@ -1558,9 +1527,9 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
@@ -1615,9 +1584,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
- /**
+/**
* @}
- */
+ */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@@ -1866,15 +1835,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
- #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
- #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
- #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
- #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@@ -2085,8 +2054,8 @@
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
@@ -2142,7 +2111,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
- #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
@@ -2279,7 +2248,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -3247,7 +3217,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3376,7 +3346,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3396,19 +3366,19 @@
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
@@ -3592,6 +3562,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16 0x00000000U
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_adc.h b/Inc/stm32g4xx_hal_adc.h
index 30160c3..7013801 100644
--- a/Inc/stm32g4xx_hal_adc.h
+++ b/Inc/stm32g4xx_hal_adc.h
@@ -384,7 +384,7 @@
typedef struct __ADC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
@@ -769,7 +769,6 @@
* @}
*/
-
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
@@ -1239,7 +1238,7 @@
#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @brief Enable ADC interrupt.
@@ -1667,7 +1666,7 @@
*/
#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
@@ -1738,10 +1737,10 @@
*/
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
- __ADC_RESOLUTION_TARGET__) \
- __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
- (__ADC_RESOLUTION_CURRENT__), \
- (__ADC_RESOLUTION_TARGET__))
+ __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+ (__ADC_RESOLUTION_CURRENT__),\
+ (__ADC_RESOLUTION_TARGET__))
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@@ -1761,10 +1760,10 @@
*/
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
- (__ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+ (__ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@@ -1792,9 +1791,9 @@
* @retval Analog reference voltage (unit: mV)
*/
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1843,10 +1842,10 @@
*/
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1897,13 +1896,13 @@
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
- (__TEMPSENSOR_TYP_CALX_V__), \
- (__TEMPSENSOR_CALX_TEMP__), \
- (__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+ (__TEMPSENSOR_TYP_CALX_V__),\
+ (__TEMPSENSOR_CALX_TEMP__),\
+ (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @}
diff --git a/Inc/stm32g4xx_hal_adc_ex.h b/Inc/stm32g4xx_hal_adc_ex.h
index d23015b..2223be4 100644
--- a/Inc/stm32g4xx_hal_adc_ex.h
+++ b/Inc/stm32g4xx_hal_adc_ex.h
@@ -393,7 +393,7 @@
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
ADC_SMPR1_SMP0)
-#endif
+#endif /* ADC_SMPR1_SMPPLUS */
/**
* @}
*/
@@ -482,7 +482,7 @@
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
-#endif
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
/**
* @brief Set the selected injected Channel rank.
@@ -490,7 +490,8 @@
* @param __RANKNB__ Rank number.
* @retval None
*/
-#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
+ & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
/**
* @brief Configure ADC injected context queue
@@ -658,7 +659,7 @@
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
-#endif
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
/**
* @brief Verify the ADC instance connected to the battery voltage VBAT.
@@ -838,7 +839,7 @@
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
-#endif
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
/**
* @brief Verify the ADC channel setting in differential mode.
@@ -1360,7 +1361,8 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+ ADC_InjectionConfTypeDef *sConfigInjected);
#if defined(ADC_MULTIMODE_SUPPORT)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
#endif /* ADC_MULTIMODE_SUPPORT */
diff --git a/Inc/stm32g4xx_hal_cordic.h b/Inc/stm32g4xx_hal_cordic.h
index 53eacad..d415b75 100644
--- a/Inc/stm32g4xx_hal_cordic.h
+++ b/Inc/stm32g4xx_hal_cordic.h
@@ -198,15 +198,21 @@
#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
-#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
-#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
-#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
+ |CORDIC_CSR_PRECISION_0))
/**
* @}
*/
@@ -257,7 +263,8 @@
*/
#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
32-bit data input (Q1.31 format), or two 16-bit
- data input (Q1.15 format) packed in one 32 bits Data */
+ data input (Q1.15 format) packed in one 32 bits
+ Data */
#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
(Q1.31 format) */
/**
@@ -269,7 +276,8 @@
*/
#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
32-bit data output (Q1.31 format), or two 16-bit
- data output (Q1.15 format) packed in one 32 bits Data */
+ data output (Q1.15 format) packed in one 32 bits
+ Data */
#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
(Q1.31 format) */
/**
@@ -329,9 +337,9 @@
*/
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+ (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
@@ -346,7 +354,7 @@
* @retval None
*/
#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
+ (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
/**
* @brief Disable the CORDIC interrupt
@@ -357,7 +365,7 @@
* @retval None
*/
#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
+ (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified CORDIC interrupt occurred or not.
Dummy macro as no interrupt status flag.
@@ -383,7 +391,7 @@
* @retval SET (flag is set) or RESET (flag is reset)
*/
#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
+ ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear specified CORDIC status flag. Dummy macro as no
flag can be cleared.
@@ -403,7 +411,7 @@
* @retval FlagStatus
*/
#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
+ (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
/**
* @}
@@ -527,7 +535,8 @@
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, pCORDIC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
+ pCORDIC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
/**
* @}
@@ -539,10 +548,14 @@
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
-HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc);
-HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection);
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc);
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t DMADirection);
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_crc.h b/Inc/stm32g4xx_hal_crc.h
index dd95f38..1db487c 100644
--- a/Inc/stm32g4xx_hal_crc.h
+++ b/Inc/stm32g4xx_hal_crc.h
@@ -267,7 +267,6 @@
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
diff --git a/Inc/stm32g4xx_hal_cryp.h b/Inc/stm32g4xx_hal_cryp.h
index a9f0b2e..b6d27e2 100644
--- a/Inc/stm32g4xx_hal_cryp.h
+++ b/Inc/stm32g4xx_hal_cryp.h
@@ -109,7 +109,7 @@
typedef struct
#endif
{
- AES_TypeDef *Instance; /*!< AES Register base address */
+ AES_TypeDef *Instance; /*!< AES Register base address */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
@@ -120,13 +120,13 @@
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
- __IO uint16_t CrypInCount; /*!< Counter of input data */
+ __IO uint16_t CrypInCount; /*!< Counter of input data in words */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data in words */
- uint16_t Size; /*!< length of input data in words */
+ uint16_t Size; /*!< Length of input data */
uint32_t Phase; /*!< CRYP peripheral phase */
diff --git a/Inc/stm32g4xx_hal_dac.h b/Inc/stm32g4xx_hal_dac.h
index d6fc8a1..a9b6759 100644
--- a/Inc/stm32g4xx_hal_dac.h
+++ b/Inc/stm32g4xx_hal_dac.h
@@ -64,7 +64,7 @@
typedef struct __DAC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
@@ -79,17 +79,19 @@
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+
+
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -131,11 +133,13 @@
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection.
- Note: In case of sawtooth wave generation, this trigger corresponds to the reset trigger. */
+ Note: In case of sawtooth wave generation, this
+ trigger corresponds to the reset trigger. */
uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection.
- Note: In case of sawtooth wave generation, this trigger corresponds to the step trigger.*/
+ Note: In case of sawtooth wave generation, this
+ trigger corresponds to the step trigger.*/
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
@@ -150,9 +154,7 @@
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
-
} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -165,10 +167,12 @@
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
+
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
@@ -209,7 +213,7 @@
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
-#define DAC_TRIGGER_NONE 0x00000000U /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */
@@ -255,7 +259,9 @@
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
+
#define DAC_CHANNEL_2 0x00000010U
+
/**
* @}
*/
@@ -275,10 +281,14 @@
* @{
*/
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
+
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
+
#define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
+
#define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
+
/**
* @}
*/
@@ -287,8 +297,10 @@
* @{
*/
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
+
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
+
/**
* @}
*/
@@ -307,9 +319,8 @@
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
-#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */
-#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */
-
+#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
+#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
/**
* @}
*/
@@ -317,7 +328,7 @@
/** @defgroup DAC_SampleAndHold DAC power mode
* @{
*/
-#define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U
+#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
/**
@@ -326,10 +337,10 @@
/** @defgroup DAC_HighFrequency DAC high frequency interface mode
* @{
*/
-#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
-#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002U /*!< High frequency interface mode automatic */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */
/**
* @}
@@ -379,26 +390,28 @@
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
+
/** @brief Set DHR12R2 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
+
/** @brief Set DHR12RD alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1)
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
@@ -410,8 +423,8 @@
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1)
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
@@ -423,23 +436,24 @@
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1)
+ * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of interruption (SET or RESET)
*/
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag (1)
- * @arg DAC_FLAG_DAC1RDY: DAC channel 1 ready status flag
- * @arg DAC_FLAG_DAC2RDY: DAC channel 2 ready status flag (1)
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
+ * @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
+ * @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
@@ -451,8 +465,8 @@
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag (1)
+ * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
@@ -489,9 +503,9 @@
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
-#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU)
+#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
/**
* @}
@@ -528,9 +542,7 @@
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
-
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
@@ -554,7 +566,6 @@
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
@@ -600,7 +611,6 @@
#endif
-#endif /*STM32G4xx_HAL_DAC_H */
+#endif /* STM32G4xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32g4xx_hal_dac_ex.h b/Inc/stm32g4xx_hal_dac_ex.h
index 03e1ab5..2383fb5 100644
--- a/Inc/stm32g4xx_hal_dac_ex.h
+++ b/Inc/stm32g4xx_hal_dac_ex.h
@@ -53,7 +53,7 @@
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
-#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
@@ -65,7 +65,7 @@
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
@@ -85,7 +85,7 @@
/** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode
* @{
*/
-#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000U /*!< Sawtooth wave generation, polarity is decrement */
+#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
#define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
/**
@@ -342,6 +342,6 @@
}
#endif
-#endif /*STM32G4xx_HAL_DAC_EX_H */
+#endif /* STM32G4xx_HAL_DAC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32g4xx_hal_def.h b/Inc/stm32g4xx_hal_def.h
index e30a615..06e1e93 100644
--- a/Inc/stm32g4xx_hal_def.h
+++ b/Inc/stm32g4xx_hal_def.h
@@ -107,7 +107,14 @@
}while (0U)
#endif /* USE_RTOS */
-#if defined ( __GNUC__ )
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@@ -118,7 +125,14 @@
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__GNUC__) /* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4)))
+#endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4U)))
#endif /* __ALIGN_END */
@@ -130,7 +144,7 @@
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
-#if defined (__CC_ARM) /* ARM Compiler */
+#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4U)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@@ -141,9 +155,9 @@
/**
* @brief __RAM_FUNC definition
*/
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+ --------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@@ -173,9 +187,9 @@
/**
* @brief __NOINLINE definition
*/
-#if defined ( __CC_ARM ) || defined ( __GNUC__ )
-/* ARM & GNUCompiler
- ----------------
+#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
+/* ARM V4/V5 and V6 & GNU Compiler
+ -------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
diff --git a/Inc/stm32g4xx_hal_exti.h b/Inc/stm32g4xx_hal_exti.h
index 0872e28..c095702 100644
--- a/Inc/stm32g4xx_hal_exti.h
+++ b/Inc/stm32g4xx_hal_exti.h
@@ -228,19 +228,19 @@
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
-#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
- ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
- (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
+#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
-#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \
- (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
-#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
-#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U)
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
diff --git a/Inc/stm32g4xx_hal_flash.h b/Inc/stm32g4xx_hal_flash.h
index d4f381b..7f6a59c 100644
--- a/Inc/stm32g4xx_hal_flash.h
+++ b/Inc/stm32g4xx_hal_flash.h
@@ -273,6 +273,9 @@
#define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */
#define OB_USER_DBANK 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits data */
#endif
+#if defined (FLASH_OPTR_PB4_PUPEN)
+#define OB_USER_PB4_PUPEN 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */
+#endif
#define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */
#define OB_USER_SRAM_PE 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
#define OB_USER_CCMSRAM_RST 0x00000800U /*!< CCMSRAM Erase when system reset */
@@ -380,6 +383,17 @@
*/
#endif
+#if defined (FLASH_OPTR_PB4_PUPEN)
+/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit
+ * @{
+ */
+#define OB_PB4_PUPEN_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */
+#define OB_PB4_PUPEN_ENABLE FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */
+/**
+ * @}
+ */
+#endif
+
/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
* @{
*/
@@ -952,6 +966,10 @@
#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
#endif
+#if defined (FLASH_OPTR_PB4_PUPEN)
+#define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE))
+#endif
+
#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
#define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
diff --git a/Inc/stm32g4xx_hal_fmac.h b/Inc/stm32g4xx_hal_fmac.h
index 1f289dd..221f640 100644
--- a/Inc/stm32g4xx_hal_fmac.h
+++ b/Inc/stm32g4xx_hal_fmac.h
@@ -28,6 +28,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
+#if defined(FMAC)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
@@ -80,14 +81,16 @@
uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
- In case of early interruption of the filter operation, its value will be updated. */
+ In case of early interruption of the filter operation,
+ its value will be updated. */
int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
- In case of early interruption of the filter operation, its value will be updated. */
+ In case of early interruption of the filter operation,
+ its value will be updated. */
DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
@@ -163,7 +166,8 @@
typedef struct
{
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
- Ignored if InputBufferSize is set to 0 (previous configuration kept).
+ Ignored if InputBufferSize is set to 0
+ (previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom").
@@ -171,17 +175,20 @@
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
in the buffer is lower than this threshold.
- This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+ This parameter can be a value
+ of @ref FMAC_Data_Buffer_Threshold. */
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
- Ignored if CoeffBufferSize is set to 0 (previous configuration kept).
+ Ignored if CoeffBufferSize is set to 0
+ (previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
0 if a previous configuration should be kept. */
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
- Ignored if OuputBufferSize is set to 0 (previous configuration kept).
+ Ignored if OuputBufferSize is set to 0
+ (previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom").
@@ -189,7 +196,8 @@
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
in the buffer is lower than this threshold.
- This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+ This parameter can be a value
+ of @ref FMAC_Data_Buffer_Threshold. */
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
If not needed, it should be set to NULL. */
@@ -197,7 +205,8 @@
uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
- If not needed (re-use of a previously loaded buffer), it should be set to NULL. */
+ If not needed (re-use of a previously loaded buffer),
+ it should be set to NULL. */
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
@@ -208,12 +217,13 @@
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping
- is done when the clipping feature is disabled and saturation is done when the
- clipping feature is enabled.
+ is done when the clipping feature is disabled
+ and saturation is done when the clipping feature is enabled.
This parameter can be a value of @ref FMAC_Clip_State. */
uint32_t Filter; /*!< Filter type.
- This parameter can be a value of @ref FMAC_Functions (filter related values). */
+ This parameter can be a value
+ of @ref FMAC_Functions (filter related values). */
uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
@@ -271,13 +281,17 @@
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
*/
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 1. */
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 2. */
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 4. */
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
- Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */
+ Output: Buffer empty flag set if the number
+ of unread values in the buffer is less than 8. */
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
/**
* @}
@@ -333,6 +347,13 @@
/* External variables --------------------------------------------------------*/
+/** @defgroup FMAC_External_variables FMAC External variables
+ * @{
+ */
+/**
+ * @}
+ */
+
/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
* @{
@@ -444,7 +465,8 @@
* @}
*/
-/** @addtogroup FMAC_Private_Macros
+/* Private Macros-----------------------------------------------------------*/
+/** @addtogroup FMAC_Private_Macros FMAC Private Macros
* @{
*/
@@ -559,11 +581,13 @@
* @param __ACCESS__ Access to the buffer (polling, it, dma, none).
* @retval THRESHOLD
*/
-#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
- ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
- ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
- ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \
- ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
+ (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+ ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+ ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
+ ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
+ ((__WM__) == FMAC_THRESHOLD_1))|| \
+ ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
/**
* @}
@@ -650,18 +674,20 @@
* @}
*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMAC */
+
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_FMAC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32g4xx_hal_irda.h b/Inc/stm32g4xx_hal_irda.h
index 7190535..d72c1af 100644
--- a/Inc/stm32g4xx_hal_irda.h
+++ b/Inc/stm32g4xx_hal_irda.h
@@ -90,7 +90,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -107,7 +107,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -262,15 +262,15 @@
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
* @{
*/
-#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
+#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
@@ -574,12 +574,12 @@
* @retval None
*/
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
- ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << \
+ ((__HANDLE__)->Instance->CR1 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
- ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << \
+ ((__HANDLE__)->Instance->CR2 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << \
+ ((__HANDLE__)->Instance->CR3 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
@@ -595,12 +595,12 @@
* @retval None
*/
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
- ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << \
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
- ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << \
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
@@ -635,7 +635,7 @@
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
- & ((uint32_t)0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+ & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
diff --git a/Inc/stm32g4xx_hal_iwdg.h b/Inc/stm32g4xx_hal_iwdg.h
index da0c946..c79de2c 100644
--- a/Inc/stm32g4xx_hal_iwdg.h
+++ b/Inc/stm32g4xx_hal_iwdg.h
@@ -87,7 +87,6 @@
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-
/**
* @}
*/
@@ -100,7 +99,6 @@
* @}
*/
-
/**
* @}
*/
@@ -138,7 +136,7 @@
* @{
*/
/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
@@ -147,7 +145,7 @@
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_lptim.h b/Inc/stm32g4xx_hal_lptim.h
index d5bb166..6972921 100644
--- a/Inc/stm32g4xx_hal_lptim.h
+++ b/Inc/stm32g4xx_hal_lptim.h
@@ -391,10 +391,10 @@
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -544,31 +544,36 @@
* @retval Interrupt status.
*/
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR2\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR2\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR2 |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR2\
+ |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
-#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR2\
+ &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @}
@@ -580,9 +585,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group1
- * @brief Initialization and Configuration functions.
- * @{
- */
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -595,9 +600,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group2
- * @brief Start-Stop operation functions.
- * @{
- */
+ * @brief Start-Stop operation functions.
+ * @{
+ */
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@@ -651,9 +656,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group3
- * @brief Read operation functions.
- * @{
- */
+ * @brief Read operation functions.
+ * @{
+ */
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
@@ -663,9 +668,9 @@
*/
/** @addtogroup LPTIM_Exported_Functions_Group4
- * @brief LPTIM IRQ handler and callback functions.
- * @{
- */
+ * @brief LPTIM IRQ handler and callback functions.
+ * @{
+ */
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@@ -680,7 +685,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
@@ -688,9 +694,9 @@
*/
/** @addtogroup LPTIM_Group5
- * @brief Peripheral State functions.
- * @{
- */
+ * @brief Peripheral State functions.
+ * @{
+ */
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
@@ -814,31 +820,31 @@
#if defined(COMP5) && defined(COMP6) && defined(COMP7)
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
- ((((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7))))
+ ((((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7))))
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
- (((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6)))
+ (((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6)))
#else
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
- ((((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
- ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3))))
+ ((((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
+ ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3))))
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
- (((__INSTANCE__) == LPTIM1) && \
- (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
- ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4)))
+ (((__INSTANCE__) == LPTIM1) && \
+ (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
+ ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4)))
#endif /* COMP5 && COMP6 && COMP7 */
/**
diff --git a/Inc/stm32g4xx_hal_nand.h b/Inc/stm32g4xx_hal_nand.h
index 4edf511..a2eb70b 100644
--- a/Inc/stm32g4xx_hal_nand.h
+++ b/Inc/stm32g4xx_hal_nand.h
@@ -131,10 +131,10 @@
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
- void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
- void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
-#endif
+ void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
+ void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
+ void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
@@ -146,13 +146,13 @@
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
-}HAL_NAND_CallbackIDTypeDef;
+} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -161,8 +161,8 @@
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
@@ -176,7 +176,7 @@
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -192,7 +192,8 @@
*/
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
@@ -213,18 +214,25 @@
*/
/* IO operation functions ****************************************************/
-
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@@ -232,9 +240,10 @@
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
-HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -266,39 +275,40 @@
/**
* @}
*/
+
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
-#define NAND_DEVICE ((uint32_t)0x80000000U)
-#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
+#define NAND_DEVICE 0x80000000UL
+#define NAND_WRITE_TIMEOUT 0x01000000UL
-#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
+#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
+#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00U)
-#define NAND_CMD_AREA_B ((uint8_t)0x01U)
-#define NAND_CMD_AREA_C ((uint8_t)0x50U)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
-#define NAND_CMD_READID ((uint8_t)0x90U)
-#define NAND_CMD_STATUS ((uint8_t)0x70U)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
-#define NAND_CMD_RESET ((uint8_t)0xFFU)
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
-#define NAND_BUSY ((uint32_t)0x00000000U)
-#define NAND_ERROR ((uint32_t)0x00000001U)
-#define NAND_READY ((uint32_t)0x00000040U)
+#define NAND_VALID_ADDRESS 0x00000100UL
+#define NAND_INVALID_ADDRESS 0x00000200UL
+#define NAND_TIMEOUT_ERROR 0x00000400UL
+#define NAND_BUSY 0x00000000UL
+#define NAND_ERROR 0x00000001UL
+#define NAND_READY 0x00000040UL
/**
* @}
*/
@@ -315,8 +325,14 @@
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+/**
+ * @brief NAND memory Column address computation.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
diff --git a/Inc/stm32g4xx_hal_nor.h b/Inc/stm32g4xx_hal_nor.h
index cf6d5cf..ce87ef5 100644
--- a/Inc/stm32g4xx_hal_nor.h
+++ b/Inc/stm32g4xx_hal_nor.h
@@ -30,7 +30,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_ll_fmc.h"
-
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
@@ -122,10 +121,12 @@
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+ uint32_t CommandSet; /*!< NOR algorithm command set and control */
+
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
- void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
-#endif
+ void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
+ void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
} NOR_HandleTypeDef;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
@@ -136,13 +137,13 @@
{
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
-}HAL_NOR_CallbackIDTypeDef;
+} HAL_NOR_CallbackIDTypeDef;
/**
* @brief HAL NOR Callback pointer definition
*/
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -164,7 +165,7 @@
} while(0)
#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -179,7 +180,8 @@
*/
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
@@ -198,8 +200,10 @@
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
@@ -207,9 +211,10 @@
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/* NOR callback registering/unregistering */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -247,29 +252,29 @@
* @{
*/
/* NOR device IDs addresses */
-#define MC_ADDRESS ((uint16_t)0x0000U)
-#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
-#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
-#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x61U)
-#define CFI2_ADDRESS ((uint16_t)0x62U)
-#define CFI3_ADDRESS ((uint16_t)0x63U)
-#define CFI4_ADDRESS ((uint16_t)0x64U)
+#define CFI1_ADDRESS ((uint16_t)0x0061)
+#define CFI2_ADDRESS ((uint16_t)0x0062)
+#define CFI3_ADDRESS ((uint16_t)0x0063)
+#define CFI4_ADDRESS ((uint16_t)0x0064)
/* NOR operation wait timeout */
-#define NOR_TMEOUT ((uint16_t)0xFFFFU)
+#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0U)
-#define NOR_MEMORY_16B ((uint8_t)0x1U)
+#define NOR_MEMORY_8B ((uint8_t)0x00)
+#define NOR_MEMORY_16B ((uint8_t)0x01)
/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
-#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
-#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
-#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
+#define NOR_MEMORY_ADRESS1 (0x60000000U)
+#define NOR_MEMORY_ADRESS2 (0x64000000U)
+#define NOR_MEMORY_ADRESS3 (0x68000000U)
+#define NOR_MEMORY_ADRESS4 (0x6C000000U)
/**
* @}
*/
@@ -286,7 +291,7 @@
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
- ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
diff --git a/Inc/stm32g4xx_hal_opamp.h b/Inc/stm32g4xx_hal_opamp.h
index 31050a3..c45a199 100644
--- a/Inc/stm32g4xx_hal_opamp.h
+++ b/Inc/stm32g4xx_hal_opamp.h
@@ -335,7 +335,7 @@
/** @defgroup OPAMP_PowerMode OPAMP PowerMode
* @{
*/
-#define OPAMP_POWERMODE_NORMAL (0x00000000UL) /*!< Output in normal mode */
+#define OPAMP_POWERMODE_NORMALSPEED (0x00000000UL) /*!< Output in normal mode */
#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN /*!< Output in highspeed mode */
/**
* @}
diff --git a/Inc/stm32g4xx_hal_pcd.h b/Inc/stm32g4xx_hal_pcd.h
index df2d62b..17ec764 100644
--- a/Inc/stm32g4xx_hal_pcd.h
+++ b/Inc/stm32g4xx_hal_pcd.h
@@ -260,25 +260,41 @@
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_BcdCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_LpmCallbackTypeDef pCallback);
+
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -317,16 +333,24 @@
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type);
+
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint8_t *pBuf, uint32_t len);
+
+
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -412,10 +436,10 @@
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
/* ENDPOINT transfer */
-#define USB_EP0StartXfer USB_EPStartXfer
+#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -424,8 +448,7 @@
* @param wType Endpoint Type.
* @retval None
*/
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -442,18 +465,19 @@
* @param bEpNum, bDir
* @retval None
*/
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
- if ((bDir) == 0U) \
- { \
- /* OUT double buffered endpoint */ \
- PCD_TX_DTOG((USBx), (bEpNum)); \
- } \
- else if ((bDir) == 1U) \
- { \
- /* IN double buffered endpoint */ \
- PCD_RX_DTOG((USBx), (bEpNum)); \
- } \
-} while(0)
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
+ do { \
+ if ((bDir) == 0U) \
+ { \
+ /* OUT double buffered endpoint */ \
+ PCD_TX_DTOG((USBx), (bEpNum)); \
+ } \
+ else if ((bDir) == 1U) \
+ { \
+ /* IN double buffered endpoint */ \
+ PCD_RX_DTOG((USBx), (bEpNum)); \
+ } \
+ } while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
@@ -462,21 +486,22 @@
* @param wState new state
* @retval None
*/
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
- uint16_t _wRegVal; \
- \
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
+ do { \
+ uint16_t _wRegVal; \
+ \
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
- /* toggle first bit ? */ \
- if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
- { \
+ /* toggle first bit ? */ \
+ if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
+ { \
_wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
- { \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
+ { \
_wRegVal ^= USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
/**
@@ -486,19 +511,20 @@
* @param wState new state
* @retval None
*/
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
- _wRegVal ^= USB_EPRX_DTOG1; \
+ _wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
- _wRegVal ^= USB_EPRX_DTOG2; \
+ _wRegVal ^= USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
@@ -511,7 +537,8 @@
* @param wStatetx new state.
* @retval None
*/
-#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
+#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
@@ -573,7 +600,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
+#define PCD_SET_EP_KIND(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@@ -581,7 +609,8 @@
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
@@ -613,7 +642,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
@@ -621,7 +651,8 @@
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
@@ -635,7 +666,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_RX_DTOG(USBx, bEpNum) do { \
+#define PCD_RX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@@ -643,7 +675,8 @@
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
-#define PCD_TX_DTOG(USBx, bEpNum) do { \
+#define PCD_TX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@@ -656,7 +689,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
@@ -667,7 +701,8 @@
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
@@ -685,7 +720,8 @@
* @param bAddr Address.
* @retval None
*/
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
+ do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
@@ -711,23 +747,25 @@
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
- __IO uint16_t *_wRegVal; \
- uint32_t _wRegBase = (uint32_t)USBx; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
- *_wRegVal = ((wAddr) >> 1) << 1; \
-} while(0) /* PCD_SET_EP_TX_ADDRESS */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
+ do { \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+ } while(0) /* PCD_SET_EP_TX_ADDRESS */
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
- __IO uint16_t *_wRegVal; \
- uint32_t _wRegBase = (uint32_t)USBx; \
- \
- _wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
- *_wRegVal = ((wAddr) >> 1) << 1; \
-} while(0) /* PCD_SET_EP_RX_ADDRESS */
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
+ do { \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+ } while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
@@ -745,7 +783,8 @@
* @param wNBlocks no. of Blocks.
* @retval None
*/
-#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
+#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
+ do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
@@ -754,7 +793,8 @@
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
-#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
+#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
+ do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
@@ -763,7 +803,8 @@
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
-#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
+#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
+ do { \
uint32_t wNBlocks; \
if ((wCount) == 0U) \
{ \
@@ -780,10 +821,11 @@
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
- uint32_t _wRegBase = (uint32_t)(USBx); \
- __IO uint16_t *pdwReg; \
- \
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
+ do { \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *pdwReg; \
+ \
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
@@ -796,23 +838,25 @@
* @param wCount Counter value.
* @retval None
*/
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
+ do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
-} while(0)
+ } while(0)
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
+ do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
-} while(0)
+ } while(0)
/**
* @brief gets counter of the tx buffer.
@@ -830,10 +874,13 @@
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
+ do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
+
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
+ do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
@@ -845,7 +892,8 @@
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
+ do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
@@ -868,7 +916,8 @@
* @param wCount: Counter value
* @retval None
*/
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
@@ -884,7 +933,8 @@
} \
} while(0) /* SetEPDblBuf0Count*/
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
@@ -905,7 +955,8 @@
} \
} while(0) /* SetEPDblBuf1Count */
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
+ do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */
diff --git a/Inc/stm32g4xx_hal_pcd_ex.h b/Inc/stm32g4xx_hal_pcd_ex.h
index e8c1b2e..2c74eb0 100644
--- a/Inc/stm32g4xx_hal_pcd_ex.h
+++ b/Inc/stm32g4xx_hal_pcd_ex.h
@@ -49,10 +49,8 @@
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress);
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+ uint16_t ep_kind, uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
diff --git a/Inc/stm32g4xx_hal_rtc.h b/Inc/stm32g4xx_hal_rtc.h
index 5e66443..3fa2e84 100644
--- a/Inc/stm32g4xx_hal_rtc.h
+++ b/Inc/stm32g4xx_hal_rtc.h
@@ -111,12 +111,11 @@
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
- uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
- This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+ uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
+ please use HAL_RTC_DST_xxx functions */
- uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit
- in CR register to store the operation.
- This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+ uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
+ please use HAL_RTC_DST_xxx functions */
} RTC_TimeTypeDef;
/**
@@ -562,6 +561,8 @@
/**
* @brief Add 1 hour (summer time change).
+ * @note This interface is deprecated.
+ * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
* @param __HANDLE__ specifies the RTC handle.
* @param __BKP__ Backup
* This parameter can be:
@@ -579,6 +580,8 @@
/**
* @brief Subtract 1 hour (winter time change).
+ * @note This interface is deprecated.
+ * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
* @param __HANDLE__ specifies the RTC handle.
* @param __BKP__ Backup
* This parameter can be:
@@ -815,6 +818,11 @@
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
@@ -870,7 +878,6 @@
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
RTC_DR_DU)
#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
#define RTC_TIMEOUT_VALUE 1000U
diff --git a/Inc/stm32g4xx_hal_smartcard.h b/Inc/stm32g4xx_hal_smartcard.h
index 4af3163..7896477 100644
--- a/Inc/stm32g4xx_hal_smartcard.h
+++ b/Inc/stm32g4xx_hal_smartcard.h
@@ -163,7 +163,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -180,7 +180,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -346,15 +346,15 @@
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
* @{
*/
-#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
+#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
@@ -690,13 +690,13 @@
*/
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 1U)?\
- ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U <<\
+ ((__HANDLE__)->Instance->CR1 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 2U)?\
- ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U <<\
+ ((__HANDLE__)->Instance->CR2 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U <<\
+ ((__HANDLE__)->Instance->CR3 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
@@ -723,13 +723,13 @@
*/
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 1U)?\
- ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U <<\
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 2U)?\
- ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U <<\
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U <<\
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
@@ -754,9 +754,9 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__)\
- & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U)\
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
+ (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
+ & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
@@ -788,8 +788,9 @@
SMARTCARD_CR_POS) == 0x02U)?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) &\
- ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__))\
- & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
+ (0x01UL << (((uint16_t)(__INTERRUPT__))\
+ & SMARTCARD_IT_MASK))) != 0U)\
+ ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
diff --git a/Inc/stm32g4xx_hal_smbus.h b/Inc/stm32g4xx_hal_smbus.h
index 2bb2d88..a81bbb2 100644
--- a/Inc/stm32g4xx_hal_smbus.h
+++ b/Inc/stm32g4xx_hal_smbus.h
@@ -27,6 +27,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
+#include "stm32g4xx_hal_smbus_ex.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
diff --git a/Inc/stm32g4xx_hal_smbus_ex.h b/Inc/stm32g4xx_hal_smbus_ex.h
new file mode 100644
index 0000000..5b02396
--- /dev/null
+++ b/Inc/stm32g4xx_hal_smbus_ex.h
@@ -0,0 +1,146 @@
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_smbus_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SMBUS HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_SMBUS_EX_H
+#define STM32G4xx_HAL_SMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUSEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
+ * @{
+ */
+#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
+#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
+#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#if defined(SYSCFG_CFGR1_I2C4_FMP)
+#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
+#else
+#define SMBUS_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
+ * @{
+ */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
+ * @{
+ */
+#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
+ ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \
+ (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4)))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32g4xx_hal_smbus_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_SMBUS_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32g4xx_hal_sram.h b/Inc/stm32g4xx_hal_sram.h
index 90c674d..9ccff8c 100644
--- a/Inc/stm32g4xx_hal_sram.h
+++ b/Inc/stm32g4xx_hal_sram.h
@@ -62,7 +62,7 @@
typedef struct __SRAM_HandleTypeDef
#else
typedef struct
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
@@ -77,11 +77,11 @@
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
- void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
- void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
- void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
-#endif
+ void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
+ void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
+ void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
} SRAM_HandleTypeDef;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
@@ -94,14 +94,14 @@
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
-}HAL_SRAM_CallbackIDTypeDef;
+} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
*/
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -110,8 +110,8 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
@@ -125,7 +125,7 @@
} while(0)
#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
@@ -137,11 +137,12 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
@@ -151,36 +152,46 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @{
- */
+ * @{
+ */
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
-#endif
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
- * @{
- */
+ * @{
+ */
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
@@ -191,8 +202,8 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
+ * @{
+ */
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
diff --git a/Inc/stm32g4xx_hal_tim.h b/Inc/stm32g4xx_hal_tim.h
index b7516e4..f9ac00d 100644
--- a/Inc/stm32g4xx_hal_tim.h
+++ b/Inc/stm32g4xx_hal_tim.h
@@ -1142,32 +1142,32 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
@@ -2299,7 +2299,7 @@
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
-
+
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
@@ -2322,7 +2322,7 @@
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
-
+
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
diff --git a/Inc/stm32g4xx_hal_uart.h b/Inc/stm32g4xx_hal_uart.h
index bf38d1a..64fb89d 100644
--- a/Inc/stm32g4xx_hal_uart.h
+++ b/Inc/stm32g4xx_hal_uart.h
@@ -46,54 +46,54 @@
*/
typedef struct
{
- uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate register is computed using the following formula:
- LPUART:
- =======
- Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
- where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
- UART:
- =====
- - If oversampling is 16 or in LIN mode,
- Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
- - If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
- ((huart->Init.BaudRate)))[15:4]
- Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
- ((huart->Init.BaudRate)))[3:0]) >> 1
- where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ LPUART:
+ =======
+ Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+ where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+ UART:
+ =====
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck_pres is the UART input clock divided by a prescaler */
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UARTEx_Word_Length. */
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length. */
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits. */
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits. */
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode. */
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode. */
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
- to achieve higher speed (up to f_PCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling. */
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+ to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling. */
- uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
- uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
- This parameter can be a value of @ref UART_ClockPrescaler. */
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
+ This parameter can be a value of @ref UART_ClockPrescaler. */
} UART_InitTypeDef;
@@ -151,7 +151,7 @@
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
+ * 1 : Init done (Peripheral initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@@ -168,7 +168,7 @@
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -193,6 +193,17 @@
} UART_ClockSourceTypeDef;
/**
+ * @brief HAL UART Reception type definition
+ * @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
+ * It is expected to admit following values :
+ * HAL_UART_RECEPTION_STANDARD = 0x00U,
+ * HAL_UART_RECEPTION_TOIDLE = 0x01U,
+ * HAL_UART_RECEPTION_TORTO = 0x02U,
+ * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
+ */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -224,6 +235,8 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -255,6 +268,7 @@
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
+ void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
@@ -288,7 +302,9 @@
/**
* @brief HAL UART Callback pointer definition
*/
-typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -328,16 +344,16 @@
/** @defgroup UART_Error_Definition UART Error Definition
* @{
*/
-#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
-#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
+#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@@ -790,6 +806,20 @@
* @}
*/
+/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+ * @{
+ */
+#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
+#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
+#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
+#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
+/**
+ * @}
+ */
+
+/* Prescaler Table used in BRR computation macros.
+ Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
/**
* @}
@@ -1200,7 +1230,6 @@
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
-
/** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock.
* @param __BAUD__ Baud rate set by the user.
@@ -1547,12 +1576,6 @@
/* Include UART HAL Extended module */
#include "stm32g4xx_hal_uart_ex.h"
-
-/* Prescaler Table used in BRR computation macros.
- Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
-extern const uint16_t UARTPrescTable[12];
-
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
@@ -1576,6 +1599,9 @@
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@@ -1614,6 +1640,8 @@
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
/**
* @}
*/
@@ -1659,13 +1687,15 @@
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}
diff --git a/Inc/stm32g4xx_hal_uart_ex.h b/Inc/stm32g4xx_hal_uart_ex.h
index 2450681..d88d61f 100644
--- a/Inc/stm32g4xx_hal_uart_ex.h
+++ b/Inc/stm32g4xx_hal_uart_ex.h
@@ -99,12 +99,12 @@
* @brief UART TXFIFO threshold level
* @{
*/
-#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
-#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
-#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
-#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
+#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
@@ -113,12 +113,12 @@
* @brief UART RXFIFO threshold level
* @{
*/
-#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
-#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
-#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
-#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
+#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
@@ -174,6 +174,12 @@
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_usart.h b/Inc/stm32g4xx_hal_usart.h
index a51ac4e..5d213cb 100644
--- a/Inc/stm32g4xx_hal_usart.h
+++ b/Inc/stm32g4xx_hal_usart.h
@@ -220,17 +220,17 @@
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */
+#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */
+#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
@@ -266,15 +266,6 @@
* @}
*/
-/** @defgroup USART_Over_Sampling USART Over Sampling
- * @{
- */
-#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
/** @defgroup USART_Clock USART Clock
* @{
*/
@@ -556,10 +547,10 @@
*/
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
- ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
- ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
+ ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
@@ -581,10 +572,10 @@
*/
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
- ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
- ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
+ ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -607,7 +598,7 @@
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
+ & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
@@ -837,14 +828,6 @@
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
- * @brief Ensure that USART oversampling is valid.
- * @param __SAMPLING__ USART oversampling.
- * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == USART_OVERSAMPLING_8))
-
-/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
diff --git a/Inc/stm32g4xx_hal_usart_ex.h b/Inc/stm32g4xx_hal_usart_ex.h
index 96a67cd..e03d595 100644
--- a/Inc/stm32g4xx_hal_usart_ex.h
+++ b/Inc/stm32g4xx_hal_usart_ex.h
@@ -45,9 +45,9 @@
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_adc.h b/Inc/stm32g4xx_ll_adc.h
index beb7ba6..ddedfba 100644
--- a/Inc/stm32g4xx_ll_adc.h
+++ b/Inc/stm32g4xx_ll_adc.h
@@ -58,7 +58,8 @@
#define ADC_SQR3_REGOFFSET (0x00000200UL)
#define ADC_SQR4_REGOFFSET (0x00000300UL)
-#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+ | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
@@ -95,7 +96,8 @@
#define ADC_JDR3_REGOFFSET (0x00000200UL)
#define ADC_JDR4_REGOFFSET (0x00000300UL)
-#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+ | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
@@ -178,7 +180,8 @@
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
-#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
+ | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
@@ -200,24 +203,25 @@
/* Definition of channels ID number information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
-#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
-#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
-#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
+ ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
/* Definition of channels ID bitfield information to be inserted into */
/* channels literals definition. */
@@ -321,7 +325,8 @@
#define ADC_OFR2_REGOFFSET (0x00000001UL)
#define ADC_OFR3_REGOFFSET (0x00000002UL)
#define ADC_OFR4_REGOFFSET (0x00000003UL)
-#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+ | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
/* ADC registers bits positions */
@@ -347,7 +352,6 @@
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
-
/**
* @}
*/
@@ -615,7 +619,7 @@
#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
@@ -648,7 +652,7 @@
#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#if defined(ADC_MULTIMODE_SUPPORT)
#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
@@ -1515,19 +1519,19 @@
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tADCVREG_STUP"). */
/* Unit: us */
-#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
/* Delay for internal voltage reference stabilization time. */
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tstart_vrefint"). */
/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
/* Note: On this STM32 series, a minimum number of ADC clock cycles */
@@ -1536,7 +1540,7 @@
/* equivalent number of CPU cycles, by taking into account */
/* ratio of CPU clock versus ADC clock prescalers. */
/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
/**
* @}
@@ -1634,10 +1638,10 @@
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
- ? ( \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
+ ( \
((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
- ) \
+ ) \
: \
( \
(uint32_t)POSITION_VAL((__CHANNEL__)) \
@@ -1698,12 +1702,12 @@
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9UL) \
- ? ( \
+ (((__DECIMAL_NB__) <= 9UL) ? \
+ ( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
+ ) \
: \
( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
@@ -2275,7 +2279,7 @@
*/
#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
(((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
#if defined(ADC_MULTIMODE_SUPPORT)
/**
@@ -2311,8 +2315,8 @@
: \
(__ADCx__) \
)
-#endif
-#endif
+#endif /* ADC5 */
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
@@ -2337,7 +2341,7 @@
)
#else
#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
-#endif
+#endif /* ADC345_COMMON */
/**
* @brief Helper macro to check if all ADC instances sharing the same
* ADC common instance are disabled.
@@ -2422,11 +2426,11 @@
*/
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
- __ADC_RESOLUTION_TARGET__) \
- (((__DATA__) \
- << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
- >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
- )
+ __ADC_RESOLUTION_TARGET__) \
+(((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+)
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@@ -2446,10 +2450,10 @@
*/
#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- )
+ __ADC_RESOLUTION__) \
+((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+)
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@@ -2477,11 +2481,12 @@
* @retval Analog reference voltage (unit: mV)
*/
#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
- / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_12B))
+ __ADC_RESOLUTION__) \
+(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2530,17 +2535,17 @@
*/
#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_12B) \
- * (__VREFANALOG_VOLTAGE__)) \
- / TEMPSENSOR_CAL_VREFANALOG) \
- - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
- ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
- ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
- ) + TEMPSENSOR_CAL1_TEMP \
- )
+ __ADC_RESOLUTION__) \
+(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2591,18 +2596,17 @@
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((( ( \
- (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
- * 1000UL) \
- - \
- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
- * 1000UL) \
- ) \
- ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
- ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
- )
+ __ADC_RESOLUTION__) \
+(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000UL) \
+ - \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000UL) \
+ ) \
+ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
+)
/**
* @}
@@ -2682,7 +2686,7 @@
/* Retrieve address of register DR */
return (uint32_t) &(ADCx->DR);
}
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
@@ -2944,7 +2948,9 @@
/* "SingleDiff". */
/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
/* containing other bits reserved for other purpose. */
- return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+ return (uint32_t)(READ_BIT(ADCx->CALFACT,
+ (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+ ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
}
/**
@@ -5716,7 +5722,7 @@
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
/* containing other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
MODIFY_REG(*preg,
(AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
@@ -5848,7 +5854,7 @@
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
@@ -6026,7 +6032,8 @@
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+ ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
@@ -6063,12 +6070,13 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
- const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+ ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
(AWDThresholdsHighLow | ADC_TR1_LT1))
- >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
- );
+ >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
+ & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
}
/**
diff --git a/Inc/stm32g4xx_ll_cordic.h b/Inc/stm32g4xx_ll_cordic.h
index 5e1126d..ec3796f 100644
--- a/Inc/stm32g4xx_ll_cordic.h
+++ b/Inc/stm32g4xx_ll_cordic.h
@@ -95,15 +95,21 @@
#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
-#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
-#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
-#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
-#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
+#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
+#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
+ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
+ | CORDIC_CSR_PRECISION_0))
/**
* @}
*/
@@ -127,8 +133,9 @@
* @{
*/
#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
- 32-bit data input (Q1.31 format), or two 16-bit
- data input (Q1.15 format) packed in one 32 bits Data */
+ 32-bit data input (Q1.31 format), or two
+ 16-bit data input (Q1.15 format) packed
+ in one 32 bits Data */
#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
(Q1.31 format) */
/**
@@ -139,8 +146,9 @@
* @{
*/
#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
- 32-bit data output (Q1.31 format), or two 16-bit
- data output (Q1.15 format) packed in one 32 bits Data */
+ 32-bit data output (Q1.31 format), or two
+ 16-bit data output (Q1.15 format) packed
+ in one 32 bits Data */
#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
(Q1.31 format) */
/**
@@ -292,7 +300,8 @@
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
* @retval None
*/
-__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
+__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale,
+ uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
{
MODIFY_REG(CORDICx->CSR,
CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |
@@ -676,12 +685,12 @@
if (Direction == LL_CORDIC_DMA_REG_DATA_OUT)
{
/* return address of RDATA register */
- data_reg_addr = (uint32_t) & (CORDICx->RDATA);
+ data_reg_addr = (uint32_t) &(CORDICx->RDATA);
}
else
{
/* return address of WDATA register */
- data_reg_addr = (uint32_t) & (CORDICx->WDATA);
+ data_reg_addr = (uint32_t) &(CORDICx->WDATA);
}
return data_reg_addr;
diff --git a/Inc/stm32g4xx_ll_dac.h b/Inc/stm32g4xx_ll_dac.h
index 1eaed74..2135c66 100644
--- a/Inc/stm32g4xx_ll_dac.h
+++ b/Inc/stm32g4xx_ll_dac.h
@@ -55,8 +55,10 @@
/* - channel register offset of data output register DORx */
/* - channel register offset of sample-and-hold sample time register SHSRx */
/* - channel register offset of sawtooth register STRx */
-#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
+#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
+ CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
@@ -67,39 +69,68 @@
#define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
#define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
-#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
-#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
-#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
+#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 28 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
+ DHR12Rx channel 1 (shifted left of 24 bits) */
+
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
+ | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
+
+#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
+ DORx channel 2 (shifted left of 5 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-#define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */
-#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
+
+#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
+#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
+ SHSRx channel 2 (shifted left of 6 bits) */
#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
-#define DAC_REG_STR1_REGOFFSET 0x00000000U /* Register STRx channel 1 taken as reference */
-#define DAC_REG_STR2_REGOFFSET 0x00000080U /* Register offset of STRx channel 1 versus STRx channel 2 (shifted left of 7 bits) */
+#define DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */
+#define DAC_REG_STR2_REGOFFSET 0x00000080UL /* Register offset of STRx channel 1 versus
+ STRx channel 2 (shifted left of 7 bits) */
#define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
-#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
-#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */
-#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */
-#define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of STRx registers offset when shifted to position 0 */
+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
+ DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
+ to position 0 */
+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
+ to position 0 */
+#define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of STRx registers offset when shifted
+ to position 0 */
-#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
-#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
-#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
-#define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7U /* Position of bits register offset of STRx channel 1 or 2 versus STRx channel 1 (shifted left of 7 bits) */
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 28 bits) */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 20 bits) */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
+ channel 1 or 2 versus DHR12Rx channel 1
+ (shifted left of 24 bits) */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
+ channel 1 or 2 versus DORx channel 1
+ (shifted left of 5 bits) */
+#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
+ channel 1 or 2 versus SHSRx channel 1
+ (shifted left of 6 bits) */
+#define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7UL /* Position of bits register offset of STRx
+ channel 1 or 2 versus STRx channel 1
+ (shifted left of 7 bits) */
/* DAC registers bits positions */
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
@@ -107,7 +138,9 @@
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
+ bits (voltage range determined by analog voltage
+ references Vref+ and Vref-, refer to reference manual) */
/**
* @}
@@ -126,9 +159,9 @@
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
-*/
+ */
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
@@ -146,48 +179,68 @@
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
+ internal (SW start) or from external peripheral
+ (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource().
- @note If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth RESET trigger */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetTriggerSource().
+ @note If waveform automatic generation mode is set to sawtooth,
+ this parameter is used as sawtooth RESET trigger */
- uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel:
+ internal (SW start) or from external peripheral
+ (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource2().
- @note If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth
- step trigger */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetTriggerSource2().
+ @note If waveform automatic generation mode is set to sawtooth,
+ this parameter is used as sawtooth step trigger */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- If waveform automatic generation mode is set to sawtooth, this parameter host the sawtooth configuration: polarity, reset data, increment data. Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to
- set this parameter value.
- @note If waveform automatic generation mode is disabled, this parameter is discarded.
+ If waveform automatic generation mode is set to noise, this parameter
+ can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle,
+ this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ If waveform automatic generation mode is set to sawtooth, this parameter
+ host the sawtooth configuration: polarity, reset data, increment data.
+ Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value.
+ @note If waveform automatic generation mode is disabled,
+ this parameter is discarded.
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude(), @ref LL_DAC_SetWaveSawtoothPolarity(), @ref LL_DAC_SetWaveSawtoothResetData() or @ref LL_DAC_SetWaveSawtoothStepData(), depending on the wave automatic generation selected. */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetWaveNoiseLFSR(),
+ @ref LL_DAC_SetWaveTriangleAmplitude(),
+ @ref LL_DAC_SetWaveSawtoothPolarity(),
+ @ref LL_DAC_SetWaveSawtoothResetData()
+ or @ref LL_DAC_SetWaveSawtoothStepData(),
+ depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
-
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputBuffer(). */
uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputConnection(). */
- uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
+ uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
+ channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
+ This feature can be modified afterwards using unitary
+ function @ref LL_DAC_SetOutputMode(). */
} LL_DAC_InitTypeDef;
/**
@@ -217,6 +270,7 @@
#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
#define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
#define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
+
/**
* @}
*/
@@ -226,7 +280,9 @@
* @{
*/
#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+
#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+
/**
* @}
*/
@@ -241,10 +297,11 @@
*/
/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
- * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
+ * @brief High frequency interface mode defines that can be used
+ * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
* @{
*/
-#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */
+#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
#define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
/**
@@ -254,7 +311,7 @@
/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
* @{
*/
-#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /*!< DAC channel in mode normal operation */
+#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
/**
* @}
@@ -263,7 +320,7 @@
/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
* @{
*/
-#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC (all) channel conversion trigger internal (SW start) */
+#define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC (all) channel conversion trigger internal (SW start) */
#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */
@@ -296,7 +353,7 @@
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
* @{
*/
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
#define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */
@@ -307,7 +364,7 @@
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
* @{
*/
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
@@ -326,7 +383,7 @@
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
* @{
*/
-#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
@@ -345,7 +402,7 @@
/** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode
* @{
*/
-#define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000U /*!< Sawtooth wave generation, polarity is decrement */
+#define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
#define LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
/**
* @}
@@ -354,7 +411,7 @@
/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
* @{
*/
-#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */
+#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
/**
* @}
@@ -363,7 +420,7 @@
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
* @{
*/
-#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
/**
* @}
@@ -372,7 +429,7 @@
/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
* @{
*/
-#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */
+#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
/**
* @}
@@ -381,7 +438,7 @@
/** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
* @{
*/
-#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000U /*!< The selected DAC channel data format is not signed */
+#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
#define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
/**
* @}
@@ -390,8 +447,8 @@
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
* @{
*/
-#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
+#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
/**
* @}
*/
@@ -429,7 +486,7 @@
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
@@ -442,7 +499,7 @@
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSETTLING"). */
/* Unit: us */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
/**
* @}
@@ -521,22 +578,8 @@
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
*/
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
- ? ( \
- LL_DAC_CHANNEL_1 \
- ) \
- : \
- (((__DECIMAL_NB__) == 2U) \
- ? ( \
- LL_DAC_CHANNEL_2 \
- ) \
- : \
- ( \
- 0U \
- ) \
- ) \
- )
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
+ (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
/**
* @brief Helper macro to define the DAC conversion data full-scale digital
@@ -550,7 +593,7 @@
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+ ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
/**
* @brief Helper macro to calculate the DAC conversion data (unit: digital
@@ -561,7 +604,7 @@
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
@@ -573,9 +616,9 @@
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
__DAC_VOLTAGE__,\
__DAC_RESOLUTION__) \
- ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
- )
+((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+)
/**
* @brief Helper macro to format sawtooth wave generation configuration
@@ -589,10 +632,10 @@
#define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__,\
__RESET_DATA__,\
__STEP_DATA__) \
- ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \
- | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \
- | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \
- )
+( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \
+ | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \
+ | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \
+)
/**
* @}
@@ -607,7 +650,7 @@
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DAC_LL_EF_Configuration Configuration of DAC instance
+/** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
* @{
*/
/**
@@ -1633,11 +1676,10 @@
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_SHSR1_TSAMPLE1,
- SampleTime);
+ MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
}
/**
@@ -1656,7 +1698,8 @@
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
}
@@ -1942,7 +1985,8 @@
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
+ * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
@@ -1967,8 +2011,8 @@
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
- ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
@@ -2211,11 +2255,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR12R1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
@@ -2236,11 +2279,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR12L1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
@@ -2261,11 +2303,10 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
- MODIFY_REG(*preg,
- DAC_DHR8R1_DACC1DHR,
- Data);
+ MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
@@ -2349,7 +2390,8 @@
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
+ & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
@@ -2396,7 +2438,6 @@
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
}
-
/**
* @brief Get DAC busy writing sample time flag for DAC channel 2
* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
@@ -2456,7 +2497,6 @@
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
}
-
/**
* @brief Get DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
diff --git a/Inc/stm32g4xx_ll_dma.h b/Inc/stm32g4xx_ll_dma.h
index 0a4e3b3..441a10d 100644
--- a/Inc/stm32g4xx_ll_dma.h
+++ b/Inc/stm32g4xx_ll_dma.h
@@ -1933,6 +1933,10 @@
/**
* @brief Clear Channel 1 global interrupt flag.
+ * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
+ LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
* @param DMAx DMAx Instance
* @retval None
@@ -1944,6 +1948,10 @@
/**
* @brief Clear Channel 2 global interrupt flag.
+ * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
+ LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
* @param DMAx DMAx Instance
* @retval None
@@ -1955,6 +1963,10 @@
/**
* @brief Clear Channel 3 global interrupt flag.
+ * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
+ LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
* @param DMAx DMAx Instance
* @retval None
@@ -1966,6 +1978,10 @@
/**
* @brief Clear Channel 4 global interrupt flag.
+ * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
+ LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
* @param DMAx DMAx Instance
* @retval None
@@ -1977,6 +1993,10 @@
/**
* @brief Clear Channel 5 global interrupt flag.
+ * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
+ LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
* @param DMAx DMAx Instance
* @retval None
@@ -1988,6 +2008,10 @@
/**
* @brief Clear Channel 6 global interrupt flag.
+ * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
+ LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
* @param DMAx DMAx Instance
* @retval None
@@ -2000,6 +2024,10 @@
#if defined (DMA1_Channel7)
/**
* @brief Clear Channel 7 global interrupt flag.
+ * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
+ LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
* @param DMAx DMAx Instance
* @retval None
@@ -2013,6 +2041,10 @@
#if defined (DMA1_Channel8)
/**
* @brief Clear Channel 8 global interrupt flag.
+ * @note Do not Clear Channel 8 global interrupt flag when the channel in ON.
+ Instead clear specific flags transfer complete, half transfer & transfer
+ error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8,
+ LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
* @param DMAx DMAx Instance
* @retval None
diff --git a/Inc/stm32g4xx_ll_fmac.h b/Inc/stm32g4xx_ll_fmac.h
index 5d860c8..d67834e 100644
--- a/Inc/stm32g4xx_ll_fmac.h
+++ b/Inc/stm32g4xx_ll_fmac.h
@@ -201,7 +201,8 @@
* @brief Return X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
* @param FMACx FMAC instance
- * @retval uint8_t Number of 16-bit words allocated to the input buffer (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
+ * @retval uint8_t Number of 16-bit words allocated to the input buffer
+ * (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
{
@@ -225,7 +226,8 @@
* @brief Return X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base
* @param FMACx FMAC instance
- * @retval uint8_t Base address of the input buffer (X1) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).
+ * @retval uint8_t Base address of the input buffer (X1) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
{
@@ -249,7 +251,8 @@
* @brief Return X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
* @param FMACx FMAC instance
- * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer (value between Min_Data=0x01 and Max_Data=0xFF).
+ * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
+ * (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
{
@@ -273,7 +276,8 @@
* @brief Return X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base
* @param FMACx FMAC instance
- * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).
+ * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
{
@@ -328,7 +332,8 @@
* @brief Return Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
* @param FMACx FMAC instance
- * @retval uint8_t Number of 16-bit words allocated to the output buffer (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
+ * @retval uint8_t Number of 16-bit words allocated to the output buffer
+ * (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
{
@@ -352,7 +357,8 @@
* @brief Return Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase
* @param FMACx FMAC instance
- * @retval uint8_t Base address of the output buffer (Y) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF).
+ * @retval uint8_t Base address of the output buffer (Y) within the internal memory
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
{
@@ -490,7 +496,8 @@
* @brief Return input parameter P.
* @rmtoll PARAM P LL_FMAC_GetParamP
* @param FMACx FMAC instance
- * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
+ * @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
+ * (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
{
@@ -938,7 +945,8 @@
__STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
- Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
+ Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
}
/**
@@ -955,7 +963,8 @@
__STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
- (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
+ (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
}
/**
@@ -978,7 +987,8 @@
__STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
- Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
+ Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) |
+ (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
}
/**
@@ -1010,7 +1020,8 @@
uint8_t ParamQ, uint8_t ParamR)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
- (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
+ (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) |
+ (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
}
/**
diff --git a/Inc/stm32g4xx_ll_fmc.h b/Inc/stm32g4xx_ll_fmc.h
index 8d97426..7084348 100644
--- a/Inc/stm32g4xx_ll_fmc.h
+++ b/Inc/stm32g4xx_ll_fmc.h
@@ -157,76 +157,75 @@
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
- This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
- This parameter can be a value of @ref FMC_Memory_Type */
+ This parameter can be a value of @ref FMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FMC_Burst_Access_Mode */
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FMC_Wait_Timing */
+ This parameter can be a value of @ref FMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
- This parameter can be a value of @ref FMC_Write_Operation */
+ This parameter can be a value of @ref FMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal */
+ This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FMC_Extended_Mode */
+ This parameter can be a value of @ref FMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FMC_AsynchronousWait */
+ This parameter can be a value of @ref FMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
+ This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Continous_Clock */
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Write_FIFO */
+ This parameter is only enabled through the FMC_BCR1 register,
+ and don't care through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Write_FIFO */
uint32_t PageSize; /*!< Specifies the memory page size.
- This parameter can be a value of @ref FMC_Page_Size */
+ This parameter can be a value of @ref FMC_Page_Size */
uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
- This parameter can be a value of @ref FMC_Byte_Lane */
+ This parameter can be a value of @ref FMC_Byte_Lane */
- FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank
- for PSRAM refresh.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this
+ NSBank for PSRAM refresh.
+ This parameter can be set to ENABLE or DISABLE */
- uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous
- accesses and in HCLK cycles for asynchronous accesses,
+ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for
+ synchronous accesses and in HCLK cycles for asynchronous accesses,
valid only if MaxChipSelectPulse is ENABLE.
This parameter can be a value between Min_Data = 1 and Max_Data = 65535.
- @note: This parameter is common to all NSBank. */
-
-}FMC_NORSRAM_InitTypeDef;
+ @note: This parameter is common to all NSBank. */
+} FMC_NORSRAM_InitTypeDef;
/**
* @brief FMC NORSRAM Timing parameters structure definition
@@ -236,45 +235,46 @@
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
+ @note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
+ @note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
- NOR Flash memories. */
+ NOR Flash memories. */
uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data hold time.
This parameter can be a value between Min_Data = 0 and Max_Data = 3.
- @note This parameter is used for used in asynchronous accesses. */
+ @note This parameter is used for used in asynchronous accesses. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
+ @note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
- HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and
+ Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
- accesses. */
+ accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
- with synchronous burst mode enable */
+ - It may assume a value between Min_Data = 2 and Max_Data = 17
+ in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FMC_Access_Mode */
-}FMC_NORSRAM_TimingTypeDef;
+ This parameter can be a value of @ref FMC_Access_Mode */
+} FMC_NORSRAM_TimingTypeDef;
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
@@ -284,19 +284,19 @@
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
+ This parameter can be a value of @ref FMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FMC_Wait_feature */
+ This parameter can be any value of @ref FMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FMC_NAND_Data_Width */
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FMC_ECC */
+ This parameter can be any value of @ref FMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FMC_ECC_Page_Size */
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
@@ -305,8 +305,10 @@
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FMC_NAND_InitTypeDef;
+} FMC_NAND_InitTypeDef;
+#endif
+#if defined(FMC_BANK3)
/**
* @brief FMC NAND Timing parameters structure definition
*/
@@ -336,9 +338,10 @@
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-}FMC_NAND_PCC_TimingTypeDef;
+} FMC_NAND_PCC_TimingTypeDef;
#endif /* FMC_BANK3 */
+
/**
* @}
*/
@@ -356,10 +359,10 @@
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
-#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
-#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
-#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
-#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
+#define FMC_NORSRAM_BANK1 (0x00000000U)
+#define FMC_NORSRAM_BANK2 (0x00000002U)
+#define FMC_NORSRAM_BANK3 (0x00000004U)
+#define FMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
@@ -367,8 +370,8 @@
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
+#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
+#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
@@ -376,9 +379,9 @@
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
+#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
+#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
+#define FMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
@@ -386,9 +389,9 @@
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
@@ -396,8 +399,8 @@
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
@@ -405,8 +408,8 @@
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
+#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
+#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
@@ -414,8 +417,8 @@
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
+#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
@@ -423,8 +426,8 @@
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
+#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
+#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
@@ -432,8 +435,8 @@
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
+#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
+#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
@@ -441,8 +444,8 @@
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
+#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
+#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
@@ -450,8 +453,8 @@
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
+#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
+#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
@@ -459,8 +462,8 @@
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
@@ -468,11 +471,12 @@
/** @defgroup FMC_Page_Size FMC Page Size
* @{
*/
-#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
-#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
-#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
-#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
-#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
+#define FMC_PAGE_SIZE_NONE (0x00000000U)
+#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
+#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
+#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
+ | FMC_BCRx_CPSIZE_1)
+#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
/**
* @}
*/
@@ -480,8 +484,8 @@
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
+#define FMC_WRITE_BURST_DISABLE (0x00000000U)
+#define FMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
@@ -489,8 +493,8 @@
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
@@ -498,8 +502,8 @@
/** @defgroup FMC_Write_FIFO FMC Write FIFO
* @{
*/
-#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
-#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
+#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
+#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
/**
* @}
*/
@@ -507,10 +511,10 @@
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
-#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
-#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
-#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
-#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
+#define FMC_ACCESS_MODE_A (0x00000000U)
+#define FMC_ACCESS_MODE_B (0x10000000U)
+#define FMC_ACCESS_MODE_C (0x20000000U)
+#define FMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
@@ -518,10 +522,10 @@
/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
* @{
*/
-#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U)
-#define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000U)
-#define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000U)
-#define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000U)
+#define FMC_NBL_SETUPTIME_0 (0x00000000U)
+#define FMC_NBL_SETUPTIME_1 (0x00400000U)
+#define FMC_NBL_SETUPTIME_2 (0x00800000U)
+#define FMC_NBL_SETUPTIME_3 (0x00C00000U)
/**
* @}
*/
@@ -539,7 +543,7 @@
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
+#define FMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
@@ -547,8 +551,8 @@
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
-#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
-#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
+#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
+#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
@@ -556,7 +560,7 @@
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
+#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
@@ -564,8 +568,8 @@
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
-#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
-#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
+#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
+#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
@@ -573,8 +577,8 @@
/** @defgroup FMC_ECC FMC ECC
* @{
*/
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
+#define FMC_NAND_ECC_DISABLE (0x00000000U)
+#define FMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
@@ -582,12 +586,12 @@
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
@@ -602,9 +606,9 @@
* @{
*/
#if defined(FMC_BANK3)
-#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
-#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
-#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
+#define FMC_IT_RISING_EDGE (0x00000008U)
+#define FMC_IT_LEVEL (0x00000010U)
+#define FMC_IT_FALLING_EDGE (0x00000020U)
#endif /* FMC_BANK3 */
/**
* @}
@@ -614,14 +618,15 @@
* @{
*/
#if defined(FMC_BANK3)
-#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
-#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
+#define FMC_FLAG_RISING_EDGE (0x00000001U)
+#define FMC_FLAG_LEVEL (0x00000002U)
+#define FMC_FLAG_FALLING_EDGE (0x00000004U)
+#define FMC_FLAG_FEMPT (0x00000040U)
#endif /* FMC_BANK3 */
/**
* @}
*/
+
/**
* @}
*/
@@ -646,7 +651,8 @@
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
-#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ |= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
@@ -654,7 +660,8 @@
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ &= ~FMC_BCRx_MBKEN)
/**
* @}
@@ -663,9 +670,9 @@
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
/**
* @brief Enable the NAND device access.
@@ -685,7 +692,9 @@
/**
* @}
*/
+#endif
+#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
* @brief macros to handle NAND interrupts
* @{
@@ -747,6 +756,7 @@
*/
#endif /* FMC_BANK3 */
+
/**
* @}
*/
@@ -767,10 +777,15 @@
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
@@ -796,8 +811,10 @@
* @{
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
@@ -808,7 +825,8 @@
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout);
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_hrtim.h b/Inc/stm32g4xx_ll_hrtim.h
index 2b974b2..d2437da 100644
--- a/Inc/stm32g4xx_ll_hrtim.h
+++ b/Inc/stm32g4xx_ll_hrtim.h
@@ -9644,10 +9644,10 @@
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
- uint64_t cfg = ((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
- (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
- uint64_t mask = ((uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */
- ((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U) ; /* this for SouRCe bit 1 */
+ uint64_t cfg = ( (uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */
+ (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
+ uint64_t mask = ( (uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */
+ (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */
MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
diff --git a/Inc/stm32g4xx_ll_iwdg.h b/Inc/stm32g4xx_ll_iwdg.h
index 40f4ab8..9a1b24a 100644
--- a/Inc/stm32g4xx_ll_iwdg.h
+++ b/Inc/stm32g4xx_ll_iwdg.h
@@ -304,8 +304,8 @@
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
- * SR WVU LL_IWDG_IsReady\n
- * SR RVU LL_IWDG_IsReady
+ * SR RVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
@@ -318,7 +318,6 @@
* @}
*/
-
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_lptim.h b/Inc/stm32g4xx_ll_lptim.h
index 1b0198a..feb22f4 100644
--- a/Inc/stm32g4xx_ll_lptim.h
+++ b/Inc/stm32g4xx_ll_lptim.h
@@ -100,9 +100,9 @@
* @{
*/
#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
+#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
-#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
@@ -114,13 +114,13 @@
* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
* @{
*/
-#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
-#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
-#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
-#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
-#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
-#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
-#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
+#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
+#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
+#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
+#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
+#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
+#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
+#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
/**
* @}
*/
@@ -1367,7 +1367,7 @@
/**
* @brief Enable autoreload register write completed interrupt (ARROKIE).
- * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1378,7 +1378,7 @@
/**
* @brief Disable autoreload register write completed interrupt (ARROKIE).
- * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1389,7 +1389,7 @@
/**
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
- * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
+ * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1400,7 +1400,7 @@
/**
* @brief Enable direction change to up interrupt (UPIE).
- * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1411,7 +1411,7 @@
/**
* @brief Disable direction change to up interrupt (UPIE).
- * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1422,7 +1422,7 @@
/**
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
- * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
+ * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
@@ -1433,7 +1433,7 @@
/**
* @brief Enable direction change to down interrupt (DOWNIE).
- * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1444,7 +1444,7 @@
/**
* @brief Disable direction change to down interrupt (DOWNIE).
- * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
@@ -1455,7 +1455,7 @@
/**
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
- * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
+ * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
diff --git a/Inc/stm32g4xx_ll_lpuart.h b/Inc/stm32g4xx_ll_lpuart.h
index 5ffe06b..7abf32f 100644
--- a/Inc/stm32g4xx_ll_lpuart.h
+++ b/Inc/stm32g4xx_ll_lpuart.h
@@ -154,16 +154,16 @@
* @brief Flags defines which can be used with LL_LPUART_WriteReg function
* @{
*/
-#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
-#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */
-#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
-#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
-#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
-#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
-#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
-#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
@@ -172,27 +172,27 @@
* @brief Flags defines which can be used with LL_LPUART_ReadReg function
* @{
*/
-#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
-#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
-#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
-#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
-#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
-#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
-#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
-#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
-#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
-#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
-#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
-#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
-#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
-#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
-#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
-#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
-#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
-#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
-#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
-#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
-#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
+#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
/**
* @}
*/
@@ -201,19 +201,21 @@
* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
* @{
*/
-#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
-#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
-#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
-#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
-#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
-#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
-#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
-#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
-#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
-#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
+#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+ interrupt enable */
+#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
+ not full interrupt enable */
+#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
/**
* @}
*/
@@ -234,10 +236,10 @@
/** @defgroup LPUART_LL_EC_DIRECTION Direction
* @{
*/
-#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
/**
* @}
*/
@@ -245,9 +247,9 @@
/** @defgroup LPUART_LL_EC_PARITY Parity Control
* @{
*/
-#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
-#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
@@ -255,8 +257,8 @@
/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
* @{
*/
-#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
-#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
+#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
/**
* @}
*/
@@ -264,9 +266,9 @@
/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
* @{
*/
-#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
/**
* @}
*/
@@ -274,18 +276,27 @@
/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
-#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
-#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
-#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
-#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
-#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
-#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
-#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
-#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
-#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
-#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
-#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+ USART_PRESC_PRESCALER_1 |\
+ USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -293,8 +304,8 @@
/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
* @{
*/
-#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
*/
@@ -302,8 +313,8 @@
/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
* @{
*/
-#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
/**
* @}
*/
@@ -311,8 +322,8 @@
/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
* @{
*/
-#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
-#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
/**
* @}
*/
@@ -320,8 +331,8 @@
/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
* @{
*/
-#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
-#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
/**
* @}
*/
@@ -329,8 +340,11 @@
/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
* @{
*/
-#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
-#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
+ in positive/direct logic. (1=H, 0=L) */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+ in negative/inverse logic. (1=L, 0=H).
+ The parity bit is also inverted. */
/**
* @}
*/
@@ -338,8 +352,10 @@
/** @defgroup LPUART_LL_EC_BITORDER Bit Order
* @{
*/
-#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
-#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
+ following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+ following the start bit */
/**
* @}
*/
@@ -347,8 +363,8 @@
/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
* @{
*/
-#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
-#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
/**
* @}
*/
@@ -356,10 +372,12 @@
/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
* @{
*/
-#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
+ when there is space in the receive buffer */
+#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
+ when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
/**
* @}
*/
@@ -367,9 +385,9 @@
/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
* @{
*/
-#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
-#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
-#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
/**
* @}
*/
@@ -377,8 +395,8 @@
/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
*/
-#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
-#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
/**
* @}
*/
@@ -386,8 +404,8 @@
/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
-#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
-#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_opamp.h b/Inc/stm32g4xx_ll_opamp.h
index dafdfa2..88bd165 100644
--- a/Inc/stm32g4xx_ll_opamp.h
+++ b/Inc/stm32g4xx_ll_opamp.h
@@ -297,8 +297,11 @@
/** @defgroup OPAMP_LL_EC_POWER_MODE OPAMP PowerMode
* @{
*/
-#define LL_OPAMP_POWERMODE_NORMAL (0x00000000UL) /*!< OPAMP output in normal mode */
+#define LL_OPAMP_POWERMODE_NORMALSPEED (0x00000000UL) /*!< OPAMP output in normal mode */
#define LL_OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN /*!< OPAMP output in highspeed mode */
+
+#define LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALSPEED /*!< OPAMP power mode normal - Old Naming for compatibility */
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_tim.h b/Inc/stm32g4xx_ll_tim.h
index c72956b..66d7b28 100644
--- a/Inc/stm32g4xx_ll_tim.h
+++ b/Inc/stm32g4xx_ll_tim.h
@@ -605,8 +605,8 @@
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
* @{
*/
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
@@ -2102,7 +2102,16 @@
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+ uint32_t counter_mode;
+
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+ if (counter_mode == 0U)
+ {
+ counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+ }
+
+ return counter_mode;
}
/**
@@ -2606,8 +2615,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -2653,8 +2662,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -2694,8 +2703,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -2730,7 +2739,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2764,7 +2773,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@@ -2803,7 +2812,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@@ -2837,7 +2846,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@@ -2862,8 +2871,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2888,8 +2897,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2914,9 +2923,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2940,8 +2949,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2965,8 +2974,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2990,9 +2999,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -3019,8 +3028,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -3046,8 +3055,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -3075,9 +3084,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -3432,8 +3441,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -3460,8 +3469,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -3484,8 +3493,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -3510,8 +3519,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -3535,8 +3544,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -3573,8 +3582,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -3610,8 +3619,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -3639,7 +3648,7 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -3667,7 +3676,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
@@ -4610,7 +4619,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
SET_BIT(*pReg, Source);
}
@@ -4653,7 +4662,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@@ -4689,7 +4698,7 @@
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
- __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
/**
diff --git a/Inc/stm32g4xx_ll_usart.h b/Inc/stm32g4xx_ll_usart.h
index f716e2e..fd0fbd5 100644
--- a/Inc/stm32g4xx_ll_usart.h
+++ b/Inc/stm32g4xx_ll_usart.h
@@ -184,21 +184,21 @@
* @brief Flags defines which can be used with LL_USART_WriteReg function
* @{
*/
-#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
-#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */
-#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
-#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
-#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */
-#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
-#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */
-#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
-#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
-#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
-#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
-#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */
-#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_usb.h b/Inc/stm32g4xx_ll_usb.h
index 2620a8d..f527f66 100644
--- a/Inc/stm32g4xx_ll_usb.h
+++ b/Inc/stm32g4xx_ll_usb.h
@@ -135,10 +135,10 @@
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
-#define EP_MPS_64 0U
-#define EP_MPS_32 1U
-#define EP_MPS_16 2U
-#define EP_MPS_8 3U
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
/**
* @}
*/
@@ -163,10 +163,10 @@
* @}
*/
-#define BTABLE_ADDRESS 0x000U
+#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
-#define EP_ADDR_MSK 0x7U
+#define EP_ADDR_MSK 0x7U
/**
* @}
*/
@@ -187,32 +187,28 @@
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
+
+#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
-void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+#endif
+
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
-void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
-
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes);
+
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
+ uint16_t wPMABufAddr, uint16_t wNBytes);
/**
* @}
diff --git a/README.md b/README.md
index bf1c190..5f90a99 100644
--- a/README.md
+++ b/README.md
@@ -42,6 +42,7 @@
Tag v1.1.0 | Tag v1.1.0 | Tag v5.4.0_cm4 | Tag v1.1.0 (and following, if any, till next new tag)
Tag v1.1.1 | Tag v1.1.1 | Tag v5.4.0_cm4 | Tag v1.2.0 (and following, if any, till next new tag)
Tag v1.2.0 | Tag v1.2.0 | Tag v5.6.0_cm4 | Tag v1.3.0 (and following, if any, till next new tag)
+Tag v1.2.1 | Tag v1.2.1 | Tag v5.6.0_cm4 | Tag v1.4.0 (and following, if any, till next new tag)
Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32g4xx_hal_driver/blob/master/Release_Notes.html).
@@ -51,4 +52,4 @@
If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32g4xx_hal_driver/issues/new).
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
diff --git a/Release_Notes.html b/Release_Notes.html
index 1fd9d50..c701096 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -46,11 +46,205 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.2.0 / 26-June-2020</label>
+<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.2.1 / 27-January-2021</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance Release</h3>
<ul>
+<li><p>General updates to fix known defects and enhancements implementation</p></li>
+<li><strong>HAL</strong></li>
+<li>General updates to fix known defects and enhancements implementation.</li>
+<li>Support for new ARM compiler Keil V6.</li>
+<li>Added new defines for ARM compiler V6:
+<ul>
+<li>__weak</li>
+<li>__packed</li>
+<li>__NOINLINE</li>
+</ul></li>
+<li><strong>LL RCC</strong> update
+<ul>
+<li>Private functions made static.</li>
+</ul></li>
+<li><strong>HAL CRYP</strong> update
+<ul>
+<li>Correction made for the Official NIST CCM test pattern ciphering failing when header length is null.</li>
+<li>GCM/GMAC/CCM data header is now fed using DMA instead of polling.</li>
+<li>Fixed CRYP HAL driver to manage GCM header lengths not multiple of 4 bytes in 8-bit, 16-bit and 32-bit data types.</li>
+<li>Fixed handling of AUD with size not multiple of 4 bytes in CRYP_AESGCM_Process_IT for GCM.</li>
+</ul></li>
+<li><strong>HAL RTC</strong> Update
+<ul>
+<li>New APIs to subtract or add one hour to the calendar in one single operation without going through the initialization procedure (Daylight Saving):
+<ul>
+<li>Add HAL_RTC_DST_Add1Hour()</li>
+<li>HAL_RTC_DST_Sub1Hour()</li>
+<li>HAL_RTC_DST_SetStoreOperation()</li>
+<li>HAL_RTC_DST_ClearStoreOperation()</li>
+</ul></li>
+<li>Fixed executing TimeStamp callback when HAL_RTC_SetTimeStamp is called with “Rising Edge” configuration
+<ul>
+<li>Updated HAL_RTC_SetTimeStamp() API to call __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT before configuring the TimeStamp.</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL TIM</strong> update
+<ul>
+<li>Updated HAL_TIMEx_OnePulseN_Start() and HAL_TIMEx_OnePulseN_Stop() APIs (pooling and IT mode) to take into consideration all OutputChannel parameters.</li>
+<li>Corrected reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.</li>
+<li>Updated LL_TIM_GetCounterMode() API to return the correct counter mode.</li>
+</ul></li>
+<li><strong>HAL/LL LPTIM</strong> update
+<ul>
+<li>Updated HAL_LPTIM_Init() API implementation to configure digital filter for external clock when LPTIM is configured with internal clock source.</li>
+</ul></li>
+<li><strong>HAL/LL HRTIM</strong> update
+<ul>
+<li>IRQ handlers optimized by reducing the multiple read-accesses to ISR and IER registers to one read-access per register.</li>
+<li>LL_HRTIM_FLT_SetSrc() API updated to avoid overwriting the content of FLTINR2 register on successive calls.</li>
+</ul></li>
+<li><strong>HAL EXTI</strong> update
+<ul>
+<li>__EXTI__LINE is now used instead of <strong>LINE</strong> which is a standard C macro.</li>
+</ul></li>
+<li><strong>HAL OPAMP</strong> update
+<ul>
+<li>Corrected OPAMPs outputs for the STM32G4 device table to be coherent with reference manual.</li>
+</ul></li>
+<li><strong>HAL/LL ADC</strong> Update
+<ul>
+<li>Update HAL_ADC_DeInit() to avoid ADC hardware resource deinitialization when other ADC instances sharing the same common ADC instance are disable.</li>
+<li>Update temperature sensor stabilization time management.</li>
+<li>Update timeout mechanism to avoid false timeout detection in case of preemption.</li>
+<li>Align the defined value of internal regulator stabilization time (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US) with product documentation (20us instead of 10us).</li>
+</ul></li>
+<li><strong>HAL DAC</strong> update
+<ul>
+<li>Updated HAL_DAC_Stop_DMA() API to not return HAL_ERROR when DAC is already disabled.</li>
+<li>Updated HAL_DAC_ConfigChannel to return the right timeout error for channel 2.</li>
+<li>Update HAL_DACEx_DualStart when checking if the software trigger enabled:
+<ul>
+<li>DAC_TRIGGER_SOFTWARE instead of DAC_CR_TEN1</li>
+<li>(DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)) instead of DAC_CR_TEN2</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL NOR</strong> Update
+<ul>
+<li>Corrected how p_endaddress is computed and how p_currentaddress is used in the HAL_NOR_ProgramBuffer() API.</li>
+<li>NOR command sets can now be selected by manufacturer code, as specified in JEDEC JEP137B 2004-05, using NOR_HandleTypeDef field CommandSet. the following APIs have been updated:
+<ul>
+<li>HAL_NOR_Init()</li>
+<li>HAL_NOR_Read_ID()</li>
+<li>HAL_NOR_ReturnToReadMode()</li>
+<li>HAL_NOR_Read()</li>
+<li>HAL_NOR_Program()</li>
+<li>HAL_NOR_ReadBuffer()</li>
+<li>HAL_NOR_ProgramBuffer()</li>
+<li>HAL_NOR_Erase_Block()</li>
+<li>HAL_NOR_Erase_Chip()</li>
+<li>HAL_NOR_GetStatus()</li>
+</ul></li>
+<li>Added new command operations:
+<ul>
+<li>NOR_CMD_READ_ARRAY</li>
+<li>NOR_CMD_WORD_PROGRAM</li>
+<li>NOR_CMD_BUFFERED_PROGRAM</li>
+<li>NOR_CMD_CONFIRM</li>
+<li>NOR_CMD_BLOCK_ERASE</li>
+<li>NOR_CMD_BLOCK_UNLOCK</li>
+<li>NOR_CMD_READ_STATUS_REG</li>
+<li>NOR_CMD_CLEAR_STATUS_REG</li>
+</ul></li>
+<li>Updated muliple APIs to treat separetely the different memory types.</li>
+</ul></li>
+<li><strong>LL FMC </strong> Update
+<ul>
+<li>Updated FMC_NORSRAM_Extended_Timing_Init() API to manage the “bus turn around duration” parameter availability.</li>
+<li>Updated FMC_NORSRAM_Init() API to resolve compilation issue with Microsoft Visual Studio 2017.</li>
+</ul></li>
+<li><strong>HAL NAND</strong> update
+<ul>
+<li>Updated HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b() APIs to fix the column address calculation.</li>
+</ul></li>
+<li><strong>HAL/LL SMARTCARD</strong> update
+<ul>
+<li>Fixed invalid initialization of SMARTCARD configuration by removing the FIFO mode configuration.</li>
+<li>Fixed typos in SMARTCARD State definition description.</li>
+<li>Optimized stack usage for multiple APIs.</li>
+</ul></li>
+<li><strong>HAL/LL IRDA</strong> update
+<ul>
+<li>Fixed typos in IRDA State definition description.</li>
+<li>Optimized stack usage for multiple APIs.</li>
+</ul></li>
+<li><strong>HAL/LL UART</strong> update
+<ul>
+<li>Enhanced reception for idle services (ReceptionToIdle):
+<ul>
+<li>Added a new field (HAL_UART_RxTypeTypeDef) to the UART_HandleTypeDef structure to identify the type of ongoing reception.</li>
+<li>Added UART Reception Event Callback registration.</li>
+</ul></li>
+<li>Added reception specific APIs specific to reception for Idle transfer in different modes:
+<ul>
+<li>HAL_UARTEx_ReceiveToIdle(): Receive an amount of data in blocking mode until either the expected number of data is received or an IDLE event occurs.</li>
+<li>HAL_UARTEx_ReceiveToIdle_IT(): Receive an amount of data in interrupt mode until either the expected number of data is received or an IDLE event occurs.</li>
+<li>HAL_UARTEx_ReceiveToIdle_DMA(): Receive an amount of data in DMA mode until either the expected number of data is received or an IDLE event occurs.</li>
+</ul></li>
+<li>Updated HAL_UART_Receive(), HAL_UART_Receive_IT() and HAL_UART_Receive_DMA() APIs to support the new enhancement of ReceptionToIdle.</li>
+<li>Fixed invalid initialization of UART configuration by removing FIFO mode configuration as it is not member of UART_InitTypeDef Structure.</li>
+<li>Fixed typos in UART State definition description.</li>
+<li>Optimized stack usage for multiple APIs.</li>
+</ul></li>
+<li><strong>HAL/LL USART</strong> update
+<ul>
+<li>Removed IS_USART_OVERSAMPLING() as it is unused.</li>
+<li>LL_USART_ClockInit now supports clock phase and clock polarity configuration for SPI_Slave mode.</li>
+<li>Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.</li>
+<li>Optimized stack usage for multiple APIs.</li>
+<li>Removed useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> update
+<ul>
+<li>Support for Fast Mode Plus to be SMBUS rev 3 compliant.
+<ul>
+<li>Added HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+.</li>
+</ul></li>
+</ul></li>
+<li><strong>LL SPI</strong> update
+<ul>
+<li>Updated to set the FRXTH bit for 8bit data for LL_SPI_Init() API.</li>
+</ul></li>
+<li><strong>HAL WWDG</strong> update
+<ul>
+<li>Updated HAL driver description.</li>
+</ul></li>
+<li><strong>HAL/LL USB</strong> update
+<ul>
+<li>Fixed USB ISO IN double buffer mode Transfer.</li>
+<li>Fixed PMA rx count descriptor</li>
+</ul></li>
+<li><p>Added few instructions before reading the RX count register.</p></li>
+</ul>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.50.4</strong> + ST-LINKV2</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.31</strong> + ST-LINKV2</li>
+<li>STM32CubeIDE toolchain <strong>V1.6.0</strong></li>
+</ul>
+<h2 id="supported-devices">Supported Devices</h2>
+<ul>
+<li>STM32G431/41xx</li>
+<li>STM32G471xx</li>
+<li>STM32G473/83xx</li>
+<li>STM32G474/84xx</li>
+<li>STM32G491/A1xx</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.2.0 / 26-June-2020</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-1">Maintenance Release</h3>
+<ul>
<li>Add support for STM32G491xx and STM32G4A1 part numbers</li>
<li><p>General updates to fix known defects and enhancements implementation</p></li>
<li><strong>HAL/LL GPIO</strong> update
@@ -179,13 +373,13 @@
<li>Correct some word spelling issues</li>
</ul></li>
</ul>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.1</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.29</strong></li>
<li>STM32CubeIDE toolchain <strong>V1.4.0</strong></li>
</ul>
-<h2 id="supported-devices">Supported Devices</h2>
+<h2 id="supported-devices-1">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -198,8 +392,8 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.1 / 14-February-2020</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance Release</h3>
+<h2 id="main-changes-2">Main Changes</h2>
+<h3 id="maintenance-release-2">Maintenance Release</h3>
<ul>
<li><p>General updates to fix known defects and enhancements implementation</p></li>
<li><strong>HAL/LL CRYP</strong> update
@@ -382,13 +576,13 @@
<li>API LL_PLL_ConfigSystemClock_HSI() and API LL_PLL_ConfigSystemClock_HSE() updated to set back the AHB prescaler to 1 after it has been temporarily set to 2 to avoid undershoot when configuring PLL at high frequencies.</li>
</ul></li>
</ul>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
<li>STM32CubeIDE toolchain v1.3.0</li>
</ul>
-<h2 id="supported-devices-1">Supported Devices</h2>
+<h2 id="supported-devices-2">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -400,8 +594,8 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance Release</h3>
+<h2 id="main-changes-3">Main Changes</h2>
+<h3 id="maintenance-release-3">Maintenance Release</h3>
<p>Maintenance release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
<h2 id="contents">Contents</h2>
<table>
@@ -484,13 +678,13 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-2">Supported Devices</h2>
+<h2 id="supported-devices-3">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -502,16 +696,16 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 12-April-2019</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
-<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-3">Supported Devices</h2>
+<h2 id="supported-devices-4">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
diff --git a/Src/stm32g4xx_hal.c b/Src/stm32g4xx_hal.c
index 304cef8..b6b85a7 100644
--- a/Src/stm32g4xx_hal.c
+++ b/Src/stm32g4xx_hal.c
@@ -49,11 +49,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32G4xx HAL Driver version number V1.2.0
+ * @brief STM32G4xx HAL Driver version number V1.2.1
*/
#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
-#define __STM32G4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32G4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32g4xx_hal_adc.c b/Src/stm32g4xx_hal_adc.c
index 1c05dae..01e6636 100644
--- a/Src/stm32g4xx_hal_adc.c
+++ b/Src/stm32g4xx_hal_adc.c
@@ -325,8 +325,7 @@
#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
- when no regular conversion is on-going */
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
/* Timeout values for ADC operations (enable settling time, */
/* disable settling time, ...). */
@@ -501,7 +500,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -874,31 +873,28 @@
HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
*/
ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
- }
- /* DeInit the low level hardware.
-
- For example:
- __HAL_RCC_ADC_FORCE_RESET();
- __HAL_RCC_ADC_RELEASE_RESET();
- __HAL_RCC_ADC_CLK_DISABLE();
-
- Keep in mind that all ADCs use the same clock: disabling
- the clock will reset all ADCs.
-
- */
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripherals instances */
+ /* sharing the same common ADC instance: ADC state is forced to */
+ /* a similar state as after device power-on. */
+ /* Note: A possible implementation is to add RCC bus reset of ADC */
+ /* (for example, using macro */
+ /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+ /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- if (hadc->MspDeInitCallback == NULL)
- {
- hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
- }
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
- /* DeInit the low level hardware: RCC clock, NVIC */
- hadc->MspDeInitCallback(hadc);
+ /* DeInit the low level hardware */
+ hadc->MspDeInitCallback(hadc);
#else
- /* DeInit the low level hardware: RCC clock, NVIC */
- HAL_ADC_MspDeInit(hadc);
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
@@ -973,7 +969,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1499,13 +1496,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -1615,13 +1616,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -2404,7 +2409,7 @@
/* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
/* to determine if conversion has been triggered from EOC or EOS, */
/* possibility to use: */
- /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
@@ -2459,44 +2464,46 @@
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
- if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
- ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
{
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
{
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
{
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
- }
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
}
}
}
@@ -2504,8 +2511,8 @@
/* Injected Conversion complete callback */
/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
interruption has been triggered by end of conversion or end of
sequence. */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
@@ -2760,7 +2767,7 @@
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0UL;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
@@ -2849,19 +2856,23 @@
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@@ -2913,7 +2924,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -3388,13 +3399,17 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
@@ -3404,8 +3419,6 @@
return HAL_OK;
}
-
-
/**
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
@@ -3424,7 +3437,8 @@
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Check if conditions to enable the ADC are fulfilled */
- if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3458,13 +3472,17 @@
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
}
@@ -3518,13 +3536,17 @@
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
}
}
diff --git a/Src/stm32g4xx_hal_adc_ex.c b/Src/stm32g4xx_hal_adc_ex.c
index 65d3983..9fdf1aa 100644
--- a/Src/stm32g4xx_hal_adc_ex.c
+++ b/Src/stm32g4xx_hal_adc_ex.c
@@ -62,8 +62,7 @@
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
- ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
- once the ADC is enabled */
+ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: low clock frequency, */
@@ -227,7 +226,8 @@
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ uint32_t CalibrationFactor)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
@@ -523,13 +523,17 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- /* Update ADC state machine to timeout */
- SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+ /* New check to avoid false timeout detection in case of preemption */
+ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
}
}
}
@@ -885,6 +889,10 @@
/* Process locked */
__HAL_LOCK(hadc);
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1000,6 +1008,10 @@
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1027,13 +1039,20 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
@@ -1484,6 +1503,10 @@
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
@@ -1511,13 +1534,20 @@
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* New check to avoid false timeout detection in case of preemption */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
@@ -1957,19 +1987,23 @@
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@@ -1990,7 +2024,9 @@
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
+ LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
+ + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
}
}
@@ -2021,7 +2057,7 @@
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
- wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
@@ -2080,7 +2116,7 @@
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
- ADC_HandleTypeDef tmphadcSlave;
+ ADC_HandleTypeDef tmphadcSlave;
uint32_t tmphadcSlave_conversion_on_going;
/* Check the parameters */
@@ -2095,6 +2131,10 @@
/* Process locked */
__HAL_LOCK(hadc);
+ /* Temporary handle minimum initialization */
+ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
+ ADC_CLEAR_ERRORCODE(&tmphadcSlave);
+
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
if (tmphadcSlave.Instance == NULL)
diff --git a/Src/stm32g4xx_hal_cordic.c b/Src/stm32g4xx_hal_cordic.c
index 5397c4c..e523b6a 100644
--- a/Src/stm32g4xx_hal_cordic.c
+++ b/Src/stm32g4xx_hal_cordic.c
@@ -363,7 +363,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
+HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
{
HAL_StatusTypeDef status = HAL_OK;
@@ -525,8 +526,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions
- * @brief Control functions.
- *
+ * @brief Control functions.
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -602,7 +603,8 @@
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
@@ -659,8 +661,7 @@
return HAL_ERROR;
}
}
- }
- while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
+ } while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
/* Read output data from Read Data register, and increment output buffer pointer */
CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
@@ -696,7 +697,8 @@
* @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
@@ -788,7 +790,8 @@
* @param NbCalc Number of CORDIC calculation to process.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc)
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc)
{
int32_t *tmp_pInBuff = pInBuff;
@@ -879,7 +882,8 @@
* DMA transfer to and from the Peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection)
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+ uint32_t NbCalc, uint32_t DMADirection)
{
uint32_t sizeinbuff;
uint32_t sizeoutbuff;
@@ -1026,8 +1030,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group3 Callback functions
- * @brief Callback functions.
- *
+ * @brief Callback functions.
+ *
@verbatim
==============================================================================
##### Callback functions #####
@@ -1077,8 +1081,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management
- * @brief IRQ handler.
- *
+ * @brief IRQ handler.
+ *
@verbatim
==============================================================================
##### IRQ handler management #####
@@ -1147,8 +1151,8 @@
*/
/** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
diff --git a/Src/stm32g4xx_hal_cryp.c b/Src/stm32g4xx_hal_cryp.c
index b815b70..3db536b 100644
--- a/Src/stm32g4xx_hal_cryp.c
+++ b/Src/stm32g4xx_hal_cryp.c
@@ -6,7 +6,7 @@
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
* + Initialization, de-initialization, set config and get config functions
- * + DES/TDES, AES processing functions
+ * + AES processing functions
* + DMA callback functions
* + CRYP IRQ handler management
* + Peripheral State functions
@@ -32,8 +32,8 @@
(+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+ interrupt on the two DMA channels. The output channel should have higher
+ priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#)Initialize the CRYP according to the specified parameters :
(##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
@@ -44,9 +44,13 @@
(+++) In some specific configurations, the key is written by the application
code out of the HAL scope. In that case, user can still resort to the
HAL APIs as usual but must make sure that pKey pointer is set to NULL.
+ (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
+ algorithms) is in words or bytes.
(##) The Header used only in AES GCM and CCM Algorithm for authentication.
- (##) The HeaderSize The size of header buffer in word.
- (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
+ (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
+ (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
@@ -194,11 +198,11 @@
[..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
+ Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
+ Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
(+) ErrorCallback : callback for error detection.
@@ -208,9 +212,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
@@ -220,13 +224,13 @@
(+) MspDeInitCallback : CRYP MspDeInit.
[..]
- By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
+ By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions :
- examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
+ examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
+ reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
+ if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
[..]
@@ -235,8 +239,8 @@
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
- or @ref HAL_CRYP_Init() function.
+ using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
+ or HAL_CRYP_Init() function.
[..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
@@ -321,6 +325,7 @@
#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
@@ -345,9 +350,7 @@
* @{
*/
-#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
- (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
- }while(0U)
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
/**
* @}
@@ -361,6 +364,7 @@
*/
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
@@ -370,6 +374,7 @@
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
@@ -383,6 +388,7 @@
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
@@ -418,13 +424,13 @@
(+) DeInitialize the CRYP MSP
(+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
Parameters which are configured in This section are :
- (+) Key size
- (+) Data Type : 32,16, 8 or 1bit
- (+) AlgoMode :
- - for CRYP1 peripheral :
+ (++) Key size
+ (++) Data Type : 32,16, 8 or 1bit
+ (++) AlgoMode :
+ (+++) for CRYP1 peripheral :
ECB and CBC in DES/TDES Standard
ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
- - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
+ (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
@endverbatim
@@ -581,15 +587,17 @@
__HAL_LOCK(hcryp);
/* Set CRYP parameters */
- hcryp->Init.DataType = pConf->DataType;
- hcryp->Init.pKey = pConf->pKey;
- hcryp->Init.Algorithm = pConf->Algorithm;
- hcryp->Init.KeySize = pConf->KeySize;
- hcryp->Init.pInitVect = pConf->pInitVect;
- hcryp->Init.Header = pConf->Header;
- hcryp->Init.HeaderSize = pConf->HeaderSize;
- hcryp->Init.B0 = pConf->B0;
- hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
+ hcryp->Init.DataType = pConf->DataType;
+ hcryp->Init.pKey = pConf->pKey;
+ hcryp->Init.Algorithm = pConf->Algorithm;
+ hcryp->Init.KeySize = pConf->KeySize;
+ hcryp->Init.pInitVect = pConf->pInitVect;
+ hcryp->Init.Header = pConf->Header;
+ hcryp->Init.HeaderSize = pConf->HeaderSize;
+ hcryp->Init.B0 = pConf->B0;
+ hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
+ hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
+ hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
/* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
@@ -655,7 +663,9 @@
pConf->Header = hcryp->Init.Header ;
pConf->HeaderSize = hcryp->Init.HeaderSize;
pConf->B0 = hcryp->Init.B0;
- pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
+ pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
+ pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
+ pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
@@ -687,8 +697,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspInit could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_MspInit can be implemented in the user file
*/
}
@@ -703,8 +713,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_MspDeInit could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_MspDeInit can be implemented in the user file
*/
}
@@ -1185,7 +1195,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1285,7 +1295,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1385,7 +1395,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1495,7 +1505,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1604,7 +1614,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1731,7 +1741,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1869,7 +1879,7 @@
/* Clear computation complete flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
{
/* if header phase */
@@ -1882,18 +1892,6 @@
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
- else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
- {
- /* if header phase */
- if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
- {
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
- {
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
- }
- }
else /* AES Algorithm ECB,CBC or CTR*/
{
CRYP_AES_IT(hcryp);
@@ -1935,8 +1933,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_InCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_InCpltCallback can be implemented in the user file
*/
}
@@ -1951,8 +1949,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_OutCpltCallback can be implemented in the user file
*/
}
@@ -1967,8 +1965,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_ErrorCallback could be implemented in the user file
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CRYP_ErrorCallback can be implemented in the user file
*/
}
/**
@@ -2502,18 +2500,105 @@
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
{
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
- /* Call input data transfer complete callback */
+ if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
+ {
+ /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if ((headersize_in_bytes % 16U) != 0U)
+ {
+ /* Write last words that couldn't be fed by DMA */
+ hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+
+ /* Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+ } /* if ((headersize_in_bytes % 16U) != 0U) */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
+ }
+ else
+ {
+ uint32_t algo;
+ /* ECB, CBC or CTR end of input data feeding
+ or
+ end of GCM/CCM payload data feeding through DMA */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ /* Don't call input data transfer complete callback only if
+ it remains some input data to write to the peripheral.
+ This case can only occur for GCM and CCM with a payload length
+ not a multiple of 16 bytes */
+ if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \
+ (((hcryp->Size) % 16U) != 0U)))
+ {
+ /* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */
}
/**
@@ -2526,7 +2611,7 @@
uint32_t count;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t mode;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -2577,46 +2662,31 @@
hcryp->Instance->DINR = 0x0U;
count++;
}
+ /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
/*Read the output block from the output FIFO */
for (count = 0U; count < 4U; count++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
+ temp[count] = hcryp->Instance->DOUTR;
+ }
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ count = 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
hcryp->CrypOutCount++;
+ count++;
}
}
@@ -2675,7 +2745,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr address of the input buffer
- * @param Size size of the input buffer, must be a multiple of 16.
+ * @param Size size of the input and output buffers in words, must be a multiple of 4
* @param outputaddr address of the output buffer
* @retval None
*/
@@ -2734,6 +2804,43 @@
}
/**
+ * @brief Set the DMA configuration and start the header DMA transfer
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr address of the input buffer
+ * @param Size size of the input buffer in words, must be a multiple of 4
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Mark that header is fed to the peripheral in DMA mode */
+ hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
+ /* Enable the DMA input stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ /* Call error callback */
+ }
+
+ /* Enable IN DMA requests */
+ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ return HAL_OK;
+}
+
+/**
* @brief Process Data: Write Input data in polling mode and used in AES functions.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
@@ -3162,6 +3269,12 @@
uint32_t lastwordsize;
uint32_t npblb;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@@ -3171,6 +3284,17 @@
}
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ /* Manage header size given in bytes to handle cases where
+ header size is not a multiple of 4 bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
@@ -3284,7 +3408,7 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3335,42 +3459,58 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- else if ((hcryp->Init.HeaderSize) < 4U)
+ /* Enter header data */
+ /* Cher first whether header length is small enough to enter the full header in one shot */
+ else if (headersize_in_bytes <= 16U)
{
- for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ /* Write header data, padded with zeros if need be */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++ ;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Call Input transfer complete callback */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered Input complete callback*/
- hcryp->InCpltCallback(hcryp);
-#else
- /*Call legacy weak Input complete callback*/
- HAL_CRYP_InCpltCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
{
- /* Write the input block in the IN FIFO */
+ /* Write the first input header block in the Input FIFO,
+ the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -3415,7 +3555,7 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if (hcryp->CrypInCount == (hcryp->Size / 4U))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3466,6 +3606,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -3482,12 +3630,7 @@
*/
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -3566,122 +3709,16 @@
return HAL_ERROR;
}
- /************************ Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
} /* if (DoKeyIVConfig == 1U) */
- if (hcryp->Size == 0U)
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- else if (hcryp->Size >= 16U)
- {
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else /* length of input data is < 16 */
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
-
- /* Set Npblb in case of AES GCM payload encryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
-
- /* Enable CRYP to start the final phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
- {
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -4075,6 +4112,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */
@@ -4180,6 +4225,14 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
@@ -4196,12 +4249,7 @@
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -4282,119 +4330,16 @@
return HAL_ERROR;
}
- /******************** Payload phase *****************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
} /* if (DoKeyIVConfig == 1U) */
- if (hcryp->Size == 0U)
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- else if (hcryp->Size >= 16U)
- {
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
- }
- else /* length of input data is < 16 */
- {
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
-
- /* Set Npblb in case of AES CCM payload decryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
- {
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
/* Return function status */
return HAL_OK;
}
@@ -4493,9 +4438,9 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
- if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
- /* Call output transfer complete callback */
+ /* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
@@ -4541,11 +4486,152 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
/**
+ * @brief Sets the payload phase in DMA mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @retval state
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
+{
+ uint16_t wordsize = hcryp->Size / 4U ;
+ uint32_t index;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
+ uint32_t reg;
+
+ /************************ Payload phase ************************************/
+ if (hcryp->Size == 0U)
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ /*DMA transfer must not include the last block in case of Size is not %16 */
+ wordsize = wordsize - (wordsize % 4U);
+
+ /*DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /* length of input data is < 16 */
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)hcryp->Size;
+
+ /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
+ reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE);
+ if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\
+ (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /*Read the output block from the output FIFO */
+ for (index = 0U; index < 4U; index++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+ hcryp->CrypOutCount++;
+ }
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
* @brief Sets the header phase in polling mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
@@ -4557,7 +4643,9 @@
uint32_t loopcounter;
uint32_t size_in_bytes;
uint32_t tmp;
- uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
@@ -4659,9 +4747,9 @@
}
else
{
- /* Enter last bytes, padded with zeroes */
+ /* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- tmp &= mask[size_in_bytes % 4U];
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
@@ -4691,17 +4779,14 @@
}
else
{
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
- /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+ /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
}
/* Return function status */
return HAL_OK;
@@ -4715,143 +4800,112 @@
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
- if ((hcryp->Init.HeaderSize != 0U))
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* If header size is at least equal to 16 bytes, feed the header through DMA.
+ If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
+ last bytes feeding and padding will be done in CRYP_DMAInCplt() */
+ if (headersize_in_bytes >= 16U)
+ {
+ /* Initiate header DMA transfer */
+ if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
{
- /* HeaderSize %4, no padding */
- for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
- {
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- }
- else
- {
- /*Write header block in the IN FIFO without last block */
- for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
- {
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- }
- while (loopcounter < 4U)
- {
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
- }
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ return HAL_ERROR;
}
}
else
{
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ if (headersize_in_bytes != 0U)
+ {
+ /* Header length is larger than 0 and strictly less than 16 bytes */
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ } /* if (headersize_in_bytes != 0U) */
+
+ /* Move to payload phase if header length is null or
+ if the header length was less than 16 and header written by software instead of DMA */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ } /* if (headersize_in_bytes >= 16U) */
+
/* Return function status */
return HAL_OK;
}
@@ -4868,9 +4922,25 @@
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
/***************************** Header phase *********************************/
- if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ /* Test whether or not the header phase is over.
+ If the test below is true, move to payload phase */
+ if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -4953,11 +5023,19 @@
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
+ else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
{
-
+ /* Can enter full 4 header words */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/* If suspension flag has been raised, suspend processing
only if not already at the end of the header */
@@ -4992,19 +5070,40 @@
hcryp->CrypHeaderCount++;
}
}
- else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
+ else /* Write last header block (4 words), padded with zeros if needed */
{
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
}
}
@@ -5014,6 +5113,7 @@
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Timeout Timeout duration.
+ * @note This function can only be used in thread mode.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
@@ -5037,6 +5137,47 @@
return HAL_OK;
}
+/**
+ * @brief Wait for Computation Complete Flag (CCF) to raise then clear it.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @note This function can be used in thread or handler mode.
+ * @retval HAL status
+ */
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t count = Timeout;
+
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+}
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
@@ -5341,9 +5482,9 @@
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
- if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
+ if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
- /* Call output transfer complete callback */
+ /* Call input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
diff --git a/Src/stm32g4xx_hal_dac.c b/Src/stm32g4xx_hal_dac.c
index 1d95fd7..94b1d4b 100644
--- a/Src/stm32g4xx_hal_dac.c
+++ b/Src/stm32g4xx_hal_dac.c
@@ -177,7 +177,7 @@
DAC_OUTx = VREF+ * DOR / 4095
(+) with DOR is the Data Output Register
[..]
- VEF+ is the input voltage reference (refer to the device datasheet)
+ VREF+ is the input voltage reference (refer to the device datasheet)
[..]
e.g. To set DAC_OUT1 to 0.7V, use
(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
@@ -327,7 +327,7 @@
[..]
(@) You can refer to the DAC HAL driver header file for more useful macros
- @endverbatim
+@endverbatim
******************************************************************************
* @attention
*
@@ -594,6 +594,7 @@
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
}
}
+
else
{
/* Check if software trigger enabled */
@@ -604,6 +605,7 @@
}
}
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -655,7 +657,7 @@
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
- * @param pData The destination peripheral Buffer address.
+ * @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
@@ -667,7 +669,7 @@
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
- HAL_StatusTypeDef status;
+ HAL_StatusTypeDef status = HAL_ERROR;
uint32_t tmpreg = 0U;
/* Check the parameters */
@@ -713,6 +715,7 @@
break;
}
}
+
else
{
/* Set the DMA transfer complete callback for channel2 */
@@ -747,6 +750,7 @@
}
}
+
/* Enable the DMA channel */
if (Channel == DAC_CHANNEL_1)
{
@@ -756,6 +760,7 @@
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
+
else
{
/* Enable the DAC DMA underrun interrupt */
@@ -765,6 +770,7 @@
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
+
/* Process Unlocked */
__HAL_UNLOCK(hdac);
@@ -799,8 +805,6 @@
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
- HAL_StatusTypeDef status;
-
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
@@ -818,34 +822,27 @@
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ (void)HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
+
else /* Channel2 is used for */
{
/* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ (void)HAL_DMA_Abort(hdac->DMA_Handle2);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
- /* Check if DMA Channel effectively disabled */
- if (status != HAL_OK)
- {
- /* Update DAC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -866,7 +863,7 @@
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to chanel1 DMA underrun error */
+ /* Set DAC error code to channel1 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
/* Clear the underrun flag */
@@ -884,6 +881,7 @@
}
}
+
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
{
/* Check underrun flag of DAC channel 2 */
@@ -909,6 +907,7 @@
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
+
}
/**
@@ -932,7 +931,7 @@
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
- __IO uint32_t tmp = 0;
+ __IO uint32_t tmp = 0UL;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
@@ -948,11 +947,13 @@
{
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
+
else
{
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
+
/* Set the DAC channel selected data holding register */
*(__IO uint32_t *) tmp = Data;
@@ -1058,18 +1059,23 @@
*/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ uint32_t tmp = 0U;
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
- /* Returns the DAC channel data output register value */
if (Channel == DAC_CHANNEL_1)
{
- return hdac->Instance->DOR1;
+ tmp = hdac->Instance->DOR1;
}
+
else
{
- return hdac->Instance->DOR2;
+ tmp = hdac->Instance->DOR2;
}
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
}
/**
@@ -1095,7 +1101,7 @@
{
uint32_t tmpreg1;
uint32_t tmpreg2;
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
uint32_t hclkfreq;
uint32_t connectOnChip;
@@ -1127,15 +1133,14 @@
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
+ /* Sample and hold configuration */
if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
- /* Sample on old configuration */
{
- /* SampleTime */
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
if (Channel == DAC_CHANNEL_1)
{
- /* Get timeout */
- tickstart = HAL_GetTick();
-
/* SHSR1 can be written when BWST1 is cleared */
while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
@@ -1154,10 +1159,10 @@
HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
+
else /* Channel 2 */
{
/* SHSR2 can be written when BWST2 is cleared */
-
while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Check for the Timeout */
@@ -1176,10 +1181,13 @@
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
+
/* HoldTime */
- MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
/* RefreshTime */
- MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
}
if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
@@ -1204,15 +1212,15 @@
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
- if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_EXTERNAL) == DAC_CHIPCONNECT_EXTERNAL)
+ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
{
connectOnChip = 0x00000000UL;
}
- else if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_INTERNAL) == DAC_CHIPCONNECT_INTERNAL)
+ else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
{
connectOnChip = DAC_MCR_MODE1_0;
}
- else /* (sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_BOTH) == DAC_CHIPCONNECT_BOTH */
+ else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
{
if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
{
@@ -1275,7 +1283,7 @@
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
- hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
+ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
/* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */
tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos;
@@ -1404,6 +1412,7 @@
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = pCallback;
break;
+
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = pCallback;
break;
@@ -1416,6 +1425,7 @@
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = pCallback;
break;
+
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
@@ -1503,6 +1513,7 @@
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
break;
+
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
break;
@@ -1515,6 +1526,7 @@
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
break;
+
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
@@ -1526,10 +1538,12 @@
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
hdac->MspInitCallback = HAL_DAC_MspInit;
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
diff --git a/Src/stm32g4xx_hal_dac_ex.c b/Src/stm32g4xx_hal_dac_ex.c
index 550f59c..cf40f17 100644
--- a/Src/stm32g4xx_hal_dac_ex.c
+++ b/Src/stm32g4xx_hal_dac_ex.c
@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32g4xx_hal_dac_ex.c
* @author MCD Application Team
- * @brief DAC HAL module driver.
+ * @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
*
@@ -12,8 +12,10 @@
##### How to use this driver #####
==============================================================================
[..]
+
*** Dual mode IO operation ***
==============================
+ [..]
(+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
for dual mode operation.
If software trigger is selected, using HAL_DACEx_DualStart() will start
@@ -35,6 +37,7 @@
*** Signal generation operation ***
===================================
+ [..]
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
@@ -110,6 +113,7 @@
* @{
*/
+
/**
* @brief Enables DAC and starts conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -136,11 +140,11 @@
HAL_Delay(1);
/* Check if software trigger enabled */
- if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
+ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
}
- if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
+ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
}
@@ -202,7 +206,7 @@
uint32_t Alignment)
{
HAL_StatusTypeDef status;
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg = 0UL;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
@@ -363,6 +367,7 @@
return status;
}
+
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -403,7 +408,8 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the triangle wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -455,7 +461,8 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the noise wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+ (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -563,7 +570,7 @@
/* Process locked */
__HAL_LOCK(hdac);
- if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0U /* SW TRIGGER */)
+ if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0UL /* SW TRIGGER */)
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
@@ -619,7 +626,7 @@
/* Process locked */
__HAL_LOCK(hdac);
- if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0U /* SW TRIGGER */)
+ if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0UL /* SW TRIGGER */)
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
@@ -650,6 +657,7 @@
return status;
}
+
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -759,6 +767,7 @@
*/
}
+
/**
* @brief Run the self calibration of one DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -775,7 +784,6 @@
* @retval HAL status
* @note Calibration runs about 7 ms.
*/
-
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -828,7 +836,7 @@
tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
}
- *(__IO uint32_t *) tmp = 0x0800U;
+ *(__IO uint32_t *) tmp = 0x0800UL;
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
@@ -836,9 +844,9 @@
/* Init trimming counter */
/* Medium value */
- trimmingvalue = 16U;
- delta = 8U;
- while (delta != 0U)
+ trimmingvalue = 16UL;
+ delta = 8UL;
+ while (delta != 0UL)
{
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
@@ -857,7 +865,7 @@
/* DAC_SR_CAL_FLAGx is LOW try lower trimming */
trimmingvalue += delta;
}
- delta >>= 1U;
+ delta >>= 1UL;
}
/* Still need to check if right calibration is current value or one step below */
@@ -871,7 +879,7 @@
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
- /* OPAMP_CSR_OUTCAL is actually one value more */
+ /* Trimming is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
@@ -909,7 +917,6 @@
* @param NewTrimmingValue DAC new trimming value
* @retval HAL status
*/
-
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue)
{
@@ -955,13 +962,12 @@
* @retval Trimming value : range: 0->31
*
*/
-
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
- /* Retrieve trimming */
+ /* Retrieve trimming */
return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
}
@@ -983,6 +989,7 @@
* @{
*/
+
/**
* @brief Return the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -991,20 +998,20 @@
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
{
- uint32_t tmp = 0U;
+ uint32_t tmp = 0UL;
tmp |= hdac->Instance->DOR1;
- tmp |= hdac->Instance->DOR2 << 16U;
+ tmp |= hdac->Instance->DOR2 << 16UL;
/* Returns the DAC channel data output register value */
return tmp;
}
+
/**
* @}
*/
-
/**
* @}
*/
@@ -1012,9 +1019,10 @@
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
- * @{
+ * @{
*/
+
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
@@ -1073,6 +1081,7 @@
hdac->State = HAL_DAC_STATE_READY;
}
+
/**
* @}
*/
diff --git a/Src/stm32g4xx_hal_fmac.c b/Src/stm32g4xx_hal_fmac.c
index 988428a..f55d771 100644
--- a/Src/stm32g4xx_hal_fmac.c
+++ b/Src/stm32g4xx_hal_fmac.c
@@ -213,6 +213,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal.h"
+#if defined(FMAC)
#ifdef HAL_FMAC_MODULE_ENABLED
/** @addtogroup STM32G4xx_HAL_Driver
@@ -430,13 +431,13 @@
FMAC_ResetDataPointers(hfmac);
/* Reset FMAC unit (internal pointers) */
- if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+ if (FMAC_Reset(hfmac) == HAL_ERROR)
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- status = HAL_TIMEOUT;
+ status = HAL_ERROR;
}
else
{
@@ -688,39 +689,42 @@
switch (CallbackID)
{
case HAL_FMAC_ERROR_CB_ID :
- hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */
+ hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_FMAC_HALF_GET_DATA_CB_ID :
- hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */
+ hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */
break;
case HAL_FMAC_GET_DATA_CB_ID :
- hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */
+ hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */
break;
case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
- hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak HalfOutputDataReadyCallback */
+ hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak
+ HalfOutputDataReadyCallback */
break;
case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
- hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak OutputDataReadyCallback */
+ hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak
+ OutputDataReadyCallback */
break;
case HAL_FMAC_FILTER_CONFIG_CB_ID :
- hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak FilterConfigCallback */
+ hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak
+ FilterConfigCallback */
break;
case HAL_FMAC_FILTER_PRELOAD_CB_ID :
- hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallback */
+ hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallba */
break;
case HAL_FMAC_MSPINIT_CB_ID :
- hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */
+ hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_FMAC_MSPDEINIT_CB_ID :
- hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -955,7 +959,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_ERROR;
}
return status;
@@ -999,7 +1003,7 @@
/* Check whether the previous input vector has been handled */
if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize)))
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
/* Check that FMAC was initialized and that no writing is already ongoing */
@@ -1010,7 +1014,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_ERROR;
}
return status;
@@ -1055,7 +1059,7 @@
/* Check whether the previous output vector has been handled */
if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize)))
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
/* Check that FMAC was initialized and that not reading is already ongoing */
@@ -1066,7 +1070,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_ERROR;
}
return status;
@@ -1185,7 +1189,7 @@
if ((HAL_GetTick() - tickstart) >= Timeout)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
- status = HAL_TIMEOUT;
+ status = HAL_ERROR;
}
else
{
@@ -1194,7 +1198,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_ERROR;
}
return status;
@@ -1233,12 +1237,12 @@
}
/* Reset FMAC unit (internal pointers) */
- if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+ if (FMAC_Reset(hfmac) == HAL_ERROR)
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- status = HAL_TIMEOUT;
+ status = HAL_ERROR;
}
else
{
@@ -1253,7 +1257,7 @@
}
else
{
- status = HAL_BUSY;
+ status = HAL_ERROR;
}
return status;
@@ -1589,7 +1593,7 @@
if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
@@ -1674,7 +1678,7 @@
/* Check handle state is ready */
if (hfmac->State != HAL_FMAC_STATE_READY)
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
/* Change the FMAC state */
@@ -1692,7 +1696,8 @@
MODIFY_REG(hfmac->Instance->X1BUFCFG, \
(FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
(((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
- ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE)));
+ ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \
+ FMAC_X1BUFCFG_X1_BUF_SIZE)));
}
/* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
@@ -1712,7 +1717,8 @@
MODIFY_REG(hfmac->Instance->X2BUFCFG, \
(FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
(((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
- ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE)));
+ ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\
+ FMAC_X2BUFCFG_X2_BUF_SIZE)));
}
/* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
@@ -1758,7 +1764,8 @@
x2size = FMAC_GET_X2_SIZE(hfmac);
#endif /* USE_FULL_ASSERT */
assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \
- ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
+ ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
/* Build the PARAM value that will be used when starting the filter */
hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \
@@ -1805,7 +1812,7 @@
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Change the FMAC state */
@@ -1888,7 +1895,7 @@
/* Check handle state is ready */
if (hfmac->State != HAL_FMAC_STATE_READY)
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
/* Change the FMAC state */
@@ -1914,7 +1921,7 @@
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
else
@@ -1950,7 +1957,7 @@
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
else
@@ -2035,7 +2042,7 @@
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -2532,5 +2539,6 @@
*/
#endif /* HAL_FMAC_MODULE_ENABLED */
+#endif /* FMAC */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32g4xx_hal_hrtim.c b/Src/stm32g4xx_hal_hrtim.c
index b9a8fda..19a0305 100644
--- a/Src/stm32g4xx_hal_hrtim.c
+++ b/Src/stm32g4xx_hal_hrtim.c
@@ -10319,10 +10319,13 @@
*/
static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
{
+ uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
+ uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
+
/* Fault 1 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
@@ -10336,9 +10339,9 @@
}
/* Fault 2 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
@@ -10352,9 +10355,9 @@
}
/* Fault 3 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
@@ -10368,9 +10371,9 @@
}
/* Fault 4 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
@@ -10384,9 +10387,9 @@
}
/* Fault 5 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
@@ -10400,9 +10403,9 @@
}
/* Fault 6 event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT6) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT6) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6);
@@ -10416,9 +10419,9 @@
}
/* System fault event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
@@ -10439,10 +10442,15 @@
*/
static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
{
+ uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
+ uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
+ uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
+ uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
+
/* DLL calibration ready event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
@@ -10462,9 +10470,9 @@
}
/* Burst mode period event */
- if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != (uint32_t)RESET)
+ if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
+ if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
{
__HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
@@ -10478,9 +10486,9 @@
}
/* Master timer compare 1 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
@@ -10494,9 +10502,9 @@
}
/* Master timer compare 2 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
@@ -10510,9 +10518,9 @@
}
/* Master timer compare 3 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
@@ -10526,9 +10534,9 @@
}
/* Master timer compare 4 event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
@@ -10542,9 +10550,9 @@
}
/* Master timer repetition event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
@@ -10558,9 +10566,9 @@
}
/* Synchronization input event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
@@ -10574,9 +10582,9 @@
}
/* Master timer registers update event */
- if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
+ if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
+ if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
{
__HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
@@ -10606,10 +10614,13 @@
static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx)
{
+ uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
+ uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
+
/* Timer compare 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
@@ -10623,9 +10634,9 @@
}
/* Timer compare 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
@@ -10639,9 +10650,9 @@
}
/* Timer compare 3 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
@@ -10655,9 +10666,9 @@
}
/* Timer compare 4 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
@@ -10671,9 +10682,9 @@
}
/* Timer repetition event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
@@ -10687,9 +10698,9 @@
}
/* Timer registers update event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
@@ -10703,9 +10714,9 @@
}
/* Timer capture 1 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
@@ -10719,9 +10730,9 @@
}
/* Timer capture 2 event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
@@ -10735,9 +10746,9 @@
}
/* Timer output 1 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
@@ -10751,9 +10762,9 @@
}
/* Timer output 1 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
@@ -10767,9 +10778,9 @@
}
/* Timer output 2 set event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
@@ -10783,9 +10794,9 @@
}
/* Timer output 2 reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
@@ -10799,9 +10810,9 @@
}
/* Timer reset event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
@@ -10815,9 +10826,9 @@
}
/* Delayed protection event */
- if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
+ if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
{
- if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
+ if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
{
__HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
diff --git a/Src/stm32g4xx_hal_i2c.c b/Src/stm32g4xx_hal_i2c.c
index b5a79be..199e1b9 100644
--- a/Src/stm32g4xx_hal_i2c.c
+++ b/Src/stm32g4xx_hal_i2c.c
@@ -4858,7 +4858,7 @@
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all data have already been sent */
+ /* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
diff --git a/Src/stm32g4xx_hal_i2s.c b/Src/stm32g4xx_hal_i2s.c
index bacad7d..769c4fb 100644
--- a/Src/stm32g4xx_hal_i2s.c
+++ b/Src/stm32g4xx_hal_i2s.c
@@ -743,7 +743,7 @@
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
@@ -860,7 +860,7 @@
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
@@ -961,7 +961,7 @@
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -1025,7 +1025,7 @@
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
@@ -1091,7 +1091,7 @@
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -1182,7 +1182,7 @@
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
diff --git a/Src/stm32g4xx_hal_irda.c b/Src/stm32g4xx_hal_irda.c
index 953cd02..a739c4e 100644
--- a/Src/stm32g4xx_hal_irda.c
+++ b/Src/stm32g4xx_hal_irda.c
@@ -2244,7 +2244,7 @@
uint32_t tmpreg;
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the communication parameters */
diff --git a/Src/stm32g4xx_hal_iwdg.c b/Src/stm32g4xx_hal_iwdg.c
index 38fe72d..83cd68b 100644
--- a/Src/stm32g4xx_hal_iwdg.c
+++ b/Src/stm32g4xx_hal_iwdg.c
@@ -16,33 +16,43 @@
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
- (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
- if the main clock fails.
+ (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+ active even if the main clock fails.
- (+) Once the IWDG is started, the LSI is forced ON and both can not be
+ (+) Once the IWDG is started, the LSI is forced ON and both cannot be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
- the IWDG_RLR value is reloaded in the counter and the watchdog reset is
- prevented.
+ the IWDG_RLR value is reloaded into the counter and the watchdog reset
+ is prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ (+) Debug mode: When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32G4xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM16 CH1 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
+ The IWDG timeout may vary due to LSI clock frequency dispersion.
+ STM32G4xx devices provide the capability to measure the LSI clock
+ frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+ The measured value can be used to have an IWDG timeout with an
+ acceptable accuracy.
+
+ [..] Default timeout value (necessary for IWDG_SR status register update):
+ Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+ This frequency being subject to variations as mentioned above, the
+ default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+ below) may become too short or too long.
+ In such cases, this default timeout value can be tuned by redefining
+ the constant LSI_VALUE at user-application level (based, for instance,
+ on the measured LSI clock frequency as explained above).
##### How to use this driver #####
==============================================================================
@@ -55,13 +65,13 @@
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
+ (++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@@ -108,10 +118,15 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to LSI variation, we need to wait at
- least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 48u
+/* Status register needs up to 5 LSI clock periods divided by the clock
+ prescaler to be updated. The number of LSI clock periods is upper-rounded to
+ 6 for the timeout value calculation.
+ The timeout value is also calculated using the highest prescaler (256) and
+ the LSI_VALUE constant. The value of this constant can be changed by the user
+ to take into account possible LSI clock period variations.
+ The timeout value is multiplied by 1000 to be converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
*/
@@ -182,11 +197,14 @@
tickstart = HAL_GetTick();
/* Wait for register to be updated */
- while (hiwdg->Instance->SR != 0x00u)
+ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
- return HAL_TIMEOUT;
+ if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
@@ -209,6 +227,7 @@
return HAL_OK;
}
+
/**
* @}
*/
@@ -228,7 +247,6 @@
* @{
*/
-
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
@@ -244,6 +262,7 @@
return HAL_OK;
}
+
/**
* @}
*/
diff --git a/Src/stm32g4xx_hal_lptim.c b/Src/stm32g4xx_hal_lptim.c
index e4f887f..e70e5f9 100644
--- a/Src/stm32g4xx_hal_lptim.c
+++ b/Src/stm32g4xx_hal_lptim.c
@@ -197,8 +197,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -235,19 +235,17 @@
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
- }
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
- {
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@@ -281,21 +279,18 @@
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
- }
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
- {
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
}
- /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
/* Set initialization parameters */
@@ -314,19 +309,21 @@
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- /* Configure the active edge or edges used by the counter only if LPTIM is
- * clocked by an external clock source
- */
- if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ /* Configure LPTIM external clock polarity and digital filter */
+ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ hlptim->Init.UltraLowPowerClock.SampleTime);
}
+ /* Configure LPTIM external trigger */
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge |
+ hlptim->Init.Trigger.SampleTime);
}
/* Write to LPTIMx CFGR */
@@ -432,8 +429,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
- * @brief Start-Stop operation functions.
- *
+ * @brief Start-Stop operation functions.
+ *
@verbatim
==============================================================================
##### LPTIM Start Stop operation functions #####
@@ -1558,7 +1555,8 @@
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1639,7 +1637,8 @@
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
+ && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1730,8 +1729,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
- * @brief Read operation functions.
- *
+ * @brief Read operation functions.
+ *
@verbatim
==============================================================================
##### LPTIM Read operation functions #####
@@ -1788,8 +1787,8 @@
*/
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
- * @brief LPTIM IRQ handler.
- *
+ * @brief LPTIM IRQ handler.
+ *
@verbatim
==============================================================================
##### LPTIM IRQ handler and callbacks #####
@@ -2256,8 +2255,8 @@
*/
/** @defgroup LPTIM_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
@@ -2332,8 +2331,7 @@
{
result = HAL_TIMEOUT;
}
- }
- while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+ } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
}
diff --git a/Src/stm32g4xx_hal_nand.c b/Src/stm32g4xx_hal_nand.c
index 6cf1e21..f610be3 100644
--- a/Src/stm32g4xx_hal_nand.c
+++ b/Src/stm32g4xx_hal_nand.c
@@ -156,7 +156,8 @@
* @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
{
/* Check the NAND handle state */
if (hnand == NULL)
@@ -170,7 +171,7 @@
hnand->Lock = HAL_UNLOCKED;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- if(hnand->MspInitCallback == NULL)
+ if (hnand->MspInitCallback == NULL)
{
hnand->MspInitCallback = HAL_NAND_MspInit;
}
@@ -181,7 +182,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
}
/* Initialize NAND control Interface */
@@ -195,7 +196,7 @@
/* Enable the NAND device */
__FMC_NAND_ENABLE(hnand->Instance);
-
+
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -211,7 +212,7 @@
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
{
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- if(hnand->MspDeInitCallback == NULL)
+ if (hnand->MspDeInitCallback == NULL)
{
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
}
@@ -221,7 +222,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspDeInit(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Configure the NAND registers with their reset values */
(void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
@@ -273,7 +274,7 @@
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
-*/
+ */
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
{
/* Check NAND interrupt Rising edge flag */
@@ -284,7 +285,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Rising edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
@@ -298,7 +299,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Level pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
@@ -312,7 +313,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Falling edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
@@ -326,7 +327,7 @@
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
-#endif
+#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt FIFO empty pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
@@ -380,7 +381,7 @@
{
__IO uint32_t data = 0;
__IO uint32_t data1 = 0;
- uint32_t deviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -396,18 +397,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Read ID command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
__DSB();
/* Read the electronic signature from NAND flash */
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
- data = *(__IO uint32_t *)deviceAddress;
+ data = *(__IO uint32_t *)deviceaddress;
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
@@ -417,8 +418,8 @@
}
else
{
- data = *(__IO uint32_t *)deviceAddress;
- data1 = *((__IO uint32_t *)deviceAddress + 4);
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4);
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
@@ -449,7 +450,7 @@
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
- uint32_t deviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -465,10 +466,10 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send NAND reset command */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -505,7 +506,6 @@
return HAL_OK;
}
-
/**
* @brief Read Page(s) from NAND memory block (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
@@ -515,12 +515,16 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -536,16 +540,16 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -553,22 +557,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -576,31 +580,31 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
@@ -625,25 +629,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *buff = *(uint8_t *)deviceAddress;
+ *buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -658,7 +662,6 @@
}
return HAL_OK;
-
}
/**
@@ -670,12 +673,16 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpagesread = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToRead;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -691,16 +698,16 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -708,22 +715,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -731,31 +738,31 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -779,25 +786,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *buff = *(uint16_t *)deviceAddress;
+ *buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
- numPagesRead++;
+ numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -823,12 +830,16 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -844,18 +855,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -863,22 +874,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -886,26 +897,26 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -913,12 +924,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *(__IO uint8_t *)deviceAddress = *buff;
+ *(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -940,13 +951,13 @@
}
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -972,12 +983,16 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numpageswritten = 0U;
+ uint32_t nandaddress;
+ uint32_t nbpages = NumPageToWrite;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -993,18 +1008,18 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
- while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
@@ -1012,22 +1027,22 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1035,26 +1050,26 @@
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1062,12 +1077,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
- *(__IO uint16_t *)deviceAddress = *buff;
+ *(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1089,13 +1104,13 @@
}
/* Increment written pages number */
- numPagesWritten++;
+ numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1120,13 +1135,18 @@
* @param pBuffer pointer to source buffer to write
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1142,78 +1162,78 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) read loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -1237,25 +1257,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *buff = *(uint8_t *)deviceAddress;
+ *buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1280,13 +1300,18 @@
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numsparearearead = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaToRead;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1302,78 +1327,78 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) read loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
@@ -1397,25 +1422,25 @@
}
/* Go back to read mode */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *buff = *(uint16_t *)deviceAddress;
+ *buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
- numSpareAreaRead++;
+ numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1441,12 +1466,17 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
- uint8_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1462,77 +1492,77 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Page address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = COLUMN_ADDRESS(hnand);
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) write loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1540,12 +1570,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *(__IO uint8_t *)deviceAddress = *buff;
+ *(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1567,13 +1597,13 @@
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1599,12 +1629,17 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
- uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
- uint16_t * buff = pBuffer;
+ uint32_t deviceaddress;
+ uint32_t numspareareawritten = 0U;
+ uint32_t nandaddress;
+ uint32_t columnaddress;
+ uint32_t nbspare = NumSpareAreaTowrite;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1620,77 +1655,77 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- deviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
- nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
- columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) write loop */
- while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
- *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
@@ -1698,12 +1733,12 @@
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
- *(__IO uint16_t *)deviceAddress = *buff;
+ *(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
- *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
@@ -1725,13 +1760,13 @@
}
/* Increment written spare areas number */
- numSpareAreaWritten++;
+ numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
- nandAddress = (uint32_t)(nandAddress + 1U);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -1757,7 +1792,7 @@
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
- uint32_t DeviceAddress;
+ uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1773,19 +1808,19 @@
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
- DeviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Erase block command sequence */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
__DSB();
/* Update the NAND controller state */
@@ -1852,11 +1887,12 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -1864,39 +1900,39 @@
/* Process locked */
__HAL_LOCK(hnand);
- if(hnand->State == HAL_NAND_STATE_READY)
+ if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = pCallback;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = pCallback;
- break;
- case HAL_NAND_IT_CB_ID :
- hnand->ItCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hnand->State == HAL_NAND_STATE_RESET)
+ else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = pCallback;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1921,46 +1957,46 @@
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hnand);
- if(hnand->State == HAL_NAND_STATE_READY)
+ if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = HAL_NAND_MspInit;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- break;
- case HAL_NAND_IT_CB_ID :
- hnand->ItCallback = HAL_NAND_ITCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = HAL_NAND_ITCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hnand->State == HAL_NAND_STATE_RESET)
+ else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = HAL_NAND_MspInit;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1973,15 +2009,15 @@
__HAL_UNLOCK(hnand);
return status;
}
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### NAND Control functions #####
@@ -2101,8 +2137,8 @@
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### NAND State functions #####
@@ -2135,17 +2171,17 @@
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
uint32_t data;
- uint32_t DeviceAddress;
+ uint32_t deviceaddress;
UNUSED(hnand);
/* Identify the device address */
- DeviceAddress = NAND_DEVICE;
+ deviceaddress = NAND_DEVICE;
/* Send Read status operation command */
- *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
- data = *(__IO uint8_t *)DeviceAddress;
+ data = *(__IO uint8_t *)deviceaddress;
/* Return the status */
if ((data & NAND_ERROR) == NAND_ERROR)
diff --git a/Src/stm32g4xx_hal_nor.c b/Src/stm32g4xx_hal_nor.c
index bcf7df0..f01efbe 100644
--- a/Src/stm32g4xx_hal_nor.c
+++ b/Src/stm32g4xx_hal_nor.c
@@ -151,9 +151,35 @@
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
+#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
+#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
+#define NOR_CMD_CONFIRM (uint16_t)0x00D0
+#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
+#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
+#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
+#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
+
/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
+
+/* Address of the primary command set */
+#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
+
+/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
+#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
+#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
+#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
+#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
+#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
+#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
+#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
+#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
/**
* @}
@@ -200,8 +226,11 @@
* @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
+ uint32_t deviceaddress;
+
/* Check the NOR handle parameter */
if (hnor == NULL)
{
@@ -214,7 +243,7 @@
hnor->Lock = HAL_UNLOCKED;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- if(hnor->MspInitCallback == NULL)
+ if (hnor->MspInitCallback == NULL)
{
hnor->MspInitCallback = HAL_NOR_MspInit;
}
@@ -252,7 +281,29 @@
/* Initialize the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
- return HAL_OK;
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Get the value of the command set */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ return HAL_NOR_ReturnToReadMode(hnor);
}
/**
@@ -264,7 +315,7 @@
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- if(hnor->MspDeInitCallback == NULL)
+ if (hnor->MspDeInitCallback == NULL)
{
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
}
@@ -367,6 +418,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -401,15 +453,33 @@
}
/* Send read ID command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+ if (status != HAL_ERROR)
+ {
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+ DEVICE_CODE3_ADDR);
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -422,7 +492,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -435,6 +505,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -468,7 +539,19 @@
deviceaddress = NOR_MEMORY_ADRESS4;
}
- NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -481,7 +564,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -496,6 +579,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -530,12 +614,27 @@
}
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Read the data */
- *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+ if (status != HAL_ERROR)
+ {
+ /* Read the data */
+ *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -548,7 +647,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -562,6 +661,7 @@
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -595,12 +695,27 @@
}
/* Send program data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Write the data */
- NOR_WRITE(pAddress, *pData);
+ if (status != HAL_ERROR)
+ {
+ /* Write the data */
+ NOR_WRITE(pAddress, *pData);
+ }
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -613,7 +728,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -625,11 +740,15 @@
* @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
{
- uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
+ uint32_t deviceaddress;
+ uint32_t size = uwBufferSize;
+ uint32_t address = uwAddress;
uint16_t *data = pData;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -664,17 +783,32 @@
}
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
-
- /* Read buffer */
- while (size > 0U)
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- *data = *(__IO uint16_t *)address;
- data++;
- address += 2U;
- size--;
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Read buffer */
+ while (size > 0U)
+ {
+ *data = *(__IO uint16_t *)address;
+ data++;
+ address += 2U;
+ size--;
+ }
}
/* Check the NOR controller state */
@@ -688,7 +822,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -700,12 +834,14 @@
* @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
{
uint16_t *p_currentaddress;
const uint16_t *p_endaddress;
uint16_t *data = pData;
- uint32_t lastloadedaddress, deviceaddress;
+ uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -739,31 +875,51 @@
}
/* Initialize variables */
- p_currentaddress = (uint16_t *)(uwAddress);
- p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
- lastloadedaddress = uwAddress;
+ p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
+ p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
- /* Write Buffer Load Command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
-
- /* Load Data into NOR Buffer */
- while (p_currentaddress <= p_endaddress)
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Store last loaded address & data value (for polling) */
- lastloadedaddress = (uint32_t)p_currentaddress;
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(p_currentaddress, *data);
-
- data++;
- p_currentaddress ++;
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
}
- NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+ if (status != HAL_ERROR)
+ {
+ /* Load Data into NOR Buffer */
+ while (p_currentaddress <= p_endaddress)
+ {
+ NOR_WRITE(p_currentaddress, *data);
+
+ data++;
+ p_currentaddress ++;
+ }
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+ }
+ else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
+ }
+ }
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -776,7 +932,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
@@ -791,6 +947,7 @@
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -824,12 +981,30 @@
}
/* Send block erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -842,7 +1017,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
@@ -856,6 +1031,7 @@
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
UNUSED(Address);
/* Check the NOR controller state */
@@ -890,12 +1066,23 @@
}
/* Send NOR chip erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -908,7 +1095,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -990,12 +1177,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -1004,20 +1192,20 @@
__HAL_LOCK(hnor);
state = hnor->State;
- if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_NOR_MSP_INIT_CB_ID :
- hnor->MspInitCallback = pCallback;
- break;
- case HAL_NOR_MSP_DEINIT_CB_ID :
- hnor->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = pCallback;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1041,7 +1229,7 @@
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
@@ -1050,20 +1238,20 @@
__HAL_LOCK(hnor);
state = hnor->State;
- if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_NOR_MSP_INIT_CB_ID :
- hnor->MspInitCallback = HAL_NOR_MspInit;
- break;
- case HAL_NOR_MSP_DEINIT_CB_ID :
- hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1083,8 +1271,8 @@
*/
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### NOR Control functions #####
@@ -1106,7 +1294,7 @@
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_PROTECTED)
+ if (hnor->State == HAL_NOR_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1140,7 +1328,7 @@
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_READY)
+ if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1170,8 +1358,8 @@
*/
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### NOR State functions #####
@@ -1207,7 +1395,8 @@
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
- uint16_t tmpSR1, tmpSR2;
+ uint16_t tmpsr1;
+ uint16_t tmpsr2;
uint32_t tickstart;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
@@ -1217,45 +1406,84 @@
/* Get tick */
tickstart = HAL_GetTick();
- while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
+ while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
{
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- status = HAL_NOR_STATUS_TIMEOUT;
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS ;
+ }
+
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmpsr1 = *(__IO uint16_t *)Address;
+ tmpsr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
}
}
-
- /* Read NOR status register (DQ6 and DQ5) */
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ do
{
- return HAL_NOR_STATUS_SUCCESS ;
- }
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpsr2 = *(__IO uint16_t *)(Address);
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
- {
- status = HAL_NOR_STATUS_ONGOING;
- }
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ return HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+ } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpsr1 = *(__IO uint16_t *)(Address);
+ if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
{
- return HAL_NOR_STATUS_SUCCESS;
+ /* Clear the Status Register */
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ status = HAL_NOR_STATUS_ERROR;
}
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ else
{
- return HAL_NOR_STATUS_ERROR;
+ status = HAL_NOR_STATUS_SUCCESS;
}
}
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_NOR_STATUS_ERROR;
+ }
/* Return the operation status */
return status;
diff --git a/Src/stm32g4xx_hal_pcd.c b/Src/stm32g4xx_hal_pcd.c
index e36b98a..8455511 100644
--- a/Src/stm32g4xx_hal_pcd.c
+++ b/Src/stm32g4xx_hal_pcd.c
@@ -206,7 +206,7 @@
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
-
+
return HAL_OK;
}
@@ -298,7 +298,9 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
+ HAL_PCD_CallbackIDTypeDef CallbackID,
+ pPCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -508,7 +510,8 @@
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataOutStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -581,7 +584,8 @@
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_DataInStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -654,7 +658,8 @@
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoOutIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -727,7 +732,8 @@
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
+ pPCD_IsoInIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1357,7 +1363,8 @@
* @param ep_type endpoint type
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
+ uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
@@ -1534,10 +1541,7 @@
__HAL_LOCK(hpcd);
(void)USB_EPSetStall(hpcd->Instance, ep);
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
- }
+
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -1672,6 +1676,7 @@
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
{
wIstr = hpcd->Instance->ISTR;
+
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
@@ -1754,8 +1759,11 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
+ {
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
}
}
}
@@ -1842,9 +1850,8 @@
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- /* Manage all non bulk transaction or Bulk Single Buffer Transaction */
- if ((ep->type != EP_TYPE_BULK) ||
- ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
+ /* Manage Bulk Single Buffer Transaction */
+ if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))
{
/* multi-packet on the NON control IN endpoint */
TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
@@ -1876,7 +1883,7 @@
(void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
- /* bulk in double buffer enable in case of transferLen> Ep_Mps */
+ /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
@@ -2000,6 +2007,9 @@
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2070,6 +2080,9 @@
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
@@ -2077,7 +2090,7 @@
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
- /*need to Free USB Buff*/
+ /* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
diff --git a/Src/stm32g4xx_hal_pcd_ex.c b/Src/stm32g4xx_hal_pcd_ex.c
index 1fe3b6b..91ad5f7 100644
--- a/Src/stm32g4xx_hal_pcd_ex.c
+++ b/Src/stm32g4xx_hal_pcd_ex.c
@@ -78,10 +78,8 @@
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress)
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+ uint16_t ep_kind, uint32_t pmaadress)
{
PCD_EPTypeDef *ep;
diff --git a/Src/stm32g4xx_hal_rtc.c b/Src/stm32g4xx_hal_rtc.c
index 879efa6..5d9afda 100644
--- a/Src/stm32g4xx_hal_rtc.c
+++ b/Src/stm32g4xx_hal_rtc.c
@@ -918,10 +918,10 @@
/* Set the RTC_TR register */
WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK));
- /* Clear the bits to be configured */
+ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
CLEAR_BIT(RTC->CR, RTC_CR_BKP);
- /* Configure the RTC_CR register */
+ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation));
/* Exit Initialization mode */
@@ -1744,6 +1744,10 @@
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
return HAL_TIMEOUT;
}
}
@@ -1798,7 +1802,7 @@
UNUSED(hrtc);
/* Clear RSF flag */
- SET_BIT(RTC->ICSR, RTC_RSF_MASK);
+ CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF);
tickstart = HAL_GetTick();
@@ -1960,6 +1964,72 @@
}
/**
+ * @brief Daylight Saving Time, Add one hour to the calendar in one single operation
+ * without going through the initialization procedure.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_ADD1H);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Subtract one hour from the calendar in one
+ * single operation without going through the initialization procedure.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_SUB1H);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Set the store operation bit.
+ * @note It can be used by the software in order to memorize the DST status.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ SET_BIT(RTC->CR, RTC_CR_BKP);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Clear the store operation bit.
+ * @param hrtc RTC handle
+ * @retval None
+ */
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ CLEAR_BIT(RTC->CR, RTC_CR_BKP);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+}
+
+/**
+ * @brief Daylight Saving Time, Read the store operation bit.
+ * @param hrtc RTC handle
+ * @retval operation see RTC_StoreOperation_Definitions
+ */
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
+{
+ UNUSED(hrtc);
+ return READ_BIT(RTC->CR, RTC_CR_BKP);
+}
+
+/**
* @}
*/
diff --git a/Src/stm32g4xx_hal_rtc_ex.c b/Src/stm32g4xx_hal_rtc_ex.c
index fc3adce..f43bd1f 100644
--- a/Src/stm32g4xx_hal_rtc_ex.c
+++ b/Src/stm32g4xx_hal_rtc_ex.c
@@ -225,16 +225,12 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- /* RTC timestamp Interrupt Configuration: EXTI configuration (always rising edge)*/
- __HAL_RTC_TIMESTAMP_EXTI_RISING_IT();
- __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
-
- /* Get the RTC_CR register and clear the bits to be configured */
- CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
-
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ /* Get the RTC_CR register and clear the bits to be configured */
+ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
+
/* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */
SET_BIT(RTC->CR, (uint32_t)TimeStampEdge);
@@ -247,6 +243,10 @@
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* RTC timestamp Interrupt Configuration: EXTI configuration (always rising edge)*/
+ __HAL_RTC_TIMESTAMP_EXTI_RISING_IT();
+ __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT();
+
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -490,6 +490,10 @@
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
return HAL_TIMEOUT;
}
}
@@ -792,6 +796,10 @@
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
return HAL_TIMEOUT;
}
}
@@ -1282,6 +1290,10 @@
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
return HAL_TIMEOUT;
}
}
diff --git a/Src/stm32g4xx_hal_smartcard.c b/Src/stm32g4xx_hal_smartcard.c
index 85581f3..c8137fb 100644
--- a/Src/stm32g4xx_hal_smartcard.c
+++ b/Src/stm32g4xx_hal_smartcard.c
@@ -199,23 +199,24 @@
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
- USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \
+ USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
-#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
@@ -2345,7 +2346,7 @@
uint32_t tmpreg;
SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the parameters */
@@ -2370,8 +2371,8 @@
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode;
+ tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) |
+ ((uint32_t)hsmartcard->Init.WordLength));
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
diff --git a/Src/stm32g4xx_hal_smartcard_ex.c b/Src/stm32g4xx_hal_smartcard_ex.c
index ad2626f..327d021 100644
--- a/Src/stm32g4xx_hal_smartcard_ex.c
+++ b/Src/stm32g4xx_hal_smartcard_ex.c
@@ -458,8 +458,8 @@
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
{
diff --git a/Src/stm32g4xx_hal_smbus_ex.c b/Src/stm32g4xx_hal_smbus_ex.c
new file mode 100644
index 0000000..db6ed3a
--- /dev/null
+++ b/Src/stm32g4xx_hal_smbus_ex.c
@@ -0,0 +1,156 @@
+/**
+ ******************************************************************************
+ * @file stm32g4xx_hal_smbus_ex.c
+ * @author MCD Application Team
+ * @brief SMBUS Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SMBUS Extended peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SMBUS peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SMBUS interface for STM32G4xx
+ devices contains the following additional features
+
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_SMBUSEx_EnableFastModePlus()
+ (++) HAL_SMBUSEx_DisableFastModePlus()
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUSEx SMBUSEx
+ * @brief SMBUS Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * @note For all I2C4 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
+ * @note For all I2C4 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C4 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32g4xx_hal_spi.c b/Src/stm32g4xx_hal_spi.c
index 5fa0060..58b6d39 100644
--- a/Src/stm32g4xx_hal_spi.c
+++ b/Src/stm32g4xx_hal_spi.c
@@ -1007,6 +1007,9 @@
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
@@ -1173,12 +1176,16 @@
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
/* Read 16bit CRC */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
/* Read 8bit CRC */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
@@ -1190,7 +1197,9 @@
goto error;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
@@ -1235,6 +1244,9 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
uint16_t initial_TxXferCount;
uint16_t initial_RxXferCount;
uint32_t tmp_mode;
@@ -1476,12 +1488,16 @@
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
/* Read 16bit CRC */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
/* Read 8bit CRC */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -1493,7 +1509,9 @@
goto error;
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
@@ -3048,6 +3066,9 @@
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -3072,12 +3093,16 @@
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* Read 16bit CRC */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
/* Read 8bit CRC */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -3087,7 +3112,9 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
@@ -3152,6 +3179,9 @@
{
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
uint32_t tickstart;
+#if (USE_SPI_CRC != 0U)
+ __IO uint32_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -3175,7 +3205,9 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
@@ -3185,7 +3217,9 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
#endif /* USE_SPI_CRC */
@@ -3520,8 +3554,12 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 8bit CRC to flush Data Register */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
@@ -3628,8 +3666,12 @@
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 16bit CRC to flush Data Register */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -3684,8 +3726,12 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 8bit CRC to flush Data Register */
- READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
@@ -3738,8 +3784,12 @@
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
+ __IO uint32_t tmpreg = 0U;
+
/* Read 16bit CRC to flush Data Register */
- READ_REG(hspi->Instance->DR);
+ tmpreg = READ_REG(hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -3914,6 +3964,7 @@
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
+ __IO uint32_t tmpreg;
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
@@ -3929,8 +3980,10 @@
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
- /* Read 8bit CRC to flush Data Register */
- READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
+ /* Flush Data Register by a blank read */
+ tmpreg = READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
if (Timeout != HAL_MAX_DELAY)
diff --git a/Src/stm32g4xx_hal_sram.c b/Src/stm32g4xx_hal_sram.c
index da4d951..a07ee11 100644
--- a/Src/stm32g4xx_hal_sram.c
+++ b/Src/stm32g4xx_hal_sram.c
@@ -128,20 +128,14 @@
* @{
*/
-/**
- @cond 0
- */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void SRAM_DMACplt (DMA_HandleTypeDef *hdma);
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
-static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
-/**
- @endcond
- */
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
/* Exported functions --------------------------------------------------------*/
@@ -171,7 +165,8 @@
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if (hsram == NULL)
@@ -185,7 +180,7 @@
hsram->Lock = HAL_UNLOCKED;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- if(hsram->MspInitCallback == NULL)
+ if (hsram->MspInitCallback == NULL)
{
hsram->MspInitCallback = HAL_SRAM_MspInit;
}
@@ -197,7 +192,7 @@
#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/* Initialize SRAM control Interface */
@@ -207,7 +202,8 @@
(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
- (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+ (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
+ hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
@@ -227,7 +223,7 @@
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- if(hsram->MspDeInitCallback == NULL)
+ if (hsram->MspDeInitCallback == NULL)
{
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
}
@@ -237,7 +233,7 @@
#else
/* De-Initialize the low level hardware (MSP) */
HAL_SRAM_MspDeInit(hsram);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/* Configure the SRAM registers with their reset values */
(void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
@@ -342,11 +338,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
- uint8_t * pdestbuff = pDstBuffer;
+ uint8_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@@ -389,11 +386,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
- uint8_t * psrcbuff = pSrcBuffer;
+ uint8_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@@ -435,7 +433,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
@@ -456,7 +455,7 @@
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Read data from memory */
- for (size = BufferSize; size != limit; size-=2U)
+ for (size = BufferSize; size != limit; size -= 2U)
{
*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
pdestbuff++;
@@ -494,11 +493,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
- uint16_t * psrcbuff = pSrcBuffer;
+ uint16_t *psrcbuff = pSrcBuffer;
uint8_t limit;
/* Check the SRAM controller state */
@@ -514,7 +514,7 @@
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Write data to memory */
- for (size = BufferSize; size != limit; size-=2U)
+ for (size = BufferSize; size != limit; size -= 2U)
{
*psramaddress = (uint32_t)(*psrcbuff);
psrcbuff++;
@@ -552,11 +552,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
- __IO uint32_t * psramaddress = pAddress;
- uint32_t * pdestbuff = pDstBuffer;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@@ -599,11 +600,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
- __IO uint32_t * psramaddress = pAddress;
- uint32_t * psrcbuff = pSrcBuffer;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@@ -645,7 +647,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
HAL_SRAM_StateTypeDef state = hsram->State;
@@ -678,7 +681,7 @@
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -693,7 +696,8 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
@@ -718,7 +722,7 @@
}
else
{
- return HAL_ERROR;
+ status = HAL_ERROR;
}
return status;
@@ -736,12 +740,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -750,20 +755,20 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = pCallback;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = pCallback;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -789,7 +794,7 @@
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
@@ -798,42 +803,42 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = HAL_SRAM_MspInit;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
- break;
- case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
- hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- break;
- case HAL_SRAM_DMA_XFER_ERR_CB_ID :
- hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(state == HAL_SRAM_STATE_RESET)
+ else if (state == HAL_SRAM_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = HAL_SRAM_MspInit;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -858,12 +863,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -872,20 +878,20 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
- hsram->DmaXferCpltCallback = pCallback;
- break;
- case HAL_SRAM_DMA_XFER_ERR_CB_ID :
- hsram->DmaXferErrorCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -898,15 +904,15 @@
__HAL_UNLOCK(hsram);
return status;
}
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### SRAM Control functions #####
@@ -928,7 +934,7 @@
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ if (hsram->State == HAL_SRAM_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hsram);
@@ -962,7 +968,7 @@
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_READY)
+ if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
@@ -992,8 +998,8 @@
*/
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### SRAM State functions #####
@@ -1026,16 +1032,13 @@
*/
/**
- @cond 0
- */
-/**
* @brief DMA SRAM process complete callback.
* @param hdma : DMA handle
* @retval None
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
@@ -1047,7 +1050,7 @@
hsram->DmaXferCpltCallback(hdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
@@ -1057,7 +1060,7 @@
*/
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
@@ -1069,7 +1072,7 @@
hsram->DmaXferCpltCallback(hdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
@@ -1079,7 +1082,7 @@
*/
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
@@ -1091,11 +1094,8 @@
hsram->DmaXferErrorCallback(hdma);
#else
HAL_SRAM_DMA_XferErrorCallback(hdma);
-#endif
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
-/**
- @endcond
- */
/**
* @}
diff --git a/Src/stm32g4xx_hal_tim.c b/Src/stm32g4xx_hal_tim.c
index fd78efb..e971109 100644
--- a/Src/stm32g4xx_hal_tim.c
+++ b/Src/stm32g4xx_hal_tim.c
@@ -510,7 +510,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
@@ -569,6 +569,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1085,6 +1086,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1105,6 +1107,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1125,6 +1128,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1144,6 +1148,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1721,6 +1726,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1741,6 +1747,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1760,6 +1767,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Capture/Compare 3 request */
@@ -1779,6 +1787,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2074,7 +2083,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2156,7 +2165,7 @@
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2308,12 +2317,12 @@
/* Set the TIM channel state */
if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2344,6 +2353,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -2363,6 +2373,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -2382,6 +2393,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -2401,6 +2413,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2683,11 +2696,12 @@
/**
* @brief Starts the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2702,9 +2716,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2719,7 +2733,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2739,11 +2753,12 @@
/**
* @brief Stops the TIM One Pulse signal generation.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be disable
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2755,7 +2770,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -2781,11 +2796,12 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2800,9 +2816,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2817,7 +2833,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
@@ -2843,11 +2859,12 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @note Though OutputChannel parameter is deprecated and ignored by the function
+ * it has been kept to avoid HAL_TIM API compatibility break.
+ * @note The pulse output channel is determined when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channels to be enabled
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param OutputChannel See note above
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -2865,7 +2882,7 @@
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
@@ -3137,7 +3154,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3150,7 +3167,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3163,9 +3180,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3255,7 +3272,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3291,7 +3308,7 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3304,7 +3321,7 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3317,9 +3334,9 @@
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3417,7 +3434,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3457,12 +3474,12 @@
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData1 == NULL) && (Length > 0U))
{
@@ -3482,12 +3499,12 @@
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData2 == NULL) && (Length > 0U))
{
@@ -3507,16 +3524,16 @@
else
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3550,6 +3567,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3574,6 +3592,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3599,6 +3618,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -3612,6 +3632,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the Peripheral */
@@ -3690,7 +3711,7 @@
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
}
- else
+ else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -4587,8 +4608,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4604,8 +4626,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4621,8 +4644,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4638,8 +4662,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4655,8 +4680,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4672,8 +4698,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4689,8 +4716,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4916,8 +4944,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4933,8 +4962,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4950,8 +4980,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4967,8 +4998,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4984,8 +5016,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -5001,8 +5034,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -5018,8 +5052,9 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
- DataLength) != HAL_OK)
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -5491,7 +5526,7 @@
#endif /* TIM20 */
#if defined (HRTIM1)
case TIM_CLOCKSOURCE_ITR10:
-#endif /* HRTIM1 */
+#endif /* HRTIM1 */
case TIM_CLOCKSOURCE_ITR11:
{
/* Check whether or not the timer instance supports internal trigger input */
@@ -6177,7 +6212,7 @@
* @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
* @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
* @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
- * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transistion Error Callback ID
+ * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
@@ -6509,12 +6544,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
-
+
return channel_state;
}
@@ -6527,7 +6562,7 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-
+
return htim->DMABurstState;
}
@@ -6591,14 +6626,14 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6607,7 +6642,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6616,7 +6651,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6625,7 +6660,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -6696,7 +6731,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -6706,7 +6741,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -6716,7 +6751,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -6726,7 +6761,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
diff --git a/Src/stm32g4xx_hal_tim_ex.c b/Src/stm32g4xx_hal_tim_ex.c
index 1ee2f14..6148aff 100644
--- a/Src/stm32g4xx_hal_tim_ex.c
+++ b/Src/stm32g4xx_hal_tim_ex.c
@@ -340,9 +340,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -352,7 +352,7 @@
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
+
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@@ -420,9 +420,9 @@
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -506,12 +506,12 @@
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -541,6 +541,7 @@
/* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
@@ -643,7 +644,7 @@
{
return HAL_ERROR;
}
-
+
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
@@ -925,6 +926,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -944,6 +946,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -963,6 +966,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -982,6 +986,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -1426,6 +1431,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -1445,6 +1451,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1464,6 +1471,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1483,6 +1491,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1614,8 +1623,10 @@
/**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1624,22 +1635,28 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
@@ -1655,8 +1672,10 @@
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1680,8 +1699,10 @@
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -1690,8 +1711,10 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be enabled
+ * @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1700,22 +1723,28 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
- HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
- HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
+ HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
- if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -1737,8 +1766,10 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
+ * @note OutputChannel must match the pulse output channel chosen when calling
+ * @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
- * @param OutputChannel TIM Channel to be disabled
+ * @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1768,8 +1799,10 @@
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
- TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
- TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@@ -3401,12 +3434,12 @@
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
-
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
+
return channel_state;
}
/**
@@ -3473,7 +3506,7 @@
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@@ -3482,7 +3515,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -3491,7 +3524,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@@ -3500,7 +3533,7 @@
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
+
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@@ -3525,7 +3558,7 @@
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -3548,13 +3581,13 @@
{
/* nothing to do */
}
-
+
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
diff --git a/Src/stm32g4xx_hal_uart.c b/Src/stm32g4xx_hal_uart.c
index 15d681a..fb5c3e8 100644
--- a/Src/stm32g4xx_hal_uart.c
+++ b/Src/stm32g4xx_hal_uart.c
@@ -115,6 +115,10 @@
(+) MspDeInitCallback : UART MspDeInit.
[..]
+ For specific callback RxEventCallback, use dedicated registration/reset functions:
+ respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+
+ [..]
By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
@@ -173,27 +177,23 @@
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
- USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+ USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
- USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+ USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */
#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */
#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
-
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
-
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -223,6 +223,15 @@
* @}
*/
+/* Exported Constants --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Constants
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
@@ -646,6 +655,7 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
__HAL_UNLOCK(huart);
@@ -935,6 +945,74 @@
return status;
}
+
+/**
+ * @brief Register a User UART Rx Event Callback
+ * To be used instead of the weak predefined callback
+ * @param huart Uart handle
+ * @param pCallback Pointer to the Rx Event Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = pCallback;
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the UART Rx Event Callback
+ * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+ * @param huart Uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+ return status;
+}
+
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@@ -1000,6 +1078,10 @@
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+ reception services:
+ (+) HAL_UARTEx_RxEventCallback()
+
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
@@ -1144,6 +1226,7 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
@@ -1296,58 +1379,20 @@
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
- huart->RxISR = NULL;
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Configure Rx interrupt processing*/
- if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
- huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ /* Enable the UART Receiver Timeout Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
- else
- {
- huart->RxISR = UART_RxISR_8BIT_FIFOEN;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
- }
- else
- {
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- huart->RxISR = UART_RxISR_16BIT;
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
}
- return HAL_OK;
+ return (UART_Start_Receive_IT(huart, pData, Size));
}
else
{
@@ -1453,53 +1498,20 @@
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- if (huart->hdmarx != NULL)
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- __HAL_UNLOCK(huart);
-
- /* Restore huart->gState to ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_ERROR;
+ /* Enable the UART Receiver Timeout Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
}
- __HAL_UNLOCK(huart);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
+ return (UART_Start_Receive_DMA(huart, pData, Size));
}
else
{
@@ -1660,6 +1672,12 @@
USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Tx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
@@ -1729,6 +1747,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
huart->ErrorCode = HAL_UART_ERROR_NONE;
@@ -1811,6 +1830,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
@@ -1847,6 +1872,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
return HAL_OK;
}
@@ -1874,6 +1900,12 @@
USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
@@ -1982,6 +2014,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2106,6 +2139,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
@@ -2141,6 +2180,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2165,6 +2205,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2347,6 +2388,93 @@
} /* End if some error occurs */
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ && ((isrflags & USART_ISR_IDLE) != 0U)
+ && ((cr1its & USART_ISR_IDLE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* Check if DMA mode is enabled in UART */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* DMA mode enabled */
+ /* Check received length : If all expected data are received, do nothing,
+ (DMA cplt callback will be called).
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ if ((nb_remaining_rx_data > 0U)
+ && (nb_remaining_rx_data < huart->RxXferSize))
+ {
+ /* Reception is not complete */
+ huart->RxXferCount = nb_remaining_rx_data;
+
+ /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Last bytes received, so no need as the abort is immediate */
+ (void)HAL_DMA_Abort(huart->hdmarx);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ else
+ {
+ /* DMA mode not enabled */
+ /* Check received length : If all expected data are received, do nothing.
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ if ((huart->RxXferCount > 0U)
+ && (nb_rx_data > 0U))
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxEventCallback(huart, nb_rx_data);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ return;
+ }
+ }
+
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
{
@@ -2532,6 +2660,24 @@
}
/**
+ * @brief Reception Event Callback (Rx event notification called after use of advanced reception service).
+ * @param huart UART handle
+ * @param Size Number of data available in application reception buffer (indicates a position in
+ * reception buffer until which, data are available)
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ UNUSED(Size);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -2853,6 +2999,7 @@
huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */
}
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -2899,7 +3046,6 @@
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- tmpreg |= (uint32_t)huart->FifoMode;
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -3189,6 +3335,7 @@
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
__HAL_UNLOCK(huart);
@@ -3255,6 +3402,134 @@
return HAL_OK;
}
+/**
+ * @brief Start Receive operation in interrupt mode.
+ * @note This function could be called by all HAL UART API providing reception in Interrupt mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+ huart->RxISR = NULL;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in DMA mode.
+ * @note This function could be called by all HAL UART API providing reception in DMA mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+}
+
/**
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
@@ -3283,8 +3558,15 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
@@ -3367,15 +3649,37 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+
+ /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
}
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
/**
@@ -3387,13 +3691,29 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Half complete callback*/
- huart->RxHalfCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
#else
- /*Call legacy weak Rx Half complete callback*/
- HAL_UART_RxHalfCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
/**
@@ -3498,6 +3818,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3549,6 +3870,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3616,6 +3938,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3828,13 +4151,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -3880,13 +4223,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -3907,18 +4270,66 @@
{
uint16_t uhMask = huart->Mask;
uint16_t uhdata;
- uint16_t nb_rx_data;
+ uint16_t nb_rx_data;
uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
huart->pRxBuffPtr++;
huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
if (huart->RxXferCount == 0U)
{
@@ -3935,13 +4346,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
@@ -3981,19 +4412,67 @@
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
uint16_t uhdata;
- uint16_t nb_rx_data;
+ uint16_t nb_rx_data;
uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
tmp = (uint16_t *) huart->pRxBuffPtr ;
*tmp = (uint16_t)(uhdata & uhMask);
huart->pRxBuffPtr += 2U;
huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
if (huart->RxXferCount == 0U)
{
@@ -4010,13 +4489,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
diff --git a/Src/stm32g4xx_hal_uart_ex.c b/Src/stm32g4xx_hal_uart_ex.c
index fe2678b..b854fa7 100644
--- a/Src/stm32g4xx_hal_uart_ex.c
+++ b/Src/stm32g4xx_hal_uart_ex.c
@@ -332,6 +332,41 @@
(+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
(+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+ [..] This subsection also provides a set of additional functions providing enhanced reception
+ services to user. (For example, these functions allow application to handle use cases
+ where number of data to be received is unknown).
+
+ (#) Compared to standard reception services which only consider number of received
+ data elements as reception completion criteria, these functions also consider additional events
+ as triggers for updating reception status to caller :
+ (+) Detection of inactivity period (RX line has not been active for a given period).
+ (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+ for 1 frame time, after last received byte.
+ (++) RX inactivity detected by RTO, i.e. line has been in idle state
+ for a programmable time, after last received byte.
+ (+) Detection that a specific character has been received.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+ or till IDLE event occurs. Reception is handled only during function execution.
+ When function exits, no data reception could occur. HAL status and number of actually received data elements,
+ are returned by function after finishing transfer.
+ (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+ The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+ (#) Blocking mode API:
+ (+) HAL_UARTEx_ReceiveToIdle()
+
+ (#) Non-Blocking mode API with Interrupt:
+ (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+ (#) Non-Blocking mode API with DMA:
+ (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
@endverbatim
* @{
*/
@@ -653,6 +688,259 @@
}
/**
+ * @brief Receive an amount of data in blocking mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note HAL_OK is returned if reception is completed (expected number of data has been received)
+ * or if reception is stopped after IDLE event (less than the expected number of data has been received)
+ * In this case, RxLen output parameter indicates number of data available in reception buffer.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @param RxLen Number of data elements finally received
+ * (could be lower than Size, in case reception ends on IDLE event)
+ * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+ uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Initialize output number of received elements */
+ *RxLen = 0U;
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ /* Check if IDLE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+ {
+ /* Clear IDLE flag in ISR */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* If Set, but no data ever received, clear flag without exiting loop */
+ /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+ if (*RxLen > 0U)
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ }
+
+ /* Check if RXNE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+ {
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ /* Increment number of received elements */
+ *RxLen += 1U;
+ huart->RxXferCount--;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set number of received elements in output parameter : RxLen */
+ *RxLen = huart->RxXferSize - huart->RxXferCount;
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode till either the expected number of data
+ * is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+ * number of received data elements.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_IT(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode till either the expected number
+ * of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to DMA services, transferring automatically received data elements in user reception buffer and
+ * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+ * reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_DMA(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @}
*/
@@ -694,8 +982,8 @@
uint8_t tx_fifo_depth;
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
{
diff --git a/Src/stm32g4xx_hal_usart_ex.c b/Src/stm32g4xx_hal_usart_ex.c
index a013c54..45908ad 100644
--- a/Src/stm32g4xx_hal_usart_ex.c
+++ b/Src/stm32g4xx_hal_usart_ex.c
@@ -503,8 +503,8 @@
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
- uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
- uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+ static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
{
diff --git a/Src/stm32g4xx_hal_wwdg.c b/Src/stm32g4xx_hal_wwdg.c
index 01ed73b..43ae859 100644
--- a/Src/stm32g4xx_hal_wwdg.c
+++ b/Src/stm32g4xx_hal_wwdg.c
@@ -21,6 +21,13 @@
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) If required by application, an Early Wakeup Interrupt can be triggered
+ in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+ (EWI) can be used if specific safety operations or data logging must
+ be performed before the actual reset is generated. When the downcounter
+ reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+ line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+ disabled except by a system reset.
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
@@ -34,7 +41,8 @@
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) at 170MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 24.09µs
- (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler dividing by 128:
+ (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler
+ dividing by 128:
max timeout before reset: approximately 197.38ms
##### How to use this driver #####
@@ -45,16 +53,16 @@
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
- (+) Set the WWDG prescaler, refresh window and counter value
- using HAL_WWDG_Init() function.
- (+) Start the WWDG using HAL_WWDG_Start() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
- (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
- generated when the counter reaches 0x40, and then start the WWDG using
- HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
- add his own code by customization of callback HAL_WWDG_WakeupCallback.
- Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Configure the WWDG prescaler, refresh window value, counter value and early
+ interrupt status using HAL_WWDG_Init() function. This will automatically
+ enable WWDG and start its downcounter. Time reference can be taken from
+ function exit. Care must be taken to provide a counter value
+ greater than 0x40 to prevent generation of immediate reset.
+ (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+ generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+ triggered by the interrupt service routine, flag will be automatically
+ cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+ can add his own code by customization of callback HAL_WWDG_WakeupCallback.
(+) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
@@ -64,7 +72,7 @@
=============================
[..]
- The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
HAL_WWDG_RegisterCallback() to register a user callback.
@@ -96,7 +104,7 @@
*** WWDG HAL driver macros list ***
===================================
[..]
- Below the list of most used macros in WWDG HAL driver.
+ Below the list of available macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
diff --git a/Src/stm32g4xx_ll_adc.c b/Src/stm32g4xx_ll_adc.c
index d5f4a17..868fdc0 100644
--- a/Src/stm32g4xx_ll_adc.c
+++ b/Src/stm32g4xx_ll_adc.c
@@ -83,7 +83,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
- ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
@@ -103,19 +103,19 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
- ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
)
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
- ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
- ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
)
@@ -123,7 +123,7 @@
/* ADC group regular */
#if defined(STM32G474xx) || defined(STM32G484xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
@@ -174,7 +174,7 @@
)
#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
@@ -216,7 +216,7 @@
)
#elif defined(STM32G471xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
@@ -253,7 +253,7 @@
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
@@ -275,7 +275,7 @@
)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
@@ -317,23 +317,23 @@
#endif
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
- ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
)
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
- ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
)
#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
- ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
- ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
@@ -352,7 +352,7 @@
)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
- ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
@@ -367,7 +367,7 @@
/* ADC group injected */
#if defined(STM32G474xx) || defined(STM32G484xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
@@ -417,7 +417,7 @@
)
#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
@@ -457,7 +457,7 @@
)
#elif defined(STM32G471xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
@@ -493,7 +493,7 @@
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
@@ -516,7 +516,7 @@
)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
@@ -557,25 +557,25 @@
#endif
#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
- ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
)
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
- ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
- ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
- ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
)
@@ -583,7 +583,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* multimode. */
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
- ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
@@ -594,7 +594,7 @@
)
#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
- ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
+ (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
@@ -602,7 +602,7 @@
)
#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
- ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
+ (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
@@ -617,7 +617,7 @@
)
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
- ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
)
@@ -1128,6 +1128,7 @@
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
+
return status;
}
@@ -1190,6 +1191,11 @@
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
@@ -1306,6 +1312,12 @@
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution if feature ADC group injected contexts queue is enabled
+ * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+ * using successively several times this function will appear as
+ * having no effect.
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
diff --git a/Src/stm32g4xx_ll_cordic.c b/Src/stm32g4xx_ll_cordic.c
index aad0654..8bf3949 100644
--- a/Src/stm32g4xx_ll_cordic.c
+++ b/Src/stm32g4xx_ll_cordic.c
@@ -25,7 +25,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32G4xx_LL_Driver
* @{
diff --git a/Src/stm32g4xx_ll_dac.c b/Src/stm32g4xx_ll_dac.c
index c7a8a92..73ca728 100644
--- a/Src/stm32g4xx_ll_dac.c
+++ b/Src/stm32g4xx_ll_dac.c
@@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32G4xx_LL_Driver
* @{
@@ -176,17 +176,17 @@
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
- || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
)
#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \
( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
- || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
+ || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
)
#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \
( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
- || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
+ || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
)
/**
@@ -310,7 +310,7 @@
/* Note: Hardware constraint (refer to description of this function) */
/* DAC instance must be disabled. */
- if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
+ if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL)
{
/* Configuration of DAC channel: */
/* - TriggerSource */
diff --git a/Src/stm32g4xx_ll_fmac.c b/Src/stm32g4xx_ll_fmac.c
index 7491be4..da200b7 100644
--- a/Src/stm32g4xx_ll_fmac.c
+++ b/Src/stm32g4xx_ll_fmac.c
@@ -24,7 +24,7 @@
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
-#define assert_param(expr) ((void)0)
+#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32G4xx_LL_Driver
diff --git a/Src/stm32g4xx_ll_fmc.c b/Src/stm32g4xx_ll_fmc.c
index 12439fe..ac6521d 100644
--- a/Src/stm32g4xx_ll_fmc.c
+++ b/Src/stm32g4xx_ll_fmc.c
@@ -16,7 +16,7 @@
==============================================================================
[..] The Flexible memory controller (FMC) includes following memory controllers:
(+) The NOR/PSRAM memory controller
- (+) The NAND memory controller
+ (+) The NAND memory controller
[..] The FMC functional block makes the interface with synchronous and asynchronous static
memories. Its main purposes are:
@@ -58,6 +58,7 @@
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
@@ -86,9 +87,15 @@
/* --- BWTR Register ---*/
/* BWTR register clear mask */
+#if defined(FMC_BWTRx_BUSTURN)
#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
+#else
+#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
+ FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD |\
+ FMC_BWTRx_DATAHLD))
+#endif /* FMC_BWTRx_BUSTURN */
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
@@ -173,9 +180,12 @@
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
+ uint32_t btcr_reg;
+ uint32_t mask;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@@ -210,40 +220,44 @@
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
}
- MODIFY_REG(Device->BTCR[Init->NSBank],
- (FMC_BCRx_MBKEN |
- FMC_BCRx_MUXEN |
- FMC_BCRx_MTYP |
- FMC_BCRx_MWID |
- FMC_BCRx_FACCEN |
- FMC_BCRx_BURSTEN |
- FMC_BCRx_WAITPOL |
- FMC_BCRx_WAITCFG |
- FMC_BCRx_WREN |
- FMC_BCRx_WAITEN |
- FMC_BCRx_EXTMOD |
- FMC_BCRx_ASYNCWAIT |
- FMC_BCRx_CBURSTRW |
- FMC_BCR1_CCLKEN |
- FMC_BCR1_WFDIS |
- FMC_BCRx_NBLSET |
- FMC_BCRx_CPSIZE),
- (flashaccess |
- Init->DataAddressMux |
- Init->MemoryType |
- Init->MemoryDataWidth |
- Init->BurstAccessMode |
- Init->WaitSignalPolarity |
- Init->WaitSignalActive |
- Init->WriteOperation |
- Init->WaitSignal |
- Init->ExtendedMode |
- Init->AsynchronousWait |
- Init->WriteBurst |
- Init->ContinuousClock |
- Init->WriteFifo |
- Init->NBLSetupTime |
- Init->PageSize));
+ btcr_reg = (flashaccess | \
+ Init->DataAddressMux | \
+ Init->MemoryType | \
+ Init->MemoryDataWidth | \
+ Init->BurstAccessMode | \
+ Init->WaitSignalPolarity | \
+ Init->WaitSignalActive | \
+ Init->WriteOperation | \
+ Init->WaitSignal | \
+ Init->ExtendedMode | \
+ Init->AsynchronousWait | \
+ Init->WriteBurst);
+
+ btcr_reg |= Init->ContinuousClock;
+ btcr_reg |= Init->WriteFifo;
+ btcr_reg |= Init->NBLSetupTime;
+ btcr_reg |= Init->PageSize;
+
+ mask = (FMC_BCRx_MBKEN |
+ FMC_BCRx_MUXEN |
+ FMC_BCRx_MTYP |
+ FMC_BCRx_MWID |
+ FMC_BCRx_FACCEN |
+ FMC_BCRx_BURSTEN |
+ FMC_BCRx_WAITPOL |
+ FMC_BCRx_WAITCFG |
+ FMC_BCRx_WREN |
+ FMC_BCRx_WAITEN |
+ FMC_BCRx_EXTMOD |
+ FMC_BCRx_ASYNCWAIT |
+ FMC_BCRx_CBURSTRW);
+
+ mask |= FMC_BCR1_CCLKEN;
+ mask |= FMC_BCR1_WFDIS;
+ mask |= FMC_BCRx_NBLSET;
+ mask |= FMC_BCRx_CPSIZE;
+
+ MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
@@ -258,7 +272,7 @@
}
/* Check PSRAM chip select counter state */
- if(Init->MaxChipSelectPulse == ENABLE)
+ if (Init->MaxChipSelectPulse == ENABLE)
{
/* Check the parameters */
assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime));
@@ -281,11 +295,8 @@
SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
break;
- case FMC_NORSRAM_BANK4 :
- SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
- break;
-
default :
+ SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
break;
}
}
@@ -293,7 +304,6 @@
return HAL_OK;
}
-
/**
* @brief DeInitialize the FMC_NORSRAM peripheral
* @param Device Pointer to NORSRAM device instance
@@ -301,7 +311,8 @@
* @param Bank NORSRAM bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@@ -327,32 +338,28 @@
ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
/* De-initialize PSRAM chip select counter */
- switch (Bank)
- {
- case FMC_NORSRAM_BANK1 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
- break;
+ switch (Bank)
+ {
+ case FMC_NORSRAM_BANK1 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
+ break;
- case FMC_NORSRAM_BANK2 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
- break;
+ case FMC_NORSRAM_BANK2 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
+ break;
- case FMC_NORSRAM_BANK3 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
- break;
+ case FMC_NORSRAM_BANK3 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
+ break;
- case FMC_NORSRAM_BANK4 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
- break;
-
- default :
- break;
- }
+ default :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
+ break;
+ }
return HAL_OK;
}
-
/**
* @brief Initialize the FMC_NORSRAM Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
@@ -361,7 +368,8 @@
* @param Bank NORSRAM bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr;
@@ -379,18 +387,18 @@
/* Set FMC_NORSRAM device timing parameters */
MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
- ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
- ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
+ ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
+ ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
+ ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
+ (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
+ (Timing->AccessMode)));
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
{
- tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
}
@@ -410,7 +418,9 @@
* @arg FMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+ uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
@@ -424,7 +434,9 @@
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
+#if defined(FMC_BWTRx_BUSTURN)
assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+#endif /* FMC_BWTRx_BUSTURN */
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
@@ -433,8 +445,12 @@
((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
+#if defined(FMC_BWTRx_BUSTURN)
Timing->AccessMode |
((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
+#else
+ Timing->AccessMode));
+#endif /* FMC_BWTRx_BUSTURN */
}
else
{
@@ -448,8 +464,8 @@
*/
/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FMC_NORSRAM Control functions #####
@@ -535,8 +551,8 @@
*/
/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -590,7 +606,8 @@
* @param Bank NAND bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -600,6 +617,9 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
@@ -617,7 +637,8 @@
* @param Bank NAND bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -627,6 +648,9 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
@@ -652,6 +676,9 @@
__FMC_NAND_DISABLE(Device, Bank);
/* De-initialize the NAND Bank */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* Set the FMC_NAND_BANK3 registers to their reset values */
WRITE_REG(Device->PCR, 0x00000018U);
WRITE_REG(Device->SR, 0x00000040U);
@@ -694,6 +721,9 @@
assert_param(IS_FMC_NAND_BANK(Bank));
/* Enable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
SET_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@@ -713,6 +743,9 @@
assert_param(IS_FMC_NAND_BANK(Bank));
/* Disable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@@ -726,7 +759,8 @@
* @param Timeout Timeout wait value
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -750,6 +784,9 @@
}
}
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* Get the ECCR register value */
*ECCval = (uint32_t)Device->ECCR;
@@ -771,6 +808,10 @@
* @}
*/
+#endif /* HAL_NOR_MODULE_ENABLED */
+/**
+ * @}
+ */
/**
* @}
*/
diff --git a/Src/stm32g4xx_ll_lptim.c b/Src/stm32g4xx_ll_lptim.c
index c7de8d3..5e2f141 100644
--- a/Src/stm32g4xx_ll_lptim.c
+++ b/Src/stm32g4xx_ll_lptim.c
@@ -48,22 +48,22 @@
* @{
*/
#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
- || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+ || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
@@ -242,8 +242,7 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- }
- while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
diff --git a/Src/stm32g4xx_ll_lpuart.c b/Src/stm32g4xx_ll_lpuart.c
index 670fa9b..7224eb1 100644
--- a/Src/stm32g4xx_ll_lpuart.c
+++ b/Src/stm32g4xx_ll_lpuart.c
@@ -274,7 +274,7 @@
* @}
*/
-#endif /* defined (LPUART1) */
+#endif /* LPUART1 */
/**
* @}
diff --git a/Src/stm32g4xx_ll_rcc.c b/Src/stm32g4xx_ll_rcc.c
index 57f442d..b83b468 100644
--- a/Src/stm32g4xx_ll_rcc.c
+++ b/Src/stm32g4xx_ll_rcc.c
@@ -96,13 +96,13 @@
/** @defgroup RCC_LL_Private_Functions RCC Private functions
* @{
*/
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-uint32_t RCC_PLL_GetFreqDomain_ADC(void);
-uint32_t RCC_PLL_GetFreqDomain_48M(void);
+static uint32_t RCC_GetSystemClockFreq(void);
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
+static uint32_t RCC_PLL_GetFreqDomain_48M(void);
/**
* @}
*/
@@ -981,7 +981,7 @@
* @brief Return SYSTEM clock frequency
* @retval SYSTEM clock frequency (in Hz)
*/
-uint32_t RCC_GetSystemClockFreq(void)
+static uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency;
@@ -1013,7 +1013,7 @@
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK clock frequency (in Hz)
*/
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
@@ -1024,7 +1024,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
@@ -1035,7 +1035,7 @@
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
@@ -1045,7 +1045,7 @@
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
-uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq, pllsource;
@@ -1076,7 +1076,7 @@
* @brief Return PLL clock frequency used for ADC domain
* @retval PLL clock frequency (in Hz)
*/
-uint32_t RCC_PLL_GetFreqDomain_ADC(void)
+static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
{
uint32_t pllinputfreq, pllsource;
@@ -1107,7 +1107,7 @@
* @brief Return PLL clock frequency used for 48 MHz domain
* @retval PLL clock frequency (in Hz)
*/
-uint32_t RCC_PLL_GetFreqDomain_48M(void)
+static uint32_t RCC_PLL_GetFreqDomain_48M(void)
{
uint32_t pllinputfreq, pllsource;
diff --git a/Src/stm32g4xx_ll_spi.c b/Src/stm32g4xx_ll_spi.c
index 68e63c2..dd49c5a 100644
--- a/Src/stm32g4xx_ll_spi.c
+++ b/Src/stm32g4xx_ll_spi.c
@@ -245,6 +245,12 @@
SPI_CR2_DS | SPI_CR2_SSOE,
SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+ /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
+ if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
+ {
+ LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
+ }
+
/*---------------------------- SPIx CRCPR Configuration ----------------------
* Configure SPIx CRCPR with parameters:
* - CRCPoly: CRCPOLY[15:0] bits
diff --git a/Src/stm32g4xx_ll_usart.c b/Src/stm32g4xx_ll_usart.c
index 6a64c29..97d3649 100644
--- a/Src/stm32g4xx_ll_usart.c
+++ b/Src/stm32g4xx_ll_usart.c
@@ -66,9 +66,6 @@
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
-#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
@@ -298,9 +295,6 @@
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-
- /* Check BRR is lower than or equal to 0xFFFF */
- assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
/*---------------------------- USART PRESC Configuration -----------------------
@@ -360,37 +354,25 @@
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
- /*---------------------------- USART CR2 Configuration -----------------------*/
- /* If Clock signal has to be output */
- if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
- {
- /* Deactivate Clock signal delivery :
- * - Disable Clock Output: USART_CR2_CLKEN cleared
- */
- LL_USART_DisableSCLKOutput(USARTx);
- }
- else
- {
- /* Ensure USART instance is USART capable */
- assert_param(IS_USART_INSTANCE(USARTx));
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
- /* Check clock related parameters */
- assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
- assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
- assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
- /*---------------------------- USART CR2 Configuration -----------------------
- * Configure USARTx CR2 (Clock signal related bits) with parameters:
- * - Enable Clock Output: USART_CR2_CLKEN set
- * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
- * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
- * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
- */
- MODIFY_REG(USARTx->CR2,
- USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
- USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
- USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
- }
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
/* Else (USART not in Disabled state => return ERROR */
else
diff --git a/Src/stm32g4xx_ll_usb.c b/Src/stm32g4xx_ll_usb.c
index 3611ad2..2b2a7a6 100644
--- a/Src/stm32g4xx_ll_usb.c
+++ b/Src/stm32g4xx_ll_usb.c
@@ -56,8 +56,8 @@
/**
* @brief Initializes the USB Core
- * @param USBx: USB Instance
- * @param cfg : pointer to a USB_CfgTypeDef structure that contains
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -78,7 +78,7 @@
/**
* @brief USB_EnableGlobalInt
* Enables the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
@@ -103,7 +103,7 @@
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
@@ -123,11 +123,11 @@
}
/**
- * @brief USB_SetCurrentMode : Set functional mode
- * @param USBx : Selected device
- * @param mode : current core mode
+ * @brief USB_SetCurrentMode Set functional mode
+ * @param USBx Selected device
+ * @param mode current core mode
* This parameter can be one of the these values:
- * @arg USB_DEVICE_MODE: Peripheral mode
+ * @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
@@ -144,10 +144,10 @@
}
/**
- * @brief USB_DevInit : Initializes the USB controller registers
+ * @brief USB_DevInit Initializes the USB controller registers
* for device mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_CfgTypeDef structure that contains
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -157,13 +157,13 @@
UNUSED(cfg);
/* Init Device */
- /*CNTR_FRES = 1*/
+ /* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
- /*CNTR_FRES = 0*/
+ /* CNTR_FRES = 0 */
USBx->CNTR = 0U;
- /*Clear pending interrupts*/
+ /* Clear pending interrupts */
USBx->ISTR = 0U;
/*Set Btable Address*/
@@ -172,71 +172,11 @@
return HAL_OK;
}
-/**
- * @brief USB_SetDevSpeed :Initializes the device speed
- * depending on the PHY type and the enumeration speed of the device.
- * @param USBx Selected device
- * @param speed device speed
- * @retval Hal status
- */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(speed);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_FlushTxFifo : Flush a Tx FIFO
- * @param USBx : Selected device
- * @param num : FIFO number
- * This parameter can be a value from 1 to 15
- 15 means Flush all Tx FIFOs
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(num);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-
- return HAL_OK;
-}
-
-/**
- * @brief USB_FlushRxFifo : Flush Rx FIFO
- * @param USBx : Selected device
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
-
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-
- return HAL_OK;
-}
-
+#if defined (HAL_PCD_MODULE_ENABLED)
/**
* @brief Activate and configure an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -297,9 +237,11 @@
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@@ -309,6 +251,7 @@
{
/* Set the endpoint as double buffered */
PCD_SET_EP_DBUF(USBx, ep->num);
+
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
@@ -327,7 +270,6 @@
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
-
if (ep->type != EP_TYPE_ISOC)
{
/* Configure NAK status for the Endpoint */
@@ -348,8 +290,8 @@
/**
* @brief De-activate and de-initialize an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -359,12 +301,14 @@
if (ep->is_in != 0U)
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
@@ -390,6 +334,7 @@
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
+
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
@@ -400,15 +345,15 @@
}
/**
- * @brief USB_EPStartXfer : setup and starts a transfer over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @brief USB_EPStartXfer setup and starts a transfer over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
- uint16_t pmabuffer;
uint32_t len;
+ uint16_t pmabuffer;
uint16_t wEPVal;
/* IN endpoint */
@@ -432,43 +377,43 @@
}
else
{
- /*double buffer bulk management */
+ /* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
{
if (ep->xfer_len_db > ep->maxpacket)
{
- /*enable double buffer */
+ /* enable double buffer */
PCD_SET_EP_DBUF(USBx, ep->num);
- len = ep->maxpacket;
- /*each Time to write in PMA xfer_len_db will */
+
+ /* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
- /* Fill the two first buffer in the Buffer0 & Buffer1*/
+ /* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
- /*Write the user buffer to USB PMA */
+ /* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
- len = ep->maxpacket;
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
- ep->xfer_len_db = 0;
+ ep->xfer_len_db = 0U;
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
- /*Write the user buffer to USB PMA */
+
+ /* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
else
@@ -476,60 +421,116 @@
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
- /*Write the user buffer to USB PMA */
+
+ /* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
- len = ep->maxpacket;
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
- ep->xfer_len_db = 0;
+ ep->xfer_len_db = 0U;
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
- /*Write the user buffer to USB PMA */
+
+ /* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
- /*auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer*/
+ /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
- /*disable double buffer mode */
+
+ /* disable double buffer mode */
PCD_CLEAR_EP_DBUF(USBx, ep->num);
- /*Set Tx count with nbre of byte to be transmitted */
+
+ /* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
pmabuffer = ep->pmaaddr0;
- /*Write the user buffer to USB PMA */
+
+ /* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
- }/*end if bulk double buffer */
+ }/* end if bulk double buffer */
- /*mange isochronous double buffer IN mode */
+ /* manage isochronous double buffer IN mode */
else
{
- /* Write the data to the USB endpoint */
+ /* enable double buffer */
+ PCD_SET_EP_DBUF(USBx, ep->num);
+
+ /* each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ if (len > 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ if (len > 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
}
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
}
}
@@ -539,7 +540,7 @@
{
if (ep->doublebuffer == 0U)
{
- /* Multi packet transfer*/
+ /* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
@@ -551,21 +552,22 @@
ep->xfer_len = 0U;
}
/* configure and validate Rx endpoint */
- /*Set RX buffer count*/
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
else
{
- /*First Transfer Coming From HAL_PCD_EP_Receive & From ISR*/
- /*Set the Double buffer counter*/
+ /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
+ /* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
- /*Coming from ISR*/
+
+ /* Coming from ISR */
if (ep->xfer_count != 0U)
{
- /* update last value to check if there is blocking state*/
+ /* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
+
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
@@ -574,10 +576,10 @@
}
}
}
- /*iso out double */
+ /* iso out double */
else if (ep->type == EP_TYPE_ISOC)
{
- /* Multi packet transfer*/
+ /* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
@@ -602,54 +604,11 @@
return HAL_OK;
}
-/**
- * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param src : pointer to source buffer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to write
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(src);
- UNUSED(ch_ep_num);
- UNUSED(len);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
- * with the EP/channel
- * @param USBx : Selected device
- * @param dest : destination pointer
- * @param len : Number of bytes to read
- * @retval pointer to destination buffer
- */
-void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(dest);
- UNUSED(len);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return ((void *)NULL);
-}
-
-/**
- * @brief USB_EPSetStall : set a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @brief USB_EPSetStall set a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -667,9 +626,9 @@
}
/**
- * @brief USB_EPClearStall : Clear a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @brief USB_EPClearStall Clear a stall condition over an EP
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@@ -690,17 +649,18 @@
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure VALID status for the Endpoint*/
+ /* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
}
return HAL_OK;
}
+#endif
/**
- * @brief USB_StopDevice : Stop the usb device mode
- * @param USBx : Selected device
+ * @brief USB_StopDevice Stop the usb device mode
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
@@ -718,9 +678,9 @@
}
/**
- * @brief USB_SetDevAddress : Stop the usb device mode
- * @param USBx : Selected device
- * @param address : new device address to be assigned
+ * @brief USB_SetDevAddress Stop the usb device mode
+ * @param USBx Selected device
+ * @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
@@ -736,8 +696,8 @@
}
/**
- * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
@@ -749,8 +709,8 @@
}
/**
- * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
@@ -762,8 +722,8 @@
}
/**
- * @brief USB_ReadInterrupts: return the global USB interrupt status
- * @param USBx : Selected device
+ * @brief USB_ReadInterrupts return the global USB interrupt status
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
@@ -775,113 +735,8 @@
}
/**
- * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
- * @param USBx : Selected device
- * @retval HAL status
- */
-uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief Returns Device OUT EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device OUT EP Interrupt register
- */
-uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(epnum);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief Returns Device IN EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
- * This parameter can be a value from 0 to 15
- * @retval Device IN EP Interrupt register
- */
-uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(epnum);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return (0);
-}
-
-/**
- * @brief USB_ClearInterrupts: clear a USB interrupt
- * @param USBx Selected device
- * @param interrupt flag
- * @retval None
- */
-void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(interrupt);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
-}
-
-/**
- * @brief Prepare the EP0 to start the first control setup
- * @param USBx Selected device
- * @param psetup pointer to setup packet
- * @retval HAL status
- */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(USBx);
- UNUSED(psetup);
- /* NOTE : - This function is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral.
- - This function is added to ensure compatibility across platforms.
- */
- return HAL_OK;
-}
-
-/**
* @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
- * @param USBx Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
@@ -892,13 +747,14 @@
}
/**
- * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
- * @param USBx Selected device
+ * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
{
USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
+
return HAL_OK;
}
@@ -907,7 +763,7 @@
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
- * @param wNBytes: no. of bytes to be copied.
+ * @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
@@ -938,10 +794,10 @@
/**
* @brief Copy data from packet memory area (PMA) to user memory buffer
- * @param USBx: USB peripheral instance register address.
+ * @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
- * @param wNBytes: no. of bytes to be copied.
+ * @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
